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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1036 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1618569995 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:17 PM PDT 24 886589559 ps
T132 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.949225451 Jul 30 04:49:20 PM PDT 24 Jul 30 04:49:22 PM PDT 24 54916935 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.701419923 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:19 PM PDT 24 21316943 ps
T117 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1640146300 Jul 30 04:49:20 PM PDT 24 Jul 30 04:49:26 PM PDT 24 1269516093 ps
T128 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3008861620 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:38 PM PDT 24 1161967261 ps
T1038 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.459205591 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:19 PM PDT 24 32656416 ps
T133 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1800250119 Jul 30 04:48:11 PM PDT 24 Jul 30 04:48:12 PM PDT 24 41803857 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1553933253 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:37 PM PDT 24 560664178 ps
T126 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1134754474 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:37 PM PDT 24 7138427409 ps
T1040 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.386535007 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:21 PM PDT 24 15915135 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1421196751 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:44 PM PDT 24 5015098947 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3240260721 Jul 30 04:48:09 PM PDT 24 Jul 30 04:48:13 PM PDT 24 46993091 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.677041661 Jul 30 04:48:39 PM PDT 24 Jul 30 04:48:40 PM PDT 24 184870434 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.660179475 Jul 30 04:48:11 PM PDT 24 Jul 30 04:48:20 PM PDT 24 322606067 ps
T120 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1147719815 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:25 PM PDT 24 190814752 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.913448881 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:15 PM PDT 24 15223403 ps
T125 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.112799314 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:26 PM PDT 24 105177834 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2567365911 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:09 PM PDT 24 37273739 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4019874948 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:09 PM PDT 24 611736028 ps
T1047 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3383313805 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:16 PM PDT 24 46826204 ps
T127 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3001589654 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:23 PM PDT 24 201347084 ps
T168 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1878303716 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:15 PM PDT 24 53281176 ps
T1048 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1766594354 Jul 30 04:48:22 PM PDT 24 Jul 30 04:48:22 PM PDT 24 15751515 ps
T1049 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.756525194 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:22 PM PDT 24 65491091 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3992768365 Jul 30 04:48:04 PM PDT 24 Jul 30 04:48:05 PM PDT 24 31619031 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1632964720 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:30 PM PDT 24 40855006 ps
T1052 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3701183613 Jul 30 04:48:27 PM PDT 24 Jul 30 04:48:28 PM PDT 24 12016792 ps
T1053 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3139983436 Jul 30 04:48:13 PM PDT 24 Jul 30 04:48:14 PM PDT 24 25510906 ps
T169 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3690349352 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:28 PM PDT 24 144028485 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1339033168 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:09 PM PDT 24 68514033 ps
T1054 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2049243936 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:29 PM PDT 24 53143653 ps
T1055 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2471087109 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:08 PM PDT 24 299262326 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3740708020 Jul 30 04:48:10 PM PDT 24 Jul 30 04:48:14 PM PDT 24 266185316 ps
T134 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2383613283 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:38 PM PDT 24 5676351053 ps
T118 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3276425873 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:35 PM PDT 24 151801656 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2452764576 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:12 PM PDT 24 240016842 ps
T1058 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1145907650 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:21 PM PDT 24 56578364 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2412294449 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:22 PM PDT 24 98433903 ps
T135 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3019248043 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:09 PM PDT 24 78510011 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4104826727 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:08 PM PDT 24 187449468 ps
T119 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.388960070 Jul 30 04:48:10 PM PDT 24 Jul 30 04:48:13 PM PDT 24 122874123 ps
T1061 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1864245777 Jul 30 04:48:16 PM PDT 24 Jul 30 04:48:20 PM PDT 24 199239709 ps
T1062 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1227712100 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:31 PM PDT 24 36909689 ps
T136 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3015401296 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:05 PM PDT 24 35654405 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2261978140 Jul 30 04:48:09 PM PDT 24 Jul 30 04:48:10 PM PDT 24 38948445 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2999484006 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:20 PM PDT 24 195700659 ps
T1065 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2433500542 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 27032544 ps
T122 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4171774730 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:25 PM PDT 24 615483300 ps
T137 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2365517653 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:31 PM PDT 24 145249240 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.142848008 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:25 PM PDT 24 648253961 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.400020185 Jul 30 04:48:27 PM PDT 24 Jul 30 04:48:31 PM PDT 24 294088658 ps
T138 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2000614340 Jul 30 04:48:01 PM PDT 24 Jul 30 04:48:03 PM PDT 24 50797756 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.966560191 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:08 PM PDT 24 382539701 ps
T1069 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.222211454 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:31 PM PDT 24 14766631 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1138895181 Jul 30 04:49:24 PM PDT 24 Jul 30 04:49:25 PM PDT 24 12519839 ps
T98 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.360887307 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:09 PM PDT 24 251249810 ps
T188 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2102010518 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:34 PM PDT 24 1229926305 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.63914414 Jul 30 04:48:35 PM PDT 24 Jul 30 04:48:39 PM PDT 24 133603762 ps
T1072 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3609260013 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:29 PM PDT 24 15313863 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1902858430 Jul 30 04:49:24 PM PDT 24 Jul 30 04:49:26 PM PDT 24 236001079 ps
T1074 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2262159474 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:16 PM PDT 24 41420570 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.515502054 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:25 PM PDT 24 232985631 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1755489503 Jul 30 04:48:10 PM PDT 24 Jul 30 04:48:11 PM PDT 24 13191515 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.531590373 Jul 30 04:49:18 PM PDT 24 Jul 30 04:49:19 PM PDT 24 23858520 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2163810672 Jul 30 04:48:12 PM PDT 24 Jul 30 04:48:18 PM PDT 24 271965860 ps
T191 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1724423743 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:23 PM PDT 24 1170864282 ps
T1078 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2197881067 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:11 PM PDT 24 150782144 ps
T1079 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4079987910 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:18 PM PDT 24 18046506 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.893717123 Jul 30 04:48:11 PM PDT 24 Jul 30 04:48:12 PM PDT 24 53966246 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2429016228 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:16 PM PDT 24 39489143 ps
T1082 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1226285669 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:20 PM PDT 24 32292030 ps
T1083 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1873021809 Jul 30 04:48:19 PM PDT 24 Jul 30 04:48:20 PM PDT 24 13523491 ps
T1084 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2234587608 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:30 PM PDT 24 82812011 ps
T139 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3088607391 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:19 PM PDT 24 609193405 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3069593954 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:04 PM PDT 24 37437506 ps
T140 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1629771441 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:21 PM PDT 24 395342994 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2917315336 Jul 30 04:48:09 PM PDT 24 Jul 30 04:48:10 PM PDT 24 54015745 ps
T1087 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1913286349 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:04 PM PDT 24 18508514 ps
T141 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2994842982 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:32 PM PDT 24 131645885 ps
T1088 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.124676772 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:16 PM PDT 24 16267765 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1986510772 Jul 30 04:48:26 PM PDT 24 Jul 30 04:48:27 PM PDT 24 65482591 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2091747066 Jul 30 04:48:22 PM PDT 24 Jul 30 04:48:28 PM PDT 24 128057663 ps
T185 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1593184085 Jul 30 04:48:06 PM PDT 24 Jul 30 04:48:34 PM PDT 24 5465532111 ps
T1091 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2202292127 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:26 PM PDT 24 29634312 ps
T1092 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1705388976 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 49117968 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1856553045 Jul 30 04:48:06 PM PDT 24 Jul 30 04:48:08 PM PDT 24 45871412 ps
T123 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1434450059 Jul 30 04:48:26 PM PDT 24 Jul 30 04:48:30 PM PDT 24 70159214 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3213526629 Jul 30 04:48:02 PM PDT 24 Jul 30 04:48:03 PM PDT 24 170464683 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4059330329 Jul 30 04:49:19 PM PDT 24 Jul 30 04:49:22 PM PDT 24 444761049 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1262623213 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:08 PM PDT 24 759805501 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.423723014 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:19 PM PDT 24 202623261 ps
T1097 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3508587165 Jul 30 04:48:10 PM PDT 24 Jul 30 04:48:12 PM PDT 24 99452663 ps
T1098 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.917753712 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:28 PM PDT 24 445436126 ps
T189 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3385476574 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:35 PM PDT 24 592093206 ps
T1099 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1405224192 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:08 PM PDT 24 642913466 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1091687779 Jul 30 04:48:04 PM PDT 24 Jul 30 04:48:05 PM PDT 24 60159528 ps
T1101 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.487169563 Jul 30 04:48:24 PM PDT 24 Jul 30 04:48:27 PM PDT 24 324172946 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3920683380 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:09 PM PDT 24 27525220 ps
T1103 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3428007665 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:20 PM PDT 24 39864446 ps
T1104 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3205795170 Jul 30 04:48:24 PM PDT 24 Jul 30 04:48:25 PM PDT 24 11747590 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3209700240 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:30 PM PDT 24 299354733 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1274833951 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:09 PM PDT 24 43986870 ps
T1107 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1244237231 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:31 PM PDT 24 41787102 ps
T190 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2461231408 Jul 30 04:48:06 PM PDT 24 Jul 30 04:48:20 PM PDT 24 930390139 ps
T1108 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.381372084 Jul 30 04:49:21 PM PDT 24 Jul 30 04:49:26 PM PDT 24 304939194 ps
T1109 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2007560886 Jul 30 04:48:17 PM PDT 24 Jul 30 04:48:19 PM PDT 24 59868148 ps
T1110 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2265867455 Jul 30 04:48:32 PM PDT 24 Jul 30 04:48:33 PM PDT 24 47507159 ps
T186 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2833736941 Jul 30 04:48:16 PM PDT 24 Jul 30 04:48:29 PM PDT 24 517806849 ps
T1111 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1129177508 Jul 30 04:48:36 PM PDT 24 Jul 30 04:48:37 PM PDT 24 11979030 ps
T1112 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.411010813 Jul 30 04:48:30 PM PDT 24 Jul 30 04:48:32 PM PDT 24 74596059 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3588319899 Jul 30 04:48:03 PM PDT 24 Jul 30 04:48:06 PM PDT 24 311509626 ps
T1114 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.185934117 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:37 PM PDT 24 2174102044 ps
T1115 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3305542675 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:13 PM PDT 24 560561242 ps
T1116 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.815848295 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:27 PM PDT 24 4306947455 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2020480660 Jul 30 04:48:22 PM PDT 24 Jul 30 04:48:24 PM PDT 24 28089837 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2111223478 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:26 PM PDT 24 187721101 ps
T187 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.925568230 Jul 30 04:48:25 PM PDT 24 Jul 30 04:48:46 PM PDT 24 631096647 ps
T1119 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3938649635 Jul 30 04:48:22 PM PDT 24 Jul 30 04:48:24 PM PDT 24 269789380 ps
T1120 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.25948374 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:10 PM PDT 24 142770861 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1981208895 Jul 30 04:48:09 PM PDT 24 Jul 30 04:48:13 PM PDT 24 57897931 ps
T1122 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2598155977 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:21 PM PDT 24 81998763 ps
T1123 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2892072228 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:16 PM PDT 24 34390223 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3176912694 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:06 PM PDT 24 12319245 ps
T1125 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2619382755 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:17 PM PDT 24 57405072 ps
T1126 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.757320882 Jul 30 04:48:08 PM PDT 24 Jul 30 04:48:10 PM PDT 24 79796754 ps
T1127 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.476266447 Jul 30 04:48:23 PM PDT 24 Jul 30 04:48:24 PM PDT 24 26877385 ps
T1128 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.170810366 Jul 30 04:48:29 PM PDT 24 Jul 30 04:48:30 PM PDT 24 15852262 ps
T1129 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.689193462 Jul 30 04:48:01 PM PDT 24 Jul 30 04:48:33 PM PDT 24 546753460 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2681989332 Jul 30 04:48:27 PM PDT 24 Jul 30 04:48:28 PM PDT 24 20768072 ps
T1131 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3342548212 Jul 30 04:48:24 PM PDT 24 Jul 30 04:48:27 PM PDT 24 136046193 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3211140977 Jul 30 04:48:14 PM PDT 24 Jul 30 04:48:39 PM PDT 24 1727059092 ps
T1133 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.17799124 Jul 30 04:48:43 PM PDT 24 Jul 30 04:48:43 PM PDT 24 61547224 ps
T192 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3007464217 Jul 30 04:48:02 PM PDT 24 Jul 30 04:48:23 PM PDT 24 330475029 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3985518737 Jul 30 04:48:07 PM PDT 24 Jul 30 04:48:15 PM PDT 24 116378411 ps
T1135 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1771461115 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:11 PM PDT 24 170689358 ps
T1136 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4147424704 Jul 30 04:48:26 PM PDT 24 Jul 30 04:48:27 PM PDT 24 30457652 ps
T1137 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1358033880 Jul 30 04:48:13 PM PDT 24 Jul 30 04:48:14 PM PDT 24 11280655 ps
T1138 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3866154593 Jul 30 04:48:20 PM PDT 24 Jul 30 04:48:21 PM PDT 24 26649787 ps
T1139 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2775161651 Jul 30 04:48:15 PM PDT 24 Jul 30 04:48:23 PM PDT 24 115411110 ps
T1140 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.340033215 Jul 30 04:48:05 PM PDT 24 Jul 30 04:48:07 PM PDT 24 208608292 ps
T1141 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1028953426 Jul 30 04:48:12 PM PDT 24 Jul 30 04:48:16 PM PDT 24 723656920 ps
T1142 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.331680280 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:29 PM PDT 24 44156487 ps
T1143 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.931007320 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:23 PM PDT 24 118205640 ps
T1144 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1675978196 Jul 30 04:48:18 PM PDT 24 Jul 30 04:48:20 PM PDT 24 107406287 ps
T1145 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1538626260 Jul 30 04:48:28 PM PDT 24 Jul 30 04:48:30 PM PDT 24 69832576 ps
T1146 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1535719501 Jul 30 04:48:11 PM PDT 24 Jul 30 04:48:25 PM PDT 24 3273409939 ps
T1147 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.215402209 Jul 30 04:48:01 PM PDT 24 Jul 30 04:48:03 PM PDT 24 34774819 ps
T1148 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2088087314 Jul 30 04:48:21 PM PDT 24 Jul 30 04:48:22 PM PDT 24 37202003 ps
T1149 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3824260537 Jul 30 04:49:48 PM PDT 24 Jul 30 04:49:49 PM PDT 24 14277701 ps
T1150 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4092874677 Jul 30 04:48:09 PM PDT 24 Jul 30 04:48:25 PM PDT 24 2406798175 ps
T1151 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.917893403 Jul 30 04:48:16 PM PDT 24 Jul 30 04:48:23 PM PDT 24 427811472 ps

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1735517270
Short name T2
Test name
Test status
Simulation time 81430590482 ps
CPU time 545.17 seconds
Started Jul 30 04:50:25 PM PDT 24
Finished Jul 30 04:59:30 PM PDT 24
Peak memory 256672 kb
Host smart-873d0cac-f7c6-4ea8-8504-9c4dbd1517fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735517270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1735517270
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2216708954
Short name T11
Test name
Test status
Simulation time 24123980832 ps
CPU time 158.15 seconds
Started Jul 30 04:48:55 PM PDT 24
Finished Jul 30 04:51:33 PM PDT 24
Peak memory 254740 kb
Host smart-b1f9cb01-6289-4806-ac9f-bb80e0367ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216708954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2216708954
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1391325106
Short name T21
Test name
Test status
Simulation time 32350975389 ps
CPU time 293.34 seconds
Started Jul 30 04:50:31 PM PDT 24
Finished Jul 30 04:55:25 PM PDT 24
Peak memory 286212 kb
Host smart-24ed8e9f-ad8f-47fa-bcbd-4c17a3bdbe2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391325106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1391325106
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1623193778
Short name T115
Test name
Test status
Simulation time 1096206299 ps
CPU time 15.7 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:36 PM PDT 24
Peak memory 215540 kb
Host smart-986ec1c1-3745-484c-9c19-a9c181a83a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623193778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1623193778
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2854019141
Short name T92
Test name
Test status
Simulation time 17305184391 ps
CPU time 174.14 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:52:41 PM PDT 24
Peak memory 267236 kb
Host smart-4ab46de9-4c78-412a-91d7-b06b78f68a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854019141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2854019141
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2968387888
Short name T75
Test name
Test status
Simulation time 38393174 ps
CPU time 0.73 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 216564 kb
Host smart-47e0da35-4557-458b-9bdf-6b020fdc60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968387888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2968387888
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2699124410
Short name T94
Test name
Test status
Simulation time 30173042392 ps
CPU time 474.69 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:57:07 PM PDT 24
Peak memory 288900 kb
Host smart-8c79f937-074b-45e7-9daa-f06dadff98db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699124410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2699124410
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.716397028
Short name T114
Test name
Test status
Simulation time 1362648660 ps
CPU time 5.89 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:13 PM PDT 24
Peak memory 215628 kb
Host smart-a2d9590d-21c0-4c08-bb63-69ac1cc85349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716397028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.716397028
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2281369898
Short name T32
Test name
Test status
Simulation time 163038769406 ps
CPU time 478.87 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:58:11 PM PDT 24
Peak memory 274456 kb
Host smart-91d078a9-e272-45d8-9643-102b2f265a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281369898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2281369898
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1602126390
Short name T76
Test name
Test status
Simulation time 34523877 ps
CPU time 0.9 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:25 PM PDT 24
Peak memory 235440 kb
Host smart-d264264b-7cd2-4f12-8a29-786baba41694
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602126390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1602126390
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2177960335
Short name T91
Test name
Test status
Simulation time 24115545069 ps
CPU time 259.27 seconds
Started Jul 30 04:50:56 PM PDT 24
Finished Jul 30 04:55:15 PM PDT 24
Peak memory 272356 kb
Host smart-8d2f1d11-e324-47e9-95ec-2f886eafc545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177960335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2177960335
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3344800909
Short name T93
Test name
Test status
Simulation time 116522605853 ps
CPU time 1066.4 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 05:06:48 PM PDT 24
Peak memory 282584 kb
Host smart-4ec45ca3-aaba-43b2-b67c-10186b2fd0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344800909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3344800909
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3720894708
Short name T67
Test name
Test status
Simulation time 12131117898 ps
CPU time 45.27 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 237524 kb
Host smart-e99605de-b96e-44e7-a5a5-639567e238ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720894708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3720894708
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3429807602
Short name T212
Test name
Test status
Simulation time 218072262532 ps
CPU time 538.67 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:59:58 PM PDT 24
Peak memory 258040 kb
Host smart-bac9b1f0-2315-453c-91b1-0d3ba737971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429807602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3429807602
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.360887307
Short name T98
Test name
Test status
Simulation time 251249810 ps
CPU time 1.14 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 207240 kb
Host smart-ea9baae8-2249-4878-b210-adb9b358ad48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360887307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.360887307
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1447320704
Short name T292
Test name
Test status
Simulation time 183708872393 ps
CPU time 292.6 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:54:26 PM PDT 24
Peak memory 266216 kb
Host smart-607b3dc2-cf21-4645-8b61-5114f3134f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447320704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1447320704
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3106666928
Short name T18
Test name
Test status
Simulation time 171378011724 ps
CPU time 419.75 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:56:10 PM PDT 24
Peak memory 257988 kb
Host smart-94a41562-e7b6-4614-9c0d-91d64451f8a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106666928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3106666928
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.688095094
Short name T512
Test name
Test status
Simulation time 16331148 ps
CPU time 1.09 seconds
Started Jul 30 04:48:41 PM PDT 24
Finished Jul 30 04:48:42 PM PDT 24
Peak memory 217048 kb
Host smart-2576dcaa-16ef-4dc9-9f3f-989b31a56ab4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688095094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.688095094
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.275749264
Short name T210
Test name
Test status
Simulation time 37991560927 ps
CPU time 126.64 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:52:53 PM PDT 24
Peak memory 256868 kb
Host smart-d398b3ab-3e7d-4ca3-94ed-dfa9f063bb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275749264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.275749264
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3048893100
Short name T7
Test name
Test status
Simulation time 22629931934 ps
CPU time 29.42 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 217028 kb
Host smart-4d944040-89ed-44fe-9b2a-bf3617b26a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048893100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3048893100
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1604703562
Short name T289
Test name
Test status
Simulation time 275670177514 ps
CPU time 432.94 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:56:22 PM PDT 24
Peak memory 267296 kb
Host smart-be8cb372-f5f3-4f62-b7e0-e1b5ce8cb6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604703562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1604703562
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.196657720
Short name T335
Test name
Test status
Simulation time 45784234 ps
CPU time 0.73 seconds
Started Jul 30 04:49:42 PM PDT 24
Finished Jul 30 04:49:43 PM PDT 24
Peak memory 205748 kb
Host smart-a2e1b9b5-7ead-4f3f-8609-860eda066a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196657720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.196657720
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1593184085
Short name T185
Test name
Test status
Simulation time 5465532111 ps
CPU time 27.67 seconds
Started Jul 30 04:48:06 PM PDT 24
Finished Jul 30 04:48:34 PM PDT 24
Peak memory 215724 kb
Host smart-3a9d4313-578d-430a-9e24-5cc1ad46a5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593184085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1593184085
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2763588305
Short name T240
Test name
Test status
Simulation time 6915851840 ps
CPU time 70.77 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:50:37 PM PDT 24
Peak memory 253264 kb
Host smart-b6f94394-e1d7-4b75-8c8a-c86d0d8a984a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763588305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2763588305
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3723049198
Short name T214
Test name
Test status
Simulation time 11359063258 ps
CPU time 142.69 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:51:47 PM PDT 24
Peak memory 250876 kb
Host smart-7cd0ba7d-6d6b-489a-8a03-2df1e2e6695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723049198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3723049198
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.262768360
Short name T297
Test name
Test status
Simulation time 22015262458 ps
CPU time 134.45 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:52:23 PM PDT 24
Peak memory 288028 kb
Host smart-a6f6710e-1235-47d4-a720-1059757fc0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262768360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.262768360
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4243967525
Short name T62
Test name
Test status
Simulation time 15904192196 ps
CPU time 38.93 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:51:16 PM PDT 24
Peak memory 239668 kb
Host smart-4cb10d18-3048-43b6-8a1d-9183c39f2c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243967525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4243967525
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1180728794
Short name T288
Test name
Test status
Simulation time 24812744326 ps
CPU time 247.42 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:53:54 PM PDT 24
Peak memory 241628 kb
Host smart-29315b0d-5d2d-4a7c-a31b-2b5b91a8d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180728794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1180728794
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2803712951
Short name T218
Test name
Test status
Simulation time 1907951852 ps
CPU time 49.88 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:50:35 PM PDT 24
Peak memory 255660 kb
Host smart-43384e5d-6de2-4bc6-a188-cad7a11b857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803712951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2803712951
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2113706580
Short name T236
Test name
Test status
Simulation time 3813074119 ps
CPU time 95.73 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:52:33 PM PDT 24
Peak memory 252204 kb
Host smart-e24c10fc-5e26-4d0b-bb51-fbf36ccf716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113706580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2113706580
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2839251846
Short name T274
Test name
Test status
Simulation time 492923350121 ps
CPU time 748.68 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 05:01:25 PM PDT 24
Peak memory 257096 kb
Host smart-1d98be53-640f-42f6-a20d-3cb1d5068a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839251846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2839251846
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.569572889
Short name T996
Test name
Test status
Simulation time 22662233658 ps
CPU time 97.82 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:52:35 PM PDT 24
Peak memory 266840 kb
Host smart-a17d5b7a-03ee-4d7a-9014-0940b8e076a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569572889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.569572889
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.680664413
Short name T687
Test name
Test status
Simulation time 39540598411 ps
CPU time 36.01 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:50:00 PM PDT 24
Peak memory 233424 kb
Host smart-8114bc62-5c02-461b-a8db-00884d81669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680664413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.680664413
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4141744827
Short name T173
Test name
Test status
Simulation time 165817287839 ps
CPU time 334.84 seconds
Started Jul 30 04:50:36 PM PDT 24
Finished Jul 30 04:56:11 PM PDT 24
Peak memory 253844 kb
Host smart-08978d08-04f9-49c9-9d44-abbf1d21af2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141744827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4141744827
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1154617868
Short name T130
Test name
Test status
Simulation time 87891721 ps
CPU time 3.02 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:36 PM PDT 24
Peak memory 233276 kb
Host smart-542ee14d-e37a-48f3-a1c6-5b5a28551754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154617868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1154617868
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.727065823
Short name T294
Test name
Test status
Simulation time 14764506368 ps
CPU time 119.16 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:52:45 PM PDT 24
Peak memory 265184 kb
Host smart-e499d7c7-6881-4247-90f0-ac6e78cdfd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727065823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.727065823
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1984494659
Short name T1020
Test name
Test status
Simulation time 445087455110 ps
CPU time 881.46 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 05:05:19 PM PDT 24
Peak memory 281644 kb
Host smart-396d84cd-458a-46d2-ad14-fd34a86a8ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984494659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1984494659
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1689763791
Short name T304
Test name
Test status
Simulation time 2890579660 ps
CPU time 38.35 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:51:27 PM PDT 24
Peak memory 239324 kb
Host smart-c50eec01-558e-43d2-ad7c-68ef5b3fdaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689763791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1689763791
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1084609448
Short name T101
Test name
Test status
Simulation time 17944420284 ps
CPU time 37.42 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:51:29 PM PDT 24
Peak memory 241652 kb
Host smart-3a6eed3b-ef23-4907-b454-7d43af0f1647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084609448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1084609448
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2804704398
Short name T52
Test name
Test status
Simulation time 2342494056 ps
CPU time 7.71 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 240192 kb
Host smart-f8a0c33d-d0b0-4016-a133-e54afeae370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804704398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2804704398
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1640146300
Short name T117
Test name
Test status
Simulation time 1269516093 ps
CPU time 5.31 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 215608 kb
Host smart-28c4c840-0a55-4f15-9230-52f03cf15397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640146300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1640146300
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3007464217
Short name T192
Test name
Test status
Simulation time 330475029 ps
CPU time 21.13 seconds
Started Jul 30 04:48:02 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 215476 kb
Host smart-27b2ff6e-2b9e-483e-8a70-defc56c0e4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007464217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3007464217
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.744366125
Short name T338
Test name
Test status
Simulation time 30048485 ps
CPU time 0.8 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 206472 kb
Host smart-92056a82-4116-4e9d-9b70-340c07940d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744366125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.744366125
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.354100236
Short name T154
Test name
Test status
Simulation time 116108302494 ps
CPU time 547.7 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:58:21 PM PDT 24
Peak memory 260320 kb
Host smart-a3dedc95-d50d-47ac-881b-e8ff784abe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354100236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.354100236
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1190084253
Short name T327
Test name
Test status
Simulation time 42698743708 ps
CPU time 226.29 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:54:22 PM PDT 24
Peak memory 251892 kb
Host smart-70aa083a-5def-4f49-9922-f6842eb7dfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190084253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1190084253
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3485290581
Short name T102
Test name
Test status
Simulation time 4735232275 ps
CPU time 48.22 seconds
Started Jul 30 04:48:48 PM PDT 24
Finished Jul 30 04:49:36 PM PDT 24
Peak memory 236656 kb
Host smart-9691afe3-1a7f-4f2c-a050-ca7d54b10b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485290581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3485290581
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1159806403
Short name T96
Test name
Test status
Simulation time 30903916 ps
CPU time 1.01 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 206968 kb
Host smart-08760073-6d00-42e1-b6e1-5e61b1a67492
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159806403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1159806403
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1923474918
Short name T13
Test name
Test status
Simulation time 151562116 ps
CPU time 4.59 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 225204 kb
Host smart-68c7dedc-ae1c-4228-af0c-206d0db01218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923474918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1923474918
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2634183306
Short name T34
Test name
Test status
Simulation time 45871347534 ps
CPU time 150.42 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:52:06 PM PDT 24
Peak memory 256924 kb
Host smart-74f04278-9384-4b6d-8351-365e56751ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634183306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2634183306
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4092874677
Short name T1150
Test name
Test status
Simulation time 2406798175 ps
CPU time 16.33 seconds
Started Jul 30 04:48:09 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 207344 kb
Host smart-20e905ed-47ab-4e63-a665-03c0667c4419
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092874677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4092874677
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.689193462
Short name T1129
Test name
Test status
Simulation time 546753460 ps
CPU time 31.82 seconds
Started Jul 30 04:48:01 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 207184 kb
Host smart-ec88fa1d-1de4-4d61-a35f-de248b129a7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689193462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.689193462
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1534444502
Short name T131
Test name
Test status
Simulation time 46148653 ps
CPU time 0.96 seconds
Started Jul 30 04:48:08 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 206888 kb
Host smart-a72fdcb1-0901-49dc-b9d0-13f382901e9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534444502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1534444502
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4059330329
Short name T1094
Test name
Test status
Simulation time 444761049 ps
CPU time 2.56 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 216396 kb
Host smart-4e01ced1-9486-4a9e-91fa-c2f656ca07a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059330329 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4059330329
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1856553045
Short name T142
Test name
Test status
Simulation time 45871412 ps
CPU time 1.75 seconds
Started Jul 30 04:48:06 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 215444 kb
Host smart-959e53f3-d734-4767-a52d-910fdafec650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856553045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
856553045
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3213526629
Short name T1093
Test name
Test status
Simulation time 170464683 ps
CPU time 0.84 seconds
Started Jul 30 04:48:02 PM PDT 24
Finished Jul 30 04:48:03 PM PDT 24
Peak memory 203816 kb
Host smart-c92e9f47-8c17-42c0-a90c-ea5c6b3a2c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213526629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
213526629
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3015401296
Short name T136
Test name
Test status
Simulation time 35654405 ps
CPU time 2.14 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:05 PM PDT 24
Peak memory 215432 kb
Host smart-06c22508-e95a-4e6f-b394-ce3cbb235bf9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015401296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3015401296
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1632964720
Short name T1051
Test name
Test status
Simulation time 40855006 ps
CPU time 0.69 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 202972 kb
Host smart-c9e8f9ca-fdff-4a18-9420-b97c23a36dee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632964720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1632964720
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1274833951
Short name T1106
Test name
Test status
Simulation time 43986870 ps
CPU time 2.85 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 215316 kb
Host smart-159fc02b-2ab9-4f2a-bc36-8a10fa840746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274833951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1274833951
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.76030136
Short name T113
Test name
Test status
Simulation time 55906078 ps
CPU time 4.62 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 215532 kb
Host smart-375c58b7-0301-425e-8a24-f21cae36798a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76030136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.76030136
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2452764576
Short name T1057
Test name
Test status
Simulation time 240016842 ps
CPU time 8.58 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:12 PM PDT 24
Peak memory 215368 kb
Host smart-7016f42e-b8bf-4c11-bf73-04ffb78f408f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452764576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2452764576
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3088607391
Short name T139
Test name
Test status
Simulation time 609193405 ps
CPU time 13.02 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 215296 kb
Host smart-a233da69-98fc-4b1c-bbbf-f3ad9a48ec50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088607391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3088607391
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.966560191
Short name T1068
Test name
Test status
Simulation time 382539701 ps
CPU time 3.06 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 216624 kb
Host smart-04b8b2f8-a0dd-4392-9cc8-531e5788e6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966560191 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.966560191
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2365517653
Short name T137
Test name
Test status
Simulation time 145249240 ps
CPU time 1.77 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 215148 kb
Host smart-fcf5dae2-eace-4df3-a4e2-a04f6507d019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365517653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
365517653
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2265867455
Short name T1110
Test name
Test status
Simulation time 47507159 ps
CPU time 0.7 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:33 PM PDT 24
Peak memory 204184 kb
Host smart-99896f9d-df94-4f94-b4d0-e2107bd90797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265867455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
265867455
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1091687779
Short name T1100
Test name
Test status
Simulation time 60159528 ps
CPU time 1.18 seconds
Started Jul 30 04:48:04 PM PDT 24
Finished Jul 30 04:48:05 PM PDT 24
Peak memory 215312 kb
Host smart-d972b157-7069-4b2e-aa83-9b55b3151e96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091687779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1091687779
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.531590373
Short name T1077
Test name
Test status
Simulation time 23858520 ps
CPU time 0.67 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 203752 kb
Host smart-2e644951-fde0-4bef-9a67-1ff6fd0a98f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531590373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.531590373
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1198161475
Short name T159
Test name
Test status
Simulation time 43838079 ps
CPU time 2.54 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:06 PM PDT 24
Peak memory 215468 kb
Host smart-46f5caa3-814a-45d0-b2fc-57888e637622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198161475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1198161475
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3588319899
Short name T1113
Test name
Test status
Simulation time 311509626 ps
CPU time 2.09 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:06 PM PDT 24
Peak memory 215572 kb
Host smart-e9eefdb7-df6c-4619-9982-ead8685c3d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588319899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
588319899
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3777525003
Short name T112
Test name
Test status
Simulation time 266988050 ps
CPU time 7.22 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:11 PM PDT 24
Peak memory 215408 kb
Host smart-2e8eba49-b342-4c27-814e-ae1f939a69d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777525003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3777525003
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3001589654
Short name T127
Test name
Test status
Simulation time 201347084 ps
CPU time 3.14 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 217028 kb
Host smart-0eadbcb1-fee8-4f57-b346-35ceaf982e08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001589654 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3001589654
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2261978140
Short name T1063
Test name
Test status
Simulation time 38948445 ps
CPU time 1.36 seconds
Started Jul 30 04:48:09 PM PDT 24
Finished Jul 30 04:48:10 PM PDT 24
Peak memory 207180 kb
Host smart-c29c5821-1b04-4846-b917-306a414ea970
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261978140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2261978140
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2999484006
Short name T1064
Test name
Test status
Simulation time 195700659 ps
CPU time 0.74 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 203884 kb
Host smart-55ce1d06-27ab-436e-8227-e1d1e2ea8bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999484006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2999484006
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2020480660
Short name T1117
Test name
Test status
Simulation time 28089837 ps
CPU time 1.75 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:24 PM PDT 24
Peak memory 215336 kb
Host smart-b53c10da-9575-41d6-b731-221ae90efad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020480660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2020480660
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1675978196
Short name T1144
Test name
Test status
Simulation time 107406287 ps
CPU time 1.85 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 216624 kb
Host smart-585b59ef-5bfc-4b8c-ac70-1b0c8392a612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675978196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1675978196
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.112799314
Short name T125
Test name
Test status
Simulation time 105177834 ps
CPU time 7.79 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 215464 kb
Host smart-b49b83a5-5e67-417b-a0c2-bd17a9cf59d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112799314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.112799314
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2007560886
Short name T1109
Test name
Test status
Simulation time 59868148 ps
CPU time 1.57 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 215504 kb
Host smart-5fe70c06-2e54-4125-b82f-47cf18c51f25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007560886 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2007560886
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3342548212
Short name T1131
Test name
Test status
Simulation time 136046193 ps
CPU time 2.62 seconds
Started Jul 30 04:48:24 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 215428 kb
Host smart-2058a5d6-e813-4565-b4b1-8e9e8a2345f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342548212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3342548212
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2892072228
Short name T1123
Test name
Test status
Simulation time 34390223 ps
CPU time 0.72 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 204240 kb
Host smart-5d0f94a2-7666-4e28-b482-6a2569c3956b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892072228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2892072228
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3690349352
Short name T169
Test name
Test status
Simulation time 144028485 ps
CPU time 3.1 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 215376 kb
Host smart-d0c9d30a-79dc-4904-9888-6f73f625c80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690349352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3690349352
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2598155977
Short name T1122
Test name
Test status
Simulation time 81998763 ps
CPU time 2.54 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 216788 kb
Host smart-5e32ecf5-079d-4e66-8a38-4fe61059590a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598155977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2598155977
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3385476574
Short name T189
Test name
Test status
Simulation time 592093206 ps
CPU time 14.56 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 216060 kb
Host smart-b913b6ea-0a01-4a0f-ac58-fb68cf628bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385476574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3385476574
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1145907650
Short name T1058
Test name
Test status
Simulation time 56578364 ps
CPU time 3.64 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 217492 kb
Host smart-8612489d-83d5-41dc-bde8-7db5ee33738c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145907650 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1145907650
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.411010813
Short name T1112
Test name
Test status
Simulation time 74596059 ps
CPU time 1.96 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 215508 kb
Host smart-862adbe7-da6a-433d-9d63-11fa690177e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411010813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.411010813
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2681989332
Short name T1130
Test name
Test status
Simulation time 20768072 ps
CPU time 0.79 seconds
Started Jul 30 04:48:27 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 203972 kb
Host smart-542a62f2-9a73-40df-8623-44c9a6ace58e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681989332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2681989332
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3839076212
Short name T166
Test name
Test status
Simulation time 258210747 ps
CPU time 3.17 seconds
Started Jul 30 04:48:24 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 215504 kb
Host smart-de4dfcb9-2495-4d40-8246-886b161562fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839076212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3839076212
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.815848295
Short name T1116
Test name
Test status
Simulation time 4306947455 ps
CPU time 6.56 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 215892 kb
Host smart-173f294e-62b0-4010-a582-bb4272622cee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815848295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.815848295
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1134754474
Short name T126
Test name
Test status
Simulation time 7138427409 ps
CPU time 16.25 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 215712 kb
Host smart-3defc8bf-e00f-4639-a332-4bd3e621afed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134754474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1134754474
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.142848008
Short name T1066
Test name
Test status
Simulation time 648253961 ps
CPU time 3.85 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 218564 kb
Host smart-c578cef6-419f-42fe-8f98-100a99842d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142848008 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.142848008
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1800250119
Short name T133
Test name
Test status
Simulation time 41803857 ps
CPU time 1.28 seconds
Started Jul 30 04:48:11 PM PDT 24
Finished Jul 30 04:48:12 PM PDT 24
Peak memory 207280 kb
Host smart-b234aa19-0356-4687-9cbe-a8273700b734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800250119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1800250119
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.893717123
Short name T1080
Test name
Test status
Simulation time 53966246 ps
CPU time 0.77 seconds
Started Jul 30 04:48:11 PM PDT 24
Finished Jul 30 04:48:12 PM PDT 24
Peak memory 204256 kb
Host smart-15c60c92-3c59-429e-bea3-6a301c1e5aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893717123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.893717123
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.400020185
Short name T1067
Test name
Test status
Simulation time 294088658 ps
CPU time 3.13 seconds
Started Jul 30 04:48:27 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 215452 kb
Host smart-ad3055ef-fc39-409e-b856-7fe64de97ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400020185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.400020185
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1147719815
Short name T120
Test name
Test status
Simulation time 190814752 ps
CPU time 4.69 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 215744 kb
Host smart-7d178d49-e9bc-444a-a342-177822085a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147719815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1147719815
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.185934117
Short name T1114
Test name
Test status
Simulation time 2174102044 ps
CPU time 14.46 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 216264 kb
Host smart-f437347c-699b-478f-a297-4f8b9c4857a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185934117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.185934117
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.931007320
Short name T1143
Test name
Test status
Simulation time 118205640 ps
CPU time 1.79 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 216528 kb
Host smart-816ac8ba-c853-4c34-a733-0cd31ed574a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931007320 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.931007320
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2429016228
Short name T1081
Test name
Test status
Simulation time 39489143 ps
CPU time 2.54 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 215408 kb
Host smart-6a3f9724-6980-40c0-82ac-ae6d4711bd2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429016228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2429016228
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2988348025
Short name T1032
Test name
Test status
Simulation time 13422622 ps
CPU time 0.7 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 203828 kb
Host smart-e2985107-4dc8-455e-b243-5cb5e1029fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988348025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2988348025
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.917753712
Short name T1098
Test name
Test status
Simulation time 445436126 ps
CPU time 3.11 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 215412 kb
Host smart-7c8d5b1f-da3d-47ee-a4ee-1070b93754c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917753712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.917753712
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.381372084
Short name T1108
Test name
Test status
Simulation time 304939194 ps
CPU time 4.91 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 216696 kb
Host smart-d134af64-22ce-4632-a7c8-10d15ed5c296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381372084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.381372084
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1553933253
Short name T1039
Test name
Test status
Simulation time 560664178 ps
CPU time 8.18 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 215468 kb
Host smart-e00af7ec-190f-4325-9dcb-5a3318ee836a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553933253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1553933253
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4240938716
Short name T110
Test name
Test status
Simulation time 953777924 ps
CPU time 3.08 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 217916 kb
Host smart-f05b1ff7-a4e6-449b-a222-d96903654df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240938716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4240938716
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1538626260
Short name T1145
Test name
Test status
Simulation time 69832576 ps
CPU time 2.16 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 215488 kb
Host smart-fa8297e8-c20d-4cff-a2bd-e4bfb8aa848a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538626260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1538626260
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1358033880
Short name T1137
Test name
Test status
Simulation time 11280655 ps
CPU time 0.73 seconds
Started Jul 30 04:48:13 PM PDT 24
Finished Jul 30 04:48:14 PM PDT 24
Peak memory 203760 kb
Host smart-bfe63f4f-2957-445b-86f1-e96fee3dc681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358033880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1358033880
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1902858430
Short name T1073
Test name
Test status
Simulation time 236001079 ps
CPU time 1.62 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 215388 kb
Host smart-0c59b61c-e18a-4888-92bd-5c1b833e414f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902858430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1902858430
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2111223478
Short name T1118
Test name
Test status
Simulation time 187721101 ps
CPU time 5.04 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 215740 kb
Host smart-6d8f9759-abdf-4ea4-ad4f-a949f0d10ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111223478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2111223478
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2102010518
Short name T188
Test name
Test status
Simulation time 1229926305 ps
CPU time 16 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:34 PM PDT 24
Peak memory 215392 kb
Host smart-8d169502-8c98-4fe6-8e27-a86c96fb3e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102010518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2102010518
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1864245777
Short name T1061
Test name
Test status
Simulation time 199239709 ps
CPU time 2.51 seconds
Started Jul 30 04:48:16 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 216992 kb
Host smart-fc4d5140-e535-4916-b9a8-a4babf4ee70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864245777 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1864245777
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1629771441
Short name T140
Test name
Test status
Simulation time 395342994 ps
CPU time 2.82 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 207152 kb
Host smart-7e955611-f033-4add-9c16-b6ab2635c8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629771441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1629771441
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3701183613
Short name T1052
Test name
Test status
Simulation time 12016792 ps
CPU time 0.76 seconds
Started Jul 30 04:48:27 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 203844 kb
Host smart-f1e26913-25e0-413f-b0f3-12e1a526624a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701183613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3701183613
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1618569995
Short name T1036
Test name
Test status
Simulation time 886589559 ps
CPU time 2.93 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:17 PM PDT 24
Peak memory 215368 kb
Host smart-a5bc8298-3f66-4bf7-a878-39f616d0a05e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618569995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1618569995
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3276425873
Short name T118
Test name
Test status
Simulation time 151801656 ps
CPU time 2.71 seconds
Started Jul 30 04:48:32 PM PDT 24
Finished Jul 30 04:48:35 PM PDT 24
Peak memory 215652 kb
Host smart-61d027a9-6945-4faf-9319-d118c7447fce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276425873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3276425873
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2833736941
Short name T186
Test name
Test status
Simulation time 517806849 ps
CPU time 12.12 seconds
Started Jul 30 04:48:16 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 215428 kb
Host smart-48a21829-74bb-4178-8a52-f7302f28c0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833736941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2833736941
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3428007665
Short name T1103
Test name
Test status
Simulation time 39864446 ps
CPU time 2.94 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 216688 kb
Host smart-478e53b6-717b-47d5-812f-3bdc1bdd0932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428007665 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3428007665
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.949225451
Short name T132
Test name
Test status
Simulation time 54916935 ps
CPU time 1.84 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 215336 kb
Host smart-41df3853-5006-4b28-abe4-defd2f5c1e46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949225451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.949225451
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1138895181
Short name T1070
Test name
Test status
Simulation time 12519839 ps
CPU time 0.68 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:25 PM PDT 24
Peak memory 204156 kb
Host smart-f63fa1bc-6245-4f2d-acbb-93eed8caed93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138895181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1138895181
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3508587165
Short name T1097
Test name
Test status
Simulation time 99452663 ps
CPU time 1.71 seconds
Started Jul 30 04:48:10 PM PDT 24
Finished Jul 30 04:48:12 PM PDT 24
Peak memory 207164 kb
Host smart-f6ead43b-3529-400b-a6de-e988ba2e920a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508587165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3508587165
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4171774730
Short name T122
Test name
Test status
Simulation time 615483300 ps
CPU time 3.99 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 215652 kb
Host smart-b2a3bc15-10cb-4367-b044-786868699c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171774730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4171774730
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2412294449
Short name T1059
Test name
Test status
Simulation time 98433903 ps
CPU time 2.83 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 217672 kb
Host smart-b1f5e1fa-351f-45dc-84af-6b7355ccc892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412294449 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2412294449
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3208713901
Short name T160
Test name
Test status
Simulation time 129392337 ps
CPU time 1.33 seconds
Started Jul 30 04:48:16 PM PDT 24
Finished Jul 30 04:48:17 PM PDT 24
Peak memory 215448 kb
Host smart-3174611e-66a7-40ec-b8b6-69c3865e4fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208713901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3208713901
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.476266447
Short name T1127
Test name
Test status
Simulation time 26877385 ps
CPU time 0.76 seconds
Started Jul 30 04:48:23 PM PDT 24
Finished Jul 30 04:48:24 PM PDT 24
Peak memory 204244 kb
Host smart-a138a038-d1fe-4645-9fbf-52e2f863ce4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476266447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.476266447
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1981208895
Short name T1121
Test name
Test status
Simulation time 57897931 ps
CPU time 3.11 seconds
Started Jul 30 04:48:09 PM PDT 24
Finished Jul 30 04:48:13 PM PDT 24
Peak memory 215900 kb
Host smart-b7ee7695-28d2-493a-ab3f-aa28a8d67f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981208895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1981208895
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3209700240
Short name T1105
Test name
Test status
Simulation time 299354733 ps
CPU time 4.76 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 215700 kb
Host smart-2e808b8d-8449-4fa8-bf02-6e0a901ad48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209700240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3209700240
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1724423743
Short name T191
Test name
Test status
Simulation time 1170864282 ps
CPU time 7.86 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 215556 kb
Host smart-482a789b-3fd8-4861-b7e4-8d131614e055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724423743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1724423743
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1878303716
Short name T168
Test name
Test status
Simulation time 53281176 ps
CPU time 1.64 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:15 PM PDT 24
Peak memory 215468 kb
Host smart-f724c011-20d6-4026-ad2c-d5ac4e58f60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878303716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1878303716
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2994842982
Short name T141
Test name
Test status
Simulation time 131645885 ps
CPU time 3.07 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:32 PM PDT 24
Peak memory 215320 kb
Host smart-0ea27011-b9a6-43a3-957b-52be92a4d591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994842982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2994842982
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3260436531
Short name T1030
Test name
Test status
Simulation time 16223409 ps
CPU time 0.67 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 203840 kb
Host smart-6da150ce-71d6-4177-b191-e62831111450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260436531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3260436531
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.515502054
Short name T1075
Test name
Test status
Simulation time 232985631 ps
CPU time 4.02 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 215472 kb
Host smart-0171ceaf-4abc-487b-80bd-65c12a35b5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515502054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.515502054
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.925568230
Short name T187
Test name
Test status
Simulation time 631096647 ps
CPU time 21.57 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:46 PM PDT 24
Peak memory 215380 kb
Host smart-e73a6893-5d75-46d2-ba67-c05e6a9de280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925568230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.925568230
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2383613283
Short name T134
Test name
Test status
Simulation time 5676351053 ps
CPU time 23.47 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 215464 kb
Host smart-2adf5e15-f164-4fe1-bea4-d9de30dc433f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383613283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2383613283
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1421196751
Short name T1041
Test name
Test status
Simulation time 5015098947 ps
CPU time 24.03 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:44 PM PDT 24
Peak memory 207264 kb
Host smart-0e295d38-d43d-49c7-a828-a8dded2f8add
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421196751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1421196751
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.523712255
Short name T97
Test name
Test status
Simulation time 91130377 ps
CPU time 1.42 seconds
Started Jul 30 04:48:10 PM PDT 24
Finished Jul 30 04:48:12 PM PDT 24
Peak memory 207248 kb
Host smart-82388a03-352b-4c33-a0f6-76ffeadfa05f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523712255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.523712255
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4104826727
Short name T1060
Test name
Test status
Simulation time 187449468 ps
CPU time 1.87 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 216572 kb
Host smart-b252e266-120e-4e96-b9be-06d82a9569c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104826727 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4104826727
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.215402209
Short name T1147
Test name
Test status
Simulation time 34774819 ps
CPU time 2.12 seconds
Started Jul 30 04:48:01 PM PDT 24
Finished Jul 30 04:48:03 PM PDT 24
Peak memory 215436 kb
Host smart-0a2b9a4c-f55f-46eb-be31-6a1be4eb23a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215402209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.215402209
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1755489503
Short name T1076
Test name
Test status
Simulation time 13191515 ps
CPU time 0.73 seconds
Started Jul 30 04:48:10 PM PDT 24
Finished Jul 30 04:48:11 PM PDT 24
Peak memory 203848 kb
Host smart-dcd3862e-e3a3-42e6-8b5c-d2ae4d98a7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755489503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
755489503
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3019248043
Short name T135
Test name
Test status
Simulation time 78510011 ps
CPU time 1.69 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 215392 kb
Host smart-dcb0b95f-d57e-4eb8-890d-4266c9e0ca2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019248043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3019248043
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.913448881
Short name T1044
Test name
Test status
Simulation time 15223403 ps
CPU time 0.68 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:15 PM PDT 24
Peak memory 203872 kb
Host smart-954cdc31-3aa8-4f66-a378-185ad341b0c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913448881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.913448881
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3240260721
Short name T1042
Test name
Test status
Simulation time 46993091 ps
CPU time 2.97 seconds
Started Jul 30 04:48:09 PM PDT 24
Finished Jul 30 04:48:13 PM PDT 24
Peak memory 215356 kb
Host smart-8d4e02c2-49bb-47c2-aac0-c1e4e466c4af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240260721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3240260721
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1028953426
Short name T1141
Test name
Test status
Simulation time 723656920 ps
CPU time 4.31 seconds
Started Jul 30 04:48:12 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 215648 kb
Host smart-a8bb1ece-70a2-469d-bbda-1afa8a830036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028953426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
028953426
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2461231408
Short name T190
Test name
Test status
Simulation time 930390139 ps
CPU time 14.01 seconds
Started Jul 30 04:48:06 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 215648 kb
Host smart-8fd6624b-5e61-44ba-a189-7d8aa2435c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461231408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2461231408
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1705388976
Short name T1092
Test name
Test status
Simulation time 49117968 ps
CPU time 0.73 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 204164 kb
Host smart-8b3451a9-0961-4e55-a477-d8617a6e24b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705388976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1705388976
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1226285669
Short name T1082
Test name
Test status
Simulation time 32292030 ps
CPU time 0.77 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 203860 kb
Host smart-cccf24d8-5175-48ea-9c3e-ce865440e3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226285669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1226285669
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.124676772
Short name T1088
Test name
Test status
Simulation time 16267765 ps
CPU time 0.77 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 204248 kb
Host smart-ab313655-229a-4865-bcee-81b3f7aa206e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124676772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.124676772
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1493094000
Short name T1033
Test name
Test status
Simulation time 52120451 ps
CPU time 0.78 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 203852 kb
Host smart-0197a0a7-1e6c-49e9-9a4c-72e08c7e6c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493094000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1493094000
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3609260013
Short name T1072
Test name
Test status
Simulation time 15313863 ps
CPU time 0.74 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 204212 kb
Host smart-cfc5265f-68a0-4ace-9278-3231c9553fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609260013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3609260013
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3824260537
Short name T1149
Test name
Test status
Simulation time 14277701 ps
CPU time 0.77 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 203868 kb
Host smart-64396f33-1f40-49b7-b75c-40c2a4f101fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824260537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3824260537
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.459205591
Short name T1038
Test name
Test status
Simulation time 32656416 ps
CPU time 0.68 seconds
Started Jul 30 04:48:18 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 204236 kb
Host smart-d7f293f0-123b-4a1c-a177-bc3463227f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459205591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.459205591
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.17799124
Short name T1133
Test name
Test status
Simulation time 61547224 ps
CPU time 0.74 seconds
Started Jul 30 04:48:43 PM PDT 24
Finished Jul 30 04:48:43 PM PDT 24
Peak memory 203808 kb
Host smart-25f47cd0-4c59-41b5-81f6-44a8f72603a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17799124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.17799124
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3205795170
Short name T1104
Test name
Test status
Simulation time 11747590 ps
CPU time 0.72 seconds
Started Jul 30 04:48:24 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 203844 kb
Host smart-b788701a-5b12-46fc-be09-e9b6d9d8e8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205795170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3205795170
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1928427057
Short name T1028
Test name
Test status
Simulation time 31620137 ps
CPU time 0.72 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 203920 kb
Host smart-cc56a24d-5821-4d93-ae9b-f70318ed4678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928427057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1928427057
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3985518737
Short name T1134
Test name
Test status
Simulation time 116378411 ps
CPU time 7.56 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:15 PM PDT 24
Peak memory 207276 kb
Host smart-de84b5fa-1ecc-4c26-80a5-d231ace48e8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985518737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3985518737
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1535719501
Short name T1146
Test name
Test status
Simulation time 3273409939 ps
CPU time 13.47 seconds
Started Jul 30 04:48:11 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 207360 kb
Host smart-06293676-de6d-42b6-8ff8-b2c730466e6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535719501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1535719501
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.340033215
Short name T1140
Test name
Test status
Simulation time 208608292 ps
CPU time 1.84 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:07 PM PDT 24
Peak memory 216420 kb
Host smart-0601a83e-8227-4bc3-990d-12be8710fefe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340033215 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.340033215
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2567365911
Short name T1045
Test name
Test status
Simulation time 37273739 ps
CPU time 1.41 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 207112 kb
Host smart-8dfb4ae7-1a2a-4957-bce6-4a514d7d7ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567365911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
567365911
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3139983436
Short name T1053
Test name
Test status
Simulation time 25510906 ps
CPU time 0.78 seconds
Started Jul 30 04:48:13 PM PDT 24
Finished Jul 30 04:48:14 PM PDT 24
Peak memory 203892 kb
Host smart-70530d00-a5d7-44a6-994f-033156146b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139983436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
139983436
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3920683380
Short name T1102
Test name
Test status
Simulation time 27525220 ps
CPU time 1.82 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 215516 kb
Host smart-415f0b40-9928-47a1-9a49-4a2d2f0af14a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920683380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3920683380
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.701419923
Short name T1037
Test name
Test status
Simulation time 21316943 ps
CPU time 0.66 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 203724 kb
Host smart-18478fa2-11bf-4727-986b-49b98bea9424
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701419923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.701419923
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4019874948
Short name T1046
Test name
Test status
Simulation time 611736028 ps
CPU time 4.26 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 215484 kb
Host smart-dab52d90-b550-4f84-886b-c1472f2bc550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019874948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4019874948
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1339033168
Short name T121
Test name
Test status
Simulation time 68514033 ps
CPU time 2.1 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:09 PM PDT 24
Peak memory 215692 kb
Host smart-5469fc20-45cd-4b69-9bbc-574306e09d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339033168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
339033168
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3383313805
Short name T1047
Test name
Test status
Simulation time 46826204 ps
CPU time 0.72 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 204232 kb
Host smart-7c473014-99fa-47fa-af2a-126801c3860b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383313805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3383313805
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2202292127
Short name T1091
Test name
Test status
Simulation time 29634312 ps
CPU time 0.8 seconds
Started Jul 30 04:48:25 PM PDT 24
Finished Jul 30 04:48:26 PM PDT 24
Peak memory 203916 kb
Host smart-b21876dd-4436-408d-9f91-5627671c1371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202292127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2202292127
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1227712100
Short name T1062
Test name
Test status
Simulation time 36909689 ps
CPU time 0.71 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 203848 kb
Host smart-f7f24934-9644-4230-b2cd-ef96fceb3358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227712100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1227712100
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1873021809
Short name T1083
Test name
Test status
Simulation time 13523491 ps
CPU time 0.73 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 203868 kb
Host smart-d8681857-60e9-4d7b-8a96-08eae67448e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873021809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1873021809
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4147424704
Short name T1136
Test name
Test status
Simulation time 30457652 ps
CPU time 0.77 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 204244 kb
Host smart-fd92d1d5-2acf-4244-9296-e211051dc4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147424704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4147424704
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2433500542
Short name T1065
Test name
Test status
Simulation time 27032544 ps
CPU time 0.76 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 203884 kb
Host smart-56e7014b-8e18-46a2-840b-22fbae4c58d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433500542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2433500542
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.756525194
Short name T1049
Test name
Test status
Simulation time 65491091 ps
CPU time 0.76 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 203916 kb
Host smart-52e6ad51-a7d7-40ea-b33d-74a58dee574c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756525194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.756525194
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.170810366
Short name T1128
Test name
Test status
Simulation time 15852262 ps
CPU time 0.69 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 203872 kb
Host smart-2ab69506-33db-486b-8e4e-7201afd63e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170810366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.170810366
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1798253587
Short name T1031
Test name
Test status
Simulation time 13332282 ps
CPU time 0.68 seconds
Started Jul 30 04:48:27 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 203908 kb
Host smart-e80e34ff-2f2c-4777-9b7a-7be1b458ba30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798253587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1798253587
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3866154593
Short name T1138
Test name
Test status
Simulation time 26649787 ps
CPU time 0.69 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 204200 kb
Host smart-97393e90-2c42-4e4b-8798-c5f57a4875b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866154593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3866154593
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.660179475
Short name T1043
Test name
Test status
Simulation time 322606067 ps
CPU time 8.55 seconds
Started Jul 30 04:48:11 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 207172 kb
Host smart-700eda6c-eded-4b72-b8ba-fba45e284950
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660179475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.660179475
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3211140977
Short name T1132
Test name
Test status
Simulation time 1727059092 ps
CPU time 24.52 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:39 PM PDT 24
Peak memory 215396 kb
Host smart-44920a5d-53c5-474d-b0aa-d33329fe018d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211140977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3211140977
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1913286349
Short name T1087
Test name
Test status
Simulation time 18508514 ps
CPU time 0.99 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:04 PM PDT 24
Peak memory 206780 kb
Host smart-4e2f9541-2ce0-4d12-984e-fa0e23718afd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913286349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1913286349
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3740708020
Short name T1056
Test name
Test status
Simulation time 266185316 ps
CPU time 3.98 seconds
Started Jul 30 04:48:10 PM PDT 24
Finished Jul 30 04:48:14 PM PDT 24
Peak memory 216588 kb
Host smart-34f496ca-77ba-4550-abad-6873ea9cac12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740708020 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3740708020
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.757320882
Short name T1126
Test name
Test status
Simulation time 79796754 ps
CPU time 1.47 seconds
Started Jul 30 04:48:08 PM PDT 24
Finished Jul 30 04:48:10 PM PDT 24
Peak memory 215404 kb
Host smart-b695a199-c6ca-4308-9425-74af6f116b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757320882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.757320882
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3069593954
Short name T1085
Test name
Test status
Simulation time 37437506 ps
CPU time 0.74 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:04 PM PDT 24
Peak memory 204172 kb
Host smart-f7b755fd-90b2-4ef3-b95b-247af545109d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069593954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
069593954
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2000614340
Short name T138
Test name
Test status
Simulation time 50797756 ps
CPU time 1.22 seconds
Started Jul 30 04:48:01 PM PDT 24
Finished Jul 30 04:48:03 PM PDT 24
Peak memory 215432 kb
Host smart-02ebf854-2f71-4e9d-a2fc-764cc5c119bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000614340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2000614340
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3176912694
Short name T1124
Test name
Test status
Simulation time 12319245 ps
CPU time 0.77 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:06 PM PDT 24
Peak memory 203792 kb
Host smart-31e73ce9-a5b0-4520-8056-ae2bf4edb0aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176912694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3176912694
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2471087109
Short name T1055
Test name
Test status
Simulation time 299262326 ps
CPU time 1.93 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 215364 kb
Host smart-d611f709-e388-4557-b24a-5c84a81d4b49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471087109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2471087109
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2163810672
Short name T124
Test name
Test status
Simulation time 271965860 ps
CPU time 6.16 seconds
Started Jul 30 04:48:12 PM PDT 24
Finished Jul 30 04:48:18 PM PDT 24
Peak memory 215640 kb
Host smart-6c785cda-a01f-4ade-931b-10c7fbd1de6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163810672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
163810672
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3714894672
Short name T109
Test name
Test status
Simulation time 1288726545 ps
CPU time 8.38 seconds
Started Jul 30 04:48:11 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 215484 kb
Host smart-545eb82a-7e1f-4e41-95d3-8ef47c111c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714894672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3714894672
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.222211454
Short name T1069
Test name
Test status
Simulation time 14766631 ps
CPU time 0.75 seconds
Started Jul 30 04:48:30 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 203872 kb
Host smart-5d8aaf7c-a5a2-4a90-a722-13bf4a5bf33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222211454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.222211454
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4079987910
Short name T1079
Test name
Test status
Simulation time 18046506 ps
CPU time 0.78 seconds
Started Jul 30 04:48:17 PM PDT 24
Finished Jul 30 04:48:18 PM PDT 24
Peak memory 203876 kb
Host smart-a6fb1a39-9643-414f-936d-4d884baf41db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079987910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4079987910
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1541710242
Short name T1035
Test name
Test status
Simulation time 20148800 ps
CPU time 0.71 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 204228 kb
Host smart-120e6ca0-7c3b-4f87-a216-37712bfc2e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541710242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1541710242
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.386535007
Short name T1040
Test name
Test status
Simulation time 15915135 ps
CPU time 0.71 seconds
Started Jul 30 04:48:20 PM PDT 24
Finished Jul 30 04:48:21 PM PDT 24
Peak memory 203912 kb
Host smart-c6ab8c4b-3d5e-4865-aea3-1254b5361244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386535007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.386535007
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2049243936
Short name T1054
Test name
Test status
Simulation time 53143653 ps
CPU time 0.7 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 203876 kb
Host smart-c47a5fb1-cb94-4594-95be-9b0fca3b5346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049243936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2049243936
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2088087314
Short name T1148
Test name
Test status
Simulation time 37202003 ps
CPU time 0.69 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 203912 kb
Host smart-d9ae45e2-f4a3-4bf5-857c-5b76d7c44eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088087314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2088087314
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1129177508
Short name T1111
Test name
Test status
Simulation time 11979030 ps
CPU time 0.69 seconds
Started Jul 30 04:48:36 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 203868 kb
Host smart-432ab458-65cf-4f2c-a97c-f520a3a58b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129177508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1129177508
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1766594354
Short name T1048
Test name
Test status
Simulation time 15751515 ps
CPU time 0.76 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:22 PM PDT 24
Peak memory 204196 kb
Host smart-9c89d113-495d-40e0-8718-2a70a48465ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766594354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1766594354
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2734008949
Short name T1034
Test name
Test status
Simulation time 67608374 ps
CPU time 0.74 seconds
Started Jul 30 04:48:31 PM PDT 24
Finished Jul 30 04:48:37 PM PDT 24
Peak memory 203908 kb
Host smart-e65c0f70-5c2d-432d-ac49-4afc83c73c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734008949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2734008949
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.836829160
Short name T1027
Test name
Test status
Simulation time 13569279 ps
CPU time 0.71 seconds
Started Jul 30 04:48:27 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 203852 kb
Host smart-e3ecaa02-9f78-4976-bef7-b5fa7dc239fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836829160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.836829160
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.63914414
Short name T1071
Test name
Test status
Simulation time 133603762 ps
CPU time 3.78 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:39 PM PDT 24
Peak memory 217292 kb
Host smart-42c76631-ac6d-4b79-9413-14df405439ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63914414 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.63914414
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2619382755
Short name T1125
Test name
Test status
Simulation time 57405072 ps
CPU time 2 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:17 PM PDT 24
Peak memory 215420 kb
Host smart-a9f446f1-292f-4e90-b456-4d5d64a69a9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619382755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
619382755
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3992768365
Short name T1050
Test name
Test status
Simulation time 31619031 ps
CPU time 0.73 seconds
Started Jul 30 04:48:04 PM PDT 24
Finished Jul 30 04:48:05 PM PDT 24
Peak memory 203900 kb
Host smart-2ca9ad85-9e86-4954-b16a-81b0992ee5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992768365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
992768365
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.423723014
Short name T1096
Test name
Test status
Simulation time 202623261 ps
CPU time 4.44 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:19 PM PDT 24
Peak memory 215896 kb
Host smart-d01e2143-50bd-4623-99ea-030024d005df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423723014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.423723014
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1479385172
Short name T111
Test name
Test status
Simulation time 725585095 ps
CPU time 18.6 seconds
Started Jul 30 04:48:16 PM PDT 24
Finished Jul 30 04:48:39 PM PDT 24
Peak memory 215956 kb
Host smart-5d478b6e-15c1-405b-a0ab-c321247f097f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479385172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1479385172
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1479276390
Short name T116
Test name
Test status
Simulation time 150305619 ps
CPU time 3.95 seconds
Started Jul 30 04:48:21 PM PDT 24
Finished Jul 30 04:48:25 PM PDT 24
Peak memory 217792 kb
Host smart-e02b7ba2-24fd-48c5-bdce-ef088a61cfa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479276390 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1479276390
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2262159474
Short name T1074
Test name
Test status
Simulation time 41420570 ps
CPU time 1.49 seconds
Started Jul 30 04:48:14 PM PDT 24
Finished Jul 30 04:48:16 PM PDT 24
Peak memory 215404 kb
Host smart-6a7fa2c9-2c58-46c5-b88c-22a7857ac0d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262159474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
262159474
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1986510772
Short name T1089
Test name
Test status
Simulation time 65482591 ps
CPU time 0.73 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 204236 kb
Host smart-50aae946-2fca-4c33-906c-73df66133fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986510772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
986510772
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2197881067
Short name T1078
Test name
Test status
Simulation time 150782144 ps
CPU time 3.84 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:11 PM PDT 24
Peak memory 215324 kb
Host smart-950996a5-e386-473d-9cb4-0486dc54ba15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197881067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2197881067
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.388960070
Short name T119
Test name
Test status
Simulation time 122874123 ps
CPU time 3.31 seconds
Started Jul 30 04:48:10 PM PDT 24
Finished Jul 30 04:48:13 PM PDT 24
Peak memory 215656 kb
Host smart-40afc680-bc1a-43a5-8b56-ee8151dd0f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388960070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.388960070
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2775161651
Short name T1139
Test name
Test status
Simulation time 115411110 ps
CPU time 7.35 seconds
Started Jul 30 04:48:15 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 215288 kb
Host smart-e85c42c4-5a7b-4537-a399-c8c2a5acaf19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775161651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2775161651
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1405224192
Short name T1099
Test name
Test status
Simulation time 642913466 ps
CPU time 2.76 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 216496 kb
Host smart-5a7ba128-f49f-40ad-8efb-ec220f092e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405224192 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1405224192
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1244237231
Short name T1107
Test name
Test status
Simulation time 41787102 ps
CPU time 2.42 seconds
Started Jul 30 04:48:29 PM PDT 24
Finished Jul 30 04:48:31 PM PDT 24
Peak memory 215352 kb
Host smart-e5f11302-e0da-467e-a596-150e54581afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244237231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
244237231
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2699951030
Short name T1029
Test name
Test status
Simulation time 15001623 ps
CPU time 0.72 seconds
Started Jul 30 04:48:06 PM PDT 24
Finished Jul 30 04:48:07 PM PDT 24
Peak memory 203784 kb
Host smart-fe6968b8-f37d-4c33-83a1-fd05c307b1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699951030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
699951030
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3938649635
Short name T1119
Test name
Test status
Simulation time 269789380 ps
CPU time 1.88 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:24 PM PDT 24
Peak memory 215372 kb
Host smart-10942387-9271-4804-a13a-44fa50491947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938649635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3938649635
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1262623213
Short name T1095
Test name
Test status
Simulation time 759805501 ps
CPU time 4.74 seconds
Started Jul 30 04:48:03 PM PDT 24
Finished Jul 30 04:48:08 PM PDT 24
Peak memory 215676 kb
Host smart-11726311-f904-49f5-9eb0-9ddf8d3e6cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262623213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
262623213
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3305542675
Short name T1115
Test name
Test status
Simulation time 560561242 ps
CPU time 7.24 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:13 PM PDT 24
Peak memory 215788 kb
Host smart-2b211cf6-2569-41ed-925a-6f58fa135165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305542675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3305542675
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2234587608
Short name T1084
Test name
Test status
Simulation time 82812011 ps
CPU time 1.6 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 215428 kb
Host smart-0eddd83a-356d-46d6-a4c1-11cc1281da37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234587608 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2234587608
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.677041661
Short name T167
Test name
Test status
Simulation time 184870434 ps
CPU time 1.43 seconds
Started Jul 30 04:48:39 PM PDT 24
Finished Jul 30 04:48:40 PM PDT 24
Peak memory 207228 kb
Host smart-04061cd6-f451-4c59-b7cc-96c51013af4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677041661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.677041661
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2917315336
Short name T1086
Test name
Test status
Simulation time 54015745 ps
CPU time 0.91 seconds
Started Jul 30 04:48:09 PM PDT 24
Finished Jul 30 04:48:10 PM PDT 24
Peak memory 203932 kb
Host smart-e9f52e88-1836-4d90-9717-8c3e4bfdd47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917315336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
917315336
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.25948374
Short name T1120
Test name
Test status
Simulation time 142770861 ps
CPU time 3.11 seconds
Started Jul 30 04:48:07 PM PDT 24
Finished Jul 30 04:48:10 PM PDT 24
Peak memory 215488 kb
Host smart-3fe34563-30b8-4ba5-aae0-5696c6dbc5fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi
_device_same_csr_outstanding.25948374
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2091747066
Short name T1090
Test name
Test status
Simulation time 128057663 ps
CPU time 5.35 seconds
Started Jul 30 04:48:22 PM PDT 24
Finished Jul 30 04:48:28 PM PDT 24
Peak memory 215592 kb
Host smart-115cf50f-6da5-417e-879a-3a0466a0758e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091747066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
091747066
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1797372221
Short name T129
Test name
Test status
Simulation time 1390232795 ps
CPU time 7.75 seconds
Started Jul 30 04:48:12 PM PDT 24
Finished Jul 30 04:48:20 PM PDT 24
Peak memory 215916 kb
Host smart-eb9a50f9-0a85-4405-8c41-db67d7c05b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797372221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1797372221
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.917893403
Short name T1151
Test name
Test status
Simulation time 427811472 ps
CPU time 1.79 seconds
Started Jul 30 04:48:16 PM PDT 24
Finished Jul 30 04:48:23 PM PDT 24
Peak memory 215376 kb
Host smart-4c348d46-92f8-4bd6-8608-04f1870e3f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917893403 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.917893403
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.487169563
Short name T1101
Test name
Test status
Simulation time 324172946 ps
CPU time 2.88 seconds
Started Jul 30 04:48:24 PM PDT 24
Finished Jul 30 04:48:27 PM PDT 24
Peak memory 215444 kb
Host smart-6475f454-43d4-4240-a03a-ca07ed35360f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487169563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.487169563
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.331680280
Short name T1142
Test name
Test status
Simulation time 44156487 ps
CPU time 0.74 seconds
Started Jul 30 04:48:28 PM PDT 24
Finished Jul 30 04:48:29 PM PDT 24
Peak memory 203820 kb
Host smart-e13de206-a89d-4282-86be-7b0f1a21b107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331680280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.331680280
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1771461115
Short name T1135
Test name
Test status
Simulation time 170689358 ps
CPU time 5.96 seconds
Started Jul 30 04:48:05 PM PDT 24
Finished Jul 30 04:48:11 PM PDT 24
Peak memory 215324 kb
Host smart-6db97bad-e6e9-4f62-8515-f136f168f72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771461115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1771461115
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1434450059
Short name T123
Test name
Test status
Simulation time 70159214 ps
CPU time 4.29 seconds
Started Jul 30 04:48:26 PM PDT 24
Finished Jul 30 04:48:30 PM PDT 24
Peak memory 215672 kb
Host smart-bcb8e5c1-6b59-422c-83ae-8647446ffdef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434450059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
434450059
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3008861620
Short name T128
Test name
Test status
Simulation time 1161967261 ps
CPU time 19.44 seconds
Started Jul 30 04:48:19 PM PDT 24
Finished Jul 30 04:48:38 PM PDT 24
Peak memory 215484 kb
Host smart-0040d4db-1766-4c96-a93e-7faedd5f1f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008861620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3008861620
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1208170204
Short name T475
Test name
Test status
Simulation time 12285425 ps
CPU time 0.71 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 205232 kb
Host smart-ddc646b3-5802-4479-af48-4e1d1d7d34e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208170204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
208170204
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1263264470
Short name T711
Test name
Test status
Simulation time 223240259 ps
CPU time 2.98 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 225128 kb
Host smart-21a081a5-45f6-4dc5-9f66-9656b4b6b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263264470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1263264470
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.845177313
Short name T66
Test name
Test status
Simulation time 17029536 ps
CPU time 0.74 seconds
Started Jul 30 04:48:35 PM PDT 24
Finished Jul 30 04:48:36 PM PDT 24
Peak memory 206244 kb
Host smart-237bf446-6691-4da5-9265-d28a1cd18959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845177313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.845177313
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2511685371
Short name T260
Test name
Test status
Simulation time 3594859904 ps
CPU time 26.12 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 223968 kb
Host smart-741f2aa9-f813-4ee0-9731-515dcf791e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511685371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2511685371
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.593721742
Short name T542
Test name
Test status
Simulation time 41232468618 ps
CPU time 91.27 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 249888 kb
Host smart-e084e126-5e2e-4bef-8bb6-8f8d566bcac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593721742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.593721742
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3982296732
Short name T562
Test name
Test status
Simulation time 159726915 ps
CPU time 3.49 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 225216 kb
Host smart-7cd73af0-5bc7-4f26-a39e-858f0c3038ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982296732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3982296732
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1326083226
Short name T108
Test name
Test status
Simulation time 169952369157 ps
CPU time 179.36 seconds
Started Jul 30 04:48:38 PM PDT 24
Finished Jul 30 04:51:38 PM PDT 24
Peak memory 249884 kb
Host smart-2c27c5bc-1522-4532-9681-2a4350e60f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326083226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1326083226
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4170392871
Short name T224
Test name
Test status
Simulation time 3593324168 ps
CPU time 31.14 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:49:21 PM PDT 24
Peak memory 233412 kb
Host smart-83b9a7e3-82ea-4d4d-9d71-e49c5860fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170392871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4170392871
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2244528676
Short name T903
Test name
Test status
Simulation time 149337854 ps
CPU time 3.6 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:48:49 PM PDT 24
Peak memory 225120 kb
Host smart-85757c1e-e3d9-483a-b1fc-8d739f6f5eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244528676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2244528676
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2964469086
Short name T766
Test name
Test status
Simulation time 2820904859 ps
CPU time 9.93 seconds
Started Jul 30 04:48:44 PM PDT 24
Finished Jul 30 04:48:54 PM PDT 24
Peak memory 233320 kb
Host smart-9f30ac31-e80c-4092-b8bd-fdee0214411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964469086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2964469086
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2718304785
Short name T904
Test name
Test status
Simulation time 10455886410 ps
CPU time 6.79 seconds
Started Jul 30 04:48:44 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 233460 kb
Host smart-8aa5d52a-0283-4a3c-b8ad-16a9d34bf849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718304785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2718304785
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2366052250
Short name T365
Test name
Test status
Simulation time 807846893 ps
CPU time 4.15 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 219748 kb
Host smart-d67b8cb2-fd1f-45f1-85c6-5728a5762f8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2366052250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2366052250
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2063886532
Short name T77
Test name
Test status
Simulation time 343010984 ps
CPU time 1.19 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 236936 kb
Host smart-c082192a-15fa-40d4-825e-a93f9cc6a9e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063886532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2063886532
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.824197553
Short name T890
Test name
Test status
Simulation time 109560564171 ps
CPU time 313.56 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:54:05 PM PDT 24
Peak memory 273612 kb
Host smart-4d9fd320-92b6-4986-8212-683e1a87effe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824197553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.824197553
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.933272332
Short name T738
Test name
Test status
Simulation time 935612724 ps
CPU time 12.45 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:07 PM PDT 24
Peak memory 219616 kb
Host smart-2ac1096f-2bc2-4938-8c33-27e70ef430eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933272332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.933272332
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.417780356
Short name T546
Test name
Test status
Simulation time 5107838107 ps
CPU time 15.62 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 216864 kb
Host smart-98438477-3273-45f6-8a4e-81cde883698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417780356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.417780356
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2961346794
Short name T325
Test name
Test status
Simulation time 146510411 ps
CPU time 1.59 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 216908 kb
Host smart-b1e1a581-e63c-40aa-8700-b59aefd4b485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961346794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2961346794
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3857058948
Short name T962
Test name
Test status
Simulation time 66531036 ps
CPU time 1.01 seconds
Started Jul 30 04:48:39 PM PDT 24
Finished Jul 30 04:48:40 PM PDT 24
Peak memory 206852 kb
Host smart-038e89e1-a012-43be-9cbc-59bba69726b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857058948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3857058948
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.98957274
Short name T463
Test name
Test status
Simulation time 670099181 ps
CPU time 3.3 seconds
Started Jul 30 04:48:55 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 225120 kb
Host smart-7e2340ce-99ca-404a-aa76-2b2470b81d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98957274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.98957274
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3937056031
Short name T659
Test name
Test status
Simulation time 67761493 ps
CPU time 0.7 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 206060 kb
Host smart-fc58bdcb-3896-4537-9e3a-f50ec3fb0bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937056031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
937056031
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1605607794
Short name T798
Test name
Test status
Simulation time 1259710378 ps
CPU time 7.44 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 225132 kb
Host smart-c809835f-cebb-449b-ab90-6fc704d20cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605607794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1605607794
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3408719074
Short name T376
Test name
Test status
Simulation time 35306919 ps
CPU time 0.79 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:54 PM PDT 24
Peak memory 206920 kb
Host smart-77bac8c5-417f-4c12-b06f-9e28263f54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408719074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3408719074
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3850563560
Short name T875
Test name
Test status
Simulation time 2481050037 ps
CPU time 46.62 seconds
Started Jul 30 04:48:55 PM PDT 24
Finished Jul 30 04:49:42 PM PDT 24
Peak memory 253260 kb
Host smart-be92ad26-a467-425b-b7ec-c7d2765530d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850563560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3850563560
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.928336848
Short name T838
Test name
Test status
Simulation time 2868273564 ps
CPU time 55.54 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 254756 kb
Host smart-19e68a10-cbc3-4965-b28a-70879d0a3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928336848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.928336848
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2687713958
Short name T834
Test name
Test status
Simulation time 1615044174 ps
CPU time 4.56 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 218224 kb
Host smart-851ab2c1-11fd-4761-9768-d106cc34f106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687713958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2687713958
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3292262767
Short name T403
Test name
Test status
Simulation time 3240956691 ps
CPU time 12.41 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 225160 kb
Host smart-174f6c97-f195-4036-a3a5-295cbf11469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292262767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3292262767
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.366098124
Short name T287
Test name
Test status
Simulation time 44838187427 ps
CPU time 337.78 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:54:23 PM PDT 24
Peak memory 267184 kb
Host smart-f18f3496-cddb-4ec5-bfdc-cfe5c55a8ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366098124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
366098124
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.342511793
Short name T608
Test name
Test status
Simulation time 2689399073 ps
CPU time 17.67 seconds
Started Jul 30 04:48:36 PM PDT 24
Finished Jul 30 04:48:54 PM PDT 24
Peak memory 225252 kb
Host smart-6bc3d2f8-f3d6-4d55-9bb6-6d42ba414e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342511793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.342511793
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1586292485
Short name T519
Test name
Test status
Simulation time 32817070 ps
CPU time 1.18 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 217144 kb
Host smart-1ea2760d-afee-489e-92e9-c84f47d9ba82
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586292485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1586292485
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.120804362
Short name T291
Test name
Test status
Simulation time 2083110099 ps
CPU time 8.26 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:07 PM PDT 24
Peak memory 233328 kb
Host smart-cac651fc-def4-41dd-906d-b00fd64a1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120804362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
120804362
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3529473707
Short name T748
Test name
Test status
Simulation time 3194051158 ps
CPU time 6.27 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 225164 kb
Host smart-55b9a407-da32-482f-8bfc-fcd64f1ff956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529473707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3529473707
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2236915511
Short name T163
Test name
Test status
Simulation time 6095026279 ps
CPU time 9.51 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 220352 kb
Host smart-c58f43b9-b37f-49b3-9f16-ebddeb2d99ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236915511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2236915511
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2170760612
Short name T653
Test name
Test status
Simulation time 43876221 ps
CPU time 0.97 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 206248 kb
Host smart-4041b9d4-75f4-46cb-a9ae-48dea6ea0999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170760612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2170760612
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2613830185
Short name T936
Test name
Test status
Simulation time 8625104163 ps
CPU time 25.11 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 217000 kb
Host smart-596ce94c-2943-43df-874c-d9b140b85519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613830185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2613830185
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1226816450
Short name T737
Test name
Test status
Simulation time 8665924541 ps
CPU time 22.12 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 216932 kb
Host smart-990c73c2-ffde-406e-97bc-94a78350bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226816450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1226816450
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1644757066
Short name T830
Test name
Test status
Simulation time 560748009 ps
CPU time 3.02 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 216944 kb
Host smart-cfbdda39-700e-4645-b378-ff839469b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644757066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1644757066
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1032301990
Short name T898
Test name
Test status
Simulation time 187418015 ps
CPU time 0.89 seconds
Started Jul 30 04:48:51 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 207576 kb
Host smart-edc3886f-902b-4034-a686-3c1b8cf5fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032301990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1032301990
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1179453903
Short name T569
Test name
Test status
Simulation time 14619981508 ps
CPU time 15.33 seconds
Started Jul 30 04:48:45 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 233388 kb
Host smart-f6ea9dd1-8d9f-42b8-aa35-ec8ca497d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179453903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1179453903
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1083148353
Short name T749
Test name
Test status
Simulation time 53968093 ps
CPU time 0.68 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 206080 kb
Host smart-3eed6b78-b8e8-4372-aadb-26137ac7e6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083148353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1083148353
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.998399279
Short name T331
Test name
Test status
Simulation time 2395033128 ps
CPU time 4.1 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 225260 kb
Host smart-7f37cdb5-d387-4e37-b90c-09d9efd0da4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998399279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.998399279
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2150096365
Short name T333
Test name
Test status
Simulation time 14078799 ps
CPU time 0.79 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:14 PM PDT 24
Peak memory 206984 kb
Host smart-8608f044-0dac-4326-a8a2-8e40678f6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150096365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2150096365
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3581022210
Short name T554
Test name
Test status
Simulation time 42185413 ps
CPU time 0.76 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 216368 kb
Host smart-58dca2b5-4821-41cd-89f5-6f9eaf4a2446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581022210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3581022210
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1107409060
Short name T647
Test name
Test status
Simulation time 2727693916 ps
CPU time 63.05 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 257208 kb
Host smart-f434b2fb-d963-4542-a464-7ffc7454ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107409060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1107409060
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3892491136
Short name T193
Test name
Test status
Simulation time 32698199781 ps
CPU time 67.23 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 249804 kb
Host smart-6828f426-7b51-45d3-9dd4-c14c988fb98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892491136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3892491136
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4222202701
Short name T732
Test name
Test status
Simulation time 835378104 ps
CPU time 8.79 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 233404 kb
Host smart-0de410da-7cff-4d63-b204-850c545d066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222202701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4222202701
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2211247541
Short name T771
Test name
Test status
Simulation time 3324430119 ps
CPU time 22.04 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:35 PM PDT 24
Peak memory 233380 kb
Host smart-3f61d4b1-e27a-4cd8-9e39-0adba4c481af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211247541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2211247541
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.903203096
Short name T905
Test name
Test status
Simulation time 33398032 ps
CPU time 1.07 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 217096 kb
Host smart-2d521689-8547-46df-8113-d063484d68e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903203096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.903203096
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1092460432
Short name T85
Test name
Test status
Simulation time 3349082445 ps
CPU time 11.12 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 225168 kb
Host smart-0029673b-1e78-473f-9a43-6fe41b48083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092460432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1092460432
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.719367076
Short name T329
Test name
Test status
Simulation time 60601210 ps
CPU time 2.2 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 232940 kb
Host smart-7967e0a1-e4c0-4d33-b884-483de6b1013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719367076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.719367076
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4256473340
Short name T4
Test name
Test status
Simulation time 1501093806 ps
CPU time 16.31 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 219192 kb
Host smart-bd717052-2861-415e-a542-f35f98423430
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256473340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4256473340
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2400533032
Short name T435
Test name
Test status
Simulation time 6153519595 ps
CPU time 94.11 seconds
Started Jul 30 04:49:16 PM PDT 24
Finished Jul 30 04:50:50 PM PDT 24
Peak memory 254528 kb
Host smart-e5a0f6d7-d44d-4b88-a149-991ae70bde9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400533032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2400533032
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1037080367
Short name T797
Test name
Test status
Simulation time 2490609973 ps
CPU time 18.63 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 216976 kb
Host smart-1d867621-877a-48a4-88c4-f065cb76386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037080367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1037080367
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2704718532
Short name T591
Test name
Test status
Simulation time 24857857169 ps
CPU time 14.91 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:30 PM PDT 24
Peak memory 216916 kb
Host smart-8ae5452f-a1f6-4342-91a7-da73647285f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704718532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2704718532
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1683139620
Short name T54
Test name
Test status
Simulation time 434746937 ps
CPU time 4.19 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 216760 kb
Host smart-2cefa430-b0fb-4d98-8cd2-522a6987b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683139620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1683139620
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3503524067
Short name T578
Test name
Test status
Simulation time 14178048 ps
CPU time 0.75 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 206468 kb
Host smart-0b9e3b35-5438-49b9-aa0a-b6db25eb0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503524067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3503524067
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1621391263
Short name T541
Test name
Test status
Simulation time 37389234450 ps
CPU time 40.78 seconds
Started Jul 30 04:49:17 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 225236 kb
Host smart-41628230-efd3-44bd-9635-16ee85d5dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621391263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1621391263
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.443900015
Short name T482
Test name
Test status
Simulation time 41940583 ps
CPU time 0.73 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 206120 kb
Host smart-b5c38aed-7014-41d5-acc3-e3c11db7be3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443900015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.443900015
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.351330380
Short name T539
Test name
Test status
Simulation time 485630641 ps
CPU time 7.12 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 233276 kb
Host smart-69c957e5-9f3d-4afd-b597-e5ff48515be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351330380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.351330380
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.270088411
Short name T750
Test name
Test status
Simulation time 21022655 ps
CPU time 0.76 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 206968 kb
Host smart-2b635ad4-6244-4255-99dd-65368205ea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270088411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.270088411
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3157946711
Short name T934
Test name
Test status
Simulation time 23640348566 ps
CPU time 95.06 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:50:38 PM PDT 24
Peak memory 256576 kb
Host smart-86056882-3787-47f1-9b5f-20fe9d0803f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157946711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3157946711
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.392305201
Short name T222
Test name
Test status
Simulation time 37120872402 ps
CPU time 240.45 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:53:30 PM PDT 24
Peak memory 257920 kb
Host smart-df9f300d-d160-4023-9c4e-4bd3ba0317f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392305201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.392305201
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2217173308
Short name T462
Test name
Test status
Simulation time 121794615996 ps
CPU time 184.25 seconds
Started Jul 30 04:49:04 PM PDT 24
Finished Jul 30 04:52:08 PM PDT 24
Peak memory 257960 kb
Host smart-adfddc9c-f196-4335-82db-7331d4198a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217173308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2217173308
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.874581515
Short name T658
Test name
Test status
Simulation time 135006980 ps
CPU time 6.55 seconds
Started Jul 30 04:49:22 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 241528 kb
Host smart-55233965-8524-490f-9bb5-550b1b0851a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874581515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.874581515
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1867372243
Short name T194
Test name
Test status
Simulation time 7568796377 ps
CPU time 40.5 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 249776 kb
Host smart-59e74bf1-5b5d-4574-ac27-1bd1a24d6ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867372243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1867372243
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2855209574
Short name T233
Test name
Test status
Simulation time 658792200 ps
CPU time 6.1 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 233380 kb
Host smart-db6556a5-c971-4db6-b5e6-a39c6288df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855209574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2855209574
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1809943975
Short name T353
Test name
Test status
Simulation time 21148824511 ps
CPU time 30.31 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 225144 kb
Host smart-4b625094-a40c-4de2-aa29-f8fe9c10438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809943975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1809943975
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3222830628
Short name T818
Test name
Test status
Simulation time 45660913 ps
CPU time 0.98 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 217120 kb
Host smart-a930bcdf-727b-45fa-8211-fa97918f6061
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222830628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3222830628
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3781921576
Short name T813
Test name
Test status
Simulation time 8970594380 ps
CPU time 27.59 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 239708 kb
Host smart-9c2598de-9eb1-4102-8a70-836d16a970c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781921576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3781921576
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2494387547
Short name T39
Test name
Test status
Simulation time 368326422 ps
CPU time 4.4 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:10 PM PDT 24
Peak memory 222200 kb
Host smart-64c760e9-562f-4d11-a27d-8aeb22ae04cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2494387547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2494387547
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3259471611
Short name T820
Test name
Test status
Simulation time 10953785766 ps
CPU time 9.94 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 217040 kb
Host smart-a7941350-5d28-4433-b2f3-6dcb1e4dad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259471611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3259471611
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4180227003
Short name T971
Test name
Test status
Simulation time 3099572641 ps
CPU time 3.6 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 216992 kb
Host smart-ff91ffea-c042-4cfa-a184-76d8c04f8671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180227003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4180227003
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2035669828
Short name T741
Test name
Test status
Simulation time 1090113653 ps
CPU time 3 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 216848 kb
Host smart-5301e867-8093-4c4d-b369-4e24c231a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035669828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2035669828
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2188974605
Short name T552
Test name
Test status
Simulation time 33838693 ps
CPU time 0.85 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 206492 kb
Host smart-62afcdc0-6a9b-4d37-bf05-1778646e1cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188974605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2188974605
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2860222589
Short name T204
Test name
Test status
Simulation time 2228952130 ps
CPU time 12.25 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:35 PM PDT 24
Peak memory 233488 kb
Host smart-25b85f4c-9d8d-4576-bc81-5e3a4bd2baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860222589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2860222589
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2809273467
Short name T935
Test name
Test status
Simulation time 27687218 ps
CPU time 0.7 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 205156 kb
Host smart-dc8944f2-549c-4c17-b285-4db878f24f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809273467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2809273467
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3785130803
Short name T152
Test name
Test status
Simulation time 247100023 ps
CPU time 2.68 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:49:13 PM PDT 24
Peak memory 233352 kb
Host smart-94fc6b9a-f01d-4d76-bae4-9c2f7c9c88bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785130803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3785130803
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3517030241
Short name T145
Test name
Test status
Simulation time 18436680 ps
CPU time 0.77 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 207256 kb
Host smart-2eaf4b6b-8be6-4a0c-aaba-c052990b8547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517030241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3517030241
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3024868669
Short name T953
Test name
Test status
Simulation time 20502885 ps
CPU time 0.75 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 216352 kb
Host smart-99e7a439-ca27-4fc3-bc36-3bb28f95e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024868669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3024868669
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2645547404
Short name T484
Test name
Test status
Simulation time 2500617505 ps
CPU time 21 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 225204 kb
Host smart-72d511f2-30a8-4e7c-a8e4-3c3bcf023ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645547404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2645547404
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2770565447
Short name T1015
Test name
Test status
Simulation time 17185606217 ps
CPU time 79.21 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 257644 kb
Host smart-06d2c109-d38a-4085-89e3-67ebc072e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770565447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2770565447
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2366682601
Short name T221
Test name
Test status
Simulation time 2422813486 ps
CPU time 20.4 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:49:30 PM PDT 24
Peak memory 238560 kb
Host smart-93dd8930-b191-4bac-9f5e-aa1272344a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366682601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2366682601
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.635622582
Short name T841
Test name
Test status
Simulation time 133441147 ps
CPU time 3.44 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 225152 kb
Host smart-cec323ca-b0c9-4dc1-a04e-cc5b20d901dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635622582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.635622582
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1305617875
Short name T624
Test name
Test status
Simulation time 1636899234 ps
CPU time 19.69 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 225152 kb
Host smart-f91cbebe-38e7-4f5a-a540-a760d340515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305617875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1305617875
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3793809254
Short name T526
Test name
Test status
Simulation time 15191764 ps
CPU time 1.06 seconds
Started Jul 30 04:49:16 PM PDT 24
Finished Jul 30 04:49:17 PM PDT 24
Peak memory 217140 kb
Host smart-2e52971b-6115-48f8-98d1-6edb184edbf1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793809254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3793809254
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.741301516
Short name T213
Test name
Test status
Simulation time 27084313938 ps
CPU time 19.2 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:49:39 PM PDT 24
Peak memory 241176 kb
Host smart-314f12e5-8b48-42c9-97d8-057f5906fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741301516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.741301516
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.439030327
Short name T889
Test name
Test status
Simulation time 1085570311 ps
CPU time 5.5 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 225112 kb
Host smart-4020263c-d7cf-471a-a861-bcb9e6a23ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439030327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.439030327
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3302187676
Short name T916
Test name
Test status
Simulation time 849958344 ps
CPU time 3.7 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:49:14 PM PDT 24
Peak memory 219368 kb
Host smart-82643f6c-64ad-4c4a-bfdd-d7c2335e3ec0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3302187676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3302187676
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3381385563
Short name T16
Test name
Test status
Simulation time 180589542 ps
CPU time 0.94 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 207852 kb
Host smart-43dc1ba0-6f0f-4988-8573-c33c94559956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381385563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3381385563
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.513805754
Short name T316
Test name
Test status
Simulation time 3525569595 ps
CPU time 20.06 seconds
Started Jul 30 04:49:22 PM PDT 24
Finished Jul 30 04:49:43 PM PDT 24
Peak memory 217028 kb
Host smart-20c8b35d-d390-4768-8a1d-733ca48d58f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513805754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.513805754
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.406653681
Short name T938
Test name
Test status
Simulation time 12457081383 ps
CPU time 7.82 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:49:36 PM PDT 24
Peak memory 216956 kb
Host smart-cd873237-bab8-4e0f-b8f2-760066f53651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406653681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.406653681
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.70170298
Short name T68
Test name
Test status
Simulation time 712359575 ps
CPU time 7.11 seconds
Started Jul 30 04:49:17 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 216800 kb
Host smart-9eadfdfc-e33d-406b-be55-c22ba7d80e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70170298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.70170298
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_upload.3860268154
Short name T10
Test name
Test status
Simulation time 118934133 ps
CPU time 2.27 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:17 PM PDT 24
Peak memory 224692 kb
Host smart-15056852-d990-425f-a01c-734956c8996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860268154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3860268154
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2171989296
Short name T843
Test name
Test status
Simulation time 262296981 ps
CPU time 3.31 seconds
Started Jul 30 04:49:25 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 233236 kb
Host smart-a56a6fbc-3a2a-48d1-92e8-827797a981f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171989296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2171989296
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1860099875
Short name T844
Test name
Test status
Simulation time 21288199 ps
CPU time 0.78 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 207320 kb
Host smart-0b1b267e-f584-44ec-b94f-7d0d063f0d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860099875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1860099875
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2874594586
Short name T151
Test name
Test status
Simulation time 17524544075 ps
CPU time 141.48 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:51:32 PM PDT 24
Peak memory 254532 kb
Host smart-4588d899-b887-4fb7-997a-88c4b21f8a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874594586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2874594586
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2700357816
Short name T265
Test name
Test status
Simulation time 8790605870 ps
CPU time 125.19 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:51:34 PM PDT 24
Peak memory 255288 kb
Host smart-bc6390f0-8cbe-4862-bcda-e5b3dc77a249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700357816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2700357816
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2452382944
Short name T641
Test name
Test status
Simulation time 4182827760 ps
CPU time 45.9 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 249816 kb
Host smart-fe7e3c76-cc64-44d6-8a7e-4d6d8294a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452382944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2452382944
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3665418133
Short name T816
Test name
Test status
Simulation time 12024998867 ps
CPU time 26.44 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:41 PM PDT 24
Peak memory 239000 kb
Host smart-ab622266-ed07-4606-95a3-736f71b848e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665418133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3665418133
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4156188569
Short name T1003
Test name
Test status
Simulation time 110636395 ps
CPU time 2.6 seconds
Started Jul 30 04:49:16 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 233008 kb
Host smart-6f46b938-40bf-45d6-a9b6-781a3e439870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156188569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4156188569
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4126350663
Short name T275
Test name
Test status
Simulation time 20624053681 ps
CPU time 99.05 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:51:13 PM PDT 24
Peak memory 250812 kb
Host smart-5e0483d8-19c6-44be-a7a7-520da69a8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126350663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4126350663
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.410099025
Short name T404
Test name
Test status
Simulation time 17661725 ps
CPU time 1.03 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 217124 kb
Host smart-9f237d1d-0da6-437e-9405-2983b792b40e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410099025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.410099025
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2647503085
Short name T350
Test name
Test status
Simulation time 124223259 ps
CPU time 2.32 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 233332 kb
Host smart-4b9d1a65-4827-49e8-8a5a-67f04a1e160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647503085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2647503085
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1271293709
Short name T577
Test name
Test status
Simulation time 22597997858 ps
CPU time 14.92 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 233416 kb
Host smart-e02bb09f-0212-4919-9c7d-34b408bb5842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271293709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1271293709
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2824938265
Short name T508
Test name
Test status
Simulation time 253932470 ps
CPU time 3.35 seconds
Started Jul 30 04:49:16 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 219612 kb
Host smart-35362c43-1f7e-4f54-8b3b-b3fce65001c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824938265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2824938265
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2011255649
Short name T717
Test name
Test status
Simulation time 16407835993 ps
CPU time 96.39 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 250136 kb
Host smart-60d9eae3-f5e3-4fc7-a788-1580d704bf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011255649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2011255649
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2540725361
Short name T688
Test name
Test status
Simulation time 769899979 ps
CPU time 4.31 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 216924 kb
Host smart-1b357b86-fae4-4dc9-858b-321ad4180086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540725361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2540725361
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1159151911
Short name T586
Test name
Test status
Simulation time 13161495935 ps
CPU time 7.96 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:38 PM PDT 24
Peak memory 216912 kb
Host smart-f866e872-8135-4e73-9e91-05a641245ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159151911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1159151911
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4065303790
Short name T53
Test name
Test status
Simulation time 46514385 ps
CPU time 0.98 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:15 PM PDT 24
Peak memory 207612 kb
Host smart-b4750b23-b940-4b39-a20d-41d7a6526fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065303790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4065303790
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1715092241
Short name T23
Test name
Test status
Simulation time 114764696 ps
CPU time 0.83 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:49:21 PM PDT 24
Peak memory 206504 kb
Host smart-a03501ab-131d-4806-b9fb-f0129470b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715092241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1715092241
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.523804794
Short name T548
Test name
Test status
Simulation time 536843566 ps
CPU time 2.33 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:25 PM PDT 24
Peak memory 225104 kb
Host smart-7a7600be-f49f-48b0-8a07-aa64050cbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523804794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.523804794
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2578110189
Short name T602
Test name
Test status
Simulation time 45678795 ps
CPU time 0.72 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:15 PM PDT 24
Peak memory 205740 kb
Host smart-30a4c4b6-5cbf-4c3c-bb95-7c8a004c3cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578110189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2578110189
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3765259450
Short name T768
Test name
Test status
Simulation time 3797260517 ps
CPU time 13.21 seconds
Started Jul 30 04:49:43 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 233516 kb
Host smart-9276f858-8838-4838-bc37-291f8e03cde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765259450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3765259450
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1117232503
Short name T523
Test name
Test status
Simulation time 19471485 ps
CPU time 0.84 seconds
Started Jul 30 04:49:32 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 207292 kb
Host smart-9d604dc6-5a11-4689-8a39-dbf580591b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117232503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1117232503
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.316348693
Short name T631
Test name
Test status
Simulation time 10191948797 ps
CPU time 20.37 seconds
Started Jul 30 04:49:37 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 225256 kb
Host smart-eb783c08-8a6c-4bff-af85-d989d9ed708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316348693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.316348693
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.522983739
Short name T211
Test name
Test status
Simulation time 9028973275 ps
CPU time 56.96 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 255152 kb
Host smart-63267f0c-e43a-4c4e-9f63-a780ad96bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522983739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.522983739
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.528267822
Short name T643
Test name
Test status
Simulation time 14022137749 ps
CPU time 51.68 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 235672 kb
Host smart-c86962e8-32e5-47e8-ab88-96508772a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528267822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.528267822
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1118745163
Short name T84
Test name
Test status
Simulation time 78632101197 ps
CPU time 330.98 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:54:55 PM PDT 24
Peak memory 252732 kb
Host smart-203bfab8-6eef-46fe-a16b-1f5f350fc329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118745163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1118745163
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2479651998
Short name T491
Test name
Test status
Simulation time 1890718364 ps
CPU time 5.05 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:40 PM PDT 24
Peak memory 225244 kb
Host smart-7b5b5258-fb0f-47cd-a4b5-7a5a1164b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479651998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2479651998
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.857716120
Short name T654
Test name
Test status
Simulation time 7410427085 ps
CPU time 106.3 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 233476 kb
Host smart-19dbf25d-e184-4602-9fbe-2da146c0311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857716120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.857716120
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2372370721
Short name T970
Test name
Test status
Simulation time 86994220 ps
CPU time 1.11 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 217128 kb
Host smart-fa9c975e-e946-4696-94fc-bc769e8bda90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372370721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2372370721
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2823630273
Short name T678
Test name
Test status
Simulation time 15971236037 ps
CPU time 18.72 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 233344 kb
Host smart-c6390605-ff6d-43d4-a765-d036e85a0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823630273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2823630273
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3288844873
Short name T705
Test name
Test status
Simulation time 1576642687 ps
CPU time 12.19 seconds
Started Jul 30 04:49:25 PM PDT 24
Finished Jul 30 04:49:42 PM PDT 24
Peak memory 234720 kb
Host smart-306c02e9-cf47-4080-b2ef-76bb1926c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288844873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3288844873
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2601559302
Short name T791
Test name
Test status
Simulation time 631835537 ps
CPU time 3.76 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 219988 kb
Host smart-8398cfdf-289a-4a39-b74f-7d1f8bed5137
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2601559302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2601559302
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.290638534
Short name T931
Test name
Test status
Simulation time 220648655 ps
CPU time 0.96 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 207884 kb
Host smart-9f1b4c18-2e40-43c5-8e5c-b0c41f9c5339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290638534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.290638534
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1078032562
Short name T672
Test name
Test status
Simulation time 581908579 ps
CPU time 2.46 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 216976 kb
Host smart-862a282c-8606-45e7-bdb1-08ea3918a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078032562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1078032562
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1498641113
Short name T440
Test name
Test status
Simulation time 1482995695 ps
CPU time 6.66 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 216928 kb
Host smart-00483d3b-cd33-41ad-8c83-bad0808e3118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498641113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1498641113
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.769021178
Short name T346
Test name
Test status
Simulation time 47020400 ps
CPU time 1.88 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 216868 kb
Host smart-dac8c9f5-44c5-4e53-96f7-9b4dac17105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769021178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.769021178
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1313325996
Short name T726
Test name
Test status
Simulation time 76826244 ps
CPU time 0.8 seconds
Started Jul 30 04:49:22 PM PDT 24
Finished Jul 30 04:49:23 PM PDT 24
Peak memory 206512 kb
Host smart-4992cad1-fce0-4270-a570-ecc2aab9ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313325996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1313325996
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.862060501
Short name T226
Test name
Test status
Simulation time 6404846864 ps
CPU time 13.63 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 240964 kb
Host smart-717f6e55-8a12-44cc-aecb-aa8347294788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862060501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.862060501
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3539692734
Short name T555
Test name
Test status
Simulation time 131180315 ps
CPU time 0.75 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:38 PM PDT 24
Peak memory 205208 kb
Host smart-31dc6e67-1b2f-40dc-bf29-1d090dbc5262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539692734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3539692734
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1800741867
Short name T106
Test name
Test status
Simulation time 8227749202 ps
CPU time 8.2 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 225264 kb
Host smart-83be44ad-96f3-4389-bbdb-e7dd642ba8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800741867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1800741867
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1448671084
Short name T943
Test name
Test status
Simulation time 16664361 ps
CPU time 0.74 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:25 PM PDT 24
Peak memory 205904 kb
Host smart-d1b17eb0-ab3e-4b66-ac91-927ca21fb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448671084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1448671084
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2758166911
Short name T605
Test name
Test status
Simulation time 11851548027 ps
CPU time 48.4 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 241572 kb
Host smart-8ba9c89c-8b79-4d29-ae08-29e343e53728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758166911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2758166911
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1559385904
Short name T217
Test name
Test status
Simulation time 31488030836 ps
CPU time 204.43 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:52:55 PM PDT 24
Peak memory 253320 kb
Host smart-891392f8-b824-4182-983d-6022310c4802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559385904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1559385904
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.896106218
Short name T257
Test name
Test status
Simulation time 26927127534 ps
CPU time 76.89 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 251640 kb
Host smart-062fd9ca-f74b-4c51-9711-6d7a445ba8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896106218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.896106218
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3553724398
Short name T597
Test name
Test status
Simulation time 645336282 ps
CPU time 6.89 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 225092 kb
Host smart-78e85a14-274d-4545-8e98-a487a35bfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553724398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3553724398
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2327775671
Short name T379
Test name
Test status
Simulation time 129612945429 ps
CPU time 108.87 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:51:08 PM PDT 24
Peak memory 255944 kb
Host smart-fd6ab877-14ff-45fc-8d72-9f8196805ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327775671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2327775671
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.513534484
Short name T589
Test name
Test status
Simulation time 361762418 ps
CPU time 5.49 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:35 PM PDT 24
Peak memory 233396 kb
Host smart-aeceeccc-7cb3-4c5e-868e-c707c30e571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513534484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.513534484
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1391965111
Short name T26
Test name
Test status
Simulation time 78818517507 ps
CPU time 76.28 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:50:42 PM PDT 24
Peak memory 233348 kb
Host smart-3fb91990-d5ce-4f89-a901-abf70eb8234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391965111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1391965111
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1504482284
Short name T530
Test name
Test status
Simulation time 160743728 ps
CPU time 1.05 seconds
Started Jul 30 04:49:16 PM PDT 24
Finished Jul 30 04:49:17 PM PDT 24
Peak memory 217096 kb
Host smart-e6024bf4-846d-4797-97b9-a8f7c81643f9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504482284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1504482284
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4241370451
Short name T424
Test name
Test status
Simulation time 30879744970 ps
CPU time 24.98 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 249764 kb
Host smart-5b7f378e-4e61-4559-b8ad-6f6f951ccdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241370451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4241370451
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4227804086
Short name T857
Test name
Test status
Simulation time 6415704171 ps
CPU time 8.97 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 234372 kb
Host smart-d8386c95-6193-4935-944b-56ea2458c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227804086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4227804086
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.313456814
Short name T712
Test name
Test status
Simulation time 1271384299 ps
CPU time 6.75 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:49:25 PM PDT 24
Peak memory 219364 kb
Host smart-d19bfa46-c5a4-4698-a222-a144a9ce3ed8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=313456814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.313456814
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2656961792
Short name T384
Test name
Test status
Simulation time 62828901 ps
CPU time 1.03 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 207140 kb
Host smart-8b771f69-2dfd-420b-968a-03b6e029a9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656961792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2656961792
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.482986344
Short name T691
Test name
Test status
Simulation time 447217364 ps
CPU time 7.37 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 216856 kb
Host smart-cd9e1301-1690-4a29-aee8-7d7e15d781b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482986344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.482986344
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2772137318
Short name T426
Test name
Test status
Simulation time 11594906515 ps
CPU time 10.24 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 216892 kb
Host smart-618c058e-7eb4-445a-a6d5-0eb8b0c26912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772137318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2772137318
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1984370502
Short name T671
Test name
Test status
Simulation time 39859326 ps
CPU time 1.72 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 216868 kb
Host smart-12b96180-bf5a-47f9-b322-c5ff81438f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984370502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1984370502
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3174810290
Short name T604
Test name
Test status
Simulation time 231562106 ps
CPU time 0.86 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:30 PM PDT 24
Peak memory 206840 kb
Host smart-26cd87f6-59fa-491e-9cdb-fbbc559aee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174810290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3174810290
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2582311990
Short name T556
Test name
Test status
Simulation time 6004076260 ps
CPU time 11.41 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:49:42 PM PDT 24
Peak memory 225092 kb
Host smart-624ede2b-b6d4-42d4-9c07-2937d1b2ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582311990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2582311990
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2464185507
Short name T419
Test name
Test status
Simulation time 12488761 ps
CPU time 0.69 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 206104 kb
Host smart-18482617-4d3a-40ce-8ede-422a47cfb457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464185507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2464185507
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3534631304
Short name T414
Test name
Test status
Simulation time 177839131 ps
CPU time 3.7 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 225200 kb
Host smart-d2030705-1e2f-449c-8a45-aa5458394433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534631304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3534631304
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2886272423
Short name T549
Test name
Test status
Simulation time 49165306 ps
CPU time 0.75 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 206964 kb
Host smart-0b42e3af-f420-45db-9793-eac92c6cbb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886272423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2886272423
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1437784680
Short name T143
Test name
Test status
Simulation time 21160588087 ps
CPU time 202.26 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:52:59 PM PDT 24
Peak memory 249876 kb
Host smart-898e67fe-dec0-4e4c-a50b-1782b43bd7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437784680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1437784680
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.609300236
Short name T886
Test name
Test status
Simulation time 17983763414 ps
CPU time 45.62 seconds
Started Jul 30 04:49:37 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 233416 kb
Host smart-b86ccd95-b3eb-4acf-bbaa-7179453b1232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609300236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.609300236
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.804946784
Short name T733
Test name
Test status
Simulation time 100605306555 ps
CPU time 334.88 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:55:08 PM PDT 24
Peak memory 254976 kb
Host smart-de5374cb-bff2-4013-ae18-107f32667821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804946784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.804946784
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.221055443
Short name T648
Test name
Test status
Simulation time 933630845 ps
CPU time 12.11 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 225228 kb
Host smart-6ac60c6c-7f30-4078-95b6-df0ea9f5c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221055443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.221055443
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.757431406
Short name T533
Test name
Test status
Simulation time 34040422 ps
CPU time 2.59 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 232972 kb
Host smart-5936d09c-4766-4357-b6d1-c2b23bdb6467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757431406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.757431406
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1382668835
Short name T394
Test name
Test status
Simulation time 63466482 ps
CPU time 1.07 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 217140 kb
Host smart-da9995b5-7a86-4980-a250-f4192970bcda
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382668835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1382668835
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3539164420
Short name T731
Test name
Test status
Simulation time 2726429014 ps
CPU time 7.18 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:49:39 PM PDT 24
Peak memory 225192 kb
Host smart-4382f614-601c-4750-bc2d-28a77c07b576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539164420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3539164420
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1128290365
Short name T758
Test name
Test status
Simulation time 71084796 ps
CPU time 2.64 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 233388 kb
Host smart-7f4d4fa0-671a-4d46-8163-c8bfe95a47d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128290365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1128290365
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2089865761
Short name T645
Test name
Test status
Simulation time 219114821 ps
CPU time 5.41 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:49:40 PM PDT 24
Peak memory 223660 kb
Host smart-4640dea0-11cd-4ac8-afaa-484714d434c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089865761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2089865761
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4039893095
Short name T873
Test name
Test status
Simulation time 29786415225 ps
CPU time 130.62 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:51:54 PM PDT 24
Peak memory 265940 kb
Host smart-6aab9fe0-3bdd-4f51-9fa1-39776b7c905c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039893095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4039893095
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2265960602
Short name T314
Test name
Test status
Simulation time 852140160 ps
CPU time 2.81 seconds
Started Jul 30 04:49:40 PM PDT 24
Finished Jul 30 04:49:42 PM PDT 24
Peak memory 216896 kb
Host smart-bb7ee022-9e0c-4c72-9671-f5443c50784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265960602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2265960602
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3216469083
Short name T422
Test name
Test status
Simulation time 1891101514 ps
CPU time 3.67 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 216920 kb
Host smart-dec6da62-adff-4344-a6e8-80718535ce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216469083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3216469083
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.202784023
Short name T753
Test name
Test status
Simulation time 149521877 ps
CPU time 1.12 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 208404 kb
Host smart-9b32985a-a9f1-4ede-8950-eb0c14cf122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202784023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.202784023
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1986867037
Short name T24
Test name
Test status
Simulation time 55714617 ps
CPU time 0.83 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 206440 kb
Host smart-cb1cba01-0094-4696-a82a-073a4b03593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986867037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1986867037
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3602269490
Short name T385
Test name
Test status
Simulation time 2976022882 ps
CPU time 3.94 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:38 PM PDT 24
Peak memory 225248 kb
Host smart-4ab63dea-256d-4062-84d1-17d902bf498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602269490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3602269490
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.323799072
Short name T493
Test name
Test status
Simulation time 34836333 ps
CPU time 0.7 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:35 PM PDT 24
Peak memory 205744 kb
Host smart-61a5aa86-7fe6-49e1-9ead-0f8c533583aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323799072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.323799072
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1429082842
Short name T9
Test name
Test status
Simulation time 219311821 ps
CPU time 2.85 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 225172 kb
Host smart-2d94657b-ddc6-454c-9b20-181a8ed7e229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429082842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1429082842
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3665862693
Short name T354
Test name
Test status
Simulation time 117231387 ps
CPU time 0.79 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:49:36 PM PDT 24
Peak memory 207336 kb
Host smart-226dfeeb-2cb2-4652-bef7-d29416b39d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665862693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3665862693
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1911587120
Short name T245
Test name
Test status
Simulation time 17551951392 ps
CPU time 122.96 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:51:43 PM PDT 24
Peak memory 249888 kb
Host smart-32e88136-7dc1-4bb7-9cf8-b9f18e2901d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911587120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1911587120
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1252813239
Short name T649
Test name
Test status
Simulation time 2808221975 ps
CPU time 27.35 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:50:04 PM PDT 24
Peak memory 241644 kb
Host smart-1aa945fc-c822-4575-b3c7-b756eba4ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252813239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1252813239
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2188284623
Short name T158
Test name
Test status
Simulation time 4103525708 ps
CPU time 113.73 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:51:39 PM PDT 24
Peak memory 266304 kb
Host smart-c2b6a749-cfff-4248-81b5-d15a18f0fd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188284623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2188284623
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.874425343
Short name T899
Test name
Test status
Simulation time 137249825 ps
CPU time 4.54 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:49:32 PM PDT 24
Peak memory 225200 kb
Host smart-2008e7a3-cb45-4e22-96b4-a0938b8b9695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874425343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.874425343
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1987760140
Short name T949
Test name
Test status
Simulation time 2616107169 ps
CPU time 35.74 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 257976 kb
Host smart-f6fadc50-a176-42b3-93f3-307713364b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987760140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1987760140
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2165073456
Short name T944
Test name
Test status
Simulation time 19546873538 ps
CPU time 13.73 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 233460 kb
Host smart-9016975c-b509-4382-b43f-6a6a7d6d64ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165073456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2165073456
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3651908163
Short name T919
Test name
Test status
Simulation time 210575820 ps
CPU time 2.6 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 223664 kb
Host smart-7f27e12b-6c87-4fef-b573-3e7efa041cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651908163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3651908163
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1792075197
Short name T638
Test name
Test status
Simulation time 24720243 ps
CPU time 1.09 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:49:32 PM PDT 24
Peak memory 217096 kb
Host smart-628415d3-0265-4773-848c-9deef41579a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792075197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1792075197
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.945364140
Short name T486
Test name
Test status
Simulation time 333095601 ps
CPU time 5.39 seconds
Started Jul 30 04:49:42 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 225104 kb
Host smart-52453b3e-b49a-4a9f-a567-8a038a44c4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945364140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.945364140
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2628998113
Short name T367
Test name
Test status
Simulation time 168116569 ps
CPU time 2.19 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 224500 kb
Host smart-45eb9047-501c-4596-acdf-d1e1ebfac556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628998113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2628998113
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.607030609
Short name T752
Test name
Test status
Simulation time 29877710045 ps
CPU time 20.21 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 221116 kb
Host smart-cef36b30-3217-4a03-85c2-3af5365fe144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=607030609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.607030609
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3796332664
Short name T780
Test name
Test status
Simulation time 11813837357 ps
CPU time 106.94 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:51:22 PM PDT 24
Peak memory 256600 kb
Host smart-90096a55-83ed-4164-876b-d682d3f83d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796332664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3796332664
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1175083857
Short name T31
Test name
Test status
Simulation time 1996762282 ps
CPU time 14.41 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 216832 kb
Host smart-f5568024-ceae-455b-a290-64890d863eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175083857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1175083857
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1728069209
Short name T701
Test name
Test status
Simulation time 404705660 ps
CPU time 3.02 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:41 PM PDT 24
Peak memory 216888 kb
Host smart-fe591b98-9e56-45ba-a187-904a11f271de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728069209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1728069209
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3750360442
Short name T721
Test name
Test status
Simulation time 47414247 ps
CPU time 1.33 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:32 PM PDT 24
Peak memory 216832 kb
Host smart-68ae52f6-f268-4de3-9f9e-10bbb5ca7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750360442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3750360442
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2863330768
Short name T359
Test name
Test status
Simulation time 65831792 ps
CPU time 0.9 seconds
Started Jul 30 04:49:26 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 206496 kb
Host smart-ffe22ee2-ceff-4454-a690-dbf4b7c4ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863330768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2863330768
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1953369398
Short name T565
Test name
Test status
Simulation time 3288467646 ps
CPU time 10.76 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 233420 kb
Host smart-2198a26a-4b8d-4d9c-894b-f0f3026b893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953369398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1953369398
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2687461405
Short name T334
Test name
Test status
Simulation time 12076035 ps
CPU time 0.78 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:49:46 PM PDT 24
Peak memory 205728 kb
Host smart-4ff6d8be-873d-4a7a-b116-44ffdf4909bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687461405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2687461405
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3283319675
Short name T683
Test name
Test status
Simulation time 2340742039 ps
CPU time 19.58 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 233468 kb
Host smart-44d45890-1e03-4897-bc75-200f27c684d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283319675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3283319675
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4177298395
Short name T70
Test name
Test status
Simulation time 70522068 ps
CPU time 0.77 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:30 PM PDT 24
Peak memory 206276 kb
Host smart-948f5339-75d9-4c4f-a3d6-a56cfef21fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177298395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4177298395
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3437792530
Short name T1021
Test name
Test status
Simulation time 67297125408 ps
CPU time 103.94 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:51:19 PM PDT 24
Peak memory 238288 kb
Host smart-dc11315a-7be5-441f-9ab7-c3cd7483bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437792530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3437792530
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3272644043
Short name T153
Test name
Test status
Simulation time 4415980979 ps
CPU time 112.09 seconds
Started Jul 30 04:49:41 PM PDT 24
Finished Jul 30 04:51:33 PM PDT 24
Peak memory 262140 kb
Host smart-b2dc93e6-c59a-41e8-90ba-e0641283b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272644043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3272644043
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.47171904
Short name T248
Test name
Test status
Simulation time 160760932107 ps
CPU time 337.77 seconds
Started Jul 30 04:49:32 PM PDT 24
Finished Jul 30 04:55:11 PM PDT 24
Peak memory 257972 kb
Host smart-236b1c5e-a1b6-47ed-80ca-979e9614b02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47171904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.47171904
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2764594583
Short name T370
Test name
Test status
Simulation time 1800869671 ps
CPU time 7.14 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 233356 kb
Host smart-a055796d-c390-4271-b11b-eee2c0e9b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764594583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2764594583
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.263960971
Short name T490
Test name
Test status
Simulation time 1555971169 ps
CPU time 37.46 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:50:06 PM PDT 24
Peak memory 250716 kb
Host smart-0c84aa1f-d04d-4085-9e14-8420490f74f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263960971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.263960971
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1012196898
Short name T521
Test name
Test status
Simulation time 10616330513 ps
CPU time 34.41 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 225172 kb
Host smart-e13e8568-3252-454f-b392-3ae46ec075fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012196898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1012196898
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2055297251
Short name T1018
Test name
Test status
Simulation time 625923231 ps
CPU time 10.89 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 241332 kb
Host smart-a3b54a16-bd3a-43d0-a1dd-0fd4f6d201d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055297251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2055297251
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3811191886
Short name T37
Test name
Test status
Simulation time 26391148 ps
CPU time 1.02 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 217064 kb
Host smart-410fb8b8-7f45-4011-9128-5f8198095481
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811191886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3811191886
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2642195184
Short name T835
Test name
Test status
Simulation time 48984688213 ps
CPU time 18.14 seconds
Started Jul 30 04:49:37 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 225200 kb
Host smart-fad172b9-ab89-40e7-8ac1-3fbcd2f150aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642195184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2642195184
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2275793881
Short name T247
Test name
Test status
Simulation time 4855862284 ps
CPU time 7.78 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 225148 kb
Host smart-755f8cf6-9218-48e3-9e2b-db4229f02dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275793881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2275793881
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1542432755
Short name T518
Test name
Test status
Simulation time 640573236 ps
CPU time 8.08 seconds
Started Jul 30 04:49:28 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 219808 kb
Host smart-181bca5f-baff-4c7b-945d-2a979321a2a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542432755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1542432755
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1240900140
Short name T22
Test name
Test status
Simulation time 894366566 ps
CPU time 8.68 seconds
Started Jul 30 04:49:36 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 224276 kb
Host smart-4d57e030-2b2c-4a1b-89ff-da00f5047a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240900140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1240900140
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2298481863
Short name T390
Test name
Test status
Simulation time 2281797438 ps
CPU time 26.59 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 216932 kb
Host smart-e91d94cc-027a-4fef-a842-2924fcf2da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298481863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2298481863
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1372970304
Short name T343
Test name
Test status
Simulation time 23441926179 ps
CPU time 16.73 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 216928 kb
Host smart-2758350b-1476-4a69-85ec-b48901834997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372970304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1372970304
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3876867824
Short name T781
Test name
Test status
Simulation time 88912912 ps
CPU time 1.26 seconds
Started Jul 30 04:49:32 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 216672 kb
Host smart-6ac2a341-0b9e-49f5-9776-f32941bb5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876867824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3876867824
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1023447231
Short name T391
Test name
Test status
Simulation time 47656271 ps
CPU time 0.75 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 206508 kb
Host smart-0d4fba0c-a48e-494c-b81a-49471116df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023447231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1023447231
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1886008384
Short name T698
Test name
Test status
Simulation time 517594359 ps
CPU time 5.88 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:49:24 PM PDT 24
Peak memory 233276 kb
Host smart-8aef6ff4-37c6-4599-8c7f-d7b364c4c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886008384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1886008384
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.394731671
Short name T590
Test name
Test status
Simulation time 42534899 ps
CPU time 0.74 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:39 PM PDT 24
Peak memory 205840 kb
Host smart-874281ce-9630-464a-adf0-2a39e6248522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394731671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.394731671
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4163522889
Short name T502
Test name
Test status
Simulation time 268350201 ps
CPU time 4.24 seconds
Started Jul 30 04:49:41 PM PDT 24
Finished Jul 30 04:49:46 PM PDT 24
Peak memory 225104 kb
Host smart-df38e236-19c0-49e7-8b6e-e40e9f72df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163522889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4163522889
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3121966408
Short name T410
Test name
Test status
Simulation time 58535950 ps
CPU time 0.76 seconds
Started Jul 30 04:49:40 PM PDT 24
Finished Jul 30 04:49:41 PM PDT 24
Peak memory 207228 kb
Host smart-23d835be-0e8a-45bb-8e90-a8a4d63cbd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121966408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3121966408
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3621506104
Short name T237
Test name
Test status
Simulation time 2886199846 ps
CPU time 25.95 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 254556 kb
Host smart-b56b894b-8887-4552-9e35-7e5115ecca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621506104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3621506104
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3641084081
Short name T433
Test name
Test status
Simulation time 61703543287 ps
CPU time 118.71 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:51:38 PM PDT 24
Peak memory 241028 kb
Host smart-511f4481-2c0e-4741-a908-57c94696f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641084081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3641084081
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.20249697
Short name T458
Test name
Test status
Simulation time 83940864171 ps
CPU time 211.81 seconds
Started Jul 30 04:49:41 PM PDT 24
Finished Jul 30 04:53:13 PM PDT 24
Peak memory 250212 kb
Host smart-7a21850b-3340-4054-9f3e-6e7106bf914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20249697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.20249697
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1628546946
Short name T524
Test name
Test status
Simulation time 611710087 ps
CPU time 9.62 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 233408 kb
Host smart-d2851c88-f1f2-4035-bd5d-6c4801cbd601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628546946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1628546946
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1466007713
Short name T56
Test name
Test status
Simulation time 24571349260 ps
CPU time 34.63 seconds
Started Jul 30 04:49:43 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 241612 kb
Host smart-2be724fa-60f8-40a2-a1d0-352f486dad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466007713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1466007713
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3582391627
Short name T428
Test name
Test status
Simulation time 299927293 ps
CPU time 3.05 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 219460 kb
Host smart-54f6aebf-9db7-41c8-ad38-436bf32c5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582391627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3582391627
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.448802178
Short name T656
Test name
Test status
Simulation time 926632693 ps
CPU time 20.63 seconds
Started Jul 30 04:49:33 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 249300 kb
Host smart-d9d2e170-9e9e-4407-80e3-364fe6d9762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448802178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.448802178
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2233456070
Short name T837
Test name
Test status
Simulation time 49277624 ps
CPU time 1.06 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 217060 kb
Host smart-16407254-5b9d-43fd-8b57-9a0170eae59d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233456070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2233456070
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1479611180
Short name T710
Test name
Test status
Simulation time 2489271380 ps
CPU time 10.15 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:48 PM PDT 24
Peak memory 241596 kb
Host smart-9fc46038-d467-4a70-8395-2ca1b5db89ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479611180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1479611180
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.486603237
Short name T851
Test name
Test status
Simulation time 2221770104 ps
CPU time 11.13 seconds
Started Jul 30 04:49:34 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 225260 kb
Host smart-d4153e96-2a78-49b4-b2b9-9a87ae9e1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486603237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.486603237
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2076456443
Short name T609
Test name
Test status
Simulation time 144956410 ps
CPU time 3.72 seconds
Started Jul 30 04:49:43 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 220436 kb
Host smart-0afecb4e-2038-4b9e-b650-6f0abcd29780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2076456443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2076456443
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1024336738
Short name T19
Test name
Test status
Simulation time 16061419934 ps
CPU time 133.28 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:52:02 PM PDT 24
Peak memory 257224 kb
Host smart-c78fa13d-7377-41ca-93b1-5853263723e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024336738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1024336738
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3936183700
Short name T100
Test name
Test status
Simulation time 25841960923 ps
CPU time 26.05 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 216956 kb
Host smart-55cb46e5-9c96-489f-ae8a-18988606dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936183700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3936183700
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1682576998
Short name T952
Test name
Test status
Simulation time 3108280961 ps
CPU time 8.44 seconds
Started Jul 30 04:49:35 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 216964 kb
Host smart-a4d64188-0b3e-4b0b-a3e1-d6672529da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682576998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1682576998
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1328503704
Short name T321
Test name
Test status
Simulation time 90432777 ps
CPU time 3.3 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 216924 kb
Host smart-da321a17-d18f-499c-bee3-323a13a42f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328503704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1328503704
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1027198065
Short name T563
Test name
Test status
Simulation time 26202642 ps
CPU time 0.84 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:49:48 PM PDT 24
Peak memory 206476 kb
Host smart-9da7b1f7-15d4-40ed-ad50-b3c65c5bd228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027198065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1027198065
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3339653585
Short name T846
Test name
Test status
Simulation time 2768760750 ps
CPU time 11.78 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:56 PM PDT 24
Peak memory 225180 kb
Host smart-88ec830a-35c5-4082-b48d-1566832aeed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339653585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3339653585
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2226702299
Short name T1001
Test name
Test status
Simulation time 19486493 ps
CPU time 0.7 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 205264 kb
Host smart-f67f853e-ff14-4757-80e2-a213e2540785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226702299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
226702299
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.377450621
Short name T786
Test name
Test status
Simulation time 720856196 ps
CPU time 6.87 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 225120 kb
Host smart-43ade199-52e4-444c-9075-22756b20a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377450621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.377450621
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.914483061
Short name T839
Test name
Test status
Simulation time 55230216 ps
CPU time 0.79 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 207280 kb
Host smart-9d290281-e49a-422e-9158-9ddff2deda81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914483061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.914483061
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.896884189
Short name T412
Test name
Test status
Simulation time 14223507400 ps
CPU time 114.92 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 249852 kb
Host smart-2f194763-e783-45bb-a44f-c42b1f0f8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896884189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.896884189
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3948956673
Short name T997
Test name
Test status
Simulation time 1771250020 ps
CPU time 40.7 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 252096 kb
Host smart-95f74f73-8bdf-4d85-9b2b-132d798486c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948956673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3948956673
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.505937339
Short name T762
Test name
Test status
Simulation time 16077184093 ps
CPU time 115.92 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 249776 kb
Host smart-7bd5c0ff-549e-4ff5-89f6-e63760442c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505937339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
505937339
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1717810537
Short name T161
Test name
Test status
Simulation time 2992830921 ps
CPU time 41.51 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 04:49:43 PM PDT 24
Peak memory 240068 kb
Host smart-22b6f200-633d-481e-96e5-5e73fb5463d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717810537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1717810537
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2267581872
Short name T232
Test name
Test status
Simulation time 8049434635 ps
CPU time 89.04 seconds
Started Jul 30 04:48:51 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 250360 kb
Host smart-2a57f871-18d5-48bc-94e8-30befdcfae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267581872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2267581872
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.153821491
Short name T107
Test name
Test status
Simulation time 3301041780 ps
CPU time 28.36 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 225144 kb
Host smart-362b4bb7-db51-4543-ae75-34a7d888861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153821491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.153821491
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.96365053
Short name T178
Test name
Test status
Simulation time 4911331862 ps
CPU time 44.7 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:49:37 PM PDT 24
Peak memory 225504 kb
Host smart-b022358d-ca39-4281-bb0d-3fa95cfc4a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96365053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.96365053
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3688218103
Short name T911
Test name
Test status
Simulation time 16445644 ps
CPU time 1.1 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 217088 kb
Host smart-d7fea5fa-3623-4d0e-ba1f-4510bcc2b6c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688218103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3688218103
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.958322624
Short name T408
Test name
Test status
Simulation time 1684231900 ps
CPU time 12.16 seconds
Started Jul 30 04:48:49 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 233280 kb
Host smart-961b561b-8187-4b1e-9919-beefda7e14ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958322624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
958322624
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2452294096
Short name T252
Test name
Test status
Simulation time 5342300984 ps
CPU time 12.85 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:49:03 PM PDT 24
Peak memory 233364 kb
Host smart-65a3429a-51c0-41b2-98af-94c9004f24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452294096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2452294096
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2147631886
Short name T479
Test name
Test status
Simulation time 171950025 ps
CPU time 4.35 seconds
Started Jul 30 04:48:47 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 220292 kb
Host smart-1e7f39f4-69e0-4bcf-9d78-b1d0bf136e0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2147631886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2147631886
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2046539208
Short name T79
Test name
Test status
Simulation time 604058297 ps
CPU time 0.96 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:48:58 PM PDT 24
Peak memory 235564 kb
Host smart-98e07070-eed6-4b48-a970-bea9631a990b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046539208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2046539208
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3069780329
Short name T20
Test name
Test status
Simulation time 57546227265 ps
CPU time 93.92 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 263424 kb
Host smart-ef9b6de1-d036-4245-bc9f-fc9b5e4e4d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069780329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3069780329
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3920398598
Short name T803
Test name
Test status
Simulation time 10778875347 ps
CPU time 9.9 seconds
Started Jul 30 04:48:55 PM PDT 24
Finished Jul 30 04:49:05 PM PDT 24
Peak memory 217276 kb
Host smart-33fb73a3-c1ea-4536-a289-ed6b45a283dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920398598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3920398598
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.505947131
Short name T976
Test name
Test status
Simulation time 977658807 ps
CPU time 5.52 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:04 PM PDT 24
Peak memory 216828 kb
Host smart-c11d76e0-3716-44e2-bed4-d1eb8cbec627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505947131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.505947131
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2049841711
Short name T870
Test name
Test status
Simulation time 351107684 ps
CPU time 2.86 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 216888 kb
Host smart-d33872cb-394f-4a6f-b4be-3b0a69315e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049841711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2049841711
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1760855908
Short name T646
Test name
Test status
Simulation time 41184449 ps
CPU time 0.82 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:52 PM PDT 24
Peak memory 206480 kb
Host smart-d5a07a0d-91ae-427f-b600-7c2dce6b5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760855908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1760855908
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1540354444
Short name T1007
Test name
Test status
Simulation time 13855311563 ps
CPU time 11.27 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:10 PM PDT 24
Peak memory 240020 kb
Host smart-ce733724-78ab-47e3-87f4-c9ee40dc5540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540354444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1540354444
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2486786874
Short name T985
Test name
Test status
Simulation time 12268245 ps
CPU time 0.75 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 205764 kb
Host smart-932824e4-950e-41fd-8f60-339394356f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486786874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2486786874
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3435787143
Short name T859
Test name
Test status
Simulation time 74858797 ps
CPU time 2.27 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 225072 kb
Host smart-f491fc5b-358e-4db4-84cf-9553ee65338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435787143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3435787143
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2937384004
Short name T517
Test name
Test status
Simulation time 67100317 ps
CPU time 0.8 seconds
Started Jul 30 04:49:40 PM PDT 24
Finished Jul 30 04:49:41 PM PDT 24
Peak memory 207272 kb
Host smart-044f7dc4-d039-40fb-9c7a-cbd2aa162b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937384004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2937384004
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2643647185
Short name T669
Test name
Test status
Simulation time 27955473579 ps
CPU time 251.28 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:54:03 PM PDT 24
Peak memory 253656 kb
Host smart-735baa7f-0a36-45e1-aae0-01dab6a08b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643647185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2643647185
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3997088258
Short name T290
Test name
Test status
Simulation time 628624955206 ps
CPU time 583.24 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:59:38 PM PDT 24
Peak memory 265416 kb
Host smart-eabad6af-09d0-4f99-8fba-4046a7834d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997088258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3997088258
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.419287739
Short name T301
Test name
Test status
Simulation time 4670601443 ps
CPU time 30.14 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 239088 kb
Host smart-0d77179e-b4a3-4110-9cbe-0fd646b70e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419287739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.419287739
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1045481127
Short name T464
Test name
Test status
Simulation time 5821987280 ps
CPU time 55.15 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 249804 kb
Host smart-3b7aff74-3347-46af-89f3-660f1b4523ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045481127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1045481127
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3336657025
Short name T449
Test name
Test status
Simulation time 312312010 ps
CPU time 2.41 seconds
Started Jul 30 04:49:32 PM PDT 24
Finished Jul 30 04:49:34 PM PDT 24
Peak memory 233040 kb
Host smart-4cf4fc77-262b-4043-914e-6695bd12839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336657025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3336657025
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.8729528
Short name T469
Test name
Test status
Simulation time 6027584106 ps
CPU time 32.38 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 233464 kb
Host smart-ff751b29-fe2a-4ada-8709-560b9da044fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8729528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.8729528
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1796315458
Short name T908
Test name
Test status
Simulation time 704416971 ps
CPU time 5.55 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 225136 kb
Host smart-1cf7be2e-7d3a-43e4-b4e1-b93310f19367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796315458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1796315458
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.401308350
Short name T630
Test name
Test status
Simulation time 59495730315 ps
CPU time 16.94 seconds
Started Jul 30 04:49:31 PM PDT 24
Finished Jul 30 04:49:48 PM PDT 24
Peak memory 241132 kb
Host smart-794dffd9-1074-40de-bc2b-b5420a7e5566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401308350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.401308350
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.214813816
Short name T362
Test name
Test status
Simulation time 1328028602 ps
CPU time 4.53 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 219424 kb
Host smart-3967c579-0242-44ea-98d2-3fa1c7c626ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214813816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.214813816
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3480947465
Short name T383
Test name
Test status
Simulation time 3119040164 ps
CPU time 15.91 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 217132 kb
Host smart-8b79d0a2-7340-4831-9c62-cc6be62a6fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480947465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3480947465
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.915900197
Short name T847
Test name
Test status
Simulation time 27058918 ps
CPU time 0.69 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:30 PM PDT 24
Peak memory 206076 kb
Host smart-ac7c6f1f-686b-47e8-ae2b-29807a77d45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915900197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.915900197
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3855991024
Short name T574
Test name
Test status
Simulation time 28920058 ps
CPU time 1.87 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:40 PM PDT 24
Peak memory 216916 kb
Host smart-8a932084-a73a-4f52-ac0d-c907f79aeb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855991024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3855991024
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1524045286
Short name T799
Test name
Test status
Simulation time 317598737 ps
CPU time 0.72 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 206456 kb
Host smart-79c04026-151f-4c1b-a4c8-24e9121eba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524045286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1524045286
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3226597301
Short name T42
Test name
Test status
Simulation time 4404236891 ps
CPU time 4.71 seconds
Started Jul 30 04:49:42 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 225252 kb
Host smart-2209f833-b817-45b7-bd35-1f34dd9cb86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226597301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3226597301
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1903484582
Short name T969
Test name
Test status
Simulation time 52545405 ps
CPU time 0.72 seconds
Started Jul 30 04:49:30 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 205748 kb
Host smart-241f4d25-afdc-4572-93d3-dbba50d4372d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903484582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1903484582
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2498606738
Short name T105
Test name
Test status
Simulation time 754301451 ps
CPU time 3.75 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:49:43 PM PDT 24
Peak memory 233336 kb
Host smart-f45ca317-24b9-424d-9054-9b16fd6f8fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498606738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2498606738
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3766808165
Short name T418
Test name
Test status
Simulation time 35171611 ps
CPU time 0.77 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 205968 kb
Host smart-baca4df0-457a-4658-82eb-4b9313984c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766808165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3766808165
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.432358510
Short name T945
Test name
Test status
Simulation time 63377412450 ps
CPU time 163.71 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:52:32 PM PDT 24
Peak memory 254700 kb
Host smart-ad626510-fc74-4837-b1c3-f71a8b6d23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432358510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.432358510
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.497560749
Short name T228
Test name
Test status
Simulation time 64195276476 ps
CPU time 179.63 seconds
Started Jul 30 04:49:40 PM PDT 24
Finished Jul 30 04:52:40 PM PDT 24
Peak memory 254396 kb
Host smart-f60fe546-31d6-429d-8438-b929376766eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497560749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.497560749
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3314102881
Short name T468
Test name
Test status
Simulation time 10867435542 ps
CPU time 71.88 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:51:01 PM PDT 24
Peak memory 258132 kb
Host smart-6307ada3-72b2-4872-8781-122f78b96dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314102881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3314102881
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1550181676
Short name T344
Test name
Test status
Simulation time 101273050 ps
CPU time 3.37 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 233384 kb
Host smart-1fdebc41-49f7-4430-9d5f-fc7ce1efd0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550181676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1550181676
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1242576247
Short name T507
Test name
Test status
Simulation time 4903643818 ps
CPU time 14.36 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:50:01 PM PDT 24
Peak memory 233324 kb
Host smart-7bf4158f-f073-4dc8-84fc-d0e4e57a1e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242576247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1242576247
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2348523176
Short name T89
Test name
Test status
Simulation time 814736978 ps
CPU time 7.23 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 241240 kb
Host smart-50ec5e77-5b97-4a8d-9fb6-8c817daf1635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348523176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2348523176
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2316938255
Short name T888
Test name
Test status
Simulation time 5941298862 ps
CPU time 10.8 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 233340 kb
Host smart-c9f3e043-da19-4965-a493-dbdf83606d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316938255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2316938255
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3970412806
Short name T789
Test name
Test status
Simulation time 19383219580 ps
CPU time 14.36 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 233412 kb
Host smart-50edf84d-8995-4675-884f-3426df2bc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970412806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3970412806
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3157978224
Short name T1000
Test name
Test status
Simulation time 3196068534 ps
CPU time 11.06 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 223708 kb
Host smart-55c26035-ac74-4d7d-8c99-8c8f27b62ff8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157978224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3157978224
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2715891343
Short name T33
Test name
Test status
Simulation time 202344588151 ps
CPU time 443.02 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:57:14 PM PDT 24
Peak memory 266252 kb
Host smart-64ce3408-e41e-49b3-b6f7-e9d562ad6901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715891343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2715891343
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1858831304
Short name T332
Test name
Test status
Simulation time 11537411 ps
CPU time 0.74 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 206420 kb
Host smart-58d81621-8806-4c6c-9190-51ea25a3e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858831304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1858831304
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3489017673
Short name T819
Test name
Test status
Simulation time 25078546905 ps
CPU time 19.25 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:50:10 PM PDT 24
Peak memory 216956 kb
Host smart-2fa7fa4b-8157-4e9f-9e3d-fdc35683890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489017673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3489017673
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3693216981
Short name T761
Test name
Test status
Simulation time 12667520 ps
CPU time 0.71 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:49 PM PDT 24
Peak memory 206012 kb
Host smart-8cf79f30-9a24-4dcb-a52c-1f396f3d2d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693216981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3693216981
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.383066859
Short name T149
Test name
Test status
Simulation time 10996035 ps
CPU time 0.69 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 206004 kb
Host smart-95243215-fb72-449e-bb57-e59c401e5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383066859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.383066859
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2724586791
Short name T570
Test name
Test status
Simulation time 46459948979 ps
CPU time 11.64 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:49:59 PM PDT 24
Peak memory 225148 kb
Host smart-dba471bb-2b02-4ee3-8ffd-19e7406ec084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724586791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2724586791
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2655931801
Short name T650
Test name
Test status
Simulation time 56422970 ps
CPU time 0.75 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:49:51 PM PDT 24
Peak memory 205760 kb
Host smart-fe81f6f6-f3d0-4335-b1c9-9ed9e6263f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655931801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2655931801
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4185482086
Short name T1008
Test name
Test status
Simulation time 2134247591 ps
CPU time 19.56 seconds
Started Jul 30 04:49:38 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 225160 kb
Host smart-eea3dedb-58cb-4421-bf12-450947d4e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185482086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4185482086
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.255030442
Short name T907
Test name
Test status
Simulation time 51986482 ps
CPU time 0.76 seconds
Started Jul 30 04:50:00 PM PDT 24
Finished Jul 30 04:50:01 PM PDT 24
Peak memory 206252 kb
Host smart-3de318fd-5328-4b19-b439-d8bd5647c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255030442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.255030442
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.578103763
Short name T516
Test name
Test status
Simulation time 22445940219 ps
CPU time 129.67 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:51:59 PM PDT 24
Peak memory 251620 kb
Host smart-ce2669ee-a240-4d9c-9390-b314271dc583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578103763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.578103763
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.895239954
Short name T581
Test name
Test status
Simulation time 19635686937 ps
CPU time 30.85 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:50:15 PM PDT 24
Peak memory 218452 kb
Host smart-27279672-f849-422e-abcf-3654f07dd248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895239954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.895239954
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1007980512
Short name T44
Test name
Test status
Simulation time 5811107638 ps
CPU time 103.84 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:51:31 PM PDT 24
Peak memory 265652 kb
Host smart-c1ad79ee-e171-42f6-bd72-d01c39f412eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007980512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1007980512
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1428848192
Short name T302
Test name
Test status
Simulation time 2929034939 ps
CPU time 44.39 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:50:32 PM PDT 24
Peak memory 233448 kb
Host smart-9a33a19f-b945-4973-8658-b6bcb8126f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428848192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1428848192
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2006393648
Short name T45
Test name
Test status
Simulation time 172499711593 ps
CPU time 351.07 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:55:43 PM PDT 24
Peak memory 258056 kb
Host smart-82327de9-7fc1-49ab-a64f-f291ddd2e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006393648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2006393648
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1890534308
Short name T651
Test name
Test status
Simulation time 9040204529 ps
CPU time 22.15 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:50:01 PM PDT 24
Peak memory 233380 kb
Host smart-0adbbb23-bdd7-4377-b0b0-ea23a813934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890534308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1890534308
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.792493066
Short name T993
Test name
Test status
Simulation time 1914026393 ps
CPU time 10.6 seconds
Started Jul 30 04:49:47 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 233324 kb
Host smart-974d6a2f-9ccf-46b8-b1c3-326b05efb52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792493066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.792493066
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1044325539
Short name T623
Test name
Test status
Simulation time 679054290 ps
CPU time 4.27 seconds
Started Jul 30 04:49:58 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 233312 kb
Host smart-1f865690-7f17-4ffe-aa7d-e2ddc1c8f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044325539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1044325539
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2204788837
Short name T695
Test name
Test status
Simulation time 545881954 ps
CPU time 9.27 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 240496 kb
Host smart-5ee2d1bd-5e36-4238-aa9b-df6520e30788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204788837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2204788837
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.999868154
Short name T375
Test name
Test status
Simulation time 735731501 ps
CPU time 7.27 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 222744 kb
Host smart-a81ea8bc-7d29-4bfe-8f16-71c3b646b0dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=999868154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.999868154
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.477130734
Short name T855
Test name
Test status
Simulation time 52449387656 ps
CPU time 513.8 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:58:27 PM PDT 24
Peak memory 265248 kb
Host smart-9a471be9-55f1-4e18-8fdf-9067c8dd6b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477130734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.477130734
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.305196743
Short name T568
Test name
Test status
Simulation time 12330781 ps
CPU time 0.77 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:49:47 PM PDT 24
Peak memory 206088 kb
Host smart-d0ea1149-8db3-4388-bdb4-fb75afc773a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305196743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.305196743
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4106025012
Short name T326
Test name
Test status
Simulation time 11397471101 ps
CPU time 9.87 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 216916 kb
Host smart-9c5596cd-8087-49ba-ac5b-975bd7b1f528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106025012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4106025012
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4081836430
Short name T998
Test name
Test status
Simulation time 1327417494 ps
CPU time 8.86 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:59 PM PDT 24
Peak memory 216968 kb
Host smart-eeabb1c3-dca3-4b72-9f18-7ef81b739183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081836430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4081836430
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2912430143
Short name T401
Test name
Test status
Simulation time 25029180 ps
CPU time 0.78 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:49:56 PM PDT 24
Peak memory 206464 kb
Host smart-237ac49a-0a04-4942-8228-cfcb5b4535e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912430143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2912430143
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2899230683
Short name T477
Test name
Test status
Simulation time 307809221 ps
CPU time 4.8 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 225188 kb
Host smart-78543686-0ce9-4016-8ff0-f3d9b0840bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899230683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2899230683
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1332734167
Short name T894
Test name
Test status
Simulation time 14627195 ps
CPU time 0.8 seconds
Started Jul 30 04:49:59 PM PDT 24
Finished Jul 30 04:50:00 PM PDT 24
Peak memory 206200 kb
Host smart-638d7a4c-365b-4b31-a291-8aba7b42432c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332734167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1332734167
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3733844578
Short name T1026
Test name
Test status
Simulation time 363019437 ps
CPU time 7.07 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 225200 kb
Host smart-a0ea55ad-9267-4667-a01f-727588d6260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733844578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3733844578
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4079707817
Short name T972
Test name
Test status
Simulation time 17130178 ps
CPU time 0.8 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 205948 kb
Host smart-aa8aaa77-3aa0-4d61-9b13-5074a17de164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079707817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4079707817
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.706128668
Short name T393
Test name
Test status
Simulation time 95378187534 ps
CPU time 216.57 seconds
Started Jul 30 04:50:01 PM PDT 24
Finished Jul 30 04:53:38 PM PDT 24
Peak memory 249892 kb
Host smart-62ea8d5b-08de-462f-b95d-ac2f30e16668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706128668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.706128668
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4229607936
Short name T692
Test name
Test status
Simulation time 104721891738 ps
CPU time 164.59 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:52:29 PM PDT 24
Peak memory 252780 kb
Host smart-c33f2b96-75c8-4db5-9262-71e7195ed05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229607936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4229607936
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.728424948
Short name T528
Test name
Test status
Simulation time 6007160144 ps
CPU time 31.75 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 218320 kb
Host smart-90dfb274-dbcb-46a8-97b0-732c731bbb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728424948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.728424948
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1718845040
Short name T884
Test name
Test status
Simulation time 203686507 ps
CPU time 7.65 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 233388 kb
Host smart-d2ec4418-a054-475c-b254-d54a0045fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718845040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1718845040
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3644044988
Short name T801
Test name
Test status
Simulation time 17217816553 ps
CPU time 126.11 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:52:10 PM PDT 24
Peak memory 256348 kb
Host smart-5d0dbb86-dedf-47d6-9fa7-4bbd241a6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644044988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3644044988
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1250989963
Short name T910
Test name
Test status
Simulation time 2108609477 ps
CPU time 4.3 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 233288 kb
Host smart-524c97d8-a37b-4897-9cc2-fe921e437a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250989963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1250989963
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3069508161
Short name T657
Test name
Test status
Simulation time 29948214638 ps
CPU time 31.63 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 236404 kb
Host smart-9fa50a8f-897c-40f8-bbf2-949d36b86a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069508161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3069508161
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3906971961
Short name T269
Test name
Test status
Simulation time 7822354073 ps
CPU time 20.84 seconds
Started Jul 30 04:49:44 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 233388 kb
Host smart-ce898bed-ca3e-4756-ba3a-d3656238b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906971961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3906971961
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.846637466
Short name T769
Test name
Test status
Simulation time 5682062101 ps
CPU time 12.44 seconds
Started Jul 30 04:49:45 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 225164 kb
Host smart-f14b6a4a-9872-4215-924e-e64e5035b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846637466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.846637466
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.341154808
Short name T436
Test name
Test status
Simulation time 1488959507 ps
CPU time 12.15 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:50:00 PM PDT 24
Peak memory 222084 kb
Host smart-f1067250-0a2b-4787-aa30-3a9385f07e31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=341154808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.341154808
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1416199523
Short name T610
Test name
Test status
Simulation time 8208261503 ps
CPU time 58.3 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:50:50 PM PDT 24
Peak memory 258092 kb
Host smart-f509edba-5a99-4252-b1b2-e682a50ae687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416199523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1416199523
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3008451165
Short name T594
Test name
Test status
Simulation time 56581919 ps
CPU time 0.72 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 206128 kb
Host smart-814edf2d-6157-47f4-b5e9-9e5247776712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008451165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3008451165
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3248868546
Short name T661
Test name
Test status
Simulation time 6627070137 ps
CPU time 15.9 seconds
Started Jul 30 04:49:46 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 216892 kb
Host smart-ab7e62c2-3ee2-4eac-90ca-560985d4a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248868546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3248868546
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2352098767
Short name T965
Test name
Test status
Simulation time 177345209 ps
CPU time 2.11 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:51 PM PDT 24
Peak memory 216928 kb
Host smart-b6b525ca-65be-41ec-819b-0d48576358f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352098767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2352098767
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.143089905
Short name T827
Test name
Test status
Simulation time 22564075 ps
CPU time 0.82 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 206556 kb
Host smart-0bd14129-e420-42d1-8de0-61d6330a4d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143089905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.143089905
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.357152481
Short name T259
Test name
Test status
Simulation time 236222833 ps
CPU time 4.58 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 241508 kb
Host smart-0f70fb28-8284-437b-8de8-8b301049d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357152481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.357152481
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.321074466
Short name T446
Test name
Test status
Simulation time 41597419 ps
CPU time 0.74 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 206128 kb
Host smart-7841f376-c37f-4eaa-b8de-272cc8ef122a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321074466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.321074466
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1886013435
Short name T377
Test name
Test status
Simulation time 811216378 ps
CPU time 3.87 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 233380 kb
Host smart-0254a7f8-41c9-431d-bcee-5c89e0d54bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886013435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1886013435
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.721404653
Short name T29
Test name
Test status
Simulation time 58579561 ps
CPU time 0.77 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 207296 kb
Host smart-53ea90e1-9dc3-4741-b8e3-7cf51b73d3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721404653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.721404653
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1700560513
Short name T1024
Test name
Test status
Simulation time 7313486919 ps
CPU time 56.12 seconds
Started Jul 30 04:49:39 PM PDT 24
Finished Jul 30 04:50:35 PM PDT 24
Peak memory 250256 kb
Host smart-de40b6e8-e67f-4353-8116-4f21a41a2c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700560513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1700560513
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1189021148
Short name T617
Test name
Test status
Simulation time 9385300720 ps
CPU time 58.19 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:50 PM PDT 24
Peak memory 266324 kb
Host smart-da9435b4-d04d-46c0-9be1-3c92600f0ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189021148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1189021148
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3340159609
Short name T561
Test name
Test status
Simulation time 11801639159 ps
CPU time 57.33 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 248968 kb
Host smart-6c978280-6c4c-4f90-a252-89feea320867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340159609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3340159609
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1890766689
Short name T460
Test name
Test status
Simulation time 1123770315 ps
CPU time 5.53 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 225144 kb
Host smart-fd6eb826-6581-42e7-8f3c-eadb7157be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890766689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1890766689
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.46692539
Short name T635
Test name
Test status
Simulation time 13772585 ps
CPU time 0.83 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:49:56 PM PDT 24
Peak memory 216360 kb
Host smart-fc758620-9ef7-4a34-93ae-16e079445c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46692539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.46692539
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.716293014
Short name T104
Test name
Test status
Simulation time 1893820022 ps
CPU time 6.49 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 225156 kb
Host smart-2a30142e-e43b-4323-a30c-f447833abf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716293014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.716293014
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.477711417
Short name T668
Test name
Test status
Simulation time 2332748020 ps
CPU time 13.21 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 233432 kb
Host smart-21f6262d-0217-4256-a4d8-5891f3f176a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477711417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.477711417
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.224667877
Short name T278
Test name
Test status
Simulation time 7910906429 ps
CPU time 10.57 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:14 PM PDT 24
Peak memory 225160 kb
Host smart-25b73e10-d027-499b-b956-20e41b1b10b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224667877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.224667877
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3903261707
Short name T901
Test name
Test status
Simulation time 287188345 ps
CPU time 3.91 seconds
Started Jul 30 04:49:41 PM PDT 24
Finished Jul 30 04:49:45 PM PDT 24
Peak memory 225132 kb
Host smart-51e0734d-39b8-4386-9841-1207563ad9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903261707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3903261707
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3440890812
Short name T621
Test name
Test status
Simulation time 978895907 ps
CPU time 11.01 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:50:06 PM PDT 24
Peak memory 222984 kb
Host smart-8800e5f8-77fb-4acb-92f0-9af94a188bb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440890812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3440890812
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2524820128
Short name T902
Test name
Test status
Simulation time 62750601205 ps
CPU time 132.66 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:52:21 PM PDT 24
Peak memory 260360 kb
Host smart-f6b130b7-c92f-4670-a937-f0ff24833219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524820128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2524820128
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3441548061
Short name T730
Test name
Test status
Simulation time 2781886103 ps
CPU time 13.68 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 216904 kb
Host smart-34b1455d-8e0c-47a3-9f3d-eb2ed1459bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441548061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3441548061
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.676779027
Short name T739
Test name
Test status
Simulation time 1115985256 ps
CPU time 2.31 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 216560 kb
Host smart-e7c210ed-6cee-4cdb-ad79-c5be5f22985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676779027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.676779027
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4196201904
Short name T88
Test name
Test status
Simulation time 69897727 ps
CPU time 1.54 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:04 PM PDT 24
Peak memory 216704 kb
Host smart-bb052e64-39e5-4a14-8d62-0e3fd056bed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196201904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4196201904
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1072991334
Short name T529
Test name
Test status
Simulation time 83413028 ps
CPU time 0.99 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 206400 kb
Host smart-cf232ebe-0649-4db1-8144-ba607138e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072991334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1072991334
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2475520888
Short name T627
Test name
Test status
Simulation time 723738622 ps
CPU time 3.19 seconds
Started Jul 30 04:49:58 PM PDT 24
Finished Jul 30 04:50:01 PM PDT 24
Peak memory 225104 kb
Host smart-3a961f68-c3ed-4331-a0c0-f5e4c358fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475520888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2475520888
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1715562865
Short name T722
Test name
Test status
Simulation time 15058338 ps
CPU time 0.75 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 205304 kb
Host smart-ae2ac601-4954-41a7-a7bb-f59352c6a6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715562865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1715562865
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2428104029
Short name T906
Test name
Test status
Simulation time 68542456 ps
CPU time 2.63 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 233348 kb
Host smart-cbc7688b-790a-4597-be93-b3ff17b0d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428104029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2428104029
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2014308762
Short name T729
Test name
Test status
Simulation time 54499438 ps
CPU time 0.8 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 207308 kb
Host smart-64d3aa46-70cb-49f0-b803-70cf453e121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014308762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2014308762
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1789996624
Short name T356
Test name
Test status
Simulation time 1896359817 ps
CPU time 8.84 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 225120 kb
Host smart-d4527c66-b5bc-45dc-8fa6-602c5160675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789996624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1789996624
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.924849604
Short name T793
Test name
Test status
Simulation time 7906009816 ps
CPU time 34.05 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 225252 kb
Host smart-9d2b44a2-5e1b-4dd5-896d-6903e75ea950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924849604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.924849604
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.747361151
Short name T328
Test name
Test status
Simulation time 156601396 ps
CPU time 3.05 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:50:01 PM PDT 24
Peak memory 233368 kb
Host smart-7d38510a-eb4d-4636-8c58-1d4beba8fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747361151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.747361151
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.434541151
Short name T195
Test name
Test status
Simulation time 16454269848 ps
CPU time 42.86 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 251544 kb
Host smart-667adc06-6f3b-4453-a5f7-0cc5b4c4bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434541151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.434541151
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1132018451
Short name T632
Test name
Test status
Simulation time 6084102270 ps
CPU time 16.08 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 225248 kb
Host smart-b61e2b0f-8186-4aab-9dd1-3528af7198e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132018451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1132018451
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2972918865
Short name T230
Test name
Test status
Simulation time 28129821588 ps
CPU time 58.96 seconds
Started Jul 30 04:50:01 PM PDT 24
Finished Jul 30 04:51:00 PM PDT 24
Peak memory 230132 kb
Host smart-73819918-9422-4afc-8cf6-4d2c66721530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972918865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2972918865
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.847607428
Short name T968
Test name
Test status
Simulation time 5313419696 ps
CPU time 13.74 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 225196 kb
Host smart-e255d3db-e2f0-404e-ba96-778492c8926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847607428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.847607428
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2041513103
Short name T256
Test name
Test status
Simulation time 939602873 ps
CPU time 3.55 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:56 PM PDT 24
Peak memory 225184 kb
Host smart-a9f93c0a-34fa-4363-ab18-db14e16b8803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041513103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2041513103
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3986782777
Short name T785
Test name
Test status
Simulation time 10761802310 ps
CPU time 15.53 seconds
Started Jul 30 04:50:01 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 220608 kb
Host smart-eb2531ec-8c4b-4611-a293-d397a7286611
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986782777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3986782777
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3419512640
Short name T58
Test name
Test status
Simulation time 134552702518 ps
CPU time 386 seconds
Started Jul 30 04:49:56 PM PDT 24
Finished Jul 30 04:56:22 PM PDT 24
Peak memory 274348 kb
Host smart-9c113162-2d31-4f74-ab79-ae1e8eba0182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419512640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3419512640
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2580782677
Short name T488
Test name
Test status
Simulation time 2785862048 ps
CPU time 8.03 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 216900 kb
Host smart-7f39957a-0891-401e-ac32-7f0ab03bc7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580782677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2580782677
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3140340153
Short name T700
Test name
Test status
Simulation time 440225044 ps
CPU time 3.23 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 216812 kb
Host smart-aa2ee75b-95a9-4dd6-9f69-439b762146a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140340153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3140340153
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1580629698
Short name T497
Test name
Test status
Simulation time 157706806 ps
CPU time 1.89 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:55 PM PDT 24
Peak memory 216844 kb
Host smart-7fcf37ee-bca1-4e99-9afc-833f025676d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580629698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1580629698
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.718332735
Short name T806
Test name
Test status
Simulation time 204403209 ps
CPU time 0.9 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 206496 kb
Host smart-994a4398-2218-4291-bacc-aeb0be22325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718332735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.718332735
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.728899821
Short name T856
Test name
Test status
Simulation time 25281264369 ps
CPU time 12.4 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 233400 kb
Host smart-9b3ce435-1191-4020-b4cb-db5dc523dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728899821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.728899821
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2100920491
Short name T863
Test name
Test status
Simulation time 66078408 ps
CPU time 0.68 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 205288 kb
Host smart-353ee714-3cc2-4bae-b915-b81adeb75f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100920491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2100920491
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.667423229
Short name T633
Test name
Test status
Simulation time 61026541 ps
CPU time 2.19 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:04 PM PDT 24
Peak memory 233336 kb
Host smart-5289e736-c236-446f-8a06-69b37ab73d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667423229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.667423229
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4039149846
Short name T509
Test name
Test status
Simulation time 27544753 ps
CPU time 0.77 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 206972 kb
Host smart-339e5cc0-187a-41f4-aa9e-330d0bef8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039149846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4039149846
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1790075421
Short name T776
Test name
Test status
Simulation time 12235323795 ps
CPU time 44.35 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 225204 kb
Host smart-953945bb-c9d3-448d-b01a-d7237b103536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790075421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1790075421
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1617529667
Short name T223
Test name
Test status
Simulation time 9216339870 ps
CPU time 62.88 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:50:54 PM PDT 24
Peak memory 241688 kb
Host smart-6a2a1bd0-b0a1-42c5-b1d1-eba0453fb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617529667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1617529667
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1859561769
Short name T612
Test name
Test status
Simulation time 4880436969 ps
CPU time 16.95 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 225324 kb
Host smart-5a1203d5-5014-4b51-9c94-d9d7e3a31d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859561769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1859561769
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3392196440
Short name T337
Test name
Test status
Simulation time 1888657188 ps
CPU time 9.72 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:13 PM PDT 24
Peak memory 233336 kb
Host smart-165e334d-5fc5-4ee5-ba76-58b28d11a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392196440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3392196440
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3538474832
Short name T814
Test name
Test status
Simulation time 68897755701 ps
CPU time 76.12 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 250932 kb
Host smart-b7af2cb1-54db-4c78-b1d0-b0882c52bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538474832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3538474832
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.667317659
Short name T495
Test name
Test status
Simulation time 14319601764 ps
CPU time 22.44 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:15 PM PDT 24
Peak memory 233376 kb
Host smart-8b80e348-6716-4f34-b7e2-1528d4d80216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667317659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.667317659
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2117013920
Short name T371
Test name
Test status
Simulation time 58394891 ps
CPU time 2.11 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 232944 kb
Host smart-8c71ce8c-9ee2-479a-ad90-59c9e0db290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117013920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2117013920
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2827411297
Short name T266
Test name
Test status
Simulation time 928020232 ps
CPU time 8.07 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 233332 kb
Host smart-28a8ff80-ccb4-4a13-a136-12a16a221b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827411297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2827411297
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.541079515
Short name T716
Test name
Test status
Simulation time 700359699 ps
CPU time 4.45 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 225072 kb
Host smart-f1e9e7c8-1a35-4367-9c1e-46f5fe17f57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541079515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.541079515
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.235595244
Short name T454
Test name
Test status
Simulation time 722703394 ps
CPU time 5.1 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 223716 kb
Host smart-c1d867b1-de49-4b50-a0da-f97d3512e57a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=235595244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.235595244
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2038292595
Short name T205
Test name
Test status
Simulation time 17142772926 ps
CPU time 261.86 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:54:27 PM PDT 24
Peak memory 284820 kb
Host smart-fcda4589-f37b-4105-a2bb-44f0a82d324f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038292595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2038292595
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2589077892
Short name T681
Test name
Test status
Simulation time 1782436811 ps
CPU time 27.98 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 220724 kb
Host smart-30599243-1455-4543-8931-3bb45b5439c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589077892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2589077892
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.904212305
Short name T849
Test name
Test status
Simulation time 8729731133 ps
CPU time 16.06 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 216928 kb
Host smart-d2bcd9b8-4f87-4e01-afc1-178c8e7ed3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904212305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.904212305
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1069109518
Short name T318
Test name
Test status
Simulation time 311851608 ps
CPU time 1.95 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 216940 kb
Host smart-2871e64d-c281-4b22-9fd0-843b96b7a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069109518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1069109518
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1932824517
Short name T369
Test name
Test status
Simulation time 39097960 ps
CPU time 0.8 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 206488 kb
Host smart-100e389d-c94d-4c9d-8380-04d22cc23fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932824517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1932824517
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2271905496
Short name T406
Test name
Test status
Simulation time 322642410 ps
CPU time 2.49 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 225104 kb
Host smart-748486dd-875f-420e-953d-c7ed59abb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271905496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2271905496
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2831760549
Short name T689
Test name
Test status
Simulation time 14265174 ps
CPU time 0.72 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 206208 kb
Host smart-606a18f0-b4ce-4c19-af90-12fc0ff184c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831760549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2831760549
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2726476745
Short name T772
Test name
Test status
Simulation time 232104424 ps
CPU time 2.84 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 233332 kb
Host smart-1e5c6659-01ed-4e13-a4fa-4ffb85f1e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726476745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2726476745
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2892449981
Short name T715
Test name
Test status
Simulation time 60806599 ps
CPU time 0.81 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 205964 kb
Host smart-495616e4-5c15-47e3-a622-f1d313ba730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892449981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2892449981
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4106346320
Short name T513
Test name
Test status
Simulation time 777182971 ps
CPU time 4.66 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 234484 kb
Host smart-96863b95-e728-4702-99cc-a07450de228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106346320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4106346320
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3523844160
Short name T206
Test name
Test status
Simulation time 26312147441 ps
CPU time 201.03 seconds
Started Jul 30 04:50:00 PM PDT 24
Finished Jul 30 04:53:21 PM PDT 24
Peak memory 241720 kb
Host smart-97a29dd8-24d1-4e5d-af60-83d402a3dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523844160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3523844160
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.165251263
Short name T244
Test name
Test status
Simulation time 33442268873 ps
CPU time 127.62 seconds
Started Jul 30 04:49:59 PM PDT 24
Finished Jul 30 04:52:07 PM PDT 24
Peak memory 249920 kb
Host smart-0e353ce5-8fdb-43ea-9dd4-dbee0276e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165251263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.165251263
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1050548723
Short name T305
Test name
Test status
Simulation time 3483060160 ps
CPU time 16.54 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 249832 kb
Host smart-a3a0c6e6-c8aa-4633-82bf-afdbf355bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050548723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1050548723
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1325250198
Short name T709
Test name
Test status
Simulation time 21366223664 ps
CPU time 56.89 seconds
Started Jul 30 04:50:21 PM PDT 24
Finished Jul 30 04:51:18 PM PDT 24
Peak memory 251328 kb
Host smart-4dbd9353-921e-4daf-bb89-d01a4f167b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325250198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1325250198
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2288724931
Short name T941
Test name
Test status
Simulation time 9667637745 ps
CPU time 22.31 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 233384 kb
Host smart-5dfad766-570c-4ffd-88fe-c122ddafb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288724931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2288724931
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2081351409
Short name T966
Test name
Test status
Simulation time 9713354999 ps
CPU time 18.08 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 233536 kb
Host smart-8eb96d4d-4cb7-479d-ab0a-e7ca082d50cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081351409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2081351409
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.828895326
Short name T580
Test name
Test status
Simulation time 6281341921 ps
CPU time 9.31 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:50:06 PM PDT 24
Peak memory 233388 kb
Host smart-f56172d8-dc81-4450-973a-3e066de65001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828895326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.828895326
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2862474311
Short name T613
Test name
Test status
Simulation time 2431442334 ps
CPU time 9 seconds
Started Jul 30 04:49:58 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 225208 kb
Host smart-ddb7e3ed-0e0a-4149-9456-d2cb9c5a3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862474311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2862474311
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2510625387
Short name T664
Test name
Test status
Simulation time 2465694080 ps
CPU time 5.54 seconds
Started Jul 30 04:49:48 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 221752 kb
Host smart-e79f22bb-4c20-4241-9504-30720cbde192
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2510625387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2510625387
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2690439629
Short name T17
Test name
Test status
Simulation time 12207046082 ps
CPU time 118.97 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:51:51 PM PDT 24
Peak memory 274228 kb
Host smart-7a67b9c3-d006-44c6-93de-5906cbd3fb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690439629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2690439629
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4228966750
Short name T987
Test name
Test status
Simulation time 984196802 ps
CPU time 10.54 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 216988 kb
Host smart-bd776712-f8fc-4ecd-83a2-3480b904c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228966750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4228966750
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1822551408
Short name T392
Test name
Test status
Simulation time 3350634334 ps
CPU time 6.77 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 217004 kb
Host smart-d4b7cf80-b55e-4bd7-a6db-3258b462e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822551408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1822551408
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2937952472
Short name T147
Test name
Test status
Simulation time 833516048 ps
CPU time 1.97 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 216860 kb
Host smart-095e9d9f-3541-45cf-aa7c-7f397d96a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937952472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2937952472
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3989235851
Short name T699
Test name
Test status
Simulation time 50129620 ps
CPU time 0.9 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:49:51 PM PDT 24
Peak memory 206444 kb
Host smart-2e8bcb62-5de8-4282-9069-e2303ae808a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989235851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3989235851
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3309573828
Short name T598
Test name
Test status
Simulation time 1451822938 ps
CPU time 4.14 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:49:58 PM PDT 24
Peak memory 225192 kb
Host smart-365709b7-a411-45f4-adac-9dd42eb21ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309573828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3309573828
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2219577695
Short name T999
Test name
Test status
Simulation time 50252847 ps
CPU time 0.74 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:13 PM PDT 24
Peak memory 205116 kb
Host smart-713b4418-90d8-4181-a667-2ef3ed5d4745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219577695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2219577695
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3114672388
Short name T877
Test name
Test status
Simulation time 166289662 ps
CPU time 3.7 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:10 PM PDT 24
Peak memory 225120 kb
Host smart-4c32f520-e3b3-4576-8dfb-48fc4ff3a851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114672388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3114672388
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1163776460
Short name T413
Test name
Test status
Simulation time 117384077 ps
CPU time 0.77 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:10 PM PDT 24
Peak memory 207020 kb
Host smart-d67e6198-c8ba-4024-8cac-be631dcc31e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163776460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1163776460
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3415282
Short name T293
Test name
Test status
Simulation time 4041889273 ps
CPU time 84.8 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:51:19 PM PDT 24
Peak memory 264800 kb
Host smart-7fe33178-5b0c-4acf-829f-a859ac8e4e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3415282
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4039039456
Short name T317
Test name
Test status
Simulation time 8400540335 ps
CPU time 12.68 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:24 PM PDT 24
Peak memory 218340 kb
Host smart-410e3320-4669-43a1-846e-bc870735aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039039456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4039039456
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1791696293
Short name T845
Test name
Test status
Simulation time 29039860208 ps
CPU time 101.4 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:52:01 PM PDT 24
Peak memory 258020 kb
Host smart-97733955-b41c-470a-89ff-906246fcef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791696293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1791696293
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2522376095
Short name T303
Test name
Test status
Simulation time 6868557262 ps
CPU time 21.54 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 233444 kb
Host smart-e377457a-5a42-4966-b074-833f1a3b4573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522376095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2522376095
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3982397951
Short name T913
Test name
Test status
Simulation time 22804527987 ps
CPU time 149.69 seconds
Started Jul 30 04:49:55 PM PDT 24
Finished Jul 30 04:52:25 PM PDT 24
Peak memory 249876 kb
Host smart-3724531c-c6d5-4d5d-a384-fc9ef4aeda09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982397951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3982397951
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1470947386
Short name T848
Test name
Test status
Simulation time 771940280 ps
CPU time 4.64 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 225228 kb
Host smart-e4c9094a-c7fc-4246-b0c1-d8cc18f1cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470947386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1470947386
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.74077583
Short name T994
Test name
Test status
Simulation time 12175373564 ps
CPU time 24.31 seconds
Started Jul 30 04:49:59 PM PDT 24
Finished Jul 30 04:50:24 PM PDT 24
Peak memory 233464 kb
Host smart-315e2f9f-6efa-42de-b076-73149d7579d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74077583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.74077583
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1533537265
Short name T1005
Test name
Test status
Simulation time 18075850591 ps
CPU time 15.06 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 233360 kb
Host smart-4b00ceb7-e7b0-4098-a179-b0785f97796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533537265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1533537265
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4179977857
Short name T514
Test name
Test status
Simulation time 31897430901 ps
CPU time 8.71 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:11 PM PDT 24
Peak memory 225244 kb
Host smart-246ecf8b-6f86-4489-890d-e8659b6fa25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179977857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4179977857
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3858172018
Short name T808
Test name
Test status
Simulation time 576935747 ps
CPU time 4.12 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:06 PM PDT 24
Peak memory 220184 kb
Host smart-54b97237-44ae-4a6c-b32e-24ac97f7566b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3858172018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3858172018
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1021181937
Short name T483
Test name
Test status
Simulation time 128448984 ps
CPU time 1.11 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 208156 kb
Host smart-c4a24f22-a873-4614-91d0-78a9ab6b61c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021181937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1021181937
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4032001724
Short name T330
Test name
Test status
Simulation time 11199089 ps
CPU time 0.7 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 206048 kb
Host smart-b7ac758c-2807-40f7-b568-e8304b1cd06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032001724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4032001724
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3224502405
Short name T407
Test name
Test status
Simulation time 12366544711 ps
CPU time 5.19 seconds
Started Jul 30 04:49:52 PM PDT 24
Finished Jul 30 04:49:57 PM PDT 24
Peak memory 216920 kb
Host smart-73491183-56ef-4118-b4ee-6d7c5689248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224502405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3224502405
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.368921813
Short name T425
Test name
Test status
Simulation time 18836514 ps
CPU time 0.71 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 206028 kb
Host smart-0f2c3113-459f-471f-a7b3-e16370a141bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368921813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.368921813
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3305064555
Short name T840
Test name
Test status
Simulation time 176146992 ps
CPU time 0.99 seconds
Started Jul 30 04:49:51 PM PDT 24
Finished Jul 30 04:49:52 PM PDT 24
Peak memory 207468 kb
Host smart-71f8b567-2309-4426-b911-0fd46fc15a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305064555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3305064555
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4248762236
Short name T927
Test name
Test status
Simulation time 222013312 ps
CPU time 2.56 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:49:56 PM PDT 24
Peak memory 233376 kb
Host smart-132be648-0cbc-4e1b-9901-ab048e27d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248762236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4248762236
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4276978738
Short name T445
Test name
Test status
Simulation time 95335912 ps
CPU time 0.72 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 205216 kb
Host smart-271d1b7d-6610-45e9-a47f-10af07a01a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276978738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4276978738
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2832766781
Short name T951
Test name
Test status
Simulation time 60134867 ps
CPU time 3.13 seconds
Started Jul 30 04:49:50 PM PDT 24
Finished Jul 30 04:49:54 PM PDT 24
Peak memory 233388 kb
Host smart-cb0be201-7c12-497a-89d6-a788b9ee1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832766781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2832766781
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.53221075
Short name T571
Test name
Test status
Simulation time 23183827 ps
CPU time 0.76 seconds
Started Jul 30 04:50:22 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 205932 kb
Host smart-698b0cd8-06f9-41df-af8b-ec4a6961b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53221075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.53221075
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3510934516
Short name T876
Test name
Test status
Simulation time 15586281948 ps
CPU time 59.85 seconds
Started Jul 30 04:50:14 PM PDT 24
Finished Jul 30 04:51:14 PM PDT 24
Peak memory 249832 kb
Host smart-27f14bfa-c8cb-4d50-a327-8a5452c00548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510934516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3510934516
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2015035993
Short name T243
Test name
Test status
Simulation time 31515262395 ps
CPU time 228.24 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:53:54 PM PDT 24
Peak memory 264572 kb
Host smart-279c414a-0f77-4002-bbce-28f9d8a50ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015035993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2015035993
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.686107395
Short name T200
Test name
Test status
Simulation time 7577823253 ps
CPU time 101.16 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:51:53 PM PDT 24
Peak memory 266236 kb
Host smart-3a299a5d-0257-4671-a999-3eca144f30e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686107395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.686107395
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3989678330
Short name T487
Test name
Test status
Simulation time 1047684534 ps
CPU time 3.77 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 233412 kb
Host smart-e1e0a681-2256-421e-b0c4-3503e880971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989678330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3989678330
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2089168555
Short name T618
Test name
Test status
Simulation time 288308750119 ps
CPU time 188.45 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:53:13 PM PDT 24
Peak memory 252252 kb
Host smart-fe476beb-8c68-4ab5-a98c-8eb27b379c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089168555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2089168555
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.214898443
Short name T250
Test name
Test status
Simulation time 19758532067 ps
CPU time 15.21 seconds
Started Jul 30 04:50:17 PM PDT 24
Finished Jul 30 04:50:32 PM PDT 24
Peak memory 225104 kb
Host smart-006755b3-90d4-4228-8974-4c8ba4e2ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214898443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.214898443
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1488288176
Short name T680
Test name
Test status
Simulation time 550406423 ps
CPU time 5.85 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:14 PM PDT 24
Peak memory 225084 kb
Host smart-77e447c8-4c6f-46c5-9d4f-e0b0e911feef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488288176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1488288176
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2947860667
Short name T48
Test name
Test status
Simulation time 27169768611 ps
CPU time 27.39 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:30 PM PDT 24
Peak memory 237372 kb
Host smart-ce3c2ed7-36d1-407a-aeaa-446bbf342d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947860667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2947860667
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3001713956
Short name T655
Test name
Test status
Simulation time 244170760 ps
CPU time 3.49 seconds
Started Jul 30 04:49:49 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 233424 kb
Host smart-e3952fa3-4706-4324-91e0-f99aa8fbb6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001713956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3001713956
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1218272666
Short name T809
Test name
Test status
Simulation time 3719189870 ps
CPU time 10.69 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 219772 kb
Host smart-790c7406-8c15-493b-80bc-5d5de2fd62de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1218272666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1218272666
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2000986250
Short name T532
Test name
Test status
Simulation time 125098855 ps
CPU time 0.95 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 206924 kb
Host smart-03a86aa4-bcbb-49c9-8c39-971a935adc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000986250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2000986250
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.749257026
Short name T386
Test name
Test status
Simulation time 652499470 ps
CPU time 9.79 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 217232 kb
Host smart-e915b492-91f9-4739-9f43-bf9b8a464793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749257026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.749257026
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1522880654
Short name T99
Test name
Test status
Simulation time 950979316 ps
CPU time 5.65 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 216956 kb
Host smart-3a8833f9-413d-4a12-a788-0846222d1566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522880654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1522880654
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.165250495
Short name T361
Test name
Test status
Simulation time 165127758 ps
CPU time 1.01 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 207560 kb
Host smart-329faa9e-5e2d-4011-9538-77cba37f5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165250495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.165250495
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2812373000
Short name T439
Test name
Test status
Simulation time 57235895 ps
CPU time 0.79 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:50:10 PM PDT 24
Peak memory 206424 kb
Host smart-ff430e28-1c07-4a65-bbe5-affa0e7f1fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812373000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2812373000
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.856930521
Short name T452
Test name
Test status
Simulation time 2248613096 ps
CPU time 9.69 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 240316 kb
Host smart-cf9a7614-c935-4ee8-acca-923a0c8a7278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856930521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.856930521
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1816847431
Short name T399
Test name
Test status
Simulation time 15345102 ps
CPU time 0.74 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 205164 kb
Host smart-6df1a3b3-6b5d-44c5-a4dc-4675ca920dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816847431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
816847431
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.421546504
Short name T515
Test name
Test status
Simulation time 31090268 ps
CPU time 2.19 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 232976 kb
Host smart-5c700335-7d95-41e6-8780-417d4d30b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421546504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.421546504
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3315245302
Short name T500
Test name
Test status
Simulation time 89185909 ps
CPU time 0.74 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 205900 kb
Host smart-c8740c80-eecd-48c0-8dc6-15420980ea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315245302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3315245302
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3601465896
Short name T637
Test name
Test status
Simulation time 30017561076 ps
CPU time 213.39 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:52:27 PM PDT 24
Peak memory 256536 kb
Host smart-a4328537-fdcc-42b1-aadb-923609b30259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601465896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3601465896
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3595043242
Short name T784
Test name
Test status
Simulation time 521024864062 ps
CPU time 471.87 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:57:00 PM PDT 24
Peak memory 273564 kb
Host smart-9aa9f3a0-35a9-42a5-a8e0-902ce26e5e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595043242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3595043242
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3118670864
Short name T922
Test name
Test status
Simulation time 28655594528 ps
CPU time 226.45 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:52:40 PM PDT 24
Peak memory 249944 kb
Host smart-f81cff51-d4b1-427a-9dd7-325ac1ab25ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118670864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3118670864
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3507486240
Short name T309
Test name
Test status
Simulation time 287896186 ps
CPU time 10.44 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:04 PM PDT 24
Peak memory 225064 kb
Host smart-229c6fea-6377-4e7c-b000-33deec1da62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507486240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3507486240
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2418880503
Short name T973
Test name
Test status
Simulation time 336678594 ps
CPU time 5.88 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 233376 kb
Host smart-fda3a03a-21fd-4b11-9961-7963d2658d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418880503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2418880503
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3291732783
Short name T767
Test name
Test status
Simulation time 21486978804 ps
CPU time 26.37 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 219336 kb
Host smart-4b36f542-eb92-4f9f-aec1-e0dd626e687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291732783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3291732783
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1352147447
Short name T815
Test name
Test status
Simulation time 345093595 ps
CPU time 10.38 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 233400 kb
Host smart-b9a97942-e6ae-480f-a735-04fe414d723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352147447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1352147447
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3091899159
Short name T510
Test name
Test status
Simulation time 28650000 ps
CPU time 1.09 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 217120 kb
Host smart-cc70d738-feff-4a44-acbb-f4c4f2c273b0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091899159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3091899159
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3732230756
Short name T234
Test name
Test status
Simulation time 12698126424 ps
CPU time 11.47 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:05 PM PDT 24
Peak memory 241156 kb
Host smart-683e95d9-072a-4be8-b3c2-4c8a8296ada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732230756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3732230756
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1949540407
Short name T887
Test name
Test status
Simulation time 42548385030 ps
CPU time 18.95 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 233356 kb
Host smart-bf8ab796-d6e3-4c9f-8d7d-b8d28af5d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949540407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1949540407
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3921624645
Short name T164
Test name
Test status
Simulation time 4525746075 ps
CPU time 15.09 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:49:05 PM PDT 24
Peak memory 223712 kb
Host smart-aca6efab-e089-4b30-98bf-6b679c3b61c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3921624645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3921624645
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2465969733
Short name T80
Test name
Test status
Simulation time 933461766 ps
CPU time 1.19 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:58 PM PDT 24
Peak memory 235572 kb
Host smart-e34eadb8-a77b-4fff-adf6-a53554ce2a9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465969733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2465969733
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3961799336
Short name T172
Test name
Test status
Simulation time 48489104617 ps
CPU time 241.31 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:53:05 PM PDT 24
Peak memory 267208 kb
Host smart-052e0b56-94dc-437d-be33-e64fec3c99ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961799336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3961799336
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2841292690
Short name T470
Test name
Test status
Simulation time 4049544247 ps
CPU time 15.57 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 217016 kb
Host smart-775021ef-2f81-45b9-8c6c-58150e09cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841292690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2841292690
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1373763155
Short name T511
Test name
Test status
Simulation time 1171275793 ps
CPU time 5.35 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 216936 kb
Host smart-584bc679-57c8-4b6a-b302-59090cef6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373763155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1373763155
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.948532137
Short name T527
Test name
Test status
Simulation time 16696248 ps
CPU time 0.73 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 206000 kb
Host smart-182f8b69-ffe6-4a59-941e-4f4c1a20a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948532137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.948532137
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3743259343
Short name T895
Test name
Test status
Simulation time 228924558 ps
CPU time 0.91 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:55 PM PDT 24
Peak memory 206452 kb
Host smart-86b03657-112e-4078-91ca-39175dd267cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743259343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3743259343
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.135332685
Short name T471
Test name
Test status
Simulation time 5375317662 ps
CPU time 20.36 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 233448 kb
Host smart-51f8c902-f61f-4ebf-b5c5-dee97277d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135332685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.135332685
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.404748265
Short name T893
Test name
Test status
Simulation time 13384274 ps
CPU time 0.69 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:03 PM PDT 24
Peak memory 205780 kb
Host smart-e178538a-28f2-4c8a-8c14-d0b2d01d1d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404748265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.404748265
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3371985860
Short name T727
Test name
Test status
Simulation time 465533305 ps
CPU time 8.79 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 233356 kb
Host smart-202cb980-b794-4418-8d7f-c3f2da54b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371985860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3371985860
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3607482199
Short name T662
Test name
Test status
Simulation time 59347999 ps
CPU time 0.75 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 206264 kb
Host smart-e7b6b78e-7afd-40cd-8d19-4dc4701f864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607482199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3607482199
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2385802652
Short name T57
Test name
Test status
Simulation time 11584771948 ps
CPU time 41.05 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 237884 kb
Host smart-9e1b9f9a-9fc0-46e7-bcb8-94b8cac77678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385802652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2385802652
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.162124020
Short name T926
Test name
Test status
Simulation time 8633359611 ps
CPU time 32.96 seconds
Started Jul 30 04:49:54 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 251920 kb
Host smart-1569a703-3189-4ec4-8635-ac11cab3c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162124020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.162124020
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1054302333
Short name T708
Test name
Test status
Simulation time 1770796370 ps
CPU time 38.03 seconds
Started Jul 30 04:50:02 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 241632 kb
Host smart-392b4b5d-b1d4-4621-a2b5-1c962c19fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054302333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1054302333
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1003374006
Short name T300
Test name
Test status
Simulation time 1696356360 ps
CPU time 28.14 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:50:47 PM PDT 24
Peak memory 236088 kb
Host smart-3b56f1e8-550b-40d6-8d43-d94cb8d30418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003374006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1003374006
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3770280909
Short name T585
Test name
Test status
Simulation time 5759064008 ps
CPU time 9.95 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 225200 kb
Host smart-b2e7eee8-e520-43bb-aaa2-5d0efc360128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770280909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3770280909
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.946480372
Short name T917
Test name
Test status
Simulation time 406308094 ps
CPU time 3.89 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 233324 kb
Host smart-53f8a71b-2f76-43de-85c1-301dcec73df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946480372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.946480372
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2365146019
Short name T180
Test name
Test status
Simulation time 372258041 ps
CPU time 7.59 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:15 PM PDT 24
Peak memory 237288 kb
Host smart-cf245baf-177b-4696-a6dd-fe3094ccea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365146019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2365146019
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2058696639
Short name T295
Test name
Test status
Simulation time 1191068575 ps
CPU time 6.34 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:14 PM PDT 24
Peak memory 240516 kb
Host smart-4a623434-8fee-4007-88e9-ba684cd09db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058696639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2058696639
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1959608677
Short name T251
Test name
Test status
Simulation time 5715175515 ps
CPU time 17.46 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 233400 kb
Host smart-ee52a9a7-9161-438b-8442-79934bcf0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959608677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1959608677
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3757874372
Short name T480
Test name
Test status
Simulation time 807612735 ps
CPU time 12.2 seconds
Started Jul 30 04:49:57 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 220276 kb
Host smart-e183df2b-5f01-488c-b9df-ae2dd4220ea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757874372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3757874372
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2144212108
Short name T249
Test name
Test status
Simulation time 19765297165 ps
CPU time 192.75 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:53:18 PM PDT 24
Peak memory 257632 kb
Host smart-2eb8e768-9f09-4fdf-b5d3-a60151e4158c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144212108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2144212108
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.923580167
Short name T920
Test name
Test status
Simulation time 7090006875 ps
CPU time 39.81 seconds
Started Jul 30 04:49:53 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 217184 kb
Host smart-0defe123-e462-44e3-9192-5af500abde5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923580167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.923580167
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.169291893
Short name T498
Test name
Test status
Simulation time 787066785 ps
CPU time 3.29 seconds
Started Jul 30 04:50:01 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 216884 kb
Host smart-29bf3af1-baa6-46e2-be69-99d7ffd8fd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169291893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.169291893
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.841307089
Short name T389
Test name
Test status
Simulation time 16971619 ps
CPU time 1.09 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 216656 kb
Host smart-4e85f269-6717-4f28-9a00-7a94dced841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841307089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.841307089
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1727344944
Short name T829
Test name
Test status
Simulation time 191352180 ps
CPU time 0.96 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 206512 kb
Host smart-ff98b74c-a4fd-4110-985a-0aaedadfb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727344944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1727344944
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3057097754
Short name T216
Test name
Test status
Simulation time 24363196504 ps
CPU time 11.4 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 258008 kb
Host smart-c0b993b8-672a-4290-9b6e-b56a0a70de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057097754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3057097754
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1616737034
Short name T850
Test name
Test status
Simulation time 24934970 ps
CPU time 0.72 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 206032 kb
Host smart-33653b87-4813-4177-bce1-053fe847bb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616737034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1616737034
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3957935670
Short name T682
Test name
Test status
Simulation time 521536494 ps
CPU time 8.14 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 233268 kb
Host smart-2282cacf-d4cb-4d58-876f-deda702fd2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957935670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3957935670
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3962841213
Short name T929
Test name
Test status
Simulation time 59972545 ps
CPU time 0.85 seconds
Started Jul 30 04:49:58 PM PDT 24
Finished Jul 30 04:49:59 PM PDT 24
Peak memory 206980 kb
Host smart-7b27cc29-d583-488f-bf52-21d2b594b0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962841213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3962841213
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3361140022
Short name T203
Test name
Test status
Simulation time 34094224290 ps
CPU time 237.6 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:54:04 PM PDT 24
Peak memory 257896 kb
Host smart-f2ed89c2-a1b6-4a25-97d6-1a9609501357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361140022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3361140022
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.414689982
Short name T1019
Test name
Test status
Simulation time 8185490164 ps
CPU time 93.37 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:51:41 PM PDT 24
Peak memory 257988 kb
Host smart-4803a2d6-35a9-455d-99fc-d5b013b79bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414689982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.414689982
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4105790519
Short name T227
Test name
Test status
Simulation time 12569981050 ps
CPU time 49.15 seconds
Started Jul 30 04:50:16 PM PDT 24
Finished Jul 30 04:51:05 PM PDT 24
Peak memory 258040 kb
Host smart-63a17382-bf28-41bb-998b-c46a3aec28e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105790519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4105790519
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.994863402
Short name T339
Test name
Test status
Simulation time 148437964 ps
CPU time 2.69 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 233184 kb
Host smart-cb2997f1-8cd5-49fa-822f-a0ff62d16b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994863402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.994863402
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.704662942
Short name T964
Test name
Test status
Simulation time 36667196051 ps
CPU time 140.07 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:52:29 PM PDT 24
Peak memory 249808 kb
Host smart-5e8602b0-849f-40c3-a79b-76ce78cd2661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704662942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.704662942
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1125812860
Short name T374
Test name
Test status
Simulation time 227868666 ps
CPU time 5.03 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 233420 kb
Host smart-d8273238-ebe9-40c8-bc8c-d9a4912dc478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125812860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1125812860
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1480894439
Short name T378
Test name
Test status
Simulation time 1810774392 ps
CPU time 18.43 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 225196 kb
Host smart-891425d3-10f9-4705-9649-866aeff2602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480894439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1480894439
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3710913467
Short name T740
Test name
Test status
Simulation time 8699687528 ps
CPU time 15.57 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 233364 kb
Host smart-613eaea0-7076-4359-8a39-c07409644973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710913467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3710913467
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2043646312
Short name T981
Test name
Test status
Simulation time 148684955 ps
CPU time 2.89 seconds
Started Jul 30 04:49:56 PM PDT 24
Finished Jul 30 04:49:59 PM PDT 24
Peak memory 233340 kb
Host smart-52d58d43-48a9-4092-86e5-8cdab571f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043646312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2043646312
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.755257159
Short name T862
Test name
Test status
Simulation time 1030788572 ps
CPU time 15.66 seconds
Started Jul 30 04:50:17 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 219804 kb
Host smart-70d8142c-9d59-47cc-8b62-2d01dbe87bd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=755257159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.755257159
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3916254408
Short name T170
Test name
Test status
Simulation time 19229474118 ps
CPU time 144.12 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:52:29 PM PDT 24
Peak memory 258092 kb
Host smart-ee9f76ed-3558-459e-ae86-ddee4b9a9a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916254408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3916254408
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1675459483
Short name T588
Test name
Test status
Simulation time 1590966921 ps
CPU time 5.44 seconds
Started Jul 30 04:49:59 PM PDT 24
Finished Jul 30 04:50:04 PM PDT 24
Peak memory 217064 kb
Host smart-28b3ef29-8fac-4718-b093-2fe93f3a2bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675459483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1675459483
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1236535088
Short name T64
Test name
Test status
Simulation time 814534368 ps
CPU time 6.83 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:11 PM PDT 24
Peak memory 216836 kb
Host smart-9949c75d-e282-485b-b910-149a808f2cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236535088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1236535088
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1448795022
Short name T431
Test name
Test status
Simulation time 583811562 ps
CPU time 3.3 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:50:06 PM PDT 24
Peak memory 216948 kb
Host smart-4471a27a-90da-4c3f-9a6c-c96847208828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448795022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1448795022
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3860770652
Short name T366
Test name
Test status
Simulation time 140505307 ps
CPU time 0.87 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:14 PM PDT 24
Peak memory 206328 kb
Host smart-aa5d0197-60d5-4236-9cb0-cae661f4a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860770652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3860770652
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.413541472
Short name T714
Test name
Test status
Simulation time 1248227799 ps
CPU time 4.74 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:50:13 PM PDT 24
Peak memory 232764 kb
Host smart-9a2deb70-f0e9-4ce6-9b1e-e46632243fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413541472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.413541472
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2808583452
Short name T868
Test name
Test status
Simulation time 13847319 ps
CPU time 0.75 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 205204 kb
Host smart-945552cd-5dd6-409f-8d3a-a31a5eee9622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808583452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2808583452
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.270516813
Short name T199
Test name
Test status
Simulation time 89504753 ps
CPU time 2.65 seconds
Started Jul 30 04:50:20 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 233376 kb
Host smart-6ec061c5-d4d3-4ec8-9092-5f05c0c13471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270516813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.270516813
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.381545272
Short name T782
Test name
Test status
Simulation time 20040304 ps
CPU time 0.81 seconds
Started Jul 30 04:50:16 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 206964 kb
Host smart-2841177f-fcc8-40cf-a2b5-5ba2d2ed5ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381545272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.381545272
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3224985252
Short name T271
Test name
Test status
Simulation time 69687014084 ps
CPU time 174.63 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:53:01 PM PDT 24
Peak memory 249840 kb
Host smart-bc88c1dc-93e2-4e5d-a0d0-cb53ef7451dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224985252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3224985252
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.158226021
Short name T704
Test name
Test status
Simulation time 39756826252 ps
CPU time 94.92 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:51:50 PM PDT 24
Peak memory 257144 kb
Host smart-f36dfd3f-9518-40f0-8c65-72433cc3f693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158226021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.158226021
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1906532221
Short name T879
Test name
Test status
Simulation time 21627817386 ps
CPU time 209.82 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:53:37 PM PDT 24
Peak memory 255268 kb
Host smart-5c8ff188-09e4-4771-b080-e5122261fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906532221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1906532221
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1346422708
Short name T579
Test name
Test status
Simulation time 585637095 ps
CPU time 4.47 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:50:31 PM PDT 24
Peak memory 225096 kb
Host smart-b4fdd3b2-0f05-4a27-b7f2-10b77ca3ff40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346422708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1346422708
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3799037738
Short name T27
Test name
Test status
Simulation time 54314153907 ps
CPU time 121.73 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:52:09 PM PDT 24
Peak memory 253288 kb
Host smart-fcdb5ba9-797d-476d-9b9b-055a0ebce07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799037738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3799037738
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3183034030
Short name T984
Test name
Test status
Simulation time 331377011 ps
CPU time 5.63 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 225084 kb
Host smart-f314989f-99d4-490c-81fe-7e55b41dd684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183034030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3183034030
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1860279364
Short name T506
Test name
Test status
Simulation time 102662449453 ps
CPU time 62.04 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 249668 kb
Host smart-ee66b6a4-b1da-4783-a2e7-8749d53a5264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860279364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1860279364
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3631913602
Short name T82
Test name
Test status
Simulation time 210684178 ps
CPU time 2.75 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 225108 kb
Host smart-8ce91736-f76f-4294-9526-f442868ea333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631913602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3631913602
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.498801339
Short name T235
Test name
Test status
Simulation time 1245055259 ps
CPU time 4.6 seconds
Started Jul 30 04:50:16 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 225136 kb
Host smart-87022890-bf74-4099-a9ee-6c9a8888b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498801339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.498801339
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3030655008
Short name T751
Test name
Test status
Simulation time 1189777368 ps
CPU time 5.61 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 221020 kb
Host smart-012ce7bf-79de-466c-a024-e9a111b58d94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030655008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3030655008
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1280613611
Short name T202
Test name
Test status
Simulation time 5236186024 ps
CPU time 70.37 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:51:44 PM PDT 24
Peak memory 257756 kb
Host smart-f8127e29-24f6-4b30-94e5-1b87366d74ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280613611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1280613611
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3012853648
Short name T800
Test name
Test status
Simulation time 5745760229 ps
CPU time 32.76 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 216944 kb
Host smart-db0952ee-a11c-488e-a462-6ec0ec51441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012853648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3012853648
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.401810674
Short name T867
Test name
Test status
Simulation time 3165295989 ps
CPU time 10.36 seconds
Started Jul 30 04:50:23 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 216976 kb
Host smart-abd231eb-b1d3-4723-a5a2-6c32de7bc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401810674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.401810674
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1797497599
Short name T947
Test name
Test status
Simulation time 40283808 ps
CPU time 1.27 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 216892 kb
Host smart-fbab9007-951c-4633-bf28-bd84c295dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797497599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1797497599
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2590982660
Short name T336
Test name
Test status
Simulation time 134307778 ps
CPU time 0.85 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 206488 kb
Host smart-ea31c311-8f52-437d-a2a5-a0934ca1a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590982660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2590982660
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1479855709
Short name T1
Test name
Test status
Simulation time 1569691789 ps
CPU time 2.98 seconds
Started Jul 30 04:50:30 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 233352 kb
Host smart-67d66168-e751-4bc5-94ca-0f242c7ae8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479855709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1479855709
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.847383029
Short name T770
Test name
Test status
Simulation time 13496880 ps
CPU time 0.69 seconds
Started Jul 30 04:50:36 PM PDT 24
Finished Jul 30 04:50:37 PM PDT 24
Peak memory 205768 kb
Host smart-5707055a-d132-4dfa-8806-a75020d4e988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847383029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.847383029
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.700688696
Short name T584
Test name
Test status
Simulation time 457173798 ps
CPU time 5.22 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:16 PM PDT 24
Peak memory 233416 kb
Host smart-6eeb4d38-a636-4292-b1dc-f1e3f59e4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700688696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.700688696
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.230372416
Short name T640
Test name
Test status
Simulation time 18604085 ps
CPU time 0.76 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 206916 kb
Host smart-d7b94fd4-3a4d-421d-94b1-565f50850672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230372416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.230372416
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2053701655
Short name T912
Test name
Test status
Simulation time 10745855993 ps
CPU time 72.47 seconds
Started Jul 30 04:50:23 PM PDT 24
Finished Jul 30 04:51:36 PM PDT 24
Peak memory 240560 kb
Host smart-e235c756-454a-4752-b685-631629ad6394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053701655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2053701655
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4098791505
Short name T28
Test name
Test status
Simulation time 6698826068 ps
CPU time 107.77 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:52:00 PM PDT 24
Peak memory 254500 kb
Host smart-4d5f7807-8eb3-4088-85e9-4e4fbb846df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098791505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4098791505
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2260033950
Short name T937
Test name
Test status
Simulation time 16943953398 ps
CPU time 128.1 seconds
Started Jul 30 04:50:03 PM PDT 24
Finished Jul 30 04:52:11 PM PDT 24
Peak memory 258084 kb
Host smart-68a2554e-a6c8-4de1-aab4-f689fb8caf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260033950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2260033950
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4186508722
Short name T825
Test name
Test status
Simulation time 3793953084 ps
CPU time 46.71 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 241544 kb
Host smart-ca3d5648-43b7-466f-bbf4-3c33ff985b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186508722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4186508722
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2330831748
Short name T950
Test name
Test status
Simulation time 59789502 ps
CPU time 0.97 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 216524 kb
Host smart-e790357b-771d-4ac6-9bc8-5a5fc05263ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330831748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2330831748
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3332792930
Short name T955
Test name
Test status
Simulation time 1507569279 ps
CPU time 14.89 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 233396 kb
Host smart-ec6df209-ccdd-4f43-9ed5-81538dd46a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332792930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3332792930
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2466813673
Short name T225
Test name
Test status
Simulation time 677257823 ps
CPU time 7.75 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 233360 kb
Host smart-80891d54-6986-4a1b-b91f-1a0af2c41131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466813673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2466813673
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3609398176
Short name T238
Test name
Test status
Simulation time 21392170685 ps
CPU time 27.41 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 235016 kb
Host smart-5a11fe0f-8d87-4dd9-afb4-404b7eb1475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609398176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3609398176
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.951151796
Short name T625
Test name
Test status
Simulation time 1151543767 ps
CPU time 5.89 seconds
Started Jul 30 04:50:22 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 233364 kb
Host smart-fbcd3c83-61f9-49a2-a23e-6bf116e5a341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951151796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.951151796
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2238423789
Short name T347
Test name
Test status
Simulation time 6449006906 ps
CPU time 10.83 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 223696 kb
Host smart-2e6a7516-5112-462a-af44-fc2fccf05cd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238423789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2238423789
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1117546005
Short name T989
Test name
Test status
Simulation time 387199009598 ps
CPU time 729.68 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 05:02:19 PM PDT 24
Peak memory 273748 kb
Host smart-397a0e6c-f206-4ad0-b850-169f795b620e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117546005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1117546005
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4032968432
Short name T444
Test name
Test status
Simulation time 2610886773 ps
CPU time 26.15 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 216892 kb
Host smart-206d05d6-2a59-4e6d-bb81-b680b2edab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032968432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4032968432
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2119693376
Short name T614
Test name
Test status
Simulation time 4964157016 ps
CPU time 17.03 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 216920 kb
Host smart-9e37861c-8146-49f5-8d60-340bcf80f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119693376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2119693376
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3806617122
Short name T557
Test name
Test status
Simulation time 219343993 ps
CPU time 1.36 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 208612 kb
Host smart-8ef4e2ee-33e8-44b6-ab63-1c4ae20c4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806617122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3806617122
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3633565447
Short name T697
Test name
Test status
Simulation time 28860570 ps
CPU time 0.69 seconds
Started Jul 30 04:50:14 PM PDT 24
Finished Jul 30 04:50:14 PM PDT 24
Peak memory 206048 kb
Host smart-57ead823-80f0-4ea0-b67d-d3995b7a5ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633565447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3633565447
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1527297184
Short name T457
Test name
Test status
Simulation time 326852635 ps
CPU time 4.64 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 225216 kb
Host smart-e398270d-d788-4edb-93b0-beca3fa586ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527297184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1527297184
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1596129791
Short name T437
Test name
Test status
Simulation time 31298177 ps
CPU time 0.69 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 206048 kb
Host smart-48f7e510-ee85-4f3e-8d8a-62a6dd52265f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596129791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1596129791
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1114702536
Short name T558
Test name
Test status
Simulation time 156729628 ps
CPU time 2.64 seconds
Started Jul 30 04:50:16 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 233360 kb
Host smart-f33b3651-f7dc-4d2c-839d-0480fa6943d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114702536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1114702536
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1358697693
Short name T595
Test name
Test status
Simulation time 72909308 ps
CPU time 0.86 seconds
Started Jul 30 04:50:05 PM PDT 24
Finished Jul 30 04:50:07 PM PDT 24
Peak memory 206964 kb
Host smart-208c8499-3055-46f6-ab17-9a451bc1bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358697693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1358697693
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3834984040
Short name T933
Test name
Test status
Simulation time 30300411893 ps
CPU time 102.78 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:51:58 PM PDT 24
Peak memory 238976 kb
Host smart-3bd54d0b-a5cc-4fb8-8408-6714eded6c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834984040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3834984040
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3439221084
Short name T197
Test name
Test status
Simulation time 44634701070 ps
CPU time 78.3 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:51:24 PM PDT 24
Peak memory 253472 kb
Host smart-7f3fbbce-22b9-4175-a471-6f9a99728d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439221084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3439221084
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3007410663
Short name T720
Test name
Test status
Simulation time 16563226868 ps
CPU time 27.7 seconds
Started Jul 30 04:50:23 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 225428 kb
Host smart-c78f815d-4534-43aa-86a8-94ac33070190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007410663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3007410663
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2815726065
Short name T872
Test name
Test status
Simulation time 6698301047 ps
CPU time 14.53 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 225140 kb
Host smart-ac80b455-cd38-4cf9-a398-648a89f431c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815726065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2815726065
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3720058221
Short name T103
Test name
Test status
Simulation time 44712041828 ps
CPU time 191.15 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:53:17 PM PDT 24
Peak memory 259296 kb
Host smart-4201c444-4206-4a93-8504-8e59bbdcbf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720058221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3720058221
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1353546368
Short name T382
Test name
Test status
Simulation time 1655581914 ps
CPU time 4.5 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:09 PM PDT 24
Peak memory 225112 kb
Host smart-9e3300de-1e61-47fc-9b90-dd0fa6b7e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353546368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1353546368
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1570403182
Short name T501
Test name
Test status
Simulation time 72188610598 ps
CPU time 149.28 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:52:48 PM PDT 24
Peak memory 237700 kb
Host smart-19488860-3cf4-4653-9365-ada0a8fb7bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570403182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1570403182
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.439446842
Short name T268
Test name
Test status
Simulation time 332199406 ps
CPU time 2.9 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 225108 kb
Host smart-60b5b5dd-b7ff-4668-bbee-2afe62ff708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439446842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.439446842
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1372048584
Short name T940
Test name
Test status
Simulation time 422607061 ps
CPU time 6.12 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 233368 kb
Host smart-472c2512-49f6-4493-8d8e-e3f6a02b0ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372048584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1372048584
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1046298225
Short name T869
Test name
Test status
Simulation time 1901600362 ps
CPU time 11.02 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 219932 kb
Host smart-81f2c568-993c-4726-bc7e-51d230cc8738
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1046298225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1046298225
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2462288770
Short name T601
Test name
Test status
Simulation time 53788481329 ps
CPU time 109.37 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:52:13 PM PDT 24
Peak memory 237944 kb
Host smart-f1ec113b-30f3-4a50-853b-bed1247720a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462288770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2462288770
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.924240457
Short name T559
Test name
Test status
Simulation time 2675752348 ps
CPU time 8.83 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 216988 kb
Host smart-fa284196-0855-4b71-9592-c625a037ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924240457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.924240457
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4071931847
Short name T323
Test name
Test status
Simulation time 16217254 ps
CPU time 0.81 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 206544 kb
Host smart-c19c4c7d-a1b0-4f31-bbd4-f61342eea4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071931847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4071931847
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3918687159
Short name T663
Test name
Test status
Simulation time 295168699 ps
CPU time 0.88 seconds
Started Jul 30 04:50:04 PM PDT 24
Finished Jul 30 04:50:05 PM PDT 24
Peak memory 207492 kb
Host smart-d38c8e66-c8cb-47b9-8452-f893f52a1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918687159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3918687159
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1492353941
Short name T734
Test name
Test status
Simulation time 150312722 ps
CPU time 2.39 seconds
Started Jul 30 04:50:32 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 224488 kb
Host smart-c9904fe1-e8c8-4567-933e-c0719476de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492353941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1492353941
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2537824557
Short name T538
Test name
Test status
Simulation time 15016742 ps
CPU time 0.73 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:50:10 PM PDT 24
Peak memory 205748 kb
Host smart-f9e822cb-b04e-480e-91ac-11a3f238969e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537824557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2537824557
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1066003624
Short name T866
Test name
Test status
Simulation time 4308360081 ps
CPU time 12.44 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 225240 kb
Host smart-fa31e66a-caf4-4ccf-85f2-11da623aa5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066003624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1066003624
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1020499898
Short name T811
Test name
Test status
Simulation time 26589393 ps
CPU time 0.76 seconds
Started Jul 30 04:50:28 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 205904 kb
Host smart-15729631-3966-46db-9b3b-4c1ce9893358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020499898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1020499898
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2927444529
Short name T299
Test name
Test status
Simulation time 5263787691 ps
CPU time 53.81 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:51:06 PM PDT 24
Peak memory 240680 kb
Host smart-ec6dc0c8-ccc3-4649-8230-2fa74e7fb1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927444529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2927444529
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2647205829
Short name T891
Test name
Test status
Simulation time 5061233129 ps
CPU time 20.33 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:51:01 PM PDT 24
Peak memory 225300 kb
Host smart-398cbb82-a915-4191-9709-5e244e6e2632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647205829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2647205829
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3372296927
Short name T853
Test name
Test status
Simulation time 4919518272 ps
CPU time 56.98 seconds
Started Jul 30 04:50:06 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 238400 kb
Host smart-5fb94e71-a632-49fc-838e-eb22bc7cd232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372296927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3372296927
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.165981302
Short name T1025
Test name
Test status
Simulation time 1280460378 ps
CPU time 10.54 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 237184 kb
Host smart-1e291de6-c19b-4498-af65-6ab9e6ac12c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165981302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.165981302
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2949933005
Short name T600
Test name
Test status
Simulation time 76495755152 ps
CPU time 100.65 seconds
Started Jul 30 04:50:08 PM PDT 24
Finished Jul 30 04:51:49 PM PDT 24
Peak memory 249992 kb
Host smart-9ff28033-2138-4054-8d5d-420bdcdf6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949933005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2949933005
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2448746741
Short name T283
Test name
Test status
Simulation time 574859979 ps
CPU time 4.53 seconds
Started Jul 30 04:50:14 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 233460 kb
Host smart-a8eaf394-7fc0-4bb8-811d-d1644f8c5505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448746741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2448746741
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3936035255
Short name T852
Test name
Test status
Simulation time 26059556907 ps
CPU time 65.35 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:51:29 PM PDT 24
Peak memory 233388 kb
Host smart-74de8946-7a3e-4859-bbe0-4f0d18875950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936035255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3936035255
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1827135424
Short name T914
Test name
Test status
Simulation time 710957083 ps
CPU time 6.59 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 233384 kb
Host smart-d7e32729-fbc0-4e5b-b80b-4318ad580738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827135424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1827135424
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.131169371
Short name T255
Test name
Test status
Simulation time 5619088318 ps
CPU time 8.81 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 234504 kb
Host smart-aa2c743c-8bdf-4207-8fc0-ac360da435de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131169371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.131169371
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3973629535
Short name T821
Test name
Test status
Simulation time 6525346789 ps
CPU time 7.72 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 223628 kb
Host smart-780ddb26-cf50-4ae4-80d8-8e53935557b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3973629535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3973629535
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2630418024
Short name T957
Test name
Test status
Simulation time 3785902314 ps
CPU time 22.49 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 216956 kb
Host smart-2552d3c8-383b-4789-9666-c2b1b021fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630418024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2630418024
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1331821576
Short name T421
Test name
Test status
Simulation time 4778633352 ps
CPU time 3.65 seconds
Started Jul 30 04:50:10 PM PDT 24
Finished Jul 30 04:50:13 PM PDT 24
Peak memory 208500 kb
Host smart-b004c329-cd41-4b73-a1cf-20c9d2dba9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331821576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1331821576
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1647803005
Short name T684
Test name
Test status
Simulation time 18635450 ps
CPU time 1.02 seconds
Started Jul 30 04:50:07 PM PDT 24
Finished Jul 30 04:50:08 PM PDT 24
Peak memory 216488 kb
Host smart-76f8d037-576b-46fe-bf52-11f397b18b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647803005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1647803005
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2759701958
Short name T611
Test name
Test status
Simulation time 163232435 ps
CPU time 0.97 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 207492 kb
Host smart-8e03fcf0-d724-4cbf-ad02-b65874baccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759701958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2759701958
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4083571266
Short name T281
Test name
Test status
Simulation time 1984513585 ps
CPU time 13.56 seconds
Started Jul 30 04:50:20 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 233288 kb
Host smart-be9840fc-cb77-4f0c-bca8-9da621a0cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083571266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4083571266
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2318822063
Short name T745
Test name
Test status
Simulation time 15743446 ps
CPU time 0.75 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 205760 kb
Host smart-ee1c6d77-7e75-487f-9b61-4f46086c7ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318822063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2318822063
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3467993947
Short name T448
Test name
Test status
Simulation time 700731271 ps
CPU time 3.48 seconds
Started Jul 30 04:50:09 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 225168 kb
Host smart-5fec755c-41ea-440b-94fc-2886efe3f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467993947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3467993947
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3216348168
Short name T794
Test name
Test status
Simulation time 56369913 ps
CPU time 0.75 seconds
Started Jul 30 04:50:17 PM PDT 24
Finished Jul 30 04:50:18 PM PDT 24
Peak memory 206320 kb
Host smart-87e6e0a1-91ca-4d56-a622-483938cd0300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216348168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3216348168
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3494748123
Short name T50
Test name
Test status
Simulation time 300725759643 ps
CPU time 373.36 seconds
Started Jul 30 04:50:22 PM PDT 24
Finished Jul 30 04:56:36 PM PDT 24
Peak memory 257984 kb
Host smart-87603a81-e647-4c56-b330-aa7aee9071e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494748123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3494748123
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3382815327
Short name T667
Test name
Test status
Simulation time 30893807615 ps
CPU time 49.36 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:51:35 PM PDT 24
Peak memory 253480 kb
Host smart-d1d61d52-8f8c-4b2c-a8da-51191987eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382815327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3382815327
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.373068077
Short name T956
Test name
Test status
Simulation time 1343364224 ps
CPU time 29.1 seconds
Started Jul 30 04:50:30 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 240068 kb
Host smart-ccbea11c-6277-44fb-a451-7460bc86b4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373068077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.373068077
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.254718240
Short name T725
Test name
Test status
Simulation time 246135859 ps
CPU time 7.97 seconds
Started Jul 30 04:50:20 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 233412 kb
Host smart-35d143ed-6fc5-474b-b3e2-84f1ea4f9bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254718240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.254718240
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4218325404
Short name T239
Test name
Test status
Simulation time 92843165184 ps
CPU time 197.73 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:53:33 PM PDT 24
Peak memory 241624 kb
Host smart-d49fca9d-71cf-401a-bcc3-ff387a61e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218325404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4218325404
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2458203321
Short name T148
Test name
Test status
Simulation time 3918065532 ps
CPU time 8.33 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 233444 kb
Host smart-88d830b4-eb07-4e86-8e34-61f68b9d2758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458203321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2458203321
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3152559313
Short name T1012
Test name
Test status
Simulation time 30024408359 ps
CPU time 70.02 seconds
Started Jul 30 04:50:32 PM PDT 24
Finished Jul 30 04:51:42 PM PDT 24
Peak memory 225164 kb
Host smart-6cf15af3-4c10-4f29-a226-2408241851a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152559313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3152559313
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3904896332
Short name T267
Test name
Test status
Simulation time 2051437626 ps
CPU time 7.6 seconds
Started Jul 30 04:50:21 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 233268 kb
Host smart-17cc2569-1798-460a-afd5-b9a81012f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904896332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3904896332
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3180147943
Short name T713
Test name
Test status
Simulation time 2679565842 ps
CPU time 10.3 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 233408 kb
Host smart-33a50a94-c758-4b9c-ad64-e396af9ed181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180147943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3180147943
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1961953818
Short name T787
Test name
Test status
Simulation time 1743394817 ps
CPU time 20.21 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 220620 kb
Host smart-dc527c16-e938-4015-bf9b-922d78e449d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961953818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1961953818
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1921530673
Short name T707
Test name
Test status
Simulation time 7694283820 ps
CPU time 26.67 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 217332 kb
Host smart-e6f01626-fadf-4dd0-b444-84bd84fbea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921530673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1921530673
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2673179871
Short name T87
Test name
Test status
Simulation time 543798103 ps
CPU time 3.73 seconds
Started Jul 30 04:50:17 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 216872 kb
Host smart-14009af7-d197-4174-b9b1-69f80bc03666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673179871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2673179871
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1303109545
Short name T932
Test name
Test status
Simulation time 113388441 ps
CPU time 1.03 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 207844 kb
Host smart-4095a2a2-9ad4-40b9-97a9-ac1a2fbf2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303109545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1303109545
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3120646421
Short name T560
Test name
Test status
Simulation time 823728857 ps
CPU time 1 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 206540 kb
Host smart-e55e450e-bffe-4b36-b29f-2d5d9a30be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120646421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3120646421
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.937604287
Short name T47
Test name
Test status
Simulation time 6802219614 ps
CPU time 13.73 seconds
Started Jul 30 04:50:42 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 234412 kb
Host smart-8db9506f-b3d4-4ac6-b4ba-f63ecee03fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937604287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.937604287
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.170737673
Short name T759
Test name
Test status
Simulation time 14905431 ps
CPU time 0.68 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:50:46 PM PDT 24
Peak memory 205792 kb
Host smart-82417764-d7dd-4753-8f07-7608c098ba20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170737673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.170737673
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1943587975
Short name T674
Test name
Test status
Simulation time 3309213811 ps
CPU time 14.38 seconds
Started Jul 30 04:50:23 PM PDT 24
Finished Jul 30 04:50:38 PM PDT 24
Peak memory 225120 kb
Host smart-7d66b2c2-11ec-43fc-8b1f-6d325f1440de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943587975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1943587975
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1290054595
Short name T980
Test name
Test status
Simulation time 51105691 ps
CPU time 0.76 seconds
Started Jul 30 04:50:29 PM PDT 24
Finished Jul 30 04:50:30 PM PDT 24
Peak memory 205888 kb
Host smart-82fe44cc-68dc-4308-bb61-aeda7f882797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290054595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1290054595
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3378104826
Short name T184
Test name
Test status
Simulation time 49955208148 ps
CPU time 207.93 seconds
Started Jul 30 04:50:25 PM PDT 24
Finished Jul 30 04:53:53 PM PDT 24
Peak memory 266296 kb
Host smart-c30203e9-09c4-480f-92fc-77985ef84949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378104826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3378104826
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.726239604
Short name T219
Test name
Test status
Simulation time 6286869768 ps
CPU time 38.6 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:51:14 PM PDT 24
Peak memory 249832 kb
Host smart-49dbbc8f-09a2-45cd-907e-a8422af1d77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726239604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.726239604
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3179025544
Short name T264
Test name
Test status
Simulation time 284892461037 ps
CPU time 428.59 seconds
Started Jul 30 04:50:29 PM PDT 24
Finished Jul 30 04:57:38 PM PDT 24
Peak memory 252028 kb
Host smart-a8618889-c926-4056-b2ce-8d66e75c4feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179025544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3179025544
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1901632327
Short name T790
Test name
Test status
Simulation time 996051580 ps
CPU time 6.73 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 233308 kb
Host smart-ffdca6af-fd59-4fec-9738-1660265171c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901632327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1901632327
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1347018877
Short name T810
Test name
Test status
Simulation time 765497999 ps
CPU time 6.39 seconds
Started Jul 30 04:50:11 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 233376 kb
Host smart-fb491427-7e30-478f-86b2-b1d9d5f53214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347018877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1347018877
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3417257977
Short name T826
Test name
Test status
Simulation time 13981741076 ps
CPU time 101.82 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:51:55 PM PDT 24
Peak memory 238408 kb
Host smart-5823f24c-6fbb-4d41-86fd-31be5a615ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417257977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3417257977
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2180460928
Short name T620
Test name
Test status
Simulation time 5336787617 ps
CPU time 10.51 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:50:26 PM PDT 24
Peak memory 233380 kb
Host smart-6d1ca134-ee39-4932-a035-e73091a12507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180460928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2180460928
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.627154940
Short name T41
Test name
Test status
Simulation time 3780328514 ps
CPU time 7.98 seconds
Started Jul 30 04:50:28 PM PDT 24
Finished Jul 30 04:50:36 PM PDT 24
Peak memory 233328 kb
Host smart-38f1ddba-8707-4bb2-9ac9-9735b38a1b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627154940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.627154940
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2964624856
Short name T467
Test name
Test status
Simulation time 1688060051 ps
CPU time 4.7 seconds
Started Jul 30 04:50:30 PM PDT 24
Finished Jul 30 04:50:35 PM PDT 24
Peak memory 222656 kb
Host smart-ac1abe99-bb51-43fb-b618-418298a4a510
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2964624856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2964624856
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2749060519
Short name T499
Test name
Test status
Simulation time 9038410490 ps
CPU time 96.06 seconds
Started Jul 30 04:50:15 PM PDT 24
Finished Jul 30 04:51:51 PM PDT 24
Peak memory 249856 kb
Host smart-1326f369-910e-4be6-a27c-53a44f8cd0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749060519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2749060519
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2018664963
Short name T38
Test name
Test status
Simulation time 3675264652 ps
CPU time 23.64 seconds
Started Jul 30 04:50:31 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 216908 kb
Host smart-abb2469e-46b2-45b1-8f79-bf6ab034b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018664963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2018664963
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2519830528
Short name T537
Test name
Test status
Simulation time 4687870016 ps
CPU time 3.64 seconds
Started Jul 30 04:50:18 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 216884 kb
Host smart-99c42e54-76d5-4e95-b325-23daede4854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519830528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2519830528
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2427830047
Short name T324
Test name
Test status
Simulation time 24005073 ps
CPU time 0.97 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 208488 kb
Host smart-696e1e2a-198f-4d78-ba10-5ce254464dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427830047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2427830047
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.950315098
Short name T881
Test name
Test status
Simulation time 73461688 ps
CPU time 0.97 seconds
Started Jul 30 04:50:12 PM PDT 24
Finished Jul 30 04:50:13 PM PDT 24
Peak memory 206504 kb
Host smart-8f6d4802-18c6-4725-92c4-3fbb0a166c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950315098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.950315098
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3685652864
Short name T975
Test name
Test status
Simulation time 920254828 ps
CPU time 5.79 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:50:43 PM PDT 24
Peak memory 233432 kb
Host smart-cedffc30-471c-4104-b90f-1edbe6e3cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685652864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3685652864
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2477442693
Short name T73
Test name
Test status
Simulation time 60276646 ps
CPU time 0.68 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 205188 kb
Host smart-257ec146-0c6e-4379-95f8-4e50a80b11e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477442693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2477442693
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3328154741
Short name T262
Test name
Test status
Simulation time 1829512977 ps
CPU time 6.51 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 233328 kb
Host smart-40279eef-571b-4dd4-a6c2-a584f0f8e19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328154741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3328154741
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4038712107
Short name T387
Test name
Test status
Simulation time 67716241 ps
CPU time 0.77 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 205956 kb
Host smart-61a2fe2c-9807-447b-85d0-8281a7cb4356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038712107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4038712107
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1675465813
Short name T438
Test name
Test status
Simulation time 2844558783 ps
CPU time 13.71 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 225252 kb
Host smart-d6259d34-d549-4e40-b461-c619373fc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675465813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1675465813
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3021214795
Short name T207
Test name
Test status
Simulation time 11839564097 ps
CPU time 90.23 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:52:05 PM PDT 24
Peak memory 249892 kb
Host smart-9010aaa1-6591-4a83-9488-ed7c31352429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021214795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3021214795
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1340811331
Short name T978
Test name
Test status
Simulation time 25552974189 ps
CPU time 214.08 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:54:00 PM PDT 24
Peak memory 241704 kb
Host smart-916a5103-b9c4-4812-9ada-343c2cf7dca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340811331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1340811331
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1088572774
Short name T342
Test name
Test status
Simulation time 3888733858 ps
CPU time 18.41 seconds
Started Jul 30 04:50:30 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 233448 kb
Host smart-8d42b8d1-ce33-4b99-be9f-fecefafd1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088572774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1088572774
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2355541964
Short name T520
Test name
Test status
Simulation time 887851879 ps
CPU time 16.51 seconds
Started Jul 30 04:50:13 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 225128 kb
Host smart-f6d384fb-acc4-41de-a561-a65eee96e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355541964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2355541964
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1809529338
Short name T582
Test name
Test status
Simulation time 1100410268 ps
CPU time 10.44 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 233388 kb
Host smart-b344181d-ef9b-44fe-9cd1-4de31aaeede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809529338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1809529338
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3147158400
Short name T144
Test name
Test status
Simulation time 432539326 ps
CPU time 2.99 seconds
Started Jul 30 04:50:14 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 225224 kb
Host smart-3d7c7171-b365-4dac-91a3-997ed45b7125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147158400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3147158400
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2173743634
Short name T1016
Test name
Test status
Simulation time 651958906 ps
CPU time 3.4 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:30 PM PDT 24
Peak memory 233400 kb
Host smart-52fad864-2e5f-4a33-a920-976cfe5774ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173743634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2173743634
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.968047584
Short name T603
Test name
Test status
Simulation time 42733443 ps
CPU time 2.12 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:26 PM PDT 24
Peak memory 225104 kb
Host smart-3d1a7e86-868a-4603-946f-f5a48f0784a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968047584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.968047584
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.988702291
Short name T854
Test name
Test status
Simulation time 4781378419 ps
CPU time 9.61 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 220808 kb
Host smart-a559b743-4bf6-43d5-9fce-a004528d7836
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988702291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.988702291
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.388327802
Short name T313
Test name
Test status
Simulation time 7059780416 ps
CPU time 23.18 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:47 PM PDT 24
Peak memory 217088 kb
Host smart-4d5ab3f5-1890-4890-a88f-5d5b4f0d1827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388327802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.388327802
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2328822048
Short name T340
Test name
Test status
Simulation time 386054512 ps
CPU time 2.73 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 216852 kb
Host smart-2e5fcda5-5ea5-43d8-a0c5-98457968188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328822048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2328822048
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1889458802
Short name T489
Test name
Test status
Simulation time 816215140 ps
CPU time 9.7 seconds
Started Jul 30 04:50:29 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 216800 kb
Host smart-619b4a36-2b9f-4e49-ada2-881ff772f762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889458802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1889458802
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4065951804
Short name T946
Test name
Test status
Simulation time 20421099 ps
CPU time 0.74 seconds
Started Jul 30 04:50:32 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 206516 kb
Host smart-9b31c1b0-4b2e-440b-9c3d-1c823ab55107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065951804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4065951804
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1622104450
Short name T504
Test name
Test status
Simulation time 99245500 ps
CPU time 2.42 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 233384 kb
Host smart-6b62803d-67f1-4567-9b52-fc41f04d8fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622104450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1622104450
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3136180724
Short name T381
Test name
Test status
Simulation time 12441966 ps
CPU time 0.76 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:34 PM PDT 24
Peak memory 206076 kb
Host smart-0b916709-75e5-48c4-8a04-8e485806f8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136180724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3136180724
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.517230556
Short name T942
Test name
Test status
Simulation time 860829718 ps
CPU time 6.89 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 225144 kb
Host smart-2e5af723-9482-48bd-9873-a715c88a28f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517230556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.517230556
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3659570892
Short name T69
Test name
Test status
Simulation time 15435804 ps
CPU time 0.76 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:50:20 PM PDT 24
Peak memory 206220 kb
Host smart-e948f7de-cda4-43e1-8150-1158d5a92200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659570892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3659570892
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2910066661
Short name T607
Test name
Test status
Simulation time 5140446556 ps
CPU time 66.36 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:51:39 PM PDT 24
Peak memory 250472 kb
Host smart-ec95a283-d659-4836-8e0e-daafcfe4a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910066661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2910066661
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.219077297
Short name T629
Test name
Test status
Simulation time 3589296811 ps
CPU time 35.49 seconds
Started Jul 30 04:50:19 PM PDT 24
Finished Jul 30 04:50:54 PM PDT 24
Peak memory 222788 kb
Host smart-c9c233de-e2d1-4e4d-af32-f2917dafea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219077297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.219077297
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1002031736
Short name T823
Test name
Test status
Simulation time 147079005 ps
CPU time 3.69 seconds
Started Jul 30 04:50:36 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 225056 kb
Host smart-6e6f58ff-f67e-45ad-9a39-ae2ed71db558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002031736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1002031736
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3169050202
Short name T208
Test name
Test status
Simulation time 3434367135 ps
CPU time 47.61 seconds
Started Jul 30 04:50:38 PM PDT 24
Finished Jul 30 04:51:26 PM PDT 24
Peak memory 253748 kb
Host smart-a9937569-6a80-41ef-9926-c314210486cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169050202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3169050202
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3447265685
Short name T473
Test name
Test status
Simulation time 1264987000 ps
CPU time 4.02 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 233392 kb
Host smart-045264d5-b7fa-4263-a530-f9e779ed11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447265685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3447265685
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.480635268
Short name T536
Test name
Test status
Simulation time 126193808478 ps
CPU time 43.72 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:51:21 PM PDT 24
Peak memory 225200 kb
Host smart-24e2bef5-ea83-4cb8-8a96-76ab7bdf92db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480635268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.480635268
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1817260408
Short name T272
Test name
Test status
Simulation time 873166095 ps
CPU time 2.59 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:50:38 PM PDT 24
Peak memory 225072 kb
Host smart-c313f76a-336e-4aaa-8335-e5787c42085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817260408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1817260408
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4166302989
Short name T25
Test name
Test status
Simulation time 463990678 ps
CPU time 6.31 seconds
Started Jul 30 04:50:17 PM PDT 24
Finished Jul 30 04:50:24 PM PDT 24
Peak memory 233420 kb
Host smart-af5461a3-fa86-481c-88dd-e63c43943162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166302989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4166302989
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1611302672
Short name T162
Test name
Test status
Simulation time 672501018 ps
CPU time 5.15 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 220988 kb
Host smart-3fc72518-4c5e-49d4-b311-3d4e766edbfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611302672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1611302672
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2837307124
Short name T1010
Test name
Test status
Simulation time 84254470465 ps
CPU time 293.34 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:55:20 PM PDT 24
Peak memory 257972 kb
Host smart-a6425d98-39af-4d9b-9c27-2db5c53bcb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837307124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2837307124
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3750139639
Short name T991
Test name
Test status
Simulation time 676485675 ps
CPU time 2.05 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:36 PM PDT 24
Peak memory 216800 kb
Host smart-2d05c06b-1637-45e7-9730-4dd61e77978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750139639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3750139639
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4130824651
Short name T566
Test name
Test status
Simulation time 5664360476 ps
CPU time 8.7 seconds
Started Jul 30 04:50:38 PM PDT 24
Finished Jul 30 04:50:47 PM PDT 24
Peak memory 216952 kb
Host smart-2401f0ef-86af-4b02-b7b7-841147cd9e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130824651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4130824651
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.777561363
Short name T351
Test name
Test status
Simulation time 61024156 ps
CPU time 0.87 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:50:27 PM PDT 24
Peak memory 207184 kb
Host smart-86786da2-7d1f-4bad-8ebb-7853682c4e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777561363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.777561363
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3021735234
Short name T599
Test name
Test status
Simulation time 95906912 ps
CPU time 0.75 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 206444 kb
Host smart-bb0eb831-4a8c-4752-a5da-969bf6d80696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021735234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3021735234
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4033913459
Short name T746
Test name
Test status
Simulation time 24160688433 ps
CPU time 26.26 seconds
Started Jul 30 04:50:31 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 231524 kb
Host smart-cbc4b0e2-ca1d-44e7-82e0-4bd6abd491bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033913459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4033913459
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2855636438
Short name T396
Test name
Test status
Simulation time 16093722 ps
CPU time 0.71 seconds
Started Jul 30 04:48:50 PM PDT 24
Finished Jul 30 04:48:51 PM PDT 24
Peak memory 205760 kb
Host smart-e28e73ed-5087-4389-8253-a1e00465574b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855636438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
855636438
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3260398953
Short name T679
Test name
Test status
Simulation time 991933346 ps
CPU time 2.42 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 225096 kb
Host smart-b9843db2-9dd2-4624-8720-4cad904dcaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260398953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3260398953
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2507973545
Short name T747
Test name
Test status
Simulation time 59668943 ps
CPU time 0.77 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:49:07 PM PDT 24
Peak memory 207012 kb
Host smart-db76dd6e-7d52-454d-b1eb-276558e383d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507973545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2507973545
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2870358763
Short name T764
Test name
Test status
Simulation time 2829794537 ps
CPU time 38.18 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:49:36 PM PDT 24
Peak memory 249776 kb
Host smart-4a3ceb80-0836-467e-ac72-feea3ce299d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870358763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2870358763
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1730421977
Short name T298
Test name
Test status
Simulation time 559295816865 ps
CPU time 555.23 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:58:09 PM PDT 24
Peak memory 264072 kb
Host smart-c991dacd-58a4-4a55-92d9-01cf2b3015a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730421977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1730421977
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3082622734
Short name T670
Test name
Test status
Simulation time 14208154558 ps
CPU time 83.52 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 254868 kb
Host smart-1357ed4e-8e11-4fc5-9b28-ec7b1df6d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082622734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3082622734
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3289037194
Short name T311
Test name
Test status
Simulation time 2512229999 ps
CPU time 15.47 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 233504 kb
Host smart-bdae56e7-68a2-488e-9ca8-0b6c289f1365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289037194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3289037194
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3512108859
Short name T723
Test name
Test status
Simulation time 1583723668 ps
CPU time 9.08 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 234504 kb
Host smart-00def822-d7d7-45e9-b75d-539a276f99b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512108859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3512108859
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.73911196
Short name T644
Test name
Test status
Simulation time 5672795781 ps
CPU time 14.73 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 233448 kb
Host smart-2ad974f3-7cd1-4070-8884-89365d3b354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73911196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.73911196
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4230979922
Short name T81
Test name
Test status
Simulation time 2020461678 ps
CPU time 25.82 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 233392 kb
Host smart-fc240ccf-6a7e-47ae-b504-08b359493eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230979922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4230979922
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.155391857
Short name T743
Test name
Test status
Simulation time 100901254 ps
CPU time 1.04 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 217072 kb
Host smart-c2a1d53e-b4bf-4fa8-aff3-79f0ab57949d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155391857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.155391857
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1578427821
Short name T706
Test name
Test status
Simulation time 529623087 ps
CPU time 3.14 seconds
Started Jul 30 04:49:04 PM PDT 24
Finished Jul 30 04:49:07 PM PDT 24
Peak memory 225124 kb
Host smart-28beb307-bc47-4e1c-975a-828590538907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578427821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1578427821
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2984237715
Short name T282
Test name
Test status
Simulation time 3698506578 ps
CPU time 11.85 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 233484 kb
Host smart-7c07269d-c3f4-42ee-a62a-e5a83d965c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984237715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2984237715
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2762444366
Short name T420
Test name
Test status
Simulation time 306476775 ps
CPU time 3.95 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:03 PM PDT 24
Peak memory 223744 kb
Host smart-83834567-7a12-4377-bcef-1e5f92a21641
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2762444366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2762444366
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.227316601
Short name T78
Test name
Test status
Simulation time 60707015 ps
CPU time 1.11 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 235920 kb
Host smart-753896a6-88f4-4748-ba4f-6002e8e3dd2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227316601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.227316601
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3289151852
Short name T315
Test name
Test status
Simulation time 37905278351 ps
CPU time 36.9 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:35 PM PDT 24
Peak memory 216892 kb
Host smart-6052bfb8-7ba4-4e48-8c7f-64ce8c409122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289151852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3289151852
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3800464337
Short name T545
Test name
Test status
Simulation time 21201990541 ps
CPU time 11.15 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:49:07 PM PDT 24
Peak memory 216948 kb
Host smart-5eb9adf3-b677-42b0-a0e2-90240337d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800464337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3800464337
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1423478234
Short name T702
Test name
Test status
Simulation time 719534721 ps
CPU time 12.19 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:13 PM PDT 24
Peak memory 216848 kb
Host smart-a19790aa-5e7a-48df-bfb6-9c36d0348407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423478234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1423478234
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1228415755
Short name T1009
Test name
Test status
Simulation time 367278730 ps
CPU time 0.94 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 04:49:03 PM PDT 24
Peak memory 206600 kb
Host smart-a3b06940-e415-4033-b409-c8abcdd1f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228415755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1228415755
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3795941424
Short name T434
Test name
Test status
Simulation time 129485744 ps
CPU time 3.05 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 233372 kb
Host smart-66c7d932-1848-43ca-bdb6-2036c54b1758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795941424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3795941424
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2874051054
Short name T1011
Test name
Test status
Simulation time 39665083 ps
CPU time 0.69 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:28 PM PDT 24
Peak memory 205136 kb
Host smart-5d97600a-03d4-43b5-8a52-faf3ae16886f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874051054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2874051054
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3343816732
Short name T349
Test name
Test status
Simulation time 101585245 ps
CPU time 0.76 seconds
Started Jul 30 04:50:24 PM PDT 24
Finished Jul 30 04:50:25 PM PDT 24
Peak memory 207008 kb
Host smart-73d6cbe9-bafd-4267-a051-81df2c424701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343816732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3343816732
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.645575572
Short name T364
Test name
Test status
Simulation time 324508268 ps
CPU time 0.78 seconds
Started Jul 30 04:50:32 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 216608 kb
Host smart-dbd7cd47-5ad3-4a0b-b0ae-654cd67bfe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645575572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.645575572
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.720060840
Short name T564
Test name
Test status
Simulation time 523377415 ps
CPU time 3.39 seconds
Started Jul 30 04:50:36 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 220236 kb
Host smart-f4e660e3-dd7c-4c11-8844-57a4c6f4703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720060840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.720060840
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1476738790
Short name T306
Test name
Test status
Simulation time 306902785 ps
CPU time 9.39 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 233384 kb
Host smart-5132dd70-ca27-4401-b354-1b34e5cd0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476738790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1476738790
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1794908512
Short name T930
Test name
Test status
Simulation time 49993411463 ps
CPU time 114.67 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:52:39 PM PDT 24
Peak memory 249840 kb
Host smart-bed45581-8b3e-41f0-8889-58b0b5afaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794908512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1794908512
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3668994570
Short name T231
Test name
Test status
Simulation time 1293114360 ps
CPU time 15.4 seconds
Started Jul 30 04:50:26 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 225140 kb
Host smart-a77e0349-1ebe-42f8-b936-2e8424da385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668994570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3668994570
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2585556383
Short name T983
Test name
Test status
Simulation time 4943995932 ps
CPU time 31.82 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:51:13 PM PDT 24
Peak memory 240572 kb
Host smart-77155814-f430-4db7-a851-ecb3a3564d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585556383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2585556383
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3586114007
Short name T395
Test name
Test status
Simulation time 335438474 ps
CPU time 3.28 seconds
Started Jul 30 04:50:33 PM PDT 24
Finished Jul 30 04:50:37 PM PDT 24
Peak memory 233368 kb
Host smart-f8ef1e10-316c-462f-bee1-97f6a6f68492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586114007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3586114007
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2947403923
Short name T280
Test name
Test status
Simulation time 1380864900 ps
CPU time 5.63 seconds
Started Jul 30 04:50:28 PM PDT 24
Finished Jul 30 04:50:33 PM PDT 24
Peak memory 233336 kb
Host smart-ae142ff7-a417-4cd5-84b4-db67b4f2c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947403923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2947403923
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1028518771
Short name T165
Test name
Test status
Simulation time 1342821106 ps
CPU time 6.13 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 223516 kb
Host smart-2f25c29a-2113-4828-af9f-2dd9543de3c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1028518771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1028518771
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.125852726
Short name T174
Test name
Test status
Simulation time 533594110472 ps
CPU time 443.86 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:57:59 PM PDT 24
Peak memory 266388 kb
Host smart-aa86d466-2188-4d24-b7a2-43fbdde55b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125852726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.125852726
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3568702946
Short name T628
Test name
Test status
Simulation time 46809199 ps
CPU time 0.72 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 206080 kb
Host smart-78518635-067e-42b6-b5d3-61daadf66799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568702946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3568702946
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2907952721
Short name T456
Test name
Test status
Simulation time 540790578 ps
CPU time 4.33 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:51:03 PM PDT 24
Peak memory 216900 kb
Host smart-e66777a1-8f98-4249-812a-c0b9483503b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907952721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2907952721
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2690743332
Short name T455
Test name
Test status
Simulation time 215593766 ps
CPU time 1.35 seconds
Started Jul 30 04:50:28 PM PDT 24
Finished Jul 30 04:50:29 PM PDT 24
Peak memory 216948 kb
Host smart-cd0564cd-9169-4668-8d94-8eeefa266225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690743332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2690743332
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1023661851
Short name T696
Test name
Test status
Simulation time 53250900 ps
CPU time 0.83 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 206416 kb
Host smart-218f9073-4f9e-4a86-aa9c-fd8adf1af418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023661851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1023661851
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3894492303
Short name T760
Test name
Test status
Simulation time 2337951758 ps
CPU time 6.04 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 225196 kb
Host smart-2b8810a9-72d9-4574-a092-6f976c345f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894492303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3894492303
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4160092813
Short name T177
Test name
Test status
Simulation time 13019369 ps
CPU time 0.71 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:42 PM PDT 24
Peak memory 205784 kb
Host smart-209c2e1d-d503-4896-8ca0-dc8cb757c44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160092813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4160092813
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3731963149
Short name T805
Test name
Test status
Simulation time 273258979 ps
CPU time 2.88 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:42 PM PDT 24
Peak memory 225140 kb
Host smart-722c4f60-5c1c-4dfb-b9f9-885432ab35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731963149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3731963149
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3464372338
Short name T858
Test name
Test status
Simulation time 32640275 ps
CPU time 0.75 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:50:54 PM PDT 24
Peak memory 206324 kb
Host smart-8238f154-1aa1-4780-b68c-9db066f7afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464372338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3464372338
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.132320635
Short name T215
Test name
Test status
Simulation time 23399033893 ps
CPU time 47.89 seconds
Started Jul 30 04:50:42 PM PDT 24
Finished Jul 30 04:51:30 PM PDT 24
Peak memory 241616 kb
Host smart-4a13d1d9-808b-4681-a095-edbe4a6eadc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132320635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.132320635
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1019314012
Short name T924
Test name
Test status
Simulation time 47389573116 ps
CPU time 202.22 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:54:04 PM PDT 24
Peak memory 270672 kb
Host smart-e4f07549-1a47-401b-bf58-c4a0b0043f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019314012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1019314012
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3150861724
Short name T995
Test name
Test status
Simulation time 285208780 ps
CPU time 6.7 seconds
Started Jul 30 04:50:38 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 233336 kb
Host smart-4440c9a8-af57-44fa-a8bd-7aa943bcfacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150861724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3150861724
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3105293272
Short name T465
Test name
Test status
Simulation time 142487587 ps
CPU time 0.76 seconds
Started Jul 30 04:50:50 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 216404 kb
Host smart-6f159875-51a5-4d0d-a809-64c0765fa925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105293272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3105293272
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3239805185
Short name T258
Test name
Test status
Simulation time 794221450 ps
CPU time 4.51 seconds
Started Jul 30 04:50:50 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 233372 kb
Host smart-bf4015c6-3a0e-40b8-a85b-8bc6afe62ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239805185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3239805185
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1794355411
Short name T986
Test name
Test status
Simulation time 97622770088 ps
CPU time 66.43 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:52:05 PM PDT 24
Peak memory 233380 kb
Host smart-bf39c593-9875-47dd-be11-b57a68bfe111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794355411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1794355411
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2657474563
Short name T756
Test name
Test status
Simulation time 5249912627 ps
CPU time 11.09 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 233464 kb
Host smart-545b31da-0813-483b-bc2e-5ff721f2bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657474563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2657474563
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3483949327
Short name T242
Test name
Test status
Simulation time 22807029436 ps
CPU time 12.68 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 233404 kb
Host smart-6d496db1-01e5-49a4-bb68-1dff3c17abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483949327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3483949327
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3108649920
Short name T402
Test name
Test status
Simulation time 174476830 ps
CPU time 4.36 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 223632 kb
Host smart-2438f20e-e3f1-4559-b9c3-e6835058bac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3108649920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3108649920
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2419334888
Short name T155
Test name
Test status
Simulation time 1806501053 ps
CPU time 29.19 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:51:10 PM PDT 24
Peak memory 254184 kb
Host smart-aba00ff8-7278-4bc9-8cef-fbdfce2998ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419334888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2419334888
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.969017035
Short name T765
Test name
Test status
Simulation time 3086263435 ps
CPU time 14.44 seconds
Started Jul 30 04:50:27 PM PDT 24
Finished Jul 30 04:50:42 PM PDT 24
Peak memory 216956 kb
Host smart-beec5d9e-6000-4427-a4c0-19d5aa509c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969017035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.969017035
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3898376534
Short name T181
Test name
Test status
Simulation time 7575621739 ps
CPU time 13.23 seconds
Started Jul 30 04:50:58 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 216868 kb
Host smart-22cd66ad-f754-46d8-b091-525c25d6005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898376534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3898376534
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3333682295
Short name T322
Test name
Test status
Simulation time 53218243 ps
CPU time 1.36 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:50:37 PM PDT 24
Peak memory 208616 kb
Host smart-76d15288-dcc1-41ae-8d05-7474a416b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333682295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3333682295
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.955068674
Short name T372
Test name
Test status
Simulation time 100909877 ps
CPU time 0.99 seconds
Started Jul 30 04:50:38 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 206496 kb
Host smart-30d70ac0-affe-4739-ad8e-0a8aed53b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955068674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.955068674
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4065064802
Short name T263
Test name
Test status
Simulation time 4247366520 ps
CPU time 17.91 seconds
Started Jul 30 04:50:42 PM PDT 24
Finished Jul 30 04:51:00 PM PDT 24
Peak memory 248824 kb
Host smart-a98b7693-e415-41f9-a5bf-0bedac384b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065064802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4065064802
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1926839907
Short name T592
Test name
Test status
Simulation time 34376150 ps
CPU time 0.71 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 205128 kb
Host smart-4dd8d204-842b-429d-bd9d-265be932177a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926839907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1926839907
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.557970142
Short name T744
Test name
Test status
Simulation time 1712521011 ps
CPU time 9.47 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:56 PM PDT 24
Peak memory 233240 kb
Host smart-c294570f-e3ca-42ff-af9a-7134ecac4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557970142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.557970142
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1579920281
Short name T83
Test name
Test status
Simulation time 61764425 ps
CPU time 0.75 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 205900 kb
Host smart-ccfd0c3a-173d-45b0-b9d9-d07257c656cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579920281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1579920281
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1498050405
Short name T694
Test name
Test status
Simulation time 37972924246 ps
CPU time 277.41 seconds
Started Jul 30 04:50:55 PM PDT 24
Finished Jul 30 04:55:33 PM PDT 24
Peak memory 253156 kb
Host smart-a1efcb82-35a6-417d-8113-4a1dfc717f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498050405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1498050405
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3451794211
Short name T775
Test name
Test status
Simulation time 79696311967 ps
CPU time 97.59 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:52:20 PM PDT 24
Peak memory 225312 kb
Host smart-8a6813e9-3236-4a53-b7b2-b318c323f7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451794211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3451794211
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3699020361
Short name T310
Test name
Test status
Simulation time 1088381418 ps
CPU time 8.98 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 225084 kb
Host smart-4d5e5d4c-90fb-4b80-b57a-67e29f93e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699020361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3699020361
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2829240443
Short name T736
Test name
Test status
Simulation time 1530070026 ps
CPU time 14.89 seconds
Started Jul 30 04:50:36 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 235204 kb
Host smart-21f519cc-8c03-44a5-a7b1-a0cbb42bae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829240443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2829240443
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2166954037
Short name T478
Test name
Test status
Simulation time 153589511 ps
CPU time 4.68 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 228968 kb
Host smart-9dc1197f-0193-46d7-9bab-0c3e97e2eae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166954037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2166954037
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1661664706
Short name T795
Test name
Test status
Simulation time 2910550490 ps
CPU time 15.79 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:51:00 PM PDT 24
Peak memory 225168 kb
Host smart-9582e48b-158c-4297-8f64-afab4860cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661664706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1661664706
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4109318687
Short name T773
Test name
Test status
Simulation time 86402205184 ps
CPU time 21.18 seconds
Started Jul 30 04:50:42 PM PDT 24
Finished Jul 30 04:51:03 PM PDT 24
Peak memory 233416 kb
Host smart-4e68f882-823f-41ef-bcf8-4122882d6e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109318687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4109318687
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.672262945
Short name T967
Test name
Test status
Simulation time 388918021 ps
CPU time 5.21 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 233288 kb
Host smart-0f4dc04b-ef31-40d9-9512-77b1e629d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672262945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.672262945
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.398901109
Short name T833
Test name
Test status
Simulation time 1152303525 ps
CPU time 11.53 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 223156 kb
Host smart-de8262ac-b31f-401e-9f24-b380438b184d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398901109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.398901109
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1155467836
Short name T171
Test name
Test status
Simulation time 176754722 ps
CPU time 1.01 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:50:46 PM PDT 24
Peak memory 207940 kb
Host smart-3e5da5da-d2e3-49d6-8c54-837e489e9df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155467836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1155467836
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1161431882
Short name T1017
Test name
Test status
Simulation time 2315593452 ps
CPU time 15.34 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 216892 kb
Host smart-f66b8bbe-0f67-48a4-8e02-e14c60eb6be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161431882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1161431882
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2917350949
Short name T871
Test name
Test status
Simulation time 4714483632 ps
CPU time 15.89 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 216880 kb
Host smart-0e704bb2-008e-4480-bb71-bec438c813ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917350949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2917350949
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3912248731
Short name T357
Test name
Test status
Simulation time 288547849 ps
CPU time 2.45 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 216764 kb
Host smart-9c0562f1-e292-4b7c-8f75-e4ec312bcbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912248731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3912248731
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3908827687
Short name T30
Test name
Test status
Simulation time 342612459 ps
CPU time 0.91 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:50:46 PM PDT 24
Peak memory 206428 kb
Host smart-08da49f7-8fce-4cd7-ac68-774d6ab4d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908827687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3908827687
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2182155768
Short name T254
Test name
Test status
Simulation time 977281296 ps
CPU time 5.25 seconds
Started Jul 30 04:50:56 PM PDT 24
Finished Jul 30 04:51:01 PM PDT 24
Peak memory 225216 kb
Host smart-d15dc4cf-2375-4e34-b29d-400d9309e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182155768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2182155768
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1304216488
Short name T804
Test name
Test status
Simulation time 27549421 ps
CPU time 0.72 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:50:41 PM PDT 24
Peak memory 205204 kb
Host smart-a6049a99-a893-44f8-988e-6f73ec37cc18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304216488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1304216488
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2175456356
Short name T742
Test name
Test status
Simulation time 236982335 ps
CPU time 4.65 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 233356 kb
Host smart-b42b039a-9ba9-403a-b642-b839de274d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175456356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2175456356
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3282354151
Short name T831
Test name
Test status
Simulation time 51010816 ps
CPU time 0.85 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 207256 kb
Host smart-5edb010e-aa2a-4d90-bfbe-8b9baf1e4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282354151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3282354151
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3576535783
Short name T988
Test name
Test status
Simulation time 17005915 ps
CPU time 0.74 seconds
Started Jul 30 04:51:10 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 216372 kb
Host smart-fc06a9e8-7820-4e4d-b552-3a196fa201b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576535783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3576535783
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4073681461
Short name T277
Test name
Test status
Simulation time 10335759564 ps
CPU time 54.33 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:51:41 PM PDT 24
Peak memory 252332 kb
Host smart-fa90c4e3-bc59-4b4d-a847-055f9b4a7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073681461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4073681461
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1310765150
Short name T522
Test name
Test status
Simulation time 16921404290 ps
CPU time 176.68 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:53:42 PM PDT 24
Peak memory 250156 kb
Host smart-13b2987b-d8a6-409b-a9dc-9e5c230e8b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310765150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1310765150
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.565415031
Short name T885
Test name
Test status
Simulation time 151380133 ps
CPU time 3.71 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:50:39 PM PDT 24
Peak memory 225136 kb
Host smart-76bf2829-633a-445e-9b9d-13564f46a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565415031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.565415031
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1043845295
Short name T677
Test name
Test status
Simulation time 3760623446 ps
CPU time 13.49 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 225208 kb
Host smart-c69a7634-ab49-4e85-8e9a-e0af4e3f4c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043845295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1043845295
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2719749295
Short name T1004
Test name
Test status
Simulation time 1815680975 ps
CPU time 4.65 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:50:56 PM PDT 24
Peak memory 229008 kb
Host smart-6764c410-0359-4fee-9aa7-ab7106ebd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719749295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2719749295
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2876818032
Short name T241
Test name
Test status
Simulation time 321222691 ps
CPU time 8.12 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 225160 kb
Host smart-95338b1a-f56b-4df3-895a-108c6eccada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876818032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2876818032
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2856118540
Short name T51
Test name
Test status
Simulation time 4180171847 ps
CPU time 6.69 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:50 PM PDT 24
Peak memory 233796 kb
Host smart-602c4f7c-1335-4a9b-9f36-933c77d0b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856118540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2856118540
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1424472910
Short name T583
Test name
Test status
Simulation time 6167046430 ps
CPU time 5.2 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:51:03 PM PDT 24
Peak memory 225160 kb
Host smart-59c9bb21-3feb-4042-9d3c-f15e70248b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424472910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1424472910
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.452362126
Short name T400
Test name
Test status
Simulation time 408244924 ps
CPU time 4.83 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 219904 kb
Host smart-fc511ab5-3b6a-4812-bbba-1a39d5b46ff7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=452362126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.452362126
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3290981719
Short name T175
Test name
Test status
Simulation time 42189107917 ps
CPU time 189.68 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:53:50 PM PDT 24
Peak memory 280820 kb
Host smart-0c909d8e-ad69-4eea-a1b1-64350b048952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290981719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3290981719
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3186386746
Short name T55
Test name
Test status
Simulation time 2711755356 ps
CPU time 5.66 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 217028 kb
Host smart-38ff8ca0-700c-4717-a5fd-944caf4a64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186386746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3186386746
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2942241069
Short name T65
Test name
Test status
Simulation time 20854123953 ps
CPU time 27.3 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:51:20 PM PDT 24
Peak memory 217012 kb
Host smart-437c158c-ac76-4bee-950d-11c9a74caca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942241069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2942241069
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2408246837
Short name T892
Test name
Test status
Simulation time 38080306 ps
CPU time 0.83 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 207256 kb
Host smart-9c26e19f-8d79-4971-a5fd-0df26a03407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408246837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2408246837
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1919424284
Short name T474
Test name
Test status
Simulation time 50456150 ps
CPU time 0.86 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:40 PM PDT 24
Peak memory 206436 kb
Host smart-9c57fda8-3fa5-4491-8159-2318db8d086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919424284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1919424284
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2247436663
Short name T279
Test name
Test status
Simulation time 97306214 ps
CPU time 2.96 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:37 PM PDT 24
Peak memory 233360 kb
Host smart-181f87fb-e60f-499b-805e-21dfdd819b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247436663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2247436663
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3322719061
Short name T544
Test name
Test status
Simulation time 55841365 ps
CPU time 0.71 seconds
Started Jul 30 04:50:51 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 205816 kb
Host smart-274a19af-17c1-46f7-9434-57e38f4e1604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322719061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3322719061
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3361979655
Short name T14
Test name
Test status
Simulation time 404830881 ps
CPU time 4.74 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 225192 kb
Host smart-c044c7e1-2064-4c28-b263-8a9c28bcba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361979655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3361979655
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3098140984
Short name T939
Test name
Test status
Simulation time 17617778 ps
CPU time 0.78 seconds
Started Jul 30 04:50:42 PM PDT 24
Finished Jul 30 04:50:43 PM PDT 24
Peak memory 207256 kb
Host smart-e820c9c1-f0eb-4429-8e87-062c8357fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098140984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3098140984
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4232324892
Short name T535
Test name
Test status
Simulation time 889530169 ps
CPU time 10.71 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 225168 kb
Host smart-810d200f-1df2-46cd-acb9-93f4e187e08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232324892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4232324892
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4208667017
Short name T1013
Test name
Test status
Simulation time 3622570322 ps
CPU time 42.38 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:51:36 PM PDT 24
Peak memory 241692 kb
Host smart-99f51ab2-aaed-4977-ab4d-26e8c4758c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208667017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4208667017
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1000459278
Short name T368
Test name
Test status
Simulation time 115037813 ps
CPU time 0.9 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 216660 kb
Host smart-66ef6049-d37f-42b6-8570-f34c54a798b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000459278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1000459278
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3481426420
Short name T229
Test name
Test status
Simulation time 735423505 ps
CPU time 6.17 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 233388 kb
Host smart-6e9ccd77-8510-467e-89d5-5be90ffb539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481426420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3481426420
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.210070959
Short name T261
Test name
Test status
Simulation time 82396051 ps
CPU time 3.15 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 233360 kb
Host smart-36053033-b2ee-4425-bf4b-7f14a0d86f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210070959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.210070959
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.295855270
Short name T459
Test name
Test status
Simulation time 1385635536 ps
CPU time 3.28 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 225044 kb
Host smart-9415e3f6-6649-4bb3-b956-18d196589c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295855270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.295855270
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.456019139
Short name T909
Test name
Test status
Simulation time 12639124584 ps
CPU time 13.05 seconds
Started Jul 30 04:50:51 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 241648 kb
Host smart-8501f916-1db0-4593-8ebd-d378a2100131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456019139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.456019139
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1036617142
Short name T61
Test name
Test status
Simulation time 400955856 ps
CPU time 3.18 seconds
Started Jul 30 04:50:39 PM PDT 24
Finished Jul 30 04:50:42 PM PDT 24
Peak memory 219252 kb
Host smart-6977aed4-39fa-4727-8b46-42645587ebec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1036617142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1036617142
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1204139688
Short name T429
Test name
Test status
Simulation time 551786547 ps
CPU time 7.79 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 236960 kb
Host smart-56fc115a-2ba7-4854-811c-f1ecb99502f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204139688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1204139688
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3630426485
Short name T860
Test name
Test status
Simulation time 28274354380 ps
CPU time 39.38 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:51:24 PM PDT 24
Peak memory 217028 kb
Host smart-4ef024d3-946a-4112-99d9-188de47108d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630426485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3630426485
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.609830049
Short name T86
Test name
Test status
Simulation time 4085490817 ps
CPU time 11.43 seconds
Started Jul 30 04:50:35 PM PDT 24
Finished Jul 30 04:50:46 PM PDT 24
Peak memory 216948 kb
Host smart-8c6c5d6d-7080-456d-a1e8-8b86095fa449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609830049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.609830049
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2386511788
Short name T179
Test name
Test status
Simulation time 39178784 ps
CPU time 1.36 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 216864 kb
Host smart-7a2cb9f2-fc37-4084-ab85-fe3121c7ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386511788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2386511788
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4170366781
Short name T703
Test name
Test status
Simulation time 229044474 ps
CPU time 0.91 seconds
Started Jul 30 04:50:34 PM PDT 24
Finished Jul 30 04:50:35 PM PDT 24
Peak memory 207540 kb
Host smart-ee2ddea3-0c69-4ff6-bcef-a5c9e13fefde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170366781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4170366781
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3320822351
Short name T626
Test name
Test status
Simulation time 5619575044 ps
CPU time 21.24 seconds
Started Jul 30 04:50:41 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 233324 kb
Host smart-77680969-1889-4732-9778-a510fbd4a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320822351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3320822351
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.874045125
Short name T861
Test name
Test status
Simulation time 26391477 ps
CPU time 0.75 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 205752 kb
Host smart-8022a2f1-f057-410b-88cd-112751490527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874045125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.874045125
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2014842058
Short name T807
Test name
Test status
Simulation time 165940678 ps
CPU time 2.32 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 225160 kb
Host smart-01cef342-8248-43fc-a79b-91bbf9029ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014842058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2014842058
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3388283261
Short name T718
Test name
Test status
Simulation time 42015297 ps
CPU time 0.75 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 206880 kb
Host smart-bb3895e1-b009-4573-9d44-3a4c45222a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388283261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3388283261
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.251219132
Short name T977
Test name
Test status
Simulation time 17119781794 ps
CPU time 120.5 seconds
Started Jul 30 04:51:00 PM PDT 24
Finished Jul 30 04:53:01 PM PDT 24
Peak memory 254808 kb
Host smart-bc51a134-1131-49c1-87ee-93a0054b5395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251219132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.251219132
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1840973582
Short name T690
Test name
Test status
Simulation time 27757480319 ps
CPU time 271.81 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:55:26 PM PDT 24
Peak memory 258012 kb
Host smart-68b64645-abbd-49b4-ad98-cc076ced9daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840973582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1840973582
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3745924489
Short name T728
Test name
Test status
Simulation time 3175475147 ps
CPU time 34.93 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:51:21 PM PDT 24
Peak memory 225224 kb
Host smart-f26cd767-edaf-4066-828c-c91d5be7fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745924489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3745924489
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3612568605
Short name T307
Test name
Test status
Simulation time 24964168260 ps
CPU time 59.97 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:51:48 PM PDT 24
Peak memory 235760 kb
Host smart-c191fd3c-f4d5-4caa-8a08-1f182ff808f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612568605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3612568605
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4294202843
Short name T286
Test name
Test status
Simulation time 2758220656 ps
CPU time 69.67 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:52:09 PM PDT 24
Peak memory 257256 kb
Host smart-c76e29ac-6bc4-41dd-b22d-7f7ba9c50daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294202843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4294202843
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3773714664
Short name T59
Test name
Test status
Simulation time 13969973039 ps
CPU time 27.83 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:51:12 PM PDT 24
Peak memory 233492 kb
Host smart-2e13acf1-a117-4e93-a135-dab7da88e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773714664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3773714664
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3825341849
Short name T587
Test name
Test status
Simulation time 10863307270 ps
CPU time 45.75 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:51:29 PM PDT 24
Peak memory 225252 kb
Host smart-80237e6c-6c11-40c5-afb1-c7fab86ba418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825341849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3825341849
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1117064617
Short name T693
Test name
Test status
Simulation time 279578849 ps
CPU time 3.01 seconds
Started Jul 30 04:51:05 PM PDT 24
Finished Jul 30 04:51:08 PM PDT 24
Peak memory 233376 kb
Host smart-eedfae85-53e8-4cca-b04b-97337cf584c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117064617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1117064617
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1315552722
Short name T525
Test name
Test status
Simulation time 451731688 ps
CPU time 2.46 seconds
Started Jul 30 04:50:53 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 225080 kb
Host smart-01debd75-a49b-4522-a8b1-e3797dc9e944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315552722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1315552722
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4059063672
Short name T573
Test name
Test status
Simulation time 3102681061 ps
CPU time 9.39 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 223828 kb
Host smart-f2286839-07c0-42ed-a2a7-9ab15bde0967
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4059063672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4059063672
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3716792910
Short name T285
Test name
Test status
Simulation time 574896941024 ps
CPU time 752.33 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 05:03:25 PM PDT 24
Peak memory 282672 kb
Host smart-c0a38f29-a46a-48cc-a51b-41b6af498fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716792910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3716792910
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.979369514
Short name T958
Test name
Test status
Simulation time 17676041727 ps
CPU time 24.27 seconds
Started Jul 30 04:50:40 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 216988 kb
Host smart-1759e812-dd4a-4594-9665-88885b138297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979369514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.979369514
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3404211076
Short name T1023
Test name
Test status
Simulation time 5393250125 ps
CPU time 14.6 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:51:00 PM PDT 24
Peak memory 217016 kb
Host smart-23f1c6c6-30d9-47ee-a185-70579ae09c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404211076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3404211076
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2707821294
Short name T472
Test name
Test status
Simulation time 112941234 ps
CPU time 1.22 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:51:00 PM PDT 24
Peak memory 216912 kb
Host smart-3069f96c-d4f5-4b5f-b12d-ac4d49319d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707821294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2707821294
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.807588953
Short name T411
Test name
Test status
Simulation time 92057047 ps
CPU time 0.81 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 206480 kb
Host smart-ad34aaf8-d359-4ed5-bcac-27d1a30b126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807588953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.807588953
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.276722742
Short name T253
Test name
Test status
Simulation time 2759936625 ps
CPU time 10.85 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:51:10 PM PDT 24
Peak memory 225456 kb
Host smart-19dbe5f9-b917-41f8-a258-b8b73ea63eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276722742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.276722742
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1935757429
Short name T72
Test name
Test status
Simulation time 22082641 ps
CPU time 0.71 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:48 PM PDT 24
Peak memory 205728 kb
Host smart-56d9d935-6aab-47e5-b630-6150314ecd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935757429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1935757429
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1488575184
Short name T380
Test name
Test status
Simulation time 81589723 ps
CPU time 3.38 seconds
Started Jul 30 04:51:05 PM PDT 24
Finished Jul 30 04:51:09 PM PDT 24
Peak memory 233308 kb
Host smart-5bd574ad-8a3b-4614-8157-31d12e2b2c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488575184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1488575184
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4050653454
Short name T606
Test name
Test status
Simulation time 126002961 ps
CPU time 0.78 seconds
Started Jul 30 04:50:56 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 207308 kb
Host smart-38ea602a-05e0-4386-9e31-ede84bda057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050653454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4050653454
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4253840734
Short name T296
Test name
Test status
Simulation time 34673186102 ps
CPU time 289.85 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:55:36 PM PDT 24
Peak memory 274192 kb
Host smart-3325f289-59a4-474b-86db-1ea5132addbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253840734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4253840734
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.439705337
Short name T757
Test name
Test status
Simulation time 4435617959 ps
CPU time 27.36 seconds
Started Jul 30 04:51:03 PM PDT 24
Finished Jul 30 04:51:30 PM PDT 24
Peak memory 238592 kb
Host smart-58a9c554-bab3-4b7f-b670-74e4661be70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439705337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.439705337
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3463259949
Short name T198
Test name
Test status
Simulation time 16698096219 ps
CPU time 61.79 seconds
Started Jul 30 04:51:05 PM PDT 24
Finished Jul 30 04:52:07 PM PDT 24
Peak memory 256484 kb
Host smart-955881d0-b568-4965-893e-702a40f461ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463259949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3463259949
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1660959726
Short name T355
Test name
Test status
Simulation time 217953953 ps
CPU time 5.07 seconds
Started Jul 30 04:50:58 PM PDT 24
Finished Jul 30 04:51:04 PM PDT 24
Peak memory 225128 kb
Host smart-8c4764d3-a465-42ba-a1d3-5b65c1c5f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660959726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1660959726
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2610293537
Short name T503
Test name
Test status
Simulation time 244737884 ps
CPU time 6.8 seconds
Started Jul 30 04:50:38 PM PDT 24
Finished Jul 30 04:50:45 PM PDT 24
Peak memory 225324 kb
Host smart-7b50fc90-d3b5-40a4-9113-57f5af2e4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610293537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2610293537
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.482845659
Short name T685
Test name
Test status
Simulation time 194987412 ps
CPU time 2.29 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 232992 kb
Host smart-49b5e9a3-352c-4a53-91ca-da0291978ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482845659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.482845659
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1893487805
Short name T273
Test name
Test status
Simulation time 12364230414 ps
CPU time 8.07 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 233324 kb
Host smart-6aa63780-a92c-46c0-bcb4-3cd1de17c655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893487805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1893487805
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.800758820
Short name T921
Test name
Test status
Simulation time 5346974973 ps
CPU time 7.45 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 237496 kb
Host smart-a28bd835-98a9-419e-9a4c-a78b63ec83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800758820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.800758820
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3524252618
Short name T358
Test name
Test status
Simulation time 228169392 ps
CPU time 5.43 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 222908 kb
Host smart-6dcb4672-5544-4fa7-a17c-7b908f9894da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524252618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3524252618
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3173182777
Short name T341
Test name
Test status
Simulation time 156469320 ps
CPU time 0.96 seconds
Started Jul 30 04:50:58 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 207248 kb
Host smart-76b44307-7586-48c6-a1a9-e2e1d53ce648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173182777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3173182777
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.536401817
Short name T312
Test name
Test status
Simulation time 10833769244 ps
CPU time 50.16 seconds
Started Jul 30 04:50:51 PM PDT 24
Finished Jul 30 04:51:42 PM PDT 24
Peak memory 216992 kb
Host smart-2d6fc25d-c4fd-4c92-8514-8df1a38b22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536401817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.536401817
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3335186585
Short name T615
Test name
Test status
Simulation time 10452008835 ps
CPU time 16.44 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 216972 kb
Host smart-1d082b77-7674-42d0-98b7-0b87c091b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335186585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3335186585
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2183571882
Short name T567
Test name
Test status
Simulation time 119808354 ps
CPU time 1.53 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:50:59 PM PDT 24
Peak memory 216908 kb
Host smart-61755cba-6ba9-4a27-ac08-4218442ce45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183571882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2183571882
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2259237299
Short name T398
Test name
Test status
Simulation time 66502463 ps
CPU time 0.8 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 206528 kb
Host smart-8c2c7482-9a10-4cfb-a584-407f90bfbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259237299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2259237299
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.547663356
Short name T430
Test name
Test status
Simulation time 2270215737 ps
CPU time 9.96 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 240268 kb
Host smart-5e3f59d7-f293-40da-bf1c-b4bf891f0395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547663356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.547663356
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.42420768
Short name T494
Test name
Test status
Simulation time 21683938 ps
CPU time 0.71 seconds
Started Jul 30 04:50:43 PM PDT 24
Finished Jul 30 04:50:44 PM PDT 24
Peak memory 206108 kb
Host smart-df40973c-53b8-4a91-bd8b-4973071cb2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42420768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.42420768
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.818875896
Short name T196
Test name
Test status
Simulation time 1070395787 ps
CPU time 10.79 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 233308 kb
Host smart-8d2da207-45bb-484b-b449-67739ee0cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818875896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.818875896
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4262890149
Short name T882
Test name
Test status
Simulation time 60070472 ps
CPU time 0.81 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:50:47 PM PDT 24
Peak memory 207032 kb
Host smart-f4d9dc43-cfa4-47b3-8ab1-e13f9f194fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262890149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4262890149
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1948808195
Short name T619
Test name
Test status
Simulation time 1927037050 ps
CPU time 35.59 seconds
Started Jul 30 04:50:44 PM PDT 24
Finished Jul 30 04:51:20 PM PDT 24
Peak memory 237980 kb
Host smart-86b15af0-8990-4d61-8b9f-8d9e5dd1a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948808195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1948808195
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3968294831
Short name T792
Test name
Test status
Simulation time 10200831966 ps
CPU time 34.92 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:51:23 PM PDT 24
Peak memory 233348 kb
Host smart-9bcd739c-5f8d-41d3-b835-c66291457047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968294831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3968294831
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.150352493
Short name T719
Test name
Test status
Simulation time 5159495942 ps
CPU time 54.66 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:51:40 PM PDT 24
Peak memory 250920 kb
Host smart-7c879847-ccc3-444a-b403-3a1f036b19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150352493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.150352493
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2847100572
Short name T276
Test name
Test status
Simulation time 5378634756 ps
CPU time 13.45 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 221284 kb
Host smart-7e221fb1-5e0f-47a2-825d-f7e822e812ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847100572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2847100572
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4245277151
Short name T576
Test name
Test status
Simulation time 25772199592 ps
CPU time 42.97 seconds
Started Jul 30 04:50:37 PM PDT 24
Finished Jul 30 04:51:21 PM PDT 24
Peak memory 241596 kb
Host smart-7a87b29a-b430-4f62-9f10-aced138867ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245277151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4245277151
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1119761063
Short name T417
Test name
Test status
Simulation time 152540190 ps
CPU time 2.01 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:50:56 PM PDT 24
Peak memory 224688 kb
Host smart-310192e2-0b28-4907-8c31-8dedd28eb8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119761063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1119761063
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1068736163
Short name T46
Test name
Test status
Simulation time 93847165604 ps
CPU time 38.46 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:51:26 PM PDT 24
Peak memory 249860 kb
Host smart-83300241-4558-4ea6-a26f-5ddc4fa5fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068736163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1068736163
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3524599304
Short name T416
Test name
Test status
Simulation time 1125214538 ps
CPU time 7.76 seconds
Started Jul 30 04:51:01 PM PDT 24
Finished Jul 30 04:51:09 PM PDT 24
Peak memory 222488 kb
Host smart-443ea58f-66db-4db3-8c16-519e25e371bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524599304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3524599304
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2155607620
Short name T74
Test name
Test status
Simulation time 52062060 ps
CPU time 1.1 seconds
Started Jul 30 04:51:00 PM PDT 24
Finished Jul 30 04:51:01 PM PDT 24
Peak memory 207364 kb
Host smart-efb905bf-2d17-4951-b554-17c8149e4de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155607620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2155607620
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3344227244
Short name T1002
Test name
Test status
Simulation time 42472811702 ps
CPU time 27.91 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:51:25 PM PDT 24
Peak memory 217160 kb
Host smart-a9877ad2-3d49-4288-b515-d683c22d5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344227244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3344227244
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.6322505
Short name T779
Test name
Test status
Simulation time 3879647312 ps
CPU time 9.05 seconds
Started Jul 30 04:51:07 PM PDT 24
Finished Jul 30 04:51:16 PM PDT 24
Peak memory 216936 kb
Host smart-10680a81-1f31-4cbd-857e-620cc52d06c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6322505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.6322505
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.197978285
Short name T319
Test name
Test status
Simulation time 86886492 ps
CPU time 1.5 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:49 PM PDT 24
Peak memory 216884 kb
Host smart-ed1b5539-f10b-4b5f-bcb3-aa3527d6ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197978285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.197978285
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3630518028
Short name T388
Test name
Test status
Simulation time 51711681 ps
CPU time 0.89 seconds
Started Jul 30 04:50:56 PM PDT 24
Finished Jul 30 04:50:57 PM PDT 24
Peak memory 206428 kb
Host smart-237509f3-36f0-48dc-b676-74d69b2d16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630518028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3630518028
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1481035084
Short name T505
Test name
Test status
Simulation time 624435739 ps
CPU time 8.17 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:51:06 PM PDT 24
Peak memory 241324 kb
Host smart-2f571cd6-a7fa-47f2-9f43-a725719aa4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481035084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1481035084
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3935347890
Short name T883
Test name
Test status
Simulation time 15922349 ps
CPU time 0.71 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:50:58 PM PDT 24
Peak memory 205228 kb
Host smart-86e9e44d-6463-4892-9b40-bed1acfd857d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935347890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3935347890
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3443409219
Short name T960
Test name
Test status
Simulation time 862792026 ps
CPU time 5.72 seconds
Started Jul 30 04:50:47 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 225164 kb
Host smart-023ac41e-acd6-4d1d-b1b9-d62195b0a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443409219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3443409219
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.688813019
Short name T442
Test name
Test status
Simulation time 134036593 ps
CPU time 0.74 seconds
Started Jul 30 04:50:51 PM PDT 24
Finished Jul 30 04:50:52 PM PDT 24
Peak memory 205948 kb
Host smart-fcf3b169-ca9d-460e-bf6c-4431bcc03a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688813019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.688813019
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.191896849
Short name T817
Test name
Test status
Simulation time 32516231126 ps
CPU time 55.8 seconds
Started Jul 30 04:51:05 PM PDT 24
Finished Jul 30 04:52:01 PM PDT 24
Peak memory 225208 kb
Host smart-1f1b5049-dc80-4977-9d3d-13c316dcee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191896849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.191896849
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2310162094
Short name T447
Test name
Test status
Simulation time 22626340917 ps
CPU time 30.21 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:51:24 PM PDT 24
Peak memory 218380 kb
Host smart-d5962132-f900-4624-b50d-d2e9295bc12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310162094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2310162094
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2673264110
Short name T90
Test name
Test status
Simulation time 6163445121 ps
CPU time 38.77 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:51:31 PM PDT 24
Peak memory 251908 kb
Host smart-ddb5bb2b-46f6-46e1-a826-1a0f1716465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673264110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2673264110
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2138740183
Short name T551
Test name
Test status
Simulation time 321362022 ps
CPU time 4.6 seconds
Started Jul 30 04:50:58 PM PDT 24
Finished Jul 30 04:51:03 PM PDT 24
Peak memory 233392 kb
Host smart-fba71b59-23d5-4c00-82a9-de5f55603d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138740183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2138740183
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.945803418
Short name T992
Test name
Test status
Simulation time 2565128261 ps
CPU time 8.09 seconds
Started Jul 30 04:51:18 PM PDT 24
Finished Jul 30 04:51:26 PM PDT 24
Peak memory 225268 kb
Host smart-e80a388c-a706-409e-8671-097aa8b14391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945803418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.945803418
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2598932065
Short name T622
Test name
Test status
Simulation time 291495837 ps
CPU time 2.28 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 224500 kb
Host smart-c01b51ca-7b73-490c-a155-965ca6277c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598932065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2598932065
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1919854670
Short name T12
Test name
Test status
Simulation time 23959552608 ps
CPU time 23.97 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:51:23 PM PDT 24
Peak memory 249740 kb
Host smart-8e9033f1-8944-4a27-a58a-b9ec35a59d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919854670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1919854670
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2508736572
Short name T451
Test name
Test status
Simulation time 3723534546 ps
CPU time 6 seconds
Started Jul 30 04:50:48 PM PDT 24
Finished Jul 30 04:50:54 PM PDT 24
Peak memory 225300 kb
Host smart-c6280cce-c90e-4b4f-a4ab-f832bcf8b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508736572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2508736572
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3620977621
Short name T900
Test name
Test status
Simulation time 1041160016 ps
CPU time 5.44 seconds
Started Jul 30 04:51:00 PM PDT 24
Finished Jul 30 04:51:05 PM PDT 24
Peak memory 223784 kb
Host smart-92e9c1b3-7798-402c-9898-d3ceee3de77e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620977621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3620977621
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4145454276
Short name T774
Test name
Test status
Simulation time 45413352365 ps
CPU time 125.19 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:52:52 PM PDT 24
Peak memory 258080 kb
Host smart-7860f084-d6ad-492c-be23-9bd98ef96f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145454276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4145454276
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1196678939
Short name T427
Test name
Test status
Simulation time 11071583438 ps
CPU time 28.69 seconds
Started Jul 30 04:51:04 PM PDT 24
Finished Jul 30 04:51:33 PM PDT 24
Peak memory 216936 kb
Host smart-29822e42-f643-4aac-a24e-09a809f5dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196678939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1196678939
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2336219633
Short name T461
Test name
Test status
Simulation time 20409764265 ps
CPU time 9.57 seconds
Started Jul 30 04:50:55 PM PDT 24
Finished Jul 30 04:51:05 PM PDT 24
Peak memory 216980 kb
Host smart-d974d403-f9f1-43ef-92e6-f38072c81896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336219633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2336219633
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3795121206
Short name T783
Test name
Test status
Simulation time 25290172 ps
CPU time 1.61 seconds
Started Jul 30 04:51:14 PM PDT 24
Finished Jul 30 04:51:16 PM PDT 24
Peak memory 216828 kb
Host smart-b82393df-1509-4775-9974-5836f1807b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795121206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3795121206
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1349494560
Short name T441
Test name
Test status
Simulation time 69309872 ps
CPU time 0.92 seconds
Started Jul 30 04:50:45 PM PDT 24
Finished Jul 30 04:50:46 PM PDT 24
Peak memory 206480 kb
Host smart-6e98cd9e-1289-42a3-b85b-759e34a53e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349494560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1349494560
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3373773912
Short name T543
Test name
Test status
Simulation time 4639138900 ps
CPU time 17.29 seconds
Started Jul 30 04:50:54 PM PDT 24
Finished Jul 30 04:51:11 PM PDT 24
Peak memory 241348 kb
Host smart-43e8d1cd-f736-4f64-accd-7d57591c6c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373773912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3373773912
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1531512360
Short name T183
Test name
Test status
Simulation time 16635615 ps
CPU time 0.75 seconds
Started Jul 30 04:51:08 PM PDT 24
Finished Jul 30 04:51:09 PM PDT 24
Peak memory 205104 kb
Host smart-7ca2b1fa-e499-4d0c-b894-062c490fa9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531512360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1531512360
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2187494847
Short name T1006
Test name
Test status
Simulation time 3702097048 ps
CPU time 13.52 seconds
Started Jul 30 04:50:52 PM PDT 24
Finished Jul 30 04:51:06 PM PDT 24
Peak memory 225272 kb
Host smart-577ff1d1-486e-4dd2-96e7-59e0d19cffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187494847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2187494847
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2215586055
Short name T146
Test name
Test status
Simulation time 14764941 ps
CPU time 0.78 seconds
Started Jul 30 04:51:09 PM PDT 24
Finished Jul 30 04:51:10 PM PDT 24
Peak memory 206984 kb
Host smart-a36ec5ed-4cb1-4aab-bfdd-f3c4e2dd3d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215586055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2215586055
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1773818071
Short name T550
Test name
Test status
Simulation time 20906816855 ps
CPU time 37.4 seconds
Started Jul 30 04:50:50 PM PDT 24
Finished Jul 30 04:51:28 PM PDT 24
Peak memory 236776 kb
Host smart-522a3ea0-334f-497e-a1d8-03f8de61b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773818071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1773818071
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4019347376
Short name T832
Test name
Test status
Simulation time 8408889833 ps
CPU time 53.77 seconds
Started Jul 30 04:51:07 PM PDT 24
Finished Jul 30 04:52:01 PM PDT 24
Peak memory 238972 kb
Host smart-2fd355f2-88b2-46f0-991a-913600c0a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019347376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4019347376
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1019828669
Short name T308
Test name
Test status
Simulation time 74436745 ps
CPU time 5.22 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:50:55 PM PDT 24
Peak memory 233268 kb
Host smart-e542ac38-e46d-464f-82ab-ea71e3105ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019828669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1019828669
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4013665070
Short name T925
Test name
Test status
Simulation time 55983732064 ps
CPU time 146.67 seconds
Started Jul 30 04:50:51 PM PDT 24
Finished Jul 30 04:53:18 PM PDT 24
Peak memory 255632 kb
Host smart-7f3bcef0-dcbb-456e-bca4-5d408a4ea98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013665070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4013665070
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.550792979
Short name T1022
Test name
Test status
Simulation time 172766718 ps
CPU time 3.38 seconds
Started Jul 30 04:50:59 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 225144 kb
Host smart-3f00ca0f-d732-43ba-9d35-027b96fe7e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550792979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.550792979
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2978672580
Short name T485
Test name
Test status
Simulation time 20900196719 ps
CPU time 39.07 seconds
Started Jul 30 04:50:56 PM PDT 24
Finished Jul 30 04:51:35 PM PDT 24
Peak memory 239648 kb
Host smart-e906129f-87d9-4b72-868e-de6f823e477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978672580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2978672580
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1880708825
Short name T450
Test name
Test status
Simulation time 1378368470 ps
CPU time 7.96 seconds
Started Jul 30 04:50:46 PM PDT 24
Finished Jul 30 04:50:54 PM PDT 24
Peak memory 249344 kb
Host smart-08a9555f-4b26-4064-8a17-ebdf01553e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880708825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1880708825
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.834177210
Short name T675
Test name
Test status
Simulation time 273183289 ps
CPU time 5.97 seconds
Started Jul 30 04:51:08 PM PDT 24
Finished Jul 30 04:51:14 PM PDT 24
Peak memory 233324 kb
Host smart-9713d037-4639-410d-b3f7-f1cefbbe6af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834177210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.834177210
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2502885995
Short name T954
Test name
Test status
Simulation time 3031819730 ps
CPU time 14.6 seconds
Started Jul 30 04:50:57 PM PDT 24
Finished Jul 30 04:51:12 PM PDT 24
Peak memory 223392 kb
Host smart-d68cef32-f33f-4684-b239-a227d5f27b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2502885995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2502885995
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2460227452
Short name T15
Test name
Test status
Simulation time 37053122 ps
CPU time 0.95 seconds
Started Jul 30 04:51:06 PM PDT 24
Finished Jul 30 04:51:07 PM PDT 24
Peak memory 207268 kb
Host smart-ff722c04-e9f5-42e3-867e-63882aa41d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460227452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2460227452
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1215975587
Short name T788
Test name
Test status
Simulation time 1278982712 ps
CPU time 18.2 seconds
Started Jul 30 04:50:49 PM PDT 24
Finished Jul 30 04:51:08 PM PDT 24
Peak memory 216932 kb
Host smart-d2e5aa9a-458b-4be2-bdfb-7e06a0f39b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215975587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1215975587
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2762231791
Short name T6
Test name
Test status
Simulation time 23482726368 ps
CPU time 16.3 seconds
Started Jul 30 04:51:04 PM PDT 24
Finished Jul 30 04:51:21 PM PDT 24
Peak memory 216936 kb
Host smart-e445dc91-5044-4c98-8607-d4cbb217c858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762231791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2762231791
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3262762102
Short name T634
Test name
Test status
Simulation time 39028435 ps
CPU time 0.83 seconds
Started Jul 30 04:50:50 PM PDT 24
Finished Jul 30 04:50:51 PM PDT 24
Peak memory 207208 kb
Host smart-fe63cbe5-33b4-44fb-b5d7-b5d64af37d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262762102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3262762102
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3089109990
Short name T735
Test name
Test status
Simulation time 99764124 ps
CPU time 1.01 seconds
Started Jul 30 04:51:14 PM PDT 24
Finished Jul 30 04:51:16 PM PDT 24
Peak memory 207600 kb
Host smart-3a861fe3-2fa0-460c-8277-29784c4786c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089109990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3089109990
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2289538027
Short name T246
Test name
Test status
Simulation time 513420052 ps
CPU time 2.58 seconds
Started Jul 30 04:50:50 PM PDT 24
Finished Jul 30 04:50:53 PM PDT 24
Peak memory 225280 kb
Host smart-2379c59d-5f2a-42ce-ab7a-85eb1d1dcdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289538027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2289538027
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4072783466
Short name T432
Test name
Test status
Simulation time 16030045 ps
CPU time 0.7 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 205772 kb
Host smart-89a52ed8-38e5-4e7b-b5e4-84abbe9839df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072783466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
072783466
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3061636572
Short name T673
Test name
Test status
Simulation time 167222288 ps
CPU time 4.05 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 233352 kb
Host smart-1062ec1b-98b3-4438-8502-a84a8e631c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061636572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3061636572
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2755937494
Short name T409
Test name
Test status
Simulation time 60414759 ps
CPU time 0.77 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 206304 kb
Host smart-5e002753-d4ec-429b-8741-31d4c93ec884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755937494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2755937494
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1432083026
Short name T778
Test name
Test status
Simulation time 9984920953 ps
CPU time 28.77 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:23 PM PDT 24
Peak memory 239296 kb
Host smart-a9f64cae-d213-48af-8d5c-0131c2b767d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432083026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1432083026
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2119040426
Short name T156
Test name
Test status
Simulation time 22194649065 ps
CPU time 110.88 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:51:02 PM PDT 24
Peak memory 265252 kb
Host smart-d570ec25-c75e-45ec-ab2b-aa784bf163d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119040426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2119040426
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1636522861
Short name T157
Test name
Test status
Simulation time 4666438043 ps
CPU time 55.94 seconds
Started Jul 30 04:48:55 PM PDT 24
Finished Jul 30 04:49:51 PM PDT 24
Peak memory 255460 kb
Host smart-3c858a9c-37cc-47c6-b20e-1d47214980e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636522861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1636522861
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2713169818
Short name T777
Test name
Test status
Simulation time 497254824 ps
CPU time 13.46 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 225040 kb
Host smart-b3c7c10c-c375-43ec-91b1-fe6f1c71f5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713169818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2713169818
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3228781371
Short name T481
Test name
Test status
Simulation time 48328659372 ps
CPU time 164.48 seconds
Started Jul 30 04:48:53 PM PDT 24
Finished Jul 30 04:51:37 PM PDT 24
Peak memory 250588 kb
Host smart-2ff5bdfd-b5f8-4817-a7c2-eef8eeb199c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228781371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3228781371
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2596441685
Short name T453
Test name
Test status
Simulation time 40937132 ps
CPU time 2.39 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 225144 kb
Host smart-3034b2de-fb8a-48bd-8b28-c7d22c4e4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596441685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2596441685
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1934004771
Short name T345
Test name
Test status
Simulation time 9992195577 ps
CPU time 81.12 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 249872 kb
Host smart-c314b80e-fbeb-496a-b004-b863cf6cc820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934004771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1934004771
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3939216323
Short name T496
Test name
Test status
Simulation time 75009370 ps
CPU time 1.02 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:13 PM PDT 24
Peak memory 218376 kb
Host smart-d19be4b7-f0ad-48df-85e8-0c0dd0ba770e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939216323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3939216323
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2310039589
Short name T49
Test name
Test status
Simulation time 5832296106 ps
CPU time 19.31 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:17 PM PDT 24
Peak memory 233388 kb
Host smart-67bb01bc-5984-4d1a-a9f5-a4b54632b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310039589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2310039589
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.465468543
Short name T534
Test name
Test status
Simulation time 65909895 ps
CPU time 2.96 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 233000 kb
Host smart-c465841f-abab-40b2-bdbf-9dd8aab21564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465468543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.465468543
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1972309439
Short name T686
Test name
Test status
Simulation time 23031789523 ps
CPU time 12.76 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 223104 kb
Host smart-30eab942-3c57-4926-a48e-acc428e9bc2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1972309439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1972309439
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2539845632
Short name T492
Test name
Test status
Simulation time 26030130051 ps
CPU time 35.64 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:36 PM PDT 24
Peak memory 221128 kb
Host smart-9c117405-6a1a-4f11-88f6-d561872604f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539845632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2539845632
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1283214496
Short name T60
Test name
Test status
Simulation time 21113249 ps
CPU time 0.73 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 206004 kb
Host smart-ea26d3fe-278f-4f16-9efa-fef74d0d32c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283214496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1283214496
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.827320480
Short name T982
Test name
Test status
Simulation time 360127678 ps
CPU time 3.34 seconds
Started Jul 30 04:48:54 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 216808 kb
Host smart-21b23e69-8f85-4df0-ab7a-efb74c41cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827320480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.827320480
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.895135167
Short name T176
Test name
Test status
Simulation time 217388288 ps
CPU time 0.93 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:57 PM PDT 24
Peak memory 206916 kb
Host smart-951a799f-663d-4b62-8933-5b43fa722a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895135167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.895135167
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3012745694
Short name T948
Test name
Test status
Simulation time 3048175308 ps
CPU time 12.06 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 241688 kb
Host smart-857c8f54-74b6-4c03-88b9-ddd301d2114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012745694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3012745694
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.76318149
Short name T71
Test name
Test status
Simulation time 39444704 ps
CPU time 0.73 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 205232 kb
Host smart-fc15274d-2b75-4910-be5f-46f4de25b9fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76318149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.76318149
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2645181401
Short name T1014
Test name
Test status
Simulation time 165473907 ps
CPU time 3.64 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 225120 kb
Host smart-af2afc2c-75e1-4771-939f-9938b5c37476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645181401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2645181401
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.727579341
Short name T443
Test name
Test status
Simulation time 60714191 ps
CPU time 0.76 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:49:33 PM PDT 24
Peak memory 205936 kb
Host smart-0161847c-715e-4967-9362-cfb8ed41e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727579341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.727579341
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3605349220
Short name T270
Test name
Test status
Simulation time 45404186935 ps
CPU time 307.62 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:54:06 PM PDT 24
Peak memory 256040 kb
Host smart-ef4407a3-b2f1-45bd-b311-4aac90fb7fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605349220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3605349220
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.812998387
Short name T763
Test name
Test status
Simulation time 17072474613 ps
CPU time 55.76 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:53 PM PDT 24
Peak memory 249872 kb
Host smart-bedb053d-f892-4ed6-ae9f-a4c5ff4abcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812998387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.812998387
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.89970984
Short name T397
Test name
Test status
Simulation time 23459885891 ps
CPU time 197.07 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:52:23 PM PDT 24
Peak memory 254652 kb
Host smart-cc1a5a25-850a-4310-9a80-6f62a2577409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89970984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.89970984
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3514993130
Short name T43
Test name
Test status
Simulation time 5133136288 ps
CPU time 17.88 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 241608 kb
Host smart-3831bf15-65eb-41ce-bd58-ddebd934f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514993130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3514993130
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3311019410
Short name T828
Test name
Test status
Simulation time 1123993714 ps
CPU time 3.98 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 225128 kb
Host smart-a473eed1-ed0b-4f83-bbf4-6a3361b0b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311019410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3311019410
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1087675163
Short name T880
Test name
Test status
Simulation time 2291957129 ps
CPU time 13.81 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 233372 kb
Host smart-35c786cd-4cd4-497d-ae96-33fb25081546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087675163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1087675163
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.410859156
Short name T36
Test name
Test status
Simulation time 34748234 ps
CPU time 1.06 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:49:10 PM PDT 24
Peak memory 217028 kb
Host smart-158a9e33-1258-47ef-9609-f54777aad69b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410859156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.410859156
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2411694762
Short name T802
Test name
Test status
Simulation time 43985745823 ps
CPU time 25.37 seconds
Started Jul 30 04:49:25 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 249884 kb
Host smart-6492a607-76c1-49a5-bc0a-101a6c442b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411694762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2411694762
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.710221625
Short name T842
Test name
Test status
Simulation time 665335903 ps
CPU time 2.64 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:04 PM PDT 24
Peak memory 233356 kb
Host smart-281b8a3d-c5e9-43ba-acc7-9299390e5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710221625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.710221625
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2900378409
Short name T63
Test name
Test status
Simulation time 1248963948 ps
CPU time 14.09 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 221208 kb
Host smart-aa9a5ecf-84c0-4791-a545-79adf597c653
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2900378409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2900378409
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.903417813
Short name T639
Test name
Test status
Simulation time 309243746 ps
CPU time 4.72 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:49:11 PM PDT 24
Peak memory 223696 kb
Host smart-dfb00e46-1fd5-4975-baea-369e35e1628a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903417813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.903417813
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4113838166
Short name T363
Test name
Test status
Simulation time 14156094 ps
CPU time 0.72 seconds
Started Jul 30 04:48:57 PM PDT 24
Finished Jul 30 04:48:58 PM PDT 24
Peak memory 206168 kb
Host smart-a39871ac-c445-41d5-a2e9-2dca7e0824a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113838166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4113838166
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2283940779
Short name T959
Test name
Test status
Simulation time 122405197 ps
CPU time 1.14 seconds
Started Jul 30 04:48:58 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 206604 kb
Host smart-ff291a5f-1c4a-4f42-8e2a-d11eac312e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283940779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2283940779
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.656953858
Short name T974
Test name
Test status
Simulation time 145603054 ps
CPU time 2.61 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:10 PM PDT 24
Peak memory 216764 kb
Host smart-9be47d37-662d-4c1a-9dbc-bbca82ce315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656953858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.656953858
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1037952099
Short name T642
Test name
Test status
Simulation time 252405427 ps
CPU time 0.92 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:00 PM PDT 24
Peak memory 206492 kb
Host smart-6ec823fc-a9cf-4fc6-bdee-426f62d86c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037952099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1037952099
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3055549656
Short name T3
Test name
Test status
Simulation time 754955971 ps
CPU time 4.85 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 225132 kb
Host smart-375eb5b3-685c-4cf9-af56-e59bde4a33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055549656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3055549656
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2355107694
Short name T928
Test name
Test status
Simulation time 22137308 ps
CPU time 0.71 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 205192 kb
Host smart-2f490285-3b2c-4e25-938f-58184f508acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355107694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
355107694
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.386206857
Short name T878
Test name
Test status
Simulation time 20308621401 ps
CPU time 18.84 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:20 PM PDT 24
Peak memory 233372 kb
Host smart-73d2608d-96bc-4990-ad1f-24b62a14adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386206857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.386206857
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3211513713
Short name T373
Test name
Test status
Simulation time 14911400 ps
CPU time 0.82 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 207332 kb
Host smart-fac02695-17fc-42a8-b430-3d3920149acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211513713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3211513713
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3152336298
Short name T990
Test name
Test status
Simulation time 1481171834 ps
CPU time 15.77 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:49:26 PM PDT 24
Peak memory 235432 kb
Host smart-7c65ab71-cb6b-4f86-8b75-39b52f68ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152336298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3152336298
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1934502087
Short name T636
Test name
Test status
Simulation time 6956073246 ps
CPU time 71.48 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:50:23 PM PDT 24
Peak memory 253984 kb
Host smart-c21159df-380c-46c3-b4bc-b1bd0a189a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934502087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1934502087
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1003800575
Short name T575
Test name
Test status
Simulation time 158537239533 ps
CPU time 300.84 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:54:07 PM PDT 24
Peak memory 267316 kb
Host smart-07e1ae6c-94d4-4239-9850-698045d40391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003800575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1003800575
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2960693904
Short name T360
Test name
Test status
Simulation time 64200870 ps
CPU time 3.67 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 233268 kb
Host smart-0cba374a-95b0-487e-8ba0-a0e2dd974d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960693904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2960693904
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.140379689
Short name T284
Test name
Test status
Simulation time 30646370200 ps
CPU time 120.65 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:51:21 PM PDT 24
Peak memory 252996 kb
Host smart-4d8916d7-0f7f-468b-8b02-61ed29da23da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140379689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
140379689
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.653808329
Short name T897
Test name
Test status
Simulation time 539054608 ps
CPU time 6.78 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:49:10 PM PDT 24
Peak memory 219468 kb
Host smart-533c7c85-62b5-4e6e-a8f7-8cf5edbc0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653808329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.653808329
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2026958460
Short name T547
Test name
Test status
Simulation time 11998312120 ps
CPU time 76.27 seconds
Started Jul 30 04:49:06 PM PDT 24
Finished Jul 30 04:50:22 PM PDT 24
Peak memory 233472 kb
Host smart-95e80415-f061-40f4-a9fd-108d68c6154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026958460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2026958460
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.712386488
Short name T979
Test name
Test status
Simulation time 123072152 ps
CPU time 1.24 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 217100 kb
Host smart-f28e4475-2aef-472e-9a2d-ba96f72388e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712386488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.712386488
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1180602991
Short name T466
Test name
Test status
Simulation time 4242842502 ps
CPU time 16.6 seconds
Started Jul 30 04:49:24 PM PDT 24
Finished Jul 30 04:49:41 PM PDT 24
Peak memory 240220 kb
Host smart-3a90a331-d767-4141-bc52-e1597e73f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180602991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1180602991
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3365698648
Short name T874
Test name
Test status
Simulation time 472618832 ps
CPU time 3.5 seconds
Started Jul 30 04:49:04 PM PDT 24
Finished Jul 30 04:49:08 PM PDT 24
Peak memory 233372 kb
Host smart-ebda5f0a-c058-40ed-a8ee-d0a70c35867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365698648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3365698648
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.746727432
Short name T40
Test name
Test status
Simulation time 1267960978 ps
CPU time 8.98 seconds
Started Jul 30 04:49:05 PM PDT 24
Finished Jul 30 04:49:14 PM PDT 24
Peak memory 222928 kb
Host smart-0f927ff0-8245-4e45-9ea4-f75e17840d06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746727432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.746727432
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2101717260
Short name T865
Test name
Test status
Simulation time 31922422273 ps
CPU time 43.65 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:50 PM PDT 24
Peak memory 216992 kb
Host smart-99ee2b0f-cbd6-42d1-b308-3ede00940185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101717260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2101717260
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3583946856
Short name T182
Test name
Test status
Simulation time 459761460 ps
CPU time 1.2 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:15 PM PDT 24
Peak memory 207528 kb
Host smart-ca478a87-3ca1-4b86-93d7-38da693c2a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583946856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3583946856
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.657945749
Short name T596
Test name
Test status
Simulation time 237604509 ps
CPU time 2.85 seconds
Started Jul 30 04:48:56 PM PDT 24
Finished Jul 30 04:48:59 PM PDT 24
Peak memory 216996 kb
Host smart-4c94613f-8468-4b19-be1d-600bd9316164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657945749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.657945749
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3367265464
Short name T660
Test name
Test status
Simulation time 14706384 ps
CPU time 0.81 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 206408 kb
Host smart-43d049ae-cd30-4bcf-a1dc-e6882e64938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367265464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3367265464
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.368282507
Short name T423
Test name
Test status
Simulation time 1164691387 ps
CPU time 3.69 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 233428 kb
Host smart-5f26f59f-6720-4240-a6b9-16c3f76cdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368282507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.368282507
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.545197027
Short name T918
Test name
Test status
Simulation time 25617334 ps
CPU time 0.73 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:01 PM PDT 24
Peak memory 205736 kb
Host smart-37ccb8aa-4c50-4a3c-a90e-2600cd5968c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545197027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.545197027
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3333483691
Short name T915
Test name
Test status
Simulation time 137784621 ps
CPU time 2.73 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 233324 kb
Host smart-2988d3dc-10c9-461b-98a0-57c73760d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333483691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3333483691
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.454149849
Short name T531
Test name
Test status
Simulation time 37409107 ps
CPU time 0.8 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:49:14 PM PDT 24
Peak memory 206948 kb
Host smart-879fc7a6-6794-444e-86c9-afc0b980f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454149849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.454149849
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.918011536
Short name T665
Test name
Test status
Simulation time 16580556605 ps
CPU time 50.09 seconds
Started Jul 30 04:49:22 PM PDT 24
Finished Jul 30 04:50:12 PM PDT 24
Peak memory 249944 kb
Host smart-e4507178-a05b-4147-96a8-b76f36d068e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918011536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.918011536
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.432590343
Short name T5
Test name
Test status
Simulation time 1607410207 ps
CPU time 22.01 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:22 PM PDT 24
Peak memory 257664 kb
Host smart-cb5a72f3-86cd-463a-8128-08bac849f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432590343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.432590343
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2330233166
Short name T572
Test name
Test status
Simulation time 7486345389 ps
CPU time 65.33 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:50:17 PM PDT 24
Peak memory 241676 kb
Host smart-9d5407de-70f7-4f07-8877-c4a70ecae5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330233166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2330233166
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1082572014
Short name T150
Test name
Test status
Simulation time 234362499 ps
CPU time 4.22 seconds
Started Jul 30 04:49:23 PM PDT 24
Finished Jul 30 04:49:27 PM PDT 24
Peak memory 233388 kb
Host smart-b5848caa-ac1d-4e8c-ae8c-61e38d20cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082572014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1082572014
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.4215050249
Short name T754
Test name
Test status
Simulation time 45670102331 ps
CPU time 121.37 seconds
Started Jul 30 04:49:13 PM PDT 24
Finished Jul 30 04:51:15 PM PDT 24
Peak memory 257756 kb
Host smart-2e330795-89f8-4c7b-b604-93c962736742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215050249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.4215050249
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4247705080
Short name T348
Test name
Test status
Simulation time 115884908 ps
CPU time 2.34 seconds
Started Jul 30 04:49:29 PM PDT 24
Finished Jul 30 04:49:31 PM PDT 24
Peak memory 233020 kb
Host smart-ea323793-e53c-4edc-ba68-0fc0137b97f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247705080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4247705080
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2113268118
Short name T415
Test name
Test status
Simulation time 31007751433 ps
CPU time 15.9 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 241252 kb
Host smart-741fc195-e531-4aa8-a011-150c0160ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113268118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2113268118
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2439311702
Short name T35
Test name
Test status
Simulation time 194679761 ps
CPU time 1.09 seconds
Started Jul 30 04:48:52 PM PDT 24
Finished Jul 30 04:48:53 PM PDT 24
Peak memory 217084 kb
Host smart-3165cc89-b08e-4b67-83a4-cc0c64cbe512
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439311702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2439311702
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.114164420
Short name T652
Test name
Test status
Simulation time 234209694 ps
CPU time 3.41 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 225140 kb
Host smart-796d3ccd-f3ee-4b02-855c-6fb973d26538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114164420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
114164420
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1963052695
Short name T209
Test name
Test status
Simulation time 23011612206 ps
CPU time 7.44 seconds
Started Jul 30 04:49:20 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 233460 kb
Host smart-f5947e46-766e-4d26-a2b7-8a2a5379c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963052695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1963052695
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2729908184
Short name T676
Test name
Test status
Simulation time 6344393570 ps
CPU time 21.63 seconds
Started Jul 30 04:48:59 PM PDT 24
Finished Jul 30 04:49:21 PM PDT 24
Peak memory 220864 kb
Host smart-e3c52640-b596-4434-843f-1a499de4f6b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2729908184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2729908184
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.81917592
Short name T961
Test name
Test status
Simulation time 11207968339 ps
CPU time 68.78 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:50:19 PM PDT 24
Peak memory 256860 kb
Host smart-295311d0-1c02-44f0-b6e0-0b7072102881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81917592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_
all.81917592
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4065255043
Short name T8
Test name
Test status
Simulation time 2154088799 ps
CPU time 21.27 seconds
Started Jul 30 04:49:22 PM PDT 24
Finished Jul 30 04:49:43 PM PDT 24
Peak memory 217296 kb
Host smart-608aee34-d962-4c74-a0d9-faee05e90c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065255043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4065255043
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3306335883
Short name T352
Test name
Test status
Simulation time 1118492273 ps
CPU time 5.98 seconds
Started Jul 30 04:49:03 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 216876 kb
Host smart-bf296ffc-cd18-4c03-a9e3-df15015e0a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306335883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3306335883
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.140462234
Short name T724
Test name
Test status
Simulation time 254131532 ps
CPU time 3.11 seconds
Started Jul 30 04:49:41 PM PDT 24
Finished Jul 30 04:49:44 PM PDT 24
Peak memory 217000 kb
Host smart-4a1e52d3-9073-45d3-876e-86f1df0a9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140462234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.140462234
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1944929224
Short name T963
Test name
Test status
Simulation time 93827093 ps
CPU time 0.95 seconds
Started Jul 30 04:49:14 PM PDT 24
Finished Jul 30 04:49:15 PM PDT 24
Peak memory 206484 kb
Host smart-5fb2a04c-8f01-4ec6-ae12-8d594fa94547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944929224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1944929224
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1011300138
Short name T666
Test name
Test status
Simulation time 3602592850 ps
CPU time 7.28 seconds
Started Jul 30 04:49:02 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 225248 kb
Host smart-60bc89b0-10ef-4931-b689-4ce27909cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011300138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1011300138
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2115111776
Short name T540
Test name
Test status
Simulation time 12441210 ps
CPU time 0.7 seconds
Started Jul 30 04:49:08 PM PDT 24
Finished Jul 30 04:49:09 PM PDT 24
Peak memory 205152 kb
Host smart-66888f40-6cdf-4f38-b7c1-ef94f2966524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115111776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
115111776
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3108508922
Short name T755
Test name
Test status
Simulation time 596209468 ps
CPU time 5.26 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:06 PM PDT 24
Peak memory 225188 kb
Host smart-11df6332-efc4-45df-857b-9066ea5eeec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108508922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3108508922
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3019214186
Short name T923
Test name
Test status
Simulation time 34940016 ps
CPU time 0.78 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 205928 kb
Host smart-aee166f3-5339-4039-8552-3faccc3fb486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019214186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3019214186
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1614005229
Short name T220
Test name
Test status
Simulation time 2593796010 ps
CPU time 51.41 seconds
Started Jul 30 04:49:11 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 250596 kb
Host smart-3433d7f7-fefb-477e-ad02-4f52c76d97ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614005229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1614005229
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1070766845
Short name T95
Test name
Test status
Simulation time 2591839517 ps
CPU time 61.95 seconds
Started Jul 30 04:49:19 PM PDT 24
Finished Jul 30 04:50:21 PM PDT 24
Peak memory 251964 kb
Host smart-e3f6091c-8436-4c8b-9e4a-c3dc1cbbdf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070766845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1070766845
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.236238343
Short name T616
Test name
Test status
Simulation time 8162407114 ps
CPU time 128.47 seconds
Started Jul 30 04:49:27 PM PDT 24
Finished Jul 30 04:51:36 PM PDT 24
Peak memory 265908 kb
Host smart-e305d81d-0e83-4667-b248-b9a7ca25dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236238343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
236238343
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1333993617
Short name T553
Test name
Test status
Simulation time 199038747 ps
CPU time 6.66 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:49:28 PM PDT 24
Peak memory 225180 kb
Host smart-db46134d-cad1-4ad1-952c-aed94f9486ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333993617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1333993617
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1021787493
Short name T812
Test name
Test status
Simulation time 195358802498 ps
CPU time 328.67 seconds
Started Jul 30 04:49:07 PM PDT 24
Finished Jul 30 04:54:36 PM PDT 24
Peak memory 249772 kb
Host smart-5de801d1-8a5e-486a-b654-90801f06c37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021787493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1021787493
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1797748137
Short name T796
Test name
Test status
Simulation time 234392495 ps
CPU time 3.06 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:49:14 PM PDT 24
Peak memory 233316 kb
Host smart-c750df12-dbad-4bf0-9969-f0e4125bd444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797748137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1797748137
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.317730062
Short name T896
Test name
Test status
Simulation time 107126368 ps
CPU time 2.58 seconds
Started Jul 30 04:49:09 PM PDT 24
Finished Jul 30 04:49:12 PM PDT 24
Peak memory 232980 kb
Host smart-0c67d0ec-d9db-4784-8930-65c731eaa509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317730062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.317730062
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1644946827
Short name T593
Test name
Test status
Simulation time 94418657 ps
CPU time 1.09 seconds
Started Jul 30 04:49:00 PM PDT 24
Finished Jul 30 04:49:02 PM PDT 24
Peak memory 217124 kb
Host smart-a9902c91-f910-480a-853b-8da51549f492
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644946827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1644946827
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.602155713
Short name T836
Test name
Test status
Simulation time 5927884368 ps
CPU time 5.63 seconds
Started Jul 30 04:49:12 PM PDT 24
Finished Jul 30 04:49:18 PM PDT 24
Peak memory 233448 kb
Host smart-a39914f5-b6b6-4489-943b-87de7b3c29b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602155713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
602155713
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1711106392
Short name T201
Test name
Test status
Simulation time 2095529807 ps
CPU time 8.74 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 233328 kb
Host smart-e41aa617-586a-4747-85ac-c9960fbcc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711106392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1711106392
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.98746056
Short name T476
Test name
Test status
Simulation time 801264285 ps
CPU time 6.97 seconds
Started Jul 30 04:49:21 PM PDT 24
Finished Jul 30 04:49:29 PM PDT 24
Peak memory 223608 kb
Host smart-0ab215f4-ceec-4826-9f6e-b26a3b5f5bc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98746056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct
.98746056
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.266647724
Short name T824
Test name
Test status
Simulation time 33471864341 ps
CPU time 43.09 seconds
Started Jul 30 04:49:18 PM PDT 24
Finished Jul 30 04:50:02 PM PDT 24
Peak memory 218108 kb
Host smart-94818ecc-0ba8-492c-b7e0-a7305ebcb5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266647724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.266647724
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.356726738
Short name T864
Test name
Test status
Simulation time 1747670576 ps
CPU time 4.9 seconds
Started Jul 30 04:49:10 PM PDT 24
Finished Jul 30 04:49:15 PM PDT 24
Peak memory 216900 kb
Host smart-1eb8ca5f-343b-4cef-b9f1-02e2c9908145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356726738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.356726738
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2747555880
Short name T320
Test name
Test status
Simulation time 70119802 ps
CPU time 3.29 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:19 PM PDT 24
Peak memory 217212 kb
Host smart-2112ea90-b7b6-4a2e-81c7-ba24609d5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747555880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2747555880
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3930476909
Short name T822
Test name
Test status
Simulation time 380930161 ps
CPU time 0.87 seconds
Started Jul 30 04:49:15 PM PDT 24
Finished Jul 30 04:49:16 PM PDT 24
Peak memory 207492 kb
Host smart-30d81f12-5186-473e-82f0-5dc970b54e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930476909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3930476909
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.28346313
Short name T405
Test name
Test status
Simulation time 157154922 ps
CPU time 3.75 seconds
Started Jul 30 04:49:01 PM PDT 24
Finished Jul 30 04:49:05 PM PDT 24
Peak memory 233384 kb
Host smart-23a55f6d-16f2-4053-bb7a-c2c43672cad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28346313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.28346313
Directory /workspace/9.spi_device_upload/latest
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