Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2337207	1			T1	11603		T2	1		T3	13
all_values[1]	2337207	1			T1	11603		T2	1		T3	13
all_values[2]	2337207	1			T1	11603		T2	1		T3	13
all_values[3]	2337207	1			T1	11603		T2	1		T3	13
all_values[4]	2337207	1			T1	11603		T2	1		T3	13
all_values[5]	2337207	1			T1	11603		T2	1		T3	13
all_values[6]	2337207	1			T1	11603		T2	1		T3	13
all_values[7]	2337207	1			T1	11603		T2	1		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18068670

1

T1

92824

T2

8

T3

104

auto[1]

628986

1

T16

41

T18

102

T20

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18673292

1

T1

92804

T2

8

T3

104

auto[1]

24364

1

T1

20

T8

12

T15

219

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2225092	1			T1	11593		T2	1		T3	13
all_values[0]	auto[0]	auto[1]	11085	1			T1	10		T8	12		T15	110
all_values[0]	auto[1]	auto[0]	100512	1			T16	5		T18	3		T20	5
all_values[0]	auto[1]	auto[1]	518	1			T16	2		T18	8		T22	3
all_values[1]	auto[0]	auto[0]	2237363	1			T1	11593		T2	1		T3	13
all_values[1]	auto[0]	auto[1]	7334	1			T1	10		T15	80		T53	9
all_values[1]	auto[1]	auto[0]	92036	1			T16	3		T18	10		T22	3
all_values[1]	auto[1]	auto[1]	474	1			T16	1		T18	4		T20	1
all_values[2]	auto[0]	auto[0]	2285423	1			T1	11603		T2	1		T3	13
all_values[2]	auto[0]	auto[1]	2910	1			T15	29		T16	22		T65	109
all_values[2]	auto[1]	auto[0]	48614	1			T16	6		T18	8		T22	6
all_values[2]	auto[1]	auto[1]	260	1			T16	2		T18	3		T20	1
all_values[3]	auto[0]	auto[0]	2237742	1			T1	11603		T2	1		T3	13
all_values[3]	auto[0]	auto[1]	219	1			T18	5		T20	1		T149	1
all_values[3]	auto[1]	auto[0]	99058	1			T16	3		T18	3		T22	8
all_values[3]	auto[1]	auto[1]	188	1			T16	4		T18	6		T20	1
all_values[4]	auto[0]	auto[0]	2240824	1			T1	11603		T2	1		T3	13
all_values[4]	auto[0]	auto[1]	165	1			T16	1		T18	10		T35	1
all_values[4]	auto[1]	auto[0]	96033	1			T16	3		T18	7		T20	1
all_values[4]	auto[1]	auto[1]	185	1			T18	6		T20	1		T22	1
all_values[5]	auto[0]	auto[0]	2232705	1			T1	11603		T2	1		T3	13
all_values[5]	auto[0]	auto[1]	144	1			T18	5		T22	5		T34	1
all_values[5]	auto[1]	auto[0]	104183	1			T16	5		T18	6		T20	5
all_values[5]	auto[1]	auto[1]	175	1			T16	2		T18	5		T22	1
all_values[6]	auto[0]	auto[0]	2308951	1			T1	11603		T2	1		T3	13
all_values[6]	auto[0]	auto[1]	173	1			T16	1		T18	4		T20	4
all_values[6]	auto[1]	auto[0]	27911	1			T16	2		T18	11		T34	2062
all_values[6]	auto[1]	auto[1]	172	1			T16	1		T18	5		T22	1
all_values[7]	auto[0]	auto[0]	2278356	1			T1	11603		T2	1		T3	13
all_values[7]	auto[0]	auto[1]	184	1			T16	3		T18	7		T20	1
all_values[7]	auto[1]	auto[0]	58489	1			T16	1		T18	10		T20	3
all_values[7]	auto[1]	auto[1]	178	1			T16	1		T18	7		T34	2