Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33396	1			T1	21		T2	4		T4	120
auto[SpiFlashAddrCfg]	7232	1			T1	12		T4	32		T8	43
auto[SpiFlashAddr3b]	8525	1			T1	6		T4	28		T8	52
auto[SpiFlashAddr4b]	7171	1			T1	4		T2	4		T4	35

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31756

1

T1

30

T2

8

T4

128

auto[1]

24568

1

T1

13

T4

87

T8

151

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29864

1

T1

24

T2

4

T4

115

auto[1]

26460

1

T1

19

T2

4

T4

100

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37842	1			T1	26		T2	4		T4	135
values[1]	1014	1			T4	5		T8	5		T11	8
values[2]	1385	1			T1	3		T4	4		T8	11
values[3]	1355	1			T4	5		T8	11		T11	6
values[4]	1363	1			T1	1		T4	13		T8	7
values[5]	1422	1			T1	2		T4	4		T8	5
values[6]	1350	1			T1	1		T4	2		T8	8
values[7]	1345	1			T1	3		T4	1		T8	5
values[8]	9248	1			T1	7		T2	4		T4	46

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28749

1

T1

43

T2

8

T4

215

auto[1]

27575

1

T8

487

T11

478

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53245

1

T1

41

T2

8

T4

206

write

3079

1

T1

2

T4

9

T8

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18147

1

T1

17

T2

4

T4

70

valids[0x1]

38177

1

T1

26

T2

4

T4

145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1530	1			T1	2		T4	3		T8	17
internal_process_ops[0x5a]	1483	1			T1	1		T4	5		T8	10
internal_process_ops[0x05]	20306	1			T1	6		T2	4		T4	82
internal_process_ops[0x35]	1379	1			T1	2		T4	7		T8	17
internal_process_ops[0x15]	1492	1			T1	1		T4	3		T8	2
internal_process_ops[0x03]	960	1			T1	1		T4	5		T8	4
internal_process_ops[0x0b]	1033	1			T1	1		T4	6		T8	4
internal_process_ops[0x3b]	915	1			T4	1		T11	3		T14	1
internal_process_ops[0x6b]	967	1			T1	1		T4	7		T8	3
internal_process_ops[0xbb]	965	1			T1	2		T4	3		T8	5
internal_process_ops[0xeb]	987	1			T1	1		T2	4		T4	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54825

1

T1

43

T2

8

T4

210

auto[1]

1499

1

T4

5

T8

8

T11

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54081

1

T1

41

T2

8

T4

208

auto[1]

2243

1

T1

2

T4

7

T8

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9453

1

T1

15

T2

4

T4

77

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6502

1

T1

6

T4

40

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1883

1

T1

7

T4

18

T24

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1646

1

T1

5

T4

12

T12

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2224

1

T1

5

T4

15

T13

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1931

1

T1

1

T4

12

T24

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1909

1

T1

1

T2

4

T4

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1689

1

T1

1

T4

18

T12

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T4

1

T16

4

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

67

1

T4

1

T27

4

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T16

1

T43

1

T47

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

92

1

T4

1

T24

1

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

118

1

T4

2

T27

1

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T51

2

T52

1

T22

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T16

3

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

115

1

T16

1

T43

4

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T16

3

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

88

1

T43

1

T47

3

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T4

1

T24

1

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

88

1

T43

4

T51

1

T165

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T1

2

T24

1

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T47

1

T48

3

T22

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T16

4

T43

1

T47

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T4

3

T24

1

T16

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9854

1

T8

257

T11

150

T15

271

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6789

1

T8

72

T11

176

T15

252

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1516

1

T8

25

T11

20

T15

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1397

1

T8

15

T11

28

T15

40

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1869

1

T8

25

T11

33

T14

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1787

1

T8

23

T11

13

T15

51

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1504

1

T8

21

T11

19

T46

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1292

1

T8

34

T11

16

T15

54

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T8

2

T11

1

T15

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T8

4

T11

6

T174

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

109

1

T8

2

T11

2

T15

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T11

4

T15

7

T65

8

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T15

1

T174

2

T34

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T8

1

T15

6

T65

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T8

1

T11

1

T15

9

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

133

1

T8

1

T11

2

T15

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T8

1

T11

1

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T15

6

T79

3

T22

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T8

1

T11

3

T15

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T8

2

T11

1

T15

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

92

1

T11

2

T15

9

T65

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T15

3

T65

2

T79

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T15

5

T65

1

T79

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T15

3

T65

5

T22

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3531	1			T1	9		T4	24		T24	7
auto[0]	values[0]	valids[0x1]	15124	1			T1	17		T2	4		T4	111
auto[0]	values[1]	valids[0x1]	530	1			T4	5		T12	2		T27	5
auto[0]	values[2]	valids[0x0]	451	1			T1	3		T4	3		T24	2
auto[0]	values[2]	valids[0x1]	294	1			T4	1		T27	10		T16	2
auto[0]	values[3]	valids[0x0]	490	1			T4	5		T27	9		T16	6
auto[0]	values[3]	valids[0x1]	280	1			T27	5		T16	12		T43	5
auto[0]	values[4]	valids[0x0]	478	1			T1	1		T4	13		T27	2
auto[0]	values[4]	valids[0x1]	265	1			T24	2		T27	3		T44	1
auto[0]	values[5]	valids[0x0]	513	1			T1	1		T25	4		T27	7
auto[0]	values[5]	valids[0x1]	281	1			T1	1		T4	4		T25	4
auto[0]	values[6]	valids[0x0]	508	1			T4	2		T12	2		T24	4
auto[0]	values[6]	valids[0x1]	257	1			T1	1		T27	2		T16	3
auto[0]	values[7]	valids[0x0]	469	1			T4	1		T27	4		T16	4
auto[0]	values[7]	valids[0x1]	274	1			T1	3		T13	8		T24	3
auto[0]	values[8]	valids[0x0]	3109	1			T1	3		T2	4		T4	22
auto[0]	values[8]	valids[0x1]	1895	1			T1	4		T4	24		T24	7
auto[1]	values[0]	valids[0x0]	3890	1			T8	50		T11	52		T15	130
auto[1]	values[0]	valids[0x1]	15297	1			T8	298		T11	315		T46	3
auto[1]	values[1]	valids[0x1]	484	1			T8	5		T11	8		T15	8
auto[1]	values[2]	valids[0x0]	365	1			T8	4		T11	4		T46	1
auto[1]	values[2]	valids[0x1]	275	1			T8	7		T11	1		T15	6
auto[1]	values[3]	valids[0x0]	364	1			T8	5		T11	3		T46	2
auto[1]	values[3]	valids[0x1]	221	1			T8	6		T11	3		T15	13
auto[1]	values[4]	valids[0x0]	339	1			T8	4		T11	4		T15	19
auto[1]	values[4]	valids[0x1]	281	1			T8	3		T11	5		T15	18
auto[1]	values[5]	valids[0x0]	369	1			T8	3		T11	6		T14	1
auto[1]	values[5]	valids[0x1]	259	1			T8	2		T11	6		T15	4
auto[1]	values[6]	valids[0x0]	365	1			T8	7		T11	6		T15	9
auto[1]	values[6]	valids[0x1]	220	1			T8	1		T11	1		T15	2
auto[1]	values[7]	valids[0x0]	362	1			T8	3		T15	17		T53	1
auto[1]	values[7]	valids[0x1]	240	1			T8	2		T11	5		T15	3
auto[1]	values[8]	valids[0x0]	2544	1			T8	65		T11	36		T15	74
auto[1]	values[8]	valids[0x1]	1700	1			T8	22		T11	23		T46	2