Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3041655

1

T1

3768

T2

3085

T4

12579

auto[1]

32666

1

T1

3

T4

75

T8

227

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

863392

1

T1

12

T2

2061

T4

42

auto[1]

2210929

1

T1

3759

T2

1024

T4

12612

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	557138	1			T1	12		T2	1781		T4	6307
auto[524288:1048575]	392332	1			T1	135		T2	761		T4	1119
auto[1048576:1572863]	365601	1			T5	1221		T8	434		T11	26
auto[1572864:2097151]	328142	1			T1	3185		T2	99		T4	515
auto[2097152:2621439]	348908	1			T1	438		T2	1		T4	27
auto[2621440:3145727]	333670	1			T2	415		T4	3242		T5	1350
auto[3145728:3670015]	386576	1			T4	1310		T5	3		T8	4159
auto[3670016:4194303]	361954	1			T1	1		T2	28		T4	134

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2245776

1

T1

3771

T2

1035

T4

12647

auto[1]

828545

1

T2

2050

T4

7

T5

6070

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2640184

1

T1

394

T2

3085

T4

12650

auto[1]

434137

1

T1

3377

T4

4

T8

1768

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	190346	1			T1	1		T2	760		T4	7
auto[0]	auto[0]	auto[0:524287]	auto[1]	306409	1			T1	2		T2	1021		T4	6276
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	87161	1			T1	2		T2	761		T4	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	233902	1			T1	133		T4	1111		T8	2008
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	108445	1			T5	1221		T8	3		T11	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	205762	1			T8	257		T11	1		T15	4265
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	82500	1			T2	99		T4	3		T5	736
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	202307	1			T1	256		T4	512		T8	1702
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	78300	1			T2	1		T4	2		T5	760
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	210378	1			T4	1		T8	2		T11	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	84736	1			T2	412		T4	7		T5	1350
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	196100	1			T2	3		T4	3233		T11	693
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105688	1			T4	4		T5	3		T8	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	218888	1			T4	1282		T8	3110		T11	3377
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	112441	1			T2	28		T4	2		T5	1478
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	190571	1			T4	129		T8	2249		T11	640
auto[0]	auto[1]	auto[0:524287]	auto[0]	2082	1			T1	4		T11	4		T15	8
auto[0]	auto[1]	auto[0:524287]	auto[1]	53435	1			T1	2		T8	4		T11	257
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	544	1			T8	2		T15	3		T27	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	65826	1			T15	129		T27	3		T16	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1630	1			T8	5		T11	2		T15	10
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46268	1			T8	133		T15	4		T16	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1129	1			T8	4		T15	4		T27	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	38585	1			T1	2929		T8	512		T15	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	953	1			T1	2		T4	3		T15	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	55676	1			T1	436		T15	259		T16	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	553	1			T8	2		T11	1		T15	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47231	1			T8	1		T11	128		T15	640
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2368	1			T8	6		T15	7		T27	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55982	1			T8	1037		T16	3		T174	2391
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	561	1			T1	1		T4	1		T11	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54898	1			T11	515		T15	2191		T27	520
auto[1]	auto[0]	auto[0:524287]	auto[0]	432	1			T4	1		T8	2		T15	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	3683	1			T4	23		T8	58		T15	47
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	397	1			T4	1		T8	3		T11	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3290	1			T4	1		T8	60		T11	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	406	1			T8	1		T11	1		T15	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2732	1			T8	10		T11	18		T15	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	402	1			T8	2		T11	4		T24	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2032	1			T8	7		T11	57		T24	295
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	433	1			T4	1		T8	2		T15	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2302	1			T4	20		T8	18		T15	24
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	424	1			T4	1		T15	3		T27	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3868	1			T4	1		T15	19		T27	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	325	1			T4	2		T11	1		T15	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2856	1			T4	22		T11	24		T15	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	359	1			T4	1		T8	1		T15	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2309	1			T4	1		T8	1		T15	60
auto[1]	auto[1]	auto[0:524287]	auto[0]	137	1			T1	2		T11	1		T15	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	614	1			T1	1		T11	62		T15	40
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	81	1			T15	1		T27	1		T52	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1131	1			T15	14		T27	29		T52	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	63	1			T8	2		T15	4		T16	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	295	1			T8	23		T15	13		T16	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	115	1			T15	1		T27	1		T174	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1072	1			T15	3		T27	3		T174	33
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	95	1			T65	2		T47	3		T34	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	771	1			T65	1		T34	6		T163	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	118	1			T8	1		T16	1		T34	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	640	1			T8	36		T16	46		T34	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	50	1			T174	3		T34	1		T201	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	419	1			T174	29		T201	60		T194	21
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	118	1			T11	3		T15	1		T47	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	697	1			T11	64		T15	6		T22	35

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1791146	1			T1	394		T2	1035		T4	12573
auto[0]	auto[0]	auto[1]	822788	1			T2	2050		T4	2		T5	6070
auto[0]	auto[1]	auto[0]	422595	1			T1	3374		T4	4		T8	1704
auto[0]	auto[1]	auto[1]	5126	1			T8	2		T11	4		T27	1
auto[1]	auto[0]	auto[0]	25745	1			T4	70		T8	162		T11	107
auto[1]	auto[0]	auto[1]	505	1			T4	5		T8	3		T11	1
auto[1]	auto[1]	auto[0]	6290	1			T1	3		T8	62		T11	130
auto[1]	auto[1]	auto[1]	126	1			T15	1		T27	1		T47	1