Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2337207	1			T1	11603		T2	1		T3	13
all_pins[1]	2337207	1			T1	11603		T2	1		T3	13
all_pins[2]	2337207	1			T1	11603		T2	1		T3	13
all_pins[3]	2337207	1			T1	11603		T2	1		T3	13
all_pins[4]	2337207	1			T1	11603		T2	1		T3	13
all_pins[5]	2337207	1			T1	11603		T2	1		T3	13
all_pins[6]	2337207	1			T1	11603		T2	1		T3	13
all_pins[7]	2337207	1			T1	11603		T2	1		T3	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18666774	1			T1	92824		T2	8		T3	104
values[0x1]	30882	1			T16	13		T18	44		T20	4
transitions[0x0=>0x1]	29709	1			T16	11		T18	33		T20	3
transitions[0x1=>0x0]	29720	1			T16	11		T18	33		T20	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2336610	1			T1	11603		T2	1		T3	13
all_pins[0]	values[0x1]	597	1			T16	2		T18	8		T22	3
all_pins[0]	transitions[0x0=>0x1]	340	1			T16	2		T18	6		T22	1
all_pins[0]	transitions[0x1=>0x0]	258	1			T16	1		T18	2		T20	1
all_pins[1]	values[0x0]	2336692	1			T1	11603		T2	1		T3	13
all_pins[1]	values[0x1]	515	1			T16	1		T18	4		T20	1
all_pins[1]	transitions[0x0=>0x1]	436	1			T18	3		T22	5		T34	1
all_pins[1]	transitions[0x1=>0x0]	194	1			T16	1		T18	2		T22	1
all_pins[2]	values[0x0]	2336934	1			T1	11603		T2	1		T3	13
all_pins[2]	values[0x1]	273	1			T16	2		T18	3		T20	1
all_pins[2]	transitions[0x0=>0x1]	226	1			T16	1		T18	1		T20	1
all_pins[2]	transitions[0x1=>0x0]	141	1			T16	3		T18	4		T20	1
all_pins[3]	values[0x0]	2337019	1			T1	11603		T2	1		T3	13
all_pins[3]	values[0x1]	188	1			T16	4		T18	6		T20	1
all_pins[3]	transitions[0x0=>0x1]	138	1			T16	4		T18	4		T20	1
all_pins[3]	transitions[0x1=>0x0]	135	1			T18	4		T20	1		T22	1
all_pins[4]	values[0x0]	2337022	1			T1	11603		T2	1		T3	13
all_pins[4]	values[0x1]	185	1			T18	6		T20	1		T22	1
all_pins[4]	transitions[0x0=>0x1]	146	1			T18	6		T20	1		T22	1
all_pins[4]	transitions[0x1=>0x0]	1176	1			T16	2		T18	5		T22	1
all_pins[5]	values[0x0]	2335992	1			T1	11603		T2	1		T3	13
all_pins[5]	values[0x1]	1215	1			T16	2		T18	5		T22	1
all_pins[5]	transitions[0x0=>0x1]	592	1			T16	2		T18	4		T22	1
all_pins[5]	transitions[0x1=>0x0]	27108	1			T16	1		T18	4		T22	1
all_pins[6]	values[0x0]	2309476	1			T1	11603		T2	1		T3	13
all_pins[6]	values[0x1]	27731	1			T16	1		T18	5		T22	1
all_pins[6]	transitions[0x0=>0x1]	27691	1			T16	1		T18	3		T22	1
all_pins[6]	transitions[0x1=>0x0]	138	1			T16	1		T18	5		T34	1
all_pins[7]	values[0x0]	2337029	1			T1	11603		T2	1		T3	13
all_pins[7]	values[0x1]	178	1			T16	1		T18	7		T34	2
all_pins[7]	transitions[0x0=>0x1]	140	1			T16	1		T18	6		T34	2
all_pins[7]	transitions[0x1=>0x0]	570	1			T16	2		T18	7		T22	3