Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16244

1

T1

30

T2

8

T4

128

auto[1]

12505

1

T1

13

T4

87

T12

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3168	1			T4	26		T27	20		T16	75
values[1]	3491	1			T27	31		T16	58		T43	40
values[2]	4008	1			T1	20		T4	65		T27	121
values[3]	3733	1			T1	23		T2	8		T4	64
values[4]	3620	1			T24	20		T16	160		T43	20
values[5]	3948	1			T4	40		T27	20		T16	114
values[6]	3085	1			T4	20		T13	8		T24	20
values[7]	3696	1			T12	6		T24	20		T27	54

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3985	1			T1	23		T4	24		T24	20
values[1]	3900	1			T4	64		T26	8		T27	20
values[2]	3125	1			T27	123		T43	20		T242	4
values[3]	3436	1			T4	40		T13	8		T25	16
values[4]	3613	1			T1	20		T4	41		T12	6
values[5]	3149	1			T16	36		T43	20		T44	20
values[6]	3395	1			T24	20		T27	87		T16	25
values[7]	4146	1			T2	8		T4	46		T16	205

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	307	1			T193	9		T243	10		T244	22
auto[0]	values[0]	values[1]	246	1			T16	13		T47	10		T210	16
auto[0]	values[0]	values[2]	210	1			T242	4		T130	14		T245	10
auto[0]	values[0]	values[3]	336	1			T16	43		T163	15		T130	15
auto[0]	values[0]	values[4]	103	1			T246	2		T47	14		T215	16
auto[0]	values[0]	values[5]	305	1			T44	8		T228	10		T219	14
auto[0]	values[0]	values[6]	173	1			T27	11		T51	18		T22	15
auto[0]	values[0]	values[7]	301	1			T4	13		T221	4		T247	8
auto[0]	values[1]	values[0]	251	1			T43	9		T248	10		T249	2
auto[0]	values[1]	values[1]	294	1			T16	14		T201	10		T198	8
auto[0]	values[1]	values[2]	113	1			T250	4		T163	12		T91	11
auto[0]	values[1]	values[3]	319	1			T43	12		T165	9		T88	8
auto[0]	values[1]	values[4]	203	1			T27	22		T51	27		T22	43
auto[0]	values[1]	values[5]	322	1			T16	25		T48	9		T163	16
auto[0]	values[1]	values[6]	105	1			T48	22		T212	14		T251	2
auto[0]	values[1]	values[7]	341	1			T252	8		T130	12		T202	15
auto[0]	values[2]	values[0]	257	1			T4	15		T27	39		T95	12
auto[0]	values[2]	values[1]	226	1			T27	12		T52	61		T206	14
auto[0]	values[2]	values[2]	428	1			T27	46		T49	14		T20	18
auto[0]	values[2]	values[3]	181	1			T253	2		T48	8		T163	9
auto[0]	values[2]	values[4]	200	1			T1	12		T4	36		T20	11
auto[0]	values[2]	values[5]	250	1			T43	8		T227	22		T228	10
auto[0]	values[2]	values[6]	299	1			T212	13		T223	13		T254	13
auto[0]	values[2]	values[7]	353	1			T16	10		T91	14		T243	15
auto[0]	values[3]	values[0]	321	1			T1	18		T192	18		T16	7
auto[0]	values[3]	values[1]	353	1			T4	21		T26	8		T47	17
auto[0]	values[3]	values[2]	133	1			T198	7		T91	10		T204	12
auto[0]	values[3]	values[3]	154	1			T25	16		T212	12		T208	12
auto[0]	values[3]	values[4]	274	1			T44	16		T49	7		T163	33
auto[0]	values[3]	values[5]	196	1			T52	15		T22	36		T208	14
auto[0]	values[3]	values[6]	565	1			T27	25		T52	54		T255	10
auto[0]	values[3]	values[7]	191	1			T2	8		T43	15		T96	8
auto[0]	values[4]	values[0]	392	1			T24	8		T48	24		T22	23
auto[0]	values[4]	values[1]	351	1			T51	7		T216	45		T228	11
auto[0]	values[4]	values[2]	236	1			T231	6		T35	46		T216	14
auto[0]	values[4]	values[3]	208	1			T16	101		T256	2		T163	15
auto[0]	values[4]	values[4]	232	1			T52	21		T35	11		T257	4
auto[0]	values[4]	values[5]	150	1			T35	12		T258	2		T259	20
auto[0]	values[4]	values[6]	319	1			T16	14		T35	6		T130	14
auto[0]	values[4]	values[7]	516	1			T16	16		T43	13		T47	29
auto[0]	values[5]	values[0]	191	1			T22	11		T163	10		T237	12
auto[0]	values[5]	values[1]	504	1			T47	8		T22	41		T201	11
auto[0]	values[5]	values[2]	211	1			T27	12		T43	8		T165	15
auto[0]	values[5]	values[3]	350	1			T4	30		T16	61		T22	11
auto[0]	values[5]	values[4]	216	1			T51	12		T163	7		T165	10
auto[0]	values[5]	values[5]	176	1			T22	8		T201	11		T130	18
auto[0]	values[5]	values[6]	124	1			T47	10		T76	2		T237	25
auto[0]	values[5]	values[7]	208	1			T16	10		T47	6		T22	10
auto[0]	values[6]	values[0]	168	1			T232	8		T260	22		T208	22
auto[0]	values[6]	values[1]	154	1			T261	6		T228	13		T262	12
auto[0]	values[6]	values[2]	248	1			T27	21		T165	10		T263	16
auto[0]	values[6]	values[3]	137	1			T13	8		T35	13		T194	12
auto[0]	values[6]	values[4]	251	1			T24	10		T35	11		T91	8
auto[0]	values[6]	values[5]	151	1			T237	14		T201	10		T228	12
auto[0]	values[6]	values[6]	220	1			T48	16		T227	8		T228	11
auto[0]	values[6]	values[7]	121	1			T4	13		T163	8		T155	23
auto[0]	values[7]	values[0]	229	1			T205	8		T228	12		T204	14
auto[0]	values[7]	values[1]	276	1			T43	12		T51	7		T195	22
auto[0]	values[7]	values[2]	245	1			T27	14		T52	12		T201	11
auto[0]	values[7]	values[3]	285	1			T16	15		T162	4		T220	14
auto[0]	values[7]	values[4]	335	1			T16	26		T264	12		T265	4
auto[0]	values[7]	values[5]	331	1			T51	18		T198	69		T212	19
auto[0]	values[7]	values[6]	190	1			T24	15		T27	14		T51	20
auto[0]	values[7]	values[7]	209	1			T266	2		T35	13		T201	12
auto[1]	values[0]	values[0]	216	1			T193	11		T243	13		T224	9
auto[1]	values[0]	values[1]	130	1			T16	9		T47	10		T35	10
auto[1]	values[0]	values[2]	84	1			T130	9		T199	8		T211	7
auto[1]	values[0]	values[3]	122	1			T16	10		T163	8		T130	5
auto[1]	values[0]	values[4]	39	1			T47	6		T254	5		T92	11
auto[1]	values[0]	values[5]	122	1			T44	12		T228	10		T219	6
auto[1]	values[0]	values[6]	200	1			T27	9		T51	10		T22	12
auto[1]	values[0]	values[7]	274	1			T4	13		T204	7		T196	12
auto[1]	values[1]	values[0]	325	1			T43	11		T219	95		T211	11
auto[1]	values[1]	values[1]	177	1			T16	8		T201	10		T198	12
auto[1]	values[1]	values[2]	99	1			T163	9		T91	9		T219	9
auto[1]	values[1]	values[3]	311	1			T43	8		T165	40		T198	4
auto[1]	values[1]	values[4]	179	1			T27	9		T51	15		T22	12
auto[1]	values[1]	values[5]	145	1			T16	11		T48	11		T163	12
auto[1]	values[1]	values[6]	120	1			T48	18		T212	10		T267	38
auto[1]	values[1]	values[7]	187	1			T130	8		T202	5		T227	11
auto[1]	values[2]	values[0]	333	1			T4	9		T27	8		T16	6
auto[1]	values[2]	values[1]	114	1			T27	8		T52	8		T212	21
auto[1]	values[2]	values[2]	346	1			T27	8		T49	6		T20	10
auto[1]	values[2]	values[3]	125	1			T48	12		T163	11		T91	16
auto[1]	values[2]	values[4]	311	1			T1	8		T4	5		T20	12
auto[1]	values[2]	values[5]	191	1			T43	12		T227	18		T228	16
auto[1]	values[2]	values[6]	147	1			T212	7		T223	7		T254	9
auto[1]	values[2]	values[7]	247	1			T16	124		T91	6		T243	5
auto[1]	values[3]	values[0]	271	1			T1	5		T16	13		T43	8
auto[1]	values[3]	values[1]	200	1			T4	43		T47	3		T51	18
auto[1]	values[3]	values[2]	143	1			T198	13		T91	10		T268	22
auto[1]	values[3]	values[3]	162	1			T212	12		T208	73		T196	18
auto[1]	values[3]	values[4]	185	1			T44	4		T49	13		T163	21
auto[1]	values[3]	values[5]	113	1			T52	13		T22	9		T208	37
auto[1]	values[3]	values[6]	312	1			T27	10		T52	16		T194	8
auto[1]	values[3]	values[7]	160	1			T43	5		T194	12		T269	50
auto[1]	values[4]	values[0]	221	1			T24	12		T48	16		T22	10
auto[1]	values[4]	values[1]	131	1			T51	13		T216	7		T228	9
auto[1]	values[4]	values[2]	165	1			T35	22		T216	6		T228	12
auto[1]	values[4]	values[3]	83	1			T16	10		T50	6		T163	7
auto[1]	values[4]	values[4]	101	1			T52	6		T35	12		T228	6
auto[1]	values[4]	values[5]	99	1			T35	8		T211	14		T92	9
auto[1]	values[4]	values[6]	174	1			T16	11		T35	14		T130	9
auto[1]	values[4]	values[7]	242	1			T16	8		T43	7		T47	11
auto[1]	values[5]	values[0]	193	1			T22	9		T163	10		T237	8
auto[1]	values[5]	values[1]	345	1			T47	12		T22	17		T201	44
auto[1]	values[5]	values[2]	190	1			T27	8		T43	12		T165	5
auto[1]	values[5]	values[3]	323	1			T4	10		T16	6		T22	61
auto[1]	values[5]	values[4]	271	1			T51	8		T163	13		T165	10
auto[1]	values[5]	values[5]	222	1			T22	12		T201	9		T130	2
auto[1]	values[5]	values[6]	221	1			T47	10		T237	15		T91	7
auto[1]	values[5]	values[7]	203	1			T16	37		T47	14		T22	18
auto[1]	values[6]	values[0]	98	1			T270	12		T208	7		T196	20
auto[1]	values[6]	values[1]	241	1			T228	8		T262	175		T271	8
auto[1]	values[6]	values[2]	132	1			T27	6		T165	36		T208	8
auto[1]	values[6]	values[3]	252	1			T35	9		T194	37		T272	14
auto[1]	values[6]	values[4]	318	1			T24	10		T35	13		T91	12
auto[1]	values[6]	values[5]	188	1			T237	6		T201	49		T228	8
auto[1]	values[6]	values[6]	103	1			T48	4		T227	12		T228	11
auto[1]	values[6]	values[7]	303	1			T4	7		T163	13		T155	29
auto[1]	values[7]	values[0]	212	1			T228	9		T204	99		T196	9
auto[1]	values[7]	values[1]	158	1			T43	8		T51	13		T35	8
auto[1]	values[7]	values[2]	142	1			T27	8		T52	8		T201	40
auto[1]	values[7]	values[3]	88	1			T16	13		T202	10		T92	6
auto[1]	values[7]	values[4]	395	1			T12	6		T16	6		T47	10
auto[1]	values[7]	values[5]	188	1			T51	4		T198	6		T212	11
auto[1]	values[7]	values[6]	123	1			T24	5		T27	18		T51	24
auto[1]	values[7]	values[7]	290	1			T35	7		T201	82		T219	69