Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	392	1			T4	3		T13	2		T24	1
auto[ReadAddrCrossIntoMailbox]	285	1			T1	2		T4	3		T13	2
auto[ReadAddrCrossOutOfMailbox]	284	1			T1	2		T13	4		T27	2
auto[ReadAddrCrossAllMailbox]	206	1			T27	4		T16	4		T43	1
auto[ReadAddrOutsideMailbox]	3081	1			T1	2		T2	4		T4	28

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T1

2

T2

2

T4

13

auto[1]

2070

1

T1

4

T2

2

T4

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	711	1			T1	1		T4	5		T12	2
read_ops[0x0b]	776	1			T1	1		T4	6		T13	8
read_ops[0x3b]	601	1			T4	1		T24	3		T27	9
read_ops[0x6b]	715	1			T1	1		T4	7		T24	1
read_ops[0xbb]	719	1			T1	2		T4	3		T12	2
read_ops[0xeb]	726	1			T1	1		T2	4		T4	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T225	1		T193	1		T90	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T225	1		T202	1		T90	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T44	1		T202	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T130	2		T208	2		T219	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T1	1		T35	1		T225	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T27	1		T16	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T27	1		T237	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T27	1		T35	1		T227	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T4	1		T12	1		T27	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	239	1			T4	4		T12	1		T27	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T13	1		T43	1		T266	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T4	1		T13	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T4	1		T13	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T13	1		T47	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T13	2		T51	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T1	1		T13	2		T43	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T27	1		T44	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T16	1		T48	1		T225	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T4	1		T27	6		T16	10
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T4	3		T24	1		T27	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T47	2		T51	1		T22	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T35	1		T216	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T231	1		T22	1		T228	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T24	1		T27	1		T231	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T48	1		T231	1		T51	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T27	1		T231	1		T22	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T51	1		T52	1		T237	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T16	1		T130	1		T216	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	223	1			T4	1		T24	1		T27	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T24	1		T27	2		T95	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T47	1		T163	1		T201	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T4	1		T24	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T27	1		T47	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T4	1		T48	2		T202	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T47	1		T202	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T47	1		T35	2		T193	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T27	1		T16	1		T202	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T43	1		T48	1		T163	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T4	2		T26	1		T16	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T1	1		T4	3		T26	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T27	1		T47	1		T52	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T44	1		T47	1		T273	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T47	1		T35	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T1	1		T16	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T16	1		T51	1		T52	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T44	1		T165	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T237	1		T216	2		T91	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T48	1		T198	1		T193	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T4	2		T12	1		T27	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T1	1		T4	1		T12	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T4	1		T48	3		T230	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T16	2		T20	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T1	1		T24	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T4	1		T24	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T231	1		T198	1		T130	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T16	2		T231	1		T237	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T16	1		T165	2		T130	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T44	1		T130	1		T227	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T2	2		T4	4		T24	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T2	2		T4	6		T27	4