Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2964	1			T27	22		T47	40		T48	20
values[1]	2718	1			T4	26		T27	74		T95	12
values[2]	3806	1			T4	41		T26	8		T27	78
values[3]	3260	1			T4	20		T12	6		T13	8
values[4]	4165	1			T1	43		T24	20		T16	67
values[5]	4028	1			T4	60		T27	67		T192	18
values[6]	3845	1			T16	309		T264	12		T43	40
values[7]	3963	1			T2	8		T4	68		T24	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3462	1			T4	41		T27	32		T16	47
values[1]	3684	1			T2	8		T95	12		T16	60
values[2]	3039	1			T1	20		T4	60		T13	8
values[3]	4326	1			T4	44		T24	20		T25	16
values[4]	3480	1			T4	20		T27	49		T264	12
values[5]	3540	1			T4	26		T27	20		T16	233
values[6]	3842	1			T12	6		T24	20		T26	8
values[7]	3376	1			T1	23		T4	24		T16	75

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28040

1

T1

43

T2

8

T4

210

auto[1]

709

1

T4

5

T24

2

T27

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	268	1			T47	20		T35	22		T219	28
auto[0]	values[0]	values[1]	479	1			T163	21		T210	16		T35	24
auto[0]	values[0]	values[2]	287	1			T163	24		T194	65		T274	2
auto[0]	values[0]	values[3]	437	1			T47	20		T35	19		T275	4
auto[0]	values[0]	values[4]	435	1			T27	22		T52	27		T238	26
auto[0]	values[0]	values[5]	263	1			T48	20		T52	20		T35	21
auto[0]	values[0]	values[6]	439	1			T198	20		T130	20		T202	20
auto[0]	values[0]	values[7]	290	1			T51	20		T193	20		T258	2
auto[0]	values[1]	values[0]	335	1			T43	20		T276	10		T228	22
auto[0]	values[1]	values[1]	267	1			T95	12		T163	20		T249	2
auto[0]	values[1]	values[2]	367	1			T27	53		T43	20		T47	19
auto[0]	values[1]	values[3]	394	1			T277	2		T278	21		T254	40
auto[0]	values[1]	values[4]	169	1			T220	14		T228	20		T219	20
auto[0]	values[1]	values[5]	401	1			T4	24		T202	39		T194	18
auto[0]	values[1]	values[6]	378	1			T27	20		T76	2		T22	20
auto[0]	values[1]	values[7]	337	1			T16	20		T44	20		T22	27
auto[0]	values[2]	values[0]	526	1			T4	41		T16	46		T51	20
auto[0]	values[2]	values[1]	269	1			T242	4		T48	20		T35	17
auto[0]	values[2]	values[2]	264	1			T237	39		T216	22		T92	33
auto[0]	values[2]	values[3]	905	1			T27	31		T195	22		T234	8
auto[0]	values[2]	values[4]	436	1			T27	25		T52	98		T205	8
auto[0]	values[2]	values[5]	483	1			T27	19		T194	20		T91	20
auto[0]	values[2]	values[6]	613	1			T26	8		T253	2		T230	16
auto[0]	values[2]	values[7]	230	1			T43	19		T50	2		T279	6
auto[0]	values[3]	values[0]	493	1			T280	14		T271	33		T281	18
auto[0]	values[3]	values[1]	354	1			T282	2		T201	53		T198	28
auto[0]	values[3]	values[2]	380	1			T4	20		T13	8		T47	18
auto[0]	values[3]	values[3]	445	1			T25	16		T27	47		T283	4
auto[0]	values[3]	values[4]	381	1			T20	28		T194	42		T216	27
auto[0]	values[3]	values[5]	287	1			T130	20		T228	20		T91	19
auto[0]	values[3]	values[6]	355	1			T12	6		T48	20		T51	26
auto[0]	values[3]	values[7]	482	1			T16	22		T51	20		T165	49
auto[0]	values[4]	values[0]	392	1			T48	17		T194	49		T216	20
auto[0]	values[4]	values[1]	771	1			T254	22		T155	24		T156	18
auto[0]	values[4]	values[2]	434	1			T1	20		T163	27		T201	20
auto[0]	values[4]	values[3]	394	1			T43	19		T22	20		T225	12
auto[0]	values[4]	values[4]	559	1			T246	2		T52	47		T22	63
auto[0]	values[4]	values[5]	489	1			T16	67		T20	22		T231	6
auto[0]	values[4]	values[6]	686	1			T24	19		T47	19		T163	20
auto[0]	values[4]	values[7]	344	1			T1	23		T43	20		T163	20
auto[0]	values[5]	values[0]	340	1			T27	32		T266	2		T22	33
auto[0]	values[5]	values[1]	521	1			T165	18		T88	8		T194	20
auto[0]	values[5]	values[2]	322	1			T4	39		T51	20		T130	40
auto[0]	values[5]	values[3]	451	1			T27	33		T192	18		T165	19
auto[0]	values[5]	values[4]	789	1			T4	19		T43	16		T47	19
auto[0]	values[5]	values[5]	589	1			T16	133		T265	4		T163	20
auto[0]	values[5]	values[6]	404	1			T47	40		T51	20		T237	20
auto[0]	values[5]	values[7]	489	1			T48	18		T52	20		T165	48
auto[0]	values[6]	values[0]	314	1			T221	4		T193	115		T208	73
auto[0]	values[6]	values[1]	510	1			T16	60		T252	8		T163	19
auto[0]	values[6]	values[2]	497	1			T16	70		T43	37		T91	20
auto[0]	values[6]	values[3]	634	1			T16	111		T51	25		T212	24
auto[0]	values[6]	values[4]	317	1			T264	12		T49	19		T130	24
auto[0]	values[6]	values[5]	562	1			T16	31		T198	24		T257	4
auto[0]	values[6]	values[6]	294	1			T250	4		T211	18		T92	18
auto[0]	values[6]	values[7]	643	1			T16	33		T256	2		T48	20
auto[0]	values[7]	values[0]	699	1			T163	24		T247	8		T35	20
auto[0]	values[7]	values[1]	415	1			T2	8		T49	20		T52	41
auto[0]	values[7]	values[2]	430	1			T24	20		T27	20		T16	20
auto[0]	values[7]	values[3]	560	1			T4	43		T24	19		T16	22
auto[0]	values[7]	values[4]	303	1			T198	57		T200	18		T284	22
auto[0]	values[7]	values[5]	373	1			T201	57		T130	23		T285	16
auto[0]	values[7]	values[6]	573	1			T44	20		T51	22		T286	14
auto[0]	values[7]	values[7]	493	1			T4	24		T51	22		T22	72
auto[1]	values[0]	values[0]	10	1			T35	2		T214	2		T287	4
auto[1]	values[0]	values[1]	10	1			T35	1		T216	2		T156	1
auto[1]	values[0]	values[2]	6	1			T163	3		T228	1		T288	1
auto[1]	values[0]	values[3]	8	1			T35	1		T239	2		T289	2
auto[1]	values[0]	values[4]	9	1			T130	1		T91	1		T204	3
auto[1]	values[0]	values[5]	6	1			T35	1		T156	2		T213	2
auto[1]	values[0]	values[6]	9	1			T130	3		T193	2		T290	2
auto[1]	values[0]	values[7]	8	1			T228	2		T55	2		T291	1
auto[1]	values[1]	values[0]	14	1			T138	3		T269	2		T155	1
auto[1]	values[1]	values[1]	8	1			T226	4		T197	1		T218	2
auto[1]	values[1]	values[2]	5	1			T27	1		T47	1		T224	1
auto[1]	values[1]	values[3]	10	1			T278	4		T224	1		T197	1
auto[1]	values[1]	values[4]	8	1			T292	2		T293	3		T294	3
auto[1]	values[1]	values[5]	9	1			T4	2		T202	1		T194	2
auto[1]	values[1]	values[6]	13	1			T35	5		T213	1		T241	2
auto[1]	values[1]	values[7]	3	1			T214	2		T295	1		-	-
auto[1]	values[2]	values[0]	12	1			T16	1		T239	3		T296	4
auto[1]	values[2]	values[1]	5	1			T35	3		T297	2		-	-
auto[1]	values[2]	values[2]	13	1			T237	1		T92	7		T298	1
auto[1]	values[2]	values[3]	16	1			T201	1		T202	1		T208	3
auto[1]	values[2]	values[4]	5	1			T27	2		T214	2		T299	1
auto[1]	values[2]	values[5]	8	1			T27	1		T197	1		T287	1
auto[1]	values[2]	values[6]	12	1			T213	1		T60	5		T55	3
auto[1]	values[2]	values[7]	9	1			T43	1		T50	4		T55	1
auto[1]	values[3]	values[0]	10	1			T55	1		T214	2		T300	2
auto[1]	values[3]	values[1]	14	1			T201	2		T198	1		T212	3
auto[1]	values[3]	values[2]	9	1			T47	2		T201	3		T243	2
auto[1]	values[3]	values[3]	9	1			T271	1		T241	2		T298	3
auto[1]	values[3]	values[4]	5	1			T301	2		T197	1		T218	2
auto[1]	values[3]	values[5]	9	1			T130	1		T91	1		T302	2
auto[1]	values[3]	values[6]	15	1			T51	2		T22	3		T227	3
auto[1]	values[3]	values[7]	12	1			T165	1		T227	4		T211	2
auto[1]	values[4]	values[0]	12	1			T48	3		T60	2		T303	1
auto[1]	values[4]	values[1]	15	1			T254	1		T155	1		T156	2
auto[1]	values[4]	values[2]	4	1			T156	1		T236	1		T304	2
auto[1]	values[4]	values[3]	16	1			T43	1		T211	4		T305	3
auto[1]	values[4]	values[4]	11	1			T52	2		T22	3		T35	3
auto[1]	values[4]	values[5]	20	1			T20	1		T301	1		T224	1
auto[1]	values[4]	values[6]	15	1			T24	1		T47	1		T163	3
auto[1]	values[4]	values[7]	3	1			T228	2		T306	1		-	-
auto[1]	values[5]	values[0]	6	1			T212	1		T193	2		T227	2
auto[1]	values[5]	values[1]	23	1			T165	2		T196	2		T254	4
auto[1]	values[5]	values[2]	5	1			T4	1		T51	1		T208	1
auto[1]	values[5]	values[3]	13	1			T27	2		T165	1		T130	1
auto[1]	values[5]	values[4]	32	1			T4	1		T43	4		T47	1
auto[1]	values[5]	values[5]	18	1			T16	1		T163	2		T228	4
auto[1]	values[5]	values[6]	9	1			T156	1		T241	1		T307	1
auto[1]	values[5]	values[7]	17	1			T48	2		T165	1		T35	1
auto[1]	values[6]	values[0]	3	1			T193	2		T308	1		-	-
auto[1]	values[6]	values[1]	6	1			T163	1		T92	1		T291	1
auto[1]	values[6]	values[2]	7	1			T16	3		T43	3		T309	1
auto[1]	values[6]	values[3]	15	1			T51	2		T212	1		T239	1
auto[1]	values[6]	values[4]	7	1			T49	1		T130	1		T194	1
auto[1]	values[6]	values[5]	9	1			T16	1		T198	1		T241	3
auto[1]	values[6]	values[6]	13	1			T211	2		T92	2		T236	2
auto[1]	values[6]	values[7]	14	1			T51	1		T22	1		T194	1
auto[1]	values[7]	values[0]	28	1			T163	4		T216	1		T271	2
auto[1]	values[7]	values[1]	17	1			T156	4		T92	1		T310	1
auto[1]	values[7]	values[2]	9	1			T35	1		T301	3		T241	1
auto[1]	values[7]	values[3]	19	1			T4	1		T24	1		T47	6
auto[1]	values[7]	values[4]	14	1			T198	1		T58	2		T55	1
auto[1]	values[7]	values[5]	14	1			T201	2		T91	1		T204	2
auto[1]	values[7]	values[6]	14	1			T138	3		T208	2		T311	2
auto[1]	values[7]	values[7]	2	1			T198	1		T312	1		-	-