Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	765	1			T16	7		T18	24		T20	4
all_values[1]	765	1			T16	7		T18	24		T20	4
all_values[2]	765	1			T16	7		T18	24		T20	4
all_values[3]	765	1			T16	7		T18	24		T20	4
all_values[4]	765	1			T16	7		T18	24		T20	4
all_values[5]	765	1			T16	7		T18	24		T20	4
all_values[6]	765	1			T16	7		T18	24		T20	4
all_values[7]	765	1			T16	7		T18	24		T20	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3315

1

T16

29

T18

100

T20

18

auto[1]

2805

1

T16

27

T18

92

T20

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2475

1

T16

24

T18

67

T20

14

auto[1]

3645

1

T16

32

T18

125

T20

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3550

1

T16

28

T18

107

T20

22

auto[1]

2570

1

T16

28

T18

85

T20

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	164	1			T16	2		T18	2		T22	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T16	1		T18	4		T172	1
all_values[0]	auto[0]	auto[1]	auto[0]	125	1			T16	1		T18	1		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T16	1		T18	3		T22	1
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T18	6		T22	4		T34	1
all_values[0]	auto[1]	auto[1]	auto[1]	155	1			T16	2		T18	8		T22	3
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T16	3		T18	3		T20	1
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T18	2		T20	2		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	128	1			T16	2		T18	5		T35	1
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T18	3		T22	2		T34	1
all_values[1]	auto[1]	auto[0]	auto[1]	178	1			T18	5		T20	1		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T16	2		T18	6		T22	4
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T16	1		T18	1		T22	4
all_values[2]	auto[0]	auto[0]	auto[1]	91	1			T18	5		T20	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T16	2		T18	6		T22	2
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T18	1		T134	2		T173	1
all_values[2]	auto[1]	auto[0]	auto[1]	170	1			T16	2		T18	6		T20	2
all_values[2]	auto[1]	auto[1]	auto[1]	124	1			T16	2		T18	5		T34	2
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T18	9		T20	1		T22	5
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T18	3		T20	1		T134	2
all_values[3]	auto[0]	auto[1]	auto[0]	123	1			T18	2		T22	4		T34	1
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T16	1		T34	1		T172	5
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T16	3		T18	4		T22	1
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T16	3		T18	6		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T16	2		T18	3		T20	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T18	5		T20	1		T173	1
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T16	2		T18	4		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T18	2		T35	2		T134	3
all_values[4]	auto[1]	auto[0]	auto[1]	165	1			T16	1		T18	5		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	141	1			T16	2		T18	5		T20	1
all_values[5]	auto[0]	auto[0]	auto[0]	227	1			T16	4		T18	10		T22	4
all_values[5]	auto[0]	auto[1]	auto[0]	219	1			T16	1		T18	4		T20	4
all_values[5]	auto[1]	auto[0]	auto[1]	167	1			T16	1		T18	5		T22	4
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T16	1		T18	5		T22	2
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T16	2		T18	5		T22	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T18	2		T20	2		T22	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T16	1		T18	7		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T18	3		T34	2		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T16	2		T18	3		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T16	2		T18	4		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	167	1			T16	1		T18	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T18	3		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	115	1			T18	3		T20	1		T22	2
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T18	4		T172	1		T134	4
all_values[7]	auto[1]	auto[0]	auto[1]	186	1			T16	3		T18	7		T20	1
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T16	2		T18	5		T20	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal