Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1737

1

T1

9

T3

1

T7

20

auto[1]

1750

1

T1

9

T7

8

T10

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808

1

T1

16

T3

1

T8

2

auto[1]

1679

1

T1

2

T7

28

T29

40

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2804

1

T1

15

T3

1

T7

28

auto[1]

683

1

T1

3

T10

6

T30

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	671	1			T1	7		T7	10		T10	4
valid[1]	683	1			T1	2		T3	1		T7	5
valid[2]	716	1			T1	4		T7	6		T8	1
valid[3]	727	1			T1	4		T7	2		T8	1
valid[4]	690	1			T1	1		T7	5		T10	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	108	1			T1	3		T10	2		T15	3
auto[0]	auto[0]	valid[0]	auto[1]	170	1			T1	1		T7	10		T29	3
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T1	1		T3	1		T10	6
auto[0]	auto[0]	valid[1]	auto[1]	145	1			T1	1		T7	1		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	107	1			T8	1		T10	1		T30	2
auto[0]	auto[0]	valid[2]	auto[1]	173	1			T7	5		T29	6		T15	2
auto[0]	auto[0]	valid[3]	auto[0]	122	1			T1	2		T8	1		T10	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T7	1		T29	6		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	97	1			T10	2		T30	2		T31	1
auto[0]	auto[0]	valid[4]	auto[1]	180	1			T7	3		T29	3		T15	3
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T1	2		T10	1		T30	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T29	1		T15	1		T28	3
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T10	2		T53	1		T320	1
auto[0]	auto[1]	valid[1]	auto[1]	161	1			T7	4		T29	2		T15	1
auto[0]	auto[1]	valid[2]	auto[0]	108	1			T1	4		T10	5		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	189	1			T7	1		T29	8		T15	1
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T10	3		T30	1		T15	1
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T7	1		T29	4		T28	2
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T1	1		T10	2		T30	1
auto[0]	auto[1]	valid[4]	auto[1]	157	1			T7	2		T29	5		T15	1
auto[1]	auto[0]	valid[0]	auto[0]	60	1			T1	1		T15	1		T53	3
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T10	1		T31	1		T15	1
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T30	1		T53	2		T65	2
auto[1]	auto[0]	valid[3]	auto[0]	64	1			T53	1		T65	2		T17	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T10	1		T30	1		T15	2
auto[1]	auto[1]	valid[0]	auto[0]	56	1			T10	1		T15	1		T53	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T15	3		T53	2		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T53	2		T20	1		T79	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T1	2		T10	2		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	62	1			T10	1		T15	1		T53	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal