Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47433

1

T1

436

T3

1

T8

74

auto[1]

17253

1

T1

35

T7

409

T29

498

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47387

1

T1

313

T3

1

T7

409

auto[1]

17299

1

T1

158

T8

16

T10

150

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33131	1			T1	238		T3	1		T7	205
others[1]	5425	1			T1	35		T7	33		T8	6
others[2]	5629	1			T1	35		T7	42		T8	4
others[3]	6145	1			T1	52		T7	39		T8	3
interest[1]	3604	1			T1	27		T7	21		T8	4
interest[4]	21649	1			T1	148		T3	1		T7	124
interest[64]	10752	1			T1	84		T7	69		T8	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15411	1			T1	144		T3	1		T8	39
auto[0]	auto[0]	others[1]	2562	1			T1	15		T8	4		T10	33
auto[0]	auto[0]	others[2]	2679	1			T1	22		T8	3		T10	29
auto[0]	auto[0]	others[3]	2899	1			T1	34		T8	1		T10	29
auto[0]	auto[0]	interest[1]	1592	1			T1	17		T8	2		T10	13
auto[0]	auto[0]	interest[4]	10079	1			T1	91		T3	1		T8	28
auto[0]	auto[0]	interest[64]	4991	1			T1	46		T8	9		T10	51
auto[0]	auto[1]	others[0]	8963	1			T1	15		T7	205		T29	248
auto[0]	auto[1]	others[1]	1403	1			T1	5		T7	33		T29	41
auto[0]	auto[1]	others[2]	1466	1			T1	2		T7	42		T29	46
auto[0]	auto[1]	others[3]	1615	1			T1	5		T7	39		T29	47
auto[0]	auto[1]	interest[1]	1003	1			T1	3		T7	21		T29	37
auto[0]	auto[1]	interest[4]	5946	1			T1	9		T7	124		T29	168
auto[0]	auto[1]	interest[64]	2803	1			T1	5		T7	69		T29	79
auto[1]	auto[0]	others[0]	8757	1			T1	79		T8	8		T10	78
auto[1]	auto[0]	others[1]	1460	1			T1	15		T8	2		T10	17
auto[1]	auto[0]	others[2]	1484	1			T1	11		T8	1		T10	12
auto[1]	auto[0]	others[3]	1631	1			T1	13		T8	2		T10	14
auto[1]	auto[0]	interest[1]	1009	1			T1	7		T8	2		T10	5
auto[1]	auto[0]	interest[4]	5624	1			T1	48		T8	7		T10	48
auto[1]	auto[0]	interest[64]	2958	1			T1	33		T8	1		T10	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal