Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T114 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4030202555 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 793254252 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4131028023 Jul 31 04:44:44 PM PDT 24 Jul 31 04:44:47 PM PDT 24 164574228 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.307362116 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 412521185 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3601257834 Jul 31 04:44:47 PM PDT 24 Jul 31 04:44:48 PM PDT 24 13951323 ps
T101 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.218161938 Jul 31 04:45:01 PM PDT 24 Jul 31 04:45:07 PM PDT 24 104663333 ps
T111 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.752640330 Jul 31 04:45:07 PM PDT 24 Jul 31 04:45:11 PM PDT 24 1137387902 ps
T151 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2751733041 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:51 PM PDT 24 43652233 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2083456507 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:52 PM PDT 24 35653774 ps
T102 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3022255399 Jul 31 04:44:56 PM PDT 24 Jul 31 04:45:03 PM PDT 24 215087983 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.830821517 Jul 31 04:45:29 PM PDT 24 Jul 31 04:45:31 PM PDT 24 34729765 ps
T115 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3737236382 Jul 31 04:44:56 PM PDT 24 Jul 31 04:45:04 PM PDT 24 1509705879 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1044789841 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:54 PM PDT 24 115789751 ps
T81 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3945573905 Jul 31 04:44:34 PM PDT 24 Jul 31 04:44:35 PM PDT 24 40316276 ps
T109 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1687054032 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:56 PM PDT 24 94683345 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1804766499 Jul 31 04:44:43 PM PDT 24 Jul 31 04:44:45 PM PDT 24 83051022 ps
T1046 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3629696491 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 28075375 ps
T1047 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.201553294 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:52 PM PDT 24 16344773 ps
T121 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1628601898 Jul 31 04:44:48 PM PDT 24 Jul 31 04:45:02 PM PDT 24 836594366 ps
T177 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1906247858 Jul 31 04:44:39 PM PDT 24 Jul 31 04:44:47 PM PDT 24 607278110 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.404707624 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:51 PM PDT 24 40533251 ps
T1049 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3253744476 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:57 PM PDT 24 16499143 ps
T152 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3677482481 Jul 31 04:44:35 PM PDT 24 Jul 31 04:44:36 PM PDT 24 159321867 ps
T1050 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1369268800 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:54 PM PDT 24 26059863 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1647976298 Jul 31 04:44:46 PM PDT 24 Jul 31 04:45:10 PM PDT 24 1271893329 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2399628289 Jul 31 04:45:10 PM PDT 24 Jul 31 04:45:12 PM PDT 24 52427854 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2570878532 Jul 31 04:44:38 PM PDT 24 Jul 31 04:44:42 PM PDT 24 416622101 ps
T185 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.279764005 Jul 31 04:44:49 PM PDT 24 Jul 31 04:45:04 PM PDT 24 2072370619 ps
T153 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.310642232 Jul 31 04:44:53 PM PDT 24 Jul 31 04:45:02 PM PDT 24 1745108892 ps
T1054 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2675075817 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:10 PM PDT 24 31379279 ps
T112 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.355329521 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:58 PM PDT 24 221067519 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3552433990 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 13723990 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.785555836 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:55 PM PDT 24 188437824 ps
T183 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2196876801 Jul 31 04:44:37 PM PDT 24 Jul 31 04:44:50 PM PDT 24 756925673 ps
T171 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2568004615 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:59 PM PDT 24 8052239027 ps
T122 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1142547666 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:55 PM PDT 24 30274169 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3781715144 Jul 31 04:44:55 PM PDT 24 Jul 31 04:45:01 PM PDT 24 496469557 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4029009677 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:46 PM PDT 24 150714109 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2591248569 Jul 31 04:44:38 PM PDT 24 Jul 31 04:44:44 PM PDT 24 119599796 ps
T184 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1812875672 Jul 31 04:45:01 PM PDT 24 Jul 31 04:45:22 PM PDT 24 876191211 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.401569076 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:42 PM PDT 24 16850819 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2113133997 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 200160504 ps
T1060 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1008145903 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:56 PM PDT 24 32998050 ps
T1061 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2004407351 Jul 31 04:45:06 PM PDT 24 Jul 31 04:45:07 PM PDT 24 14480816 ps
T1062 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1258385451 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:52 PM PDT 24 11242820 ps
T1063 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1354414211 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:57 PM PDT 24 41141036 ps
T1064 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1989397999 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:49 PM PDT 24 817525467 ps
T1065 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.32956962 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:52 PM PDT 24 23127929 ps
T1066 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3801484229 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:56 PM PDT 24 14321170 ps
T1067 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2592447297 Jul 31 04:45:18 PM PDT 24 Jul 31 04:45:18 PM PDT 24 43071889 ps
T1068 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1204651132 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:51 PM PDT 24 17936030 ps
T124 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.916447253 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 374389393 ps
T181 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1864648850 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:26 PM PDT 24 1199444019 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3202066884 Jul 31 04:44:46 PM PDT 24 Jul 31 04:44:48 PM PDT 24 51546165 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1995150008 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:45 PM PDT 24 74951999 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2214432657 Jul 31 04:44:46 PM PDT 24 Jul 31 04:44:59 PM PDT 24 592489583 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.99021505 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:56 PM PDT 24 134778446 ps
T1072 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1964814257 Jul 31 04:45:04 PM PDT 24 Jul 31 04:45:06 PM PDT 24 350610426 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1063238858 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:55 PM PDT 24 57607790 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2041401643 Jul 31 04:45:20 PM PDT 24 Jul 31 04:45:23 PM PDT 24 164018658 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1054554061 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:57 PM PDT 24 156582218 ps
T1075 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1053833020 Jul 31 04:45:03 PM PDT 24 Jul 31 04:45:04 PM PDT 24 44739826 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3702743124 Jul 31 04:45:27 PM PDT 24 Jul 31 04:45:28 PM PDT 24 17360127 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1986800219 Jul 31 04:44:35 PM PDT 24 Jul 31 04:44:57 PM PDT 24 1406688096 ps
T1077 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.636759388 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:51 PM PDT 24 110067501 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3313664184 Jul 31 04:44:36 PM PDT 24 Jul 31 04:44:38 PM PDT 24 43858444 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1848034137 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 107151862 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3995495385 Jul 31 04:44:36 PM PDT 24 Jul 31 04:44:40 PM PDT 24 159965708 ps
T1081 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1646780244 Jul 31 04:45:06 PM PDT 24 Jul 31 04:45:07 PM PDT 24 16776419 ps
T175 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3547970675 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:56 PM PDT 24 81704126 ps
T1082 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3667061936 Jul 31 04:45:01 PM PDT 24 Jul 31 04:45:02 PM PDT 24 87375577 ps
T1083 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.176530458 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:51 PM PDT 24 26721788 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3112925555 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:49 PM PDT 24 13982461 ps
T1085 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2749011766 Jul 31 04:44:52 PM PDT 24 Jul 31 04:44:53 PM PDT 24 19851930 ps
T1086 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3462086127 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:52 PM PDT 24 15236817 ps
T1087 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3467178426 Jul 31 04:45:11 PM PDT 24 Jul 31 04:45:14 PM PDT 24 157427059 ps
T182 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.636949270 Jul 31 04:45:00 PM PDT 24 Jul 31 04:45:22 PM PDT 24 839862275 ps
T82 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1743618226 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:51 PM PDT 24 43497711 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.284030103 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:56 PM PDT 24 30629815 ps
T127 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1796130706 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:54 PM PDT 24 21185009 ps
T1089 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.316597601 Jul 31 04:45:02 PM PDT 24 Jul 31 04:45:03 PM PDT 24 16446602 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2444247175 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:46 PM PDT 24 31872476 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1268906927 Jul 31 04:44:59 PM PDT 24 Jul 31 04:44:59 PM PDT 24 14212193 ps
T83 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2730390089 Jul 31 04:44:43 PM PDT 24 Jul 31 04:44:45 PM PDT 24 43025214 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1107074355 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:56 PM PDT 24 152020047 ps
T1093 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3897899647 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:58 PM PDT 24 387828086 ps
T1094 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4203910312 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 270669396 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2087977127 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:54 PM PDT 24 42914911 ps
T1096 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2951237409 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:46 PM PDT 24 13357786 ps
T128 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.468331477 Jul 31 04:44:37 PM PDT 24 Jul 31 04:44:38 PM PDT 24 22101981 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3213839234 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:45 PM PDT 24 61552754 ps
T1098 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1850383974 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:57 PM PDT 24 22423123 ps
T1099 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2134086199 Jul 31 04:44:58 PM PDT 24 Jul 31 04:45:01 PM PDT 24 37309790 ps
T186 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1660104397 Jul 31 04:44:50 PM PDT 24 Jul 31 04:45:07 PM PDT 24 718605861 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1449820786 Jul 31 04:44:47 PM PDT 24 Jul 31 04:44:55 PM PDT 24 1138917147 ps
T1101 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1753211212 Jul 31 04:44:58 PM PDT 24 Jul 31 04:44:59 PM PDT 24 38766626 ps
T1102 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2330566642 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:59 PM PDT 24 240488461 ps
T1103 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1817255634 Jul 31 04:44:59 PM PDT 24 Jul 31 04:45:03 PM PDT 24 701704110 ps
T1104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1119004559 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:56 PM PDT 24 309934736 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4253958309 Jul 31 04:44:29 PM PDT 24 Jul 31 04:44:46 PM PDT 24 6316586236 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4216925567 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:53 PM PDT 24 139188239 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1177597062 Jul 31 04:45:20 PM PDT 24 Jul 31 04:45:22 PM PDT 24 46657193 ps
T1108 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2973030628 Jul 31 04:44:38 PM PDT 24 Jul 31 04:44:44 PM PDT 24 16459221 ps
T1109 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.672108377 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 38397885 ps
T1110 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2363785572 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:08 PM PDT 24 12093809 ps
T1111 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1050457816 Jul 31 04:45:05 PM PDT 24 Jul 31 04:45:06 PM PDT 24 16931113 ps
T1112 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3179170966 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 71097643 ps
T1113 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1108961555 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:51 PM PDT 24 79183568 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3211004939 Jul 31 04:44:46 PM PDT 24 Jul 31 04:44:50 PM PDT 24 230309106 ps
T1114 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3501215832 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:47 PM PDT 24 919725613 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4100397182 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 335127884 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4133937062 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:51 PM PDT 24 550909208 ps
T179 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.641663020 Jul 31 04:44:56 PM PDT 24 Jul 31 04:45:18 PM PDT 24 3034233816 ps
T178 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1609708425 Jul 31 04:44:40 PM PDT 24 Jul 31 04:44:58 PM PDT 24 290209744 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3773902526 Jul 31 04:44:45 PM PDT 24 Jul 31 04:44:54 PM PDT 24 482262407 ps
T1118 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3792717687 Jul 31 04:45:01 PM PDT 24 Jul 31 04:45:05 PM PDT 24 17466038 ps
T187 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1674404385 Jul 31 04:44:44 PM PDT 24 Jul 31 04:45:00 PM PDT 24 1514557949 ps
T1119 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2813461782 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:52 PM PDT 24 16383729 ps
T1120 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1822251228 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:55 PM PDT 24 126615280 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1166177448 Jul 31 04:45:04 PM PDT 24 Jul 31 04:45:05 PM PDT 24 58005497 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4275829390 Jul 31 04:44:52 PM PDT 24 Jul 31 04:45:16 PM PDT 24 1150307655 ps
T1123 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3624138350 Jul 31 04:45:04 PM PDT 24 Jul 31 04:45:05 PM PDT 24 16090893 ps
T1124 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1354813667 Jul 31 04:45:03 PM PDT 24 Jul 31 04:45:08 PM PDT 24 296341831 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2711814391 Jul 31 04:45:25 PM PDT 24 Jul 31 04:45:28 PM PDT 24 144645619 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1149735355 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:43 PM PDT 24 25049627 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3402761148 Jul 31 04:44:44 PM PDT 24 Jul 31 04:44:47 PM PDT 24 126821701 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2841281534 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:57 PM PDT 24 102420474 ps
T1129 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3204398600 Jul 31 04:45:05 PM PDT 24 Jul 31 04:45:08 PM PDT 24 899694547 ps
T1130 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1259686896 Jul 31 04:44:52 PM PDT 24 Jul 31 04:44:55 PM PDT 24 38104711 ps
T1131 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2678088628 Jul 31 04:44:53 PM PDT 24 Jul 31 04:45:00 PM PDT 24 93573477 ps
T1132 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.371193330 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:54 PM PDT 24 11701703 ps
T1133 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3544953289 Jul 31 04:44:48 PM PDT 24 Jul 31 04:44:49 PM PDT 24 81510359 ps
T1134 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.714393520 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:54 PM PDT 24 37887149 ps
T1135 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2518803856 Jul 31 04:44:36 PM PDT 24 Jul 31 04:44:37 PM PDT 24 45226459 ps
T176 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2932861005 Jul 31 04:44:42 PM PDT 24 Jul 31 04:44:47 PM PDT 24 85161465 ps
T1136 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1006500798 Jul 31 04:44:41 PM PDT 24 Jul 31 04:44:43 PM PDT 24 82446854 ps
T1137 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2666552547 Jul 31 04:44:58 PM PDT 24 Jul 31 04:45:02 PM PDT 24 211717493 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1929829047 Jul 31 04:44:44 PM PDT 24 Jul 31 04:45:08 PM PDT 24 1407794527 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3576780258 Jul 31 04:44:41 PM PDT 24 Jul 31 04:44:46 PM PDT 24 157014319 ps
T1140 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3343531268 Jul 31 04:44:54 PM PDT 24 Jul 31 04:44:57 PM PDT 24 120185607 ps
T180 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.591921314 Jul 31 04:44:50 PM PDT 24 Jul 31 04:45:09 PM PDT 24 1177824022 ps
T1141 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2208157002 Jul 31 04:44:46 PM PDT 24 Jul 31 04:44:48 PM PDT 24 127887432 ps
T1142 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4116475605 Jul 31 04:44:59 PM PDT 24 Jul 31 04:45:00 PM PDT 24 21749004 ps
T1143 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3386973343 Jul 31 04:44:41 PM PDT 24 Jul 31 04:44:42 PM PDT 24 29933039 ps
T1144 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3996750801 Jul 31 04:44:39 PM PDT 24 Jul 31 04:44:42 PM PDT 24 195804987 ps
T1145 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.160477162 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:51 PM PDT 24 65661916 ps
T1146 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4073840863 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:57 PM PDT 24 38796997 ps
T1147 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3071879998 Jul 31 04:44:26 PM PDT 24 Jul 31 04:44:27 PM PDT 24 50095065 ps
T1148 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.565737923 Jul 31 04:44:54 PM PDT 24 Jul 31 04:45:07 PM PDT 24 491004235 ps
T1149 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2870779608 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:08 PM PDT 24 45170496 ps
T1150 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2054383617 Jul 31 04:44:52 PM PDT 24 Jul 31 04:44:53 PM PDT 24 50895557 ps
T1151 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2283119009 Jul 31 04:44:40 PM PDT 24 Jul 31 04:44:44 PM PDT 24 122300347 ps

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2999191739
Short name T1
Test name
Test status
Simulation time 40459145271 ps
CPU time 90.16 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 237644 kb
Host smart-5b3ce66e-3131-47b2-bfdd-d234ecaa4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999191739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2999191739
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1795937495
Short name T16
Test name
Test status
Simulation time 11386169190 ps
CPU time 172.81 seconds
Started Jul 31 05:02:28 PM PDT 24
Finished Jul 31 05:05:26 PM PDT 24
Peak memory 267316 kb
Host smart-22b8f9e2-8688-42c4-8acd-c912df5008a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795937495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1795937495
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3396628190
Short name T15
Test name
Test status
Simulation time 573651937131 ps
CPU time 754.01 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:14:15 PM PDT 24
Peak memory 274748 kb
Host smart-25d8bbfa-602c-4ffb-a925-a610a08bcf48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396628190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3396628190
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2381474842
Short name T98
Test name
Test status
Simulation time 995655231 ps
CPU time 21.02 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:34 PM PDT 24
Peak memory 215632 kb
Host smart-5d3d7768-9f96-4a25-bc00-666a1a0c9497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381474842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2381474842
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.856574029
Short name T35
Test name
Test status
Simulation time 101538535032 ps
CPU time 986.85 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:18:45 PM PDT 24
Peak memory 282520 kb
Host smart-37126282-a775-4ff7-86a6-46bb2c7123b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856574029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.856574029
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2672092071
Short name T22
Test name
Test status
Simulation time 7543211726 ps
CPU time 146.49 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:04:44 PM PDT 24
Peak memory 269912 kb
Host smart-9df97370-c9ec-46b9-ade4-3525b3ab114d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672092071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2672092071
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3409598958
Short name T69
Test name
Test status
Simulation time 22024779 ps
CPU time 0.75 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:02 PM PDT 24
Peak memory 216616 kb
Host smart-4680d2d4-8243-498c-aac3-7d4b60938fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409598958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3409598958
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1155901516
Short name T193
Test name
Test status
Simulation time 5301318957 ps
CPU time 125.14 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 273780 kb
Host smart-9e49b41e-d133-4a7d-8d1f-0b7b3daf7616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155901516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1155901516
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1107883056
Short name T4
Test name
Test status
Simulation time 38871413896 ps
CPU time 263.17 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:06:16 PM PDT 24
Peak memory 257960 kb
Host smart-efeeba8d-92ae-427b-9ef6-b0f5d777ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107883056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1107883056
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.650086983
Short name T228
Test name
Test status
Simulation time 259198071073 ps
CPU time 622.35 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:12:06 PM PDT 24
Peak memory 266704 kb
Host smart-97afc071-d06f-47c3-b7de-be082f49fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650086983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.650086983
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2111339680
Short name T99
Test name
Test status
Simulation time 46586666 ps
CPU time 2.73 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215640 kb
Host smart-c5565f5f-45e3-4ab5-b83e-63b0c135a156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111339680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2111339680
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.865932078
Short name T19
Test name
Test status
Simulation time 160136081 ps
CPU time 1.2 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:05 PM PDT 24
Peak memory 235532 kb
Host smart-347f0ef5-3d80-4177-8305-ee575f3b5f50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865932078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.865932078
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1365461033
Short name T55
Test name
Test status
Simulation time 7173842630 ps
CPU time 145.48 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:04:44 PM PDT 24
Peak memory 265668 kb
Host smart-fe97bef7-7828-44b5-bf81-23075ba22ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365461033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1365461033
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4217968906
Short name T75
Test name
Test status
Simulation time 3345884515 ps
CPU time 17.23 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 233428 kb
Host smart-831124e2-d7da-44b4-9b15-b18f34556e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217968906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4217968906
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4255677867
Short name T92
Test name
Test status
Simulation time 20547020400 ps
CPU time 86.75 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:02:57 PM PDT 24
Peak memory 258048 kb
Host smart-02ec5e82-6d89-434e-97ca-7583b5b2dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255677867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4255677867
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4255745653
Short name T156
Test name
Test status
Simulation time 43341624919 ps
CPU time 352.87 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 274084 kb
Host smart-d9880f2e-0f83-41a5-8064-6ff9372b23cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255745653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4255745653
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2451521766
Short name T27
Test name
Test status
Simulation time 26213973562 ps
CPU time 172.3 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:05:33 PM PDT 24
Peak memory 252988 kb
Host smart-efc5e7c9-006f-4f2d-8da7-498c7bc2b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451521766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2451521766
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1628601898
Short name T121
Test name
Test status
Simulation time 836594366 ps
CPU time 13.73 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 215392 kb
Host smart-2dcaf181-a1a6-4969-8b8f-2129fd795230
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628601898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1628601898
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.157964437
Short name T208
Test name
Test status
Simulation time 6907059044 ps
CPU time 101.61 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:03:33 PM PDT 24
Peak memory 263676 kb
Host smart-bf16b5cf-0e72-4d4e-9934-9b4058890c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157964437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.157964437
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.407173991
Short name T224
Test name
Test status
Simulation time 19699685363 ps
CPU time 114.06 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:03:45 PM PDT 24
Peak memory 258004 kb
Host smart-a739bf13-50b6-46f2-910e-b64669cab899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407173991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.407173991
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.463705292
Short name T403
Test name
Test status
Simulation time 17130295 ps
CPU time 1.05 seconds
Started Jul 31 05:01:03 PM PDT 24
Finished Jul 31 05:01:04 PM PDT 24
Peak memory 217120 kb
Host smart-d2d2b131-afc1-4f49-9d16-5137d123eb7d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463705292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.463705292
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.270639941
Short name T216
Test name
Test status
Simulation time 15441915052 ps
CPU time 91.47 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 272960 kb
Host smart-6cd71d4c-9e62-4ebf-bac4-9313b7826719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270639941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.270639941
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.735183428
Short name T130
Test name
Test status
Simulation time 35007512154 ps
CPU time 224.7 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:06:35 PM PDT 24
Peak memory 255964 kb
Host smart-a12410df-8b7c-4039-b7a7-157051fcb3cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735183428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.735183428
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3781715144
Short name T107
Test name
Test status
Simulation time 496469557 ps
CPU time 5.61 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:45:01 PM PDT 24
Peak memory 216660 kb
Host smart-64b7bdcb-5af7-436b-85e4-48ebdc68e6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781715144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
781715144
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1221572029
Short name T211
Test name
Test status
Simulation time 58769070063 ps
CPU time 179.57 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:04:10 PM PDT 24
Peak memory 267020 kb
Host smart-1bab0bf2-e76c-4044-9822-1adeff205c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221572029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1221572029
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2250322717
Short name T79
Test name
Test status
Simulation time 119236557801 ps
CPU time 284.34 seconds
Started Jul 31 05:01:19 PM PDT 24
Finished Jul 31 05:06:04 PM PDT 24
Peak memory 265340 kb
Host smart-a71f2deb-108b-4f78-83b4-bab15d1b8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250322717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2250322717
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.459535577
Short name T67
Test name
Test status
Simulation time 11635029 ps
CPU time 0.73 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 205172 kb
Host smart-7a64d146-6a5c-44d5-9d79-f220d7b96b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459535577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.459535577
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.802462080
Short name T197
Test name
Test status
Simulation time 20093910819 ps
CPU time 89.3 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:04:52 PM PDT 24
Peak memory 253840 kb
Host smart-116074df-7bd9-4c7a-b56e-50d3faf0b45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802462080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.802462080
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1864648850
Short name T181
Test name
Test status
Simulation time 1199444019 ps
CPU time 17.16 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:26 PM PDT 24
Peak memory 215524 kb
Host smart-57891b29-c0e8-477a-9d01-9c2e60d40af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864648850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1864648850
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2165199871
Short name T47
Test name
Test status
Simulation time 36164819400 ps
CPU time 251.13 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:05:50 PM PDT 24
Peak memory 262480 kb
Host smart-b15e7959-0840-4b92-8ce8-5903bf18d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165199871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2165199871
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.954867947
Short name T306
Test name
Test status
Simulation time 404190385084 ps
CPU time 256.26 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:05:24 PM PDT 24
Peak memory 264080 kb
Host smart-e80d048f-69bc-4d05-b3de-927377a0d153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954867947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
954867947
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2163592641
Short name T7
Test name
Test status
Simulation time 59888164441 ps
CPU time 23.13 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 218032 kb
Host smart-b0a03d3c-4e98-47ad-9243-8daaf379eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163592641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2163592641
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1758528593
Short name T214
Test name
Test status
Simulation time 6385514695 ps
CPU time 109.24 seconds
Started Jul 31 05:01:46 PM PDT 24
Finished Jul 31 05:03:36 PM PDT 24
Peak memory 255636 kb
Host smart-21fe29fc-e013-4fa6-bc5f-5beb5f0bb3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758528593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1758528593
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1609708425
Short name T178
Test name
Test status
Simulation time 290209744 ps
CPU time 17.89 seconds
Started Jul 31 04:44:40 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 215404 kb
Host smart-e76568b4-2a19-4cb9-ba0b-1bd6f6c3f613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609708425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1609708425
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1814669091
Short name T267
Test name
Test status
Simulation time 41582761529 ps
CPU time 181.31 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 258012 kb
Host smart-97e94b70-72bd-485a-9ba7-29bb98c223a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814669091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1814669091
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2328130332
Short name T299
Test name
Test status
Simulation time 3643833448 ps
CPU time 75.5 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 263596 kb
Host smart-e1eb9bf4-772c-474d-ae02-664f556ba10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328130332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2328130332
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1059569830
Short name T294
Test name
Test status
Simulation time 4855928579 ps
CPU time 61.56 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:03:47 PM PDT 24
Peak memory 255004 kb
Host smart-3d3ccb5d-04ba-4d76-bff5-fc51211b0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059569830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1059569830
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.700785387
Short name T25
Test name
Test status
Simulation time 6453634062 ps
CPU time 21.79 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 233356 kb
Host smart-20da176b-5f48-46f1-925c-974a95c5cedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700785387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.700785387
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1527236438
Short name T36
Test name
Test status
Simulation time 2939807446 ps
CPU time 41.91 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 241628 kb
Host smart-a83d0251-1550-4eca-838e-4ac3c356301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527236438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1527236438
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2568004615
Short name T171
Test name
Test status
Simulation time 8052239027 ps
CPU time 14.14 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 215672 kb
Host smart-9a4648f6-67f7-46e7-b0fe-9ca8fad105e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568004615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2568004615
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1709242104
Short name T204
Test name
Test status
Simulation time 9762180956 ps
CPU time 68.59 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 254168 kb
Host smart-4df4a647-0e73-4c9d-855d-d5c07a6a7686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709242104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1709242104
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2724380254
Short name T1030
Test name
Test status
Simulation time 4622108499 ps
CPU time 60.03 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 249864 kb
Host smart-0334963d-70ee-47cd-a9cd-ec32c0949e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724380254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2724380254
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2928883642
Short name T198
Test name
Test status
Simulation time 34038275100 ps
CPU time 271.58 seconds
Started Jul 31 05:02:13 PM PDT 24
Finished Jul 31 05:06:44 PM PDT 24
Peak memory 250944 kb
Host smart-a212ebf6-9ea1-4061-96cb-436a1f398245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928883642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2928883642
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1184191881
Short name T330
Test name
Test status
Simulation time 19133105943 ps
CPU time 195.39 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:05:27 PM PDT 24
Peak memory 241564 kb
Host smart-e079e96d-8d7b-486d-9a3e-50ea2544ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184191881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1184191881
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4255326272
Short name T80
Test name
Test status
Simulation time 46339966 ps
CPU time 1.43 seconds
Started Jul 31 04:44:34 PM PDT 24
Finished Jul 31 04:44:35 PM PDT 24
Peak memory 207268 kb
Host smart-3a42cd2e-27cc-459d-8487-6082afaa042a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255326272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4255326272
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3211004939
Short name T108
Test name
Test status
Simulation time 230309106 ps
CPU time 3.83 seconds
Started Jul 31 04:44:46 PM PDT 24
Finished Jul 31 04:44:50 PM PDT 24
Peak memory 215648 kb
Host smart-492f983d-019b-46b8-b269-6ed2365234d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211004939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
211004939
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1501979329
Short name T38
Test name
Test status
Simulation time 4922496264 ps
CPU time 101.61 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:04:02 PM PDT 24
Peak memory 255588 kb
Host smart-d2ecbebb-6c0e-473e-b8d1-a91da1065ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501979329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1501979329
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4253958309
Short name T1105
Test name
Test status
Simulation time 6316586236 ps
CPU time 16.36 seconds
Started Jul 31 04:44:29 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 215532 kb
Host smart-ad8c6a15-6c2d-46c4-9728-bab73e2abc6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253958309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4253958309
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1263758540
Short name T117
Test name
Test status
Simulation time 7181550279 ps
CPU time 25.55 seconds
Started Jul 31 04:44:38 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 207296 kb
Host smart-628b46a3-481c-4319-9264-60e50f8beb7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263758540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1263758540
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.249910931
Short name T113
Test name
Test status
Simulation time 57321950 ps
CPU time 1.87 seconds
Started Jul 31 04:44:40 PM PDT 24
Finished Jul 31 04:44:42 PM PDT 24
Peak memory 216476 kb
Host smart-658e3dd0-7097-4a19-97c3-d45735eab7ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249910931 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.249910931
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4100397182
Short name T1115
Test name
Test status
Simulation time 335127884 ps
CPU time 1.25 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 207340 kb
Host smart-879033d0-151e-4e43-9424-e558e226f86d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100397182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
100397182
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2973030628
Short name T1108
Test name
Test status
Simulation time 16459221 ps
CPU time 0.74 seconds
Started Jul 31 04:44:38 PM PDT 24
Finished Jul 31 04:44:44 PM PDT 24
Peak memory 203888 kb
Host smart-d3b1e45b-35fa-466b-9707-c726106f9f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973030628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
973030628
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2591248569
Short name T123
Test name
Test status
Simulation time 119599796 ps
CPU time 1.3 seconds
Started Jul 31 04:44:38 PM PDT 24
Finished Jul 31 04:44:44 PM PDT 24
Peak memory 215464 kb
Host smart-e563f82f-b392-4f32-a5bd-5047b187c17c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591248569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2591248569
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2804049097
Short name T1037
Test name
Test status
Simulation time 27137913 ps
CPU time 0.68 seconds
Started Jul 31 04:44:47 PM PDT 24
Finished Jul 31 04:44:48 PM PDT 24
Peak memory 203864 kb
Host smart-f0162721-6f2f-4885-a954-44ec95d9b38f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804049097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2804049097
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3402761148
Short name T1127
Test name
Test status
Simulation time 126821701 ps
CPU time 2.88 seconds
Started Jul 31 04:44:44 PM PDT 24
Finished Jul 31 04:44:47 PM PDT 24
Peak memory 215320 kb
Host smart-d5c9f782-6cc3-4033-830c-e8caecbeb578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402761148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3402761148
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3995495385
Short name T1080
Test name
Test status
Simulation time 159965708 ps
CPU time 3.99 seconds
Started Jul 31 04:44:36 PM PDT 24
Finished Jul 31 04:44:40 PM PDT 24
Peak memory 219840 kb
Host smart-c487c2de-1f40-41d0-8045-198308c0b2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995495385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
995495385
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1986800219
Short name T126
Test name
Test status
Simulation time 1406688096 ps
CPU time 22.37 seconds
Started Jul 31 04:44:35 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215424 kb
Host smart-c4cd6526-fe15-44b7-bbf2-a9e9eb63b236
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986800219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1986800219
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2730390089
Short name T83
Test name
Test status
Simulation time 43025214 ps
CPU time 1.38 seconds
Started Jul 31 04:44:43 PM PDT 24
Finished Jul 31 04:44:45 PM PDT 24
Peak memory 217572 kb
Host smart-6eb6d903-851a-4358-832e-12097f2fe702
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730390089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2730390089
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1044789841
Short name T1045
Test name
Test status
Simulation time 115789751 ps
CPU time 2.7 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 217980 kb
Host smart-98478291-197b-410b-b313-fa1360eaeb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044789841 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1044789841
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.468331477
Short name T128
Test name
Test status
Simulation time 22101981 ps
CPU time 1.26 seconds
Started Jul 31 04:44:37 PM PDT 24
Finished Jul 31 04:44:38 PM PDT 24
Peak memory 215340 kb
Host smart-87756243-ea86-4305-a1d6-7f22e812bbd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468331477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.468331477
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3071879998
Short name T1147
Test name
Test status
Simulation time 50095065 ps
CPU time 0.73 seconds
Started Jul 31 04:44:26 PM PDT 24
Finished Jul 31 04:44:27 PM PDT 24
Peak memory 203868 kb
Host smart-02ddb3a1-246d-4428-b180-55e01bea2fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071879998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
071879998
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3202066884
Short name T129
Test name
Test status
Simulation time 51546165 ps
CPU time 1.85 seconds
Started Jul 31 04:44:46 PM PDT 24
Finished Jul 31 04:44:48 PM PDT 24
Peak memory 215440 kb
Host smart-405a8841-2bb6-46fa-b5d4-4fcf7a48c031
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202066884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3202066884
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3552433990
Short name T1055
Test name
Test status
Simulation time 13723990 ps
CPU time 0.67 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 204092 kb
Host smart-a7a060c3-0837-4a5b-b68e-db59f64b0568
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552433990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3552433990
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1006500798
Short name T1136
Test name
Test status
Simulation time 82446854 ps
CPU time 2.02 seconds
Started Jul 31 04:44:41 PM PDT 24
Finished Jul 31 04:44:43 PM PDT 24
Peak memory 215360 kb
Host smart-21ee66cc-87c3-408b-b852-2a241f0db68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006500798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1006500798
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2208157002
Short name T1141
Test name
Test status
Simulation time 127887432 ps
CPU time 1.87 seconds
Started Jul 31 04:44:46 PM PDT 24
Finished Jul 31 04:44:48 PM PDT 24
Peak memory 215484 kb
Host smart-f0fc9a51-7d94-46b7-91fd-9b1c215fca2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208157002 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2208157002
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1166177448
Short name T1121
Test name
Test status
Simulation time 58005497 ps
CPU time 1.22 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:05 PM PDT 24
Peak memory 215484 kb
Host smart-85904aac-a7a5-479e-99ab-edabdd827a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166177448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1166177448
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1848034137
Short name T1079
Test name
Test status
Simulation time 107151862 ps
CPU time 0.7 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 203940 kb
Host smart-a002650c-efeb-4f43-99ea-2992f3ff8c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848034137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1848034137
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2693177190
Short name T141
Test name
Test status
Simulation time 28302906 ps
CPU time 1.81 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 215372 kb
Host smart-9005cb20-682f-45b0-a747-f6078af50dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693177190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2693177190
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1119004559
Short name T1104
Test name
Test status
Simulation time 309934736 ps
CPU time 5.5 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 215712 kb
Host smart-ca6463e0-651d-4fde-9760-dd2e9c86cfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119004559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1119004559
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.591921314
Short name T180
Test name
Test status
Simulation time 1177824022 ps
CPU time 17.99 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 215508 kb
Host smart-3e4e8613-101a-4e0b-8196-f8ce66876fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591921314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.591921314
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.785555836
Short name T1056
Test name
Test status
Simulation time 188437824 ps
CPU time 3.35 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 218196 kb
Host smart-3c772843-e886-43cd-9926-d5cac770b6f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785555836 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.785555836
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1796130706
Short name T127
Test name
Test status
Simulation time 21185009 ps
CPU time 1.32 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 207208 kb
Host smart-3e1ab2a1-2c14-4dad-b496-fc162d5e41a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796130706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1796130706
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.201553294
Short name T1047
Test name
Test status
Simulation time 16344773 ps
CPU time 0.79 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 204216 kb
Host smart-2012c8ec-2dfe-43a7-8733-64662e46dcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201553294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.201553294
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1063238858
Short name T1073
Test name
Test status
Simulation time 57607790 ps
CPU time 1.93 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 207076 kb
Host smart-09df85e6-2a46-4648-b743-3766d1f5c36a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063238858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1063238858
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2841281534
Short name T1128
Test name
Test status
Simulation time 102420474 ps
CPU time 2.07 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215768 kb
Host smart-46edf900-5cd0-408c-83bd-ac4987bf2858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841281534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2841281534
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4030202555
Short name T114
Test name
Test status
Simulation time 793254252 ps
CPU time 2.66 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 216888 kb
Host smart-9915e1cb-16b6-4969-9803-84380e3e5392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030202555 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4030202555
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.498036103
Short name T1039
Test name
Test status
Simulation time 149555148 ps
CPU time 1.82 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:48 PM PDT 24
Peak memory 215364 kb
Host smart-a6373219-926f-4b43-bc5c-bb90fa9eb9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498036103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.498036103
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.32956962
Short name T1065
Test name
Test status
Simulation time 23127929 ps
CPU time 0.77 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 204012 kb
Host smart-77f9b2cc-2fd5-4152-ac59-71fe174c248e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.32956962
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1031610542
Short name T143
Test name
Test status
Simulation time 794641337 ps
CPU time 4.13 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 215348 kb
Host smart-fe968a15-4cc2-4767-84d9-8bd2f3e51ae2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031610542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1031610542
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.355329521
Short name T112
Test name
Test status
Simulation time 221067519 ps
CPU time 1.81 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 215508 kb
Host smart-0a05d29a-a34f-4b8a-b2a0-6f7eb8b016fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355329521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.355329521
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.565737923
Short name T1148
Test name
Test status
Simulation time 491004235 ps
CPU time 12.48 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 215396 kb
Host smart-40d55227-d578-460b-a1b4-10c729bb7757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565737923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.565737923
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1354813667
Short name T1124
Test name
Test status
Simulation time 296341831 ps
CPU time 3.87 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 218420 kb
Host smart-008238c8-de50-4d25-b14d-48daf42b1cbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354813667 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1354813667
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.916447253
Short name T124
Test name
Test status
Simulation time 374389393 ps
CPU time 2.39 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215416 kb
Host smart-480787bc-2a8e-4123-8524-f2d7717ab094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916447253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.916447253
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3629696491
Short name T1046
Test name
Test status
Simulation time 28075375 ps
CPU time 0.76 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 204280 kb
Host smart-0eb85330-a8a6-41b4-b5aa-52152a091fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629696491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3629696491
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2666552547
Short name T1137
Test name
Test status
Simulation time 211717493 ps
CPU time 4.29 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 215464 kb
Host smart-e4181314-6c41-45ec-afcf-c0dda8d40816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666552547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2666552547
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1054554061
Short name T110
Test name
Test status
Simulation time 156582218 ps
CPU time 3.88 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215632 kb
Host smart-13d19426-02be-4b44-8af8-2e19556fce91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054554061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1054554061
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3897899647
Short name T1093
Test name
Test status
Simulation time 387828086 ps
CPU time 8.38 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 215456 kb
Host smart-7d6eed26-4ee2-424a-9b59-e10e789f36be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897899647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3897899647
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1177597062
Short name T1107
Test name
Test status
Simulation time 46657193 ps
CPU time 1.63 seconds
Started Jul 31 04:45:20 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 215484 kb
Host smart-a6f66c8c-17f8-4840-bfd4-616147e1ad4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177597062 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1177597062
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.830821517
Short name T119
Test name
Test status
Simulation time 34729765 ps
CPU time 2.3 seconds
Started Jul 31 04:45:29 PM PDT 24
Finished Jul 31 04:45:31 PM PDT 24
Peak memory 207324 kb
Host smart-369f3f39-0697-4e04-8e0c-576f8f3d315e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830821517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.830821517
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2087977127
Short name T1095
Test name
Test status
Simulation time 42914911 ps
CPU time 0.68 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 203904 kb
Host smart-0dbc60b6-2c67-41ab-af4c-ad88769e030e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087977127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2087977127
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1107074355
Short name T1092
Test name
Test status
Simulation time 152020047 ps
CPU time 3.09 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 215476 kb
Host smart-3a5068df-3b74-4faa-81c1-6ad4f50250eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107074355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1107074355
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1660104397
Short name T186
Test name
Test status
Simulation time 718605861 ps
CPU time 15.82 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 215444 kb
Host smart-a8e2dde2-9fdd-4fd0-9f12-e2e445547037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660104397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1660104397
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2330566642
Short name T1102
Test name
Test status
Simulation time 240488461 ps
CPU time 3.51 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 218188 kb
Host smart-66901baf-cc37-4e79-9f4f-afca99d8486e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330566642 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2330566642
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2751733041
Short name T151
Test name
Test status
Simulation time 43652233 ps
CPU time 1.39 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 207324 kb
Host smart-a1571f15-d1dc-470a-a9ba-a2ef1cf028ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751733041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2751733041
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.874035701
Short name T1040
Test name
Test status
Simulation time 25140526 ps
CPU time 0.74 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 203864 kb
Host smart-bc2184c4-5fda-4419-9e07-2aa8d5fdb8cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874035701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.874035701
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2041401643
Short name T1074
Test name
Test status
Simulation time 164018658 ps
CPU time 2.74 seconds
Started Jul 31 04:45:20 PM PDT 24
Finished Jul 31 04:45:23 PM PDT 24
Peak memory 215468 kb
Host smart-9d9f2171-46c4-4336-9b11-8ff7dcbee1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041401643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2041401643
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1254161924
Short name T100
Test name
Test status
Simulation time 398529372 ps
CPU time 4.71 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 217216 kb
Host smart-3249f26f-2e66-40ba-bfc1-fff5e979b1e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254161924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1254161924
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.279764005
Short name T185
Test name
Test status
Simulation time 2072370619 ps
CPU time 14.75 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 216064 kb
Host smart-88d33f30-e770-4adc-a366-97f2041aa460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279764005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.279764005
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.752640330
Short name T111
Test name
Test status
Simulation time 1137387902 ps
CPU time 3.56 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 217028 kb
Host smart-b19b70af-220d-4555-800b-4ab236019779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752640330 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.752640330
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1259686896
Short name T1130
Test name
Test status
Simulation time 38104711 ps
CPU time 2.53 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215540 kb
Host smart-398943bf-f5e5-44ae-b515-cf1054b0cb92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259686896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1259686896
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3702743124
Short name T1076
Test name
Test status
Simulation time 17360127 ps
CPU time 0.74 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 204216 kb
Host smart-7ea30844-c382-4faf-9d00-466dfcbd82ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702743124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3702743124
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3204398600
Short name T1129
Test name
Test status
Simulation time 899694547 ps
CPU time 3.4 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 215700 kb
Host smart-ac77f745-3ca3-4c05-a0ab-907a23e9dd92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204398600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3204398600
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3318124756
Short name T97
Test name
Test status
Simulation time 144008343 ps
CPU time 3.59 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:12 PM PDT 24
Peak memory 215628 kb
Host smart-208385c3-acfc-4937-b783-862b4382d77b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318124756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3318124756
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1964814257
Short name T1072
Test name
Test status
Simulation time 350610426 ps
CPU time 1.76 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 215544 kb
Host smart-85d93a2b-4f5f-478c-81ce-d8f43b6c6ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964814257 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1964814257
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2711814391
Short name T1125
Test name
Test status
Simulation time 144645619 ps
CPU time 2.65 seconds
Started Jul 31 04:45:25 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 215492 kb
Host smart-f0abb836-663d-4332-a0a5-35588cdc5bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711814391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2711814391
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.316597601
Short name T1089
Test name
Test status
Simulation time 16446602 ps
CPU time 0.74 seconds
Started Jul 31 04:45:02 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 204280 kb
Host smart-51cb43a2-b139-4eef-82c1-b0233d37b94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316597601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.316597601
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3340452903
Short name T144
Test name
Test status
Simulation time 161252012 ps
CPU time 2.61 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215336 kb
Host smart-1c59b758-6d2d-448b-8371-3d2eef703087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340452903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3340452903
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.636759388
Short name T1077
Test name
Test status
Simulation time 110067501 ps
CPU time 1.59 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 215716 kb
Host smart-0ccbcb1b-bc94-41bb-8b3b-ab9327147737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636759388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.636759388
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.636949270
Short name T182
Test name
Test status
Simulation time 839862275 ps
CPU time 21.55 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 223636 kb
Host smart-365a93f5-d4e6-4a65-8bab-236b0323acba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636949270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.636949270
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4216925567
Short name T1106
Test name
Test status
Simulation time 139188239 ps
CPU time 3.61 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 217456 kb
Host smart-1ae80f96-e09b-4b4c-a049-08ed01a95d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216925567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4216925567
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4116475605
Short name T1142
Test name
Test status
Simulation time 21749004 ps
CPU time 1.29 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 215180 kb
Host smart-ab2176ec-dccd-432f-9dcf-2872d38e311a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116475605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4116475605
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3624138350
Short name T1123
Test name
Test status
Simulation time 16090893 ps
CPU time 0.77 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:05 PM PDT 24
Peak memory 203904 kb
Host smart-1acaae43-ab3c-4b82-b45a-0edd4df3f4d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624138350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3624138350
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.307362116
Short name T1042
Test name
Test status
Simulation time 412521185 ps
CPU time 2.84 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215452 kb
Host smart-ebe97f5d-7bfe-48c9-a94f-89a21f9806fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307362116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.307362116
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3547970675
Short name T175
Test name
Test status
Simulation time 81704126 ps
CPU time 4.73 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 215644 kb
Host smart-67cfd831-e3e4-4a37-be43-ad1065635fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547970675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3547970675
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3022255399
Short name T102
Test name
Test status
Simulation time 215087983 ps
CPU time 6.81 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 215400 kb
Host smart-e3b6447d-156e-4986-b0c2-aa729df7a275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022255399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3022255399
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3467178426
Short name T1087
Test name
Test status
Simulation time 157427059 ps
CPU time 2.53 seconds
Started Jul 31 04:45:11 PM PDT 24
Finished Jul 31 04:45:14 PM PDT 24
Peak memory 216484 kb
Host smart-034e544f-8ee7-4e38-bbad-05d4d00b31db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467178426 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3467178426
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.99021505
Short name T1071
Test name
Test status
Simulation time 134778446 ps
CPU time 1.27 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 215412 kb
Host smart-93c3dffd-3fd0-4546-b79c-f4fa139ff444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99021505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.99021505
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.284030103
Short name T1088
Test name
Test status
Simulation time 30629815 ps
CPU time 0.79 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 204184 kb
Host smart-b91f366e-b52d-46ee-9135-7641d68bbb0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284030103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.284030103
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.310642232
Short name T153
Test name
Test status
Simulation time 1745108892 ps
CPU time 4.3 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 215444 kb
Host smart-669eaa72-df5b-49d2-85db-de5a3785647b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310642232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.310642232
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2678088628
Short name T1131
Test name
Test status
Simulation time 93573477 ps
CPU time 2.34 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 215560 kb
Host smart-f51cf151-3316-43b9-9140-fa2e39f16388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678088628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2678088628
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1812875672
Short name T184
Test name
Test status
Simulation time 876191211 ps
CPU time 20.53 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 217904 kb
Host smart-4c42bd24-8d95-44ac-9c1a-86f4d393967f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812875672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1812875672
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3773902526
Short name T1117
Test name
Test status
Simulation time 482262407 ps
CPU time 8.03 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 215332 kb
Host smart-b440b7ba-ff51-4666-a8dd-35c84edecfaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773902526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3773902526
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1929829047
Short name T1138
Test name
Test status
Simulation time 1407794527 ps
CPU time 23.06 seconds
Started Jul 31 04:44:44 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 215340 kb
Host smart-ebfaa746-3d61-4fe1-afec-c1b2813e2fc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929829047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1929829047
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1743618226
Short name T82
Test name
Test status
Simulation time 43497711 ps
CPU time 1.18 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 216384 kb
Host smart-c9a094d1-2270-4630-9dd2-c3998874be26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743618226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1743618226
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2570878532
Short name T1053
Test name
Test status
Simulation time 416622101 ps
CPU time 3.75 seconds
Started Jul 31 04:44:38 PM PDT 24
Finished Jul 31 04:44:42 PM PDT 24
Peak memory 218512 kb
Host smart-261503a8-505e-4601-a8b2-473fdadc356a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570878532 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2570878532
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3677482481
Short name T152
Test name
Test status
Simulation time 159321867 ps
CPU time 1.37 seconds
Started Jul 31 04:44:35 PM PDT 24
Finished Jul 31 04:44:36 PM PDT 24
Peak memory 215472 kb
Host smart-9293e571-68a2-442f-911b-e577d7f6d1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677482481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
677482481
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1149735355
Short name T1126
Test name
Test status
Simulation time 25049627 ps
CPU time 0.76 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:43 PM PDT 24
Peak memory 203888 kb
Host smart-67a6a1de-261c-438c-8f22-77e901f7bff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149735355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
149735355
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3213839234
Short name T1097
Test name
Test status
Simulation time 61552754 ps
CPU time 2.14 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:45 PM PDT 24
Peak memory 215484 kb
Host smart-1729d1c5-d711-4045-9e0f-2e70ba469d7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213839234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3213839234
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3112925555
Short name T1084
Test name
Test status
Simulation time 13982461 ps
CPU time 0.7 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 203996 kb
Host smart-4fa8901a-67e4-4530-953d-b5d3e4c67a91
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112925555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3112925555
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1108961555
Short name T1113
Test name
Test status
Simulation time 79183568 ps
CPU time 1.81 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 215368 kb
Host smart-eae4a598-026a-4b7b-82f2-cb516dd9db5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108961555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1108961555
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2283119009
Short name T1151
Test name
Test status
Simulation time 122300347 ps
CPU time 4.1 seconds
Started Jul 31 04:44:40 PM PDT 24
Finished Jul 31 04:44:44 PM PDT 24
Peak memory 215584 kb
Host smart-abbb9e5c-58e7-40eb-9d7d-b29215a8488d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283119009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
283119009
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1906247858
Short name T177
Test name
Test status
Simulation time 607278110 ps
CPU time 8.39 seconds
Started Jul 31 04:44:39 PM PDT 24
Finished Jul 31 04:44:47 PM PDT 24
Peak memory 215400 kb
Host smart-8133673b-ccf5-41bb-9910-e0f8179d3d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906247858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1906247858
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1753211212
Short name T1101
Test name
Test status
Simulation time 38766626 ps
CPU time 0.69 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 203860 kb
Host smart-1e3d79aa-e64e-45c1-aabc-6e80a1e40654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753211212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1753211212
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4099748326
Short name T1038
Test name
Test status
Simulation time 20643289 ps
CPU time 0.7 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 203904 kb
Host smart-59828734-61b5-4244-ac92-204a585357f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099748326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4099748326
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1258385451
Short name T1062
Test name
Test status
Simulation time 11242820 ps
CPU time 0.75 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 204232 kb
Host smart-9795f957-4d10-4b79-ae27-c11d7625680d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258385451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1258385451
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1204651132
Short name T1068
Test name
Test status
Simulation time 17936030 ps
CPU time 0.77 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 203904 kb
Host smart-dac3ddef-2bd6-4d82-bdc7-ccd3d7c210a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204651132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1204651132
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1053833020
Short name T1075
Test name
Test status
Simulation time 44739826 ps
CPU time 0.71 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 203908 kb
Host smart-99447362-637f-4a12-a1a0-e5e734dc4f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053833020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1053833020
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1354414211
Short name T1063
Test name
Test status
Simulation time 41141036 ps
CPU time 0.72 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 203908 kb
Host smart-600317cc-4ddc-44b1-b896-ef3ceb99c3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354414211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1354414211
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.672108377
Short name T1109
Test name
Test status
Simulation time 38397885 ps
CPU time 0.68 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 204220 kb
Host smart-b4a517a3-65c4-4df4-91f9-ec56e9d0e29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672108377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.672108377
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1646780244
Short name T1081
Test name
Test status
Simulation time 16776419 ps
CPU time 0.77 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 203864 kb
Host smart-7d1da8b2-edeb-4290-b05b-77cd29a1a8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646780244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1646780244
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1369268800
Short name T1050
Test name
Test status
Simulation time 26059863 ps
CPU time 0.67 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 203900 kb
Host smart-19728fc0-a3ca-4b3e-8072-d3bf5b3f8bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369268800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1369268800
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3667061936
Short name T1082
Test name
Test status
Simulation time 87375577 ps
CPU time 0.8 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 202576 kb
Host smart-4d58f891-ecfe-4367-80cb-ee44f70a229d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667061936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3667061936
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4275829390
Short name T1122
Test name
Test status
Simulation time 1150307655 ps
CPU time 23.68 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:45:16 PM PDT 24
Peak memory 215456 kb
Host smart-8c4d6d1e-e00d-46ee-bf65-f7b4bec37291
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275829390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4275829390
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1647976298
Short name T1051
Test name
Test status
Simulation time 1271893329 ps
CPU time 24.6 seconds
Started Jul 31 04:44:46 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 207168 kb
Host smart-a86e1c30-9508-4609-aa2f-5b6ea41e1bc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647976298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1647976298
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4266662925
Short name T1034
Test name
Test status
Simulation time 100088879 ps
CPU time 0.95 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 206996 kb
Host smart-0103b03c-b435-4cbf-8f32-d3ea58a98334
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266662925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4266662925
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1995150008
Short name T1069
Test name
Test status
Simulation time 74951999 ps
CPU time 2.24 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:45 PM PDT 24
Peak memory 216420 kb
Host smart-41a8421e-0d8b-4768-bf6a-a6e190bcb55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995150008 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1995150008
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4131028023
Short name T118
Test name
Test status
Simulation time 164574228 ps
CPU time 2.5 seconds
Started Jul 31 04:44:44 PM PDT 24
Finished Jul 31 04:44:47 PM PDT 24
Peak memory 215340 kb
Host smart-34f7720b-7cb8-4d77-b0a5-84ba2f881594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131028023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
131028023
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2518803856
Short name T1135
Test name
Test status
Simulation time 45226459 ps
CPU time 0.75 seconds
Started Jul 31 04:44:36 PM PDT 24
Finished Jul 31 04:44:37 PM PDT 24
Peak memory 203892 kb
Host smart-265511f9-ceb4-4fe5-93b8-5ebfa339d175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518803856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
518803856
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2210827079
Short name T116
Test name
Test status
Simulation time 59137698 ps
CPU time 1.66 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 215372 kb
Host smart-e9f13614-cb1b-4702-acb3-c69b8c4a9429
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210827079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2210827079
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3601257834
Short name T1043
Test name
Test status
Simulation time 13951323 ps
CPU time 0.65 seconds
Started Jul 31 04:44:47 PM PDT 24
Finished Jul 31 04:44:48 PM PDT 24
Peak memory 204148 kb
Host smart-b566eee3-488b-4a98-9e46-67126dba378d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601257834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3601257834
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3313664184
Short name T1078
Test name
Test status
Simulation time 43858444 ps
CPU time 2.69 seconds
Started Jul 31 04:44:36 PM PDT 24
Finished Jul 31 04:44:38 PM PDT 24
Peak memory 215164 kb
Host smart-2cb00a57-ff23-4e6d-9225-50f882119b9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313664184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3313664184
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2932861005
Short name T176
Test name
Test status
Simulation time 85161465 ps
CPU time 5.13 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:47 PM PDT 24
Peak memory 215640 kb
Host smart-8fa758f8-ba35-4d03-9ef8-00ca328a7a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932861005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
932861005
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1674404385
Short name T187
Test name
Test status
Simulation time 1514557949 ps
CPU time 16.16 seconds
Started Jul 31 04:44:44 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 223656 kb
Host smart-b39d20dc-2e99-4226-96da-86c37bb63022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674404385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1674404385
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2813461782
Short name T1119
Test name
Test status
Simulation time 16383729 ps
CPU time 0.7 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 203876 kb
Host smart-20003cb1-4a3a-40bc-938c-aa8e2656ec5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813461782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2813461782
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.371193330
Short name T1132
Test name
Test status
Simulation time 11701703 ps
CPU time 0.68 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 203892 kb
Host smart-46b44ffa-4431-49d1-8c83-b88a8a4e0df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371193330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.371193330
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.714393520
Short name T1134
Test name
Test status
Simulation time 37887149 ps
CPU time 0.68 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 204228 kb
Host smart-90790436-3fc0-453f-be04-7c7bd50a3704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714393520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.714393520
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2054383617
Short name T1150
Test name
Test status
Simulation time 50895557 ps
CPU time 0.75 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 203852 kb
Host smart-25d8e028-c883-4ebc-84ad-41546d335e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054383617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2054383617
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1050457816
Short name T1111
Test name
Test status
Simulation time 16931113 ps
CPU time 0.76 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 203900 kb
Host smart-b79b3a36-0aba-40de-bb7d-428ab1ed043c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050457816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1050457816
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.176530458
Short name T1083
Test name
Test status
Simulation time 26721788 ps
CPU time 0.73 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 203904 kb
Host smart-829353d1-8be5-45d8-b70f-edb13e180547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176530458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.176530458
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2791007117
Short name T1041
Test name
Test status
Simulation time 20212497 ps
CPU time 0.72 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 204188 kb
Host smart-f2432859-8d42-49d2-ba9a-7dab14369435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791007117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2791007117
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.112674386
Short name T1035
Test name
Test status
Simulation time 68231206 ps
CPU time 0.67 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 203960 kb
Host smart-3b3645fb-399c-4cf9-a086-68bb28899cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112674386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.112674386
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3792717687
Short name T1118
Test name
Test status
Simulation time 17466038 ps
CPU time 0.7 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:05 PM PDT 24
Peak memory 203980 kb
Host smart-ccf82c23-1573-48c2-81f1-a9e97ad90be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792717687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3792717687
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3253744476
Short name T1049
Test name
Test status
Simulation time 16499143 ps
CPU time 0.71 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 204312 kb
Host smart-42e70dd8-13f5-4398-9393-20e5c1646e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253744476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3253744476
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4133937062
Short name T1116
Test name
Test status
Simulation time 550909208 ps
CPU time 8.2 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 207152 kb
Host smart-8bf2b0c1-2652-4845-bfae-c16d622f2b84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133937062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4133937062
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2447256571
Short name T125
Test name
Test status
Simulation time 6255593172 ps
CPU time 24.36 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:45:16 PM PDT 24
Peak memory 207300 kb
Host smart-45a8883d-c01e-4545-9708-b8a8c959c714
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447256571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2447256571
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3945573905
Short name T81
Test name
Test status
Simulation time 40316276 ps
CPU time 0.95 seconds
Started Jul 31 04:44:34 PM PDT 24
Finished Jul 31 04:44:35 PM PDT 24
Peak memory 207040 kb
Host smart-23495a21-83a1-4d80-b0ce-2cd0b088b597
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945573905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3945573905
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3996750801
Short name T1144
Test name
Test status
Simulation time 195804987 ps
CPU time 3.37 seconds
Started Jul 31 04:44:39 PM PDT 24
Finished Jul 31 04:44:42 PM PDT 24
Peak memory 217756 kb
Host smart-e5ae1ea6-67d5-46cc-8d86-e21382267211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996750801 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3996750801
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3343531268
Short name T1140
Test name
Test status
Simulation time 120185607 ps
CPU time 2.82 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215372 kb
Host smart-27d222a0-15b1-45f7-9273-85662005291b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343531268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
343531268
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.401569076
Short name T1058
Test name
Test status
Simulation time 16850819 ps
CPU time 0.74 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:42 PM PDT 24
Peak memory 203824 kb
Host smart-89f820e4-25f2-4a9e-987a-233fe2be5c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401569076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.401569076
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1804766499
Short name T120
Test name
Test status
Simulation time 83051022 ps
CPU time 1.61 seconds
Started Jul 31 04:44:43 PM PDT 24
Finished Jul 31 04:44:45 PM PDT 24
Peak memory 215484 kb
Host smart-d0922a80-525d-4fc7-9a55-02e85468b630
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804766499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1804766499
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1268906927
Short name T1091
Test name
Test status
Simulation time 14212193 ps
CPU time 0.66 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 203880 kb
Host smart-5737939c-d3ac-41d7-9bc9-28964126cf39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268906927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1268906927
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.771764659
Short name T142
Test name
Test status
Simulation time 153263376 ps
CPU time 1.99 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 215368 kb
Host smart-86fd1407-2911-4c89-9758-e1d461c1c700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771764659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.771764659
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3576780258
Short name T1139
Test name
Test status
Simulation time 157014319 ps
CPU time 4.1 seconds
Started Jul 31 04:44:41 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 215616 kb
Host smart-9556c393-ccb5-4303-b3f2-aa830b6a4d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576780258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
576780258
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2196876801
Short name T183
Test name
Test status
Simulation time 756925673 ps
CPU time 12.5 seconds
Started Jul 31 04:44:37 PM PDT 24
Finished Jul 31 04:44:50 PM PDT 24
Peak memory 215980 kb
Host smart-1a2eca91-80cf-41e2-b7e8-3205e9787ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196876801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2196876801
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2870779608
Short name T1149
Test name
Test status
Simulation time 45170496 ps
CPU time 0.67 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 203908 kb
Host smart-a4f5b0c7-2929-4a91-8942-a4f07dfb97d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870779608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2870779608
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1008145903
Short name T1060
Test name
Test status
Simulation time 32998050 ps
CPU time 0.72 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 203892 kb
Host smart-3608b1da-aa17-4405-a972-2c0903232d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008145903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1008145903
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3801484229
Short name T1066
Test name
Test status
Simulation time 14321170 ps
CPU time 0.72 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 203888 kb
Host smart-dfc24b2f-1b09-4fb9-810e-b08efef6eea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801484229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3801484229
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2004407351
Short name T1061
Test name
Test status
Simulation time 14480816 ps
CPU time 0.69 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 204292 kb
Host smart-8456573b-0e47-4ee0-8e83-95ecaca55183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004407351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2004407351
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2592447297
Short name T1067
Test name
Test status
Simulation time 43071889 ps
CPU time 0.75 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 204232 kb
Host smart-be261e09-1a43-42c9-8495-df19c2468935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592447297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2592447297
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4073840863
Short name T1146
Test name
Test status
Simulation time 38796997 ps
CPU time 0.7 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 203968 kb
Host smart-28f914f0-5235-4a84-92c1-9c88b643d7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073840863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4073840863
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1850383974
Short name T1098
Test name
Test status
Simulation time 22423123 ps
CPU time 0.78 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 204024 kb
Host smart-0837f840-7c65-4ce6-a587-dc6ad456340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850383974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1850383974
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2675075817
Short name T1054
Test name
Test status
Simulation time 31379279 ps
CPU time 0.73 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 203812 kb
Host smart-50be4ac9-ba11-4872-a3cb-3c2b880d4890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675075817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2675075817
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2749011766
Short name T1085
Test name
Test status
Simulation time 19851930 ps
CPU time 0.73 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 203884 kb
Host smart-a7db2345-85bd-4887-96f3-539e4e0b5019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749011766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2749011766
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2363785572
Short name T1110
Test name
Test status
Simulation time 12093809 ps
CPU time 0.67 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 204192 kb
Host smart-16284cb3-88ac-4440-8392-ffc0d5e74bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363785572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2363785572
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1817255634
Short name T1103
Test name
Test status
Simulation time 701704110 ps
CPU time 3.64 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 217852 kb
Host smart-5cc9d34b-5fb2-4d7a-b8be-87990f245f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817255634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1817255634
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3386973343
Short name T1143
Test name
Test status
Simulation time 29933039 ps
CPU time 1.88 seconds
Started Jul 31 04:44:41 PM PDT 24
Finished Jul 31 04:44:42 PM PDT 24
Peak memory 215540 kb
Host smart-b2302009-0ce6-48fe-96e6-360d054cab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386973343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
386973343
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2083456507
Short name T1044
Test name
Test status
Simulation time 35653774 ps
CPU time 0.76 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 204128 kb
Host smart-2813dada-f669-43ba-8077-fe512333ad4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083456507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
083456507
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1989397999
Short name T1064
Test name
Test status
Simulation time 817525467 ps
CPU time 4.24 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 215336 kb
Host smart-e1ee36df-790d-4084-9840-9daa88c256a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989397999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1989397999
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3501215832
Short name T1114
Test name
Test status
Simulation time 919725613 ps
CPU time 1.76 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:47 PM PDT 24
Peak memory 215632 kb
Host smart-595f59ad-3210-4911-a84f-e13b7ea1c4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501215832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
501215832
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.218161938
Short name T101
Test name
Test status
Simulation time 104663333 ps
CPU time 6.61 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 215360 kb
Host smart-4954c1ea-3d3f-485d-8630-e32f004c2131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218161938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.218161938
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2399628289
Short name T1052
Test name
Test status
Simulation time 52427854 ps
CPU time 1.78 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:12 PM PDT 24
Peak memory 215420 kb
Host smart-39a041ca-d539-4afa-a22e-739f0d242f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399628289 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2399628289
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1142547666
Short name T122
Test name
Test status
Simulation time 30274169 ps
CPU time 1.82 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215492 kb
Host smart-728f12d0-2f10-4287-b467-6ad7d45527f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142547666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
142547666
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2444247175
Short name T1090
Test name
Test status
Simulation time 31872476 ps
CPU time 0.66 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 203892 kb
Host smart-5becd8af-cc46-4060-991d-6a9cf8dc06e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444247175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
444247175
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4029009677
Short name T1057
Test name
Test status
Simulation time 150714109 ps
CPU time 3.98 seconds
Started Jul 31 04:44:42 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 215328 kb
Host smart-d38fa476-9c92-4d37-8684-e3db8ed2fa56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029009677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4029009677
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.900315973
Short name T105
Test name
Test status
Simulation time 55689600 ps
CPU time 3.04 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215640 kb
Host smart-f615410b-ad49-4ff7-a11e-8fdcd85f423b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900315973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.900315973
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2214432657
Short name T1070
Test name
Test status
Simulation time 592489583 ps
CPU time 12.54 seconds
Started Jul 31 04:44:46 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 217028 kb
Host smart-b29d0320-1456-4047-87d8-cc9c353b5c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214432657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2214432657
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2113133997
Short name T1059
Test name
Test status
Simulation time 200160504 ps
CPU time 2.7 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 216900 kb
Host smart-17909893-f6a5-4447-adae-837c0fbb79cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113133997 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2113133997
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3179170966
Short name T1112
Test name
Test status
Simulation time 71097643 ps
CPU time 2.39 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215420 kb
Host smart-46729ae2-eedc-410a-8fc9-59d10804093c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179170966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
179170966
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1889261804
Short name T1036
Test name
Test status
Simulation time 56001026 ps
CPU time 0.69 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 203908 kb
Host smart-0ca5d820-8b1b-4e67-b0b0-0216962c84a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889261804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
889261804
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2113450607
Short name T145
Test name
Test status
Simulation time 29406546 ps
CPU time 1.83 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 215392 kb
Host smart-b947dcfc-27bd-4a98-b20c-959c6b59df6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113450607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2113450607
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.198823219
Short name T106
Test name
Test status
Simulation time 131558259 ps
CPU time 3.14 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 216812 kb
Host smart-ccedf606-4a5a-4ed7-909b-a4b495704551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198823219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.198823219
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1449820786
Short name T1100
Test name
Test status
Simulation time 1138917147 ps
CPU time 7.69 seconds
Started Jul 31 04:44:47 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 215312 kb
Host smart-12503e77-826f-4bb2-9e69-90dc6f6649be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449820786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1449820786
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1822251228
Short name T1120
Test name
Test status
Simulation time 126615280 ps
CPU time 3.67 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 217380 kb
Host smart-f2d5c722-b979-4af2-aab8-489b7bd10728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822251228 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1822251228
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3544953289
Short name T1133
Test name
Test status
Simulation time 81510359 ps
CPU time 1.2 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 207100 kb
Host smart-f6b99dec-9b7b-401f-8c73-c3b992f6a8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544953289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
544953289
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2951237409
Short name T1096
Test name
Test status
Simulation time 13357786 ps
CPU time 0.7 seconds
Started Jul 31 04:44:45 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 204200 kb
Host smart-1df1685f-4401-4166-aea5-3df505d06ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951237409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
951237409
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.160477162
Short name T1145
Test name
Test status
Simulation time 65661916 ps
CPU time 1.84 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 215464 kb
Host smart-e825dfac-e958-4cac-87a3-864a9a8c43e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160477162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.160477162
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3737236382
Short name T115
Test name
Test status
Simulation time 1509705879 ps
CPU time 8.72 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 215364 kb
Host smart-3ebf4f65-38d9-4c45-89a9-00673bf95f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737236382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3737236382
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.404707624
Short name T1048
Test name
Test status
Simulation time 40533251 ps
CPU time 2.93 seconds
Started Jul 31 04:44:48 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 216700 kb
Host smart-54ab89e8-e441-4e38-aa30-fde3a8edccad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404707624 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.404707624
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2134086199
Short name T1099
Test name
Test status
Simulation time 37309790 ps
CPU time 2.45 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:45:01 PM PDT 24
Peak memory 215456 kb
Host smart-ba8cca81-dc3e-4a59-8129-7a7c36f894d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134086199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
134086199
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3462086127
Short name T1086
Test name
Test status
Simulation time 15236817 ps
CPU time 0.72 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 204312 kb
Host smart-28b3b0ec-fbb6-4377-abd7-c7be4178746d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462086127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
462086127
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4203910312
Short name T1094
Test name
Test status
Simulation time 270669396 ps
CPU time 3.03 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 215368 kb
Host smart-703181a5-0c45-4b27-ad96-a665a97cc133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203910312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4203910312
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1687054032
Short name T109
Test name
Test status
Simulation time 94683345 ps
CPU time 1.77 seconds
Started Jul 31 04:44:54 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 215692 kb
Host smart-80721a83-f160-42c9-8753-92f4e0ab176e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687054032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
687054032
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.641663020
Short name T179
Test name
Test status
Simulation time 3034233816 ps
CPU time 21.9 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 216020 kb
Host smart-fc1a7c27-bc59-4e73-a5b6-a2d56cb2dbab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641663020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.641663020
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.387809907
Short name T870
Test name
Test status
Simulation time 27461413 ps
CPU time 0.71 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:13 PM PDT 24
Peak memory 205264 kb
Host smart-b3214eca-1335-48d9-ba0b-8233a2e0898a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387809907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.387809907
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3026381705
Short name T385
Test name
Test status
Simulation time 792418879 ps
CPU time 4.16 seconds
Started Jul 31 05:01:02 PM PDT 24
Finished Jul 31 05:01:06 PM PDT 24
Peak memory 233320 kb
Host smart-eca81bd5-e728-4a52-ab65-86f681251983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026381705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3026381705
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3068488430
Short name T553
Test name
Test status
Simulation time 49443302 ps
CPU time 0.78 seconds
Started Jul 31 05:01:10 PM PDT 24
Finished Jul 31 05:01:11 PM PDT 24
Peak memory 206948 kb
Host smart-6f829192-a7d3-427f-9019-c085b1dcab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068488430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3068488430
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1476180322
Short name T585
Test name
Test status
Simulation time 1554167503 ps
CPU time 14.85 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 233332 kb
Host smart-d87fcae8-fecb-4a82-b863-a2659e02e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476180322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1476180322
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3272744815
Short name T556
Test name
Test status
Simulation time 1284906472 ps
CPU time 2.33 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:58 PM PDT 24
Peak memory 223792 kb
Host smart-0ac87517-5fb7-41d0-a7ef-672792acadb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272744815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3272744815
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1506268043
Short name T883
Test name
Test status
Simulation time 8518069291 ps
CPU time 51.44 seconds
Started Jul 31 05:00:58 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 250548 kb
Host smart-c195d333-654f-4af3-b307-b77c383b71c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506268043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1506268043
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.223966692
Short name T314
Test name
Test status
Simulation time 10144832650 ps
CPU time 18.76 seconds
Started Jul 31 05:01:00 PM PDT 24
Finished Jul 31 05:01:19 PM PDT 24
Peak memory 225180 kb
Host smart-5e91e97b-6560-4e9e-bf87-1a50edf3c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223966692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.223966692
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.749214169
Short name T746
Test name
Test status
Simulation time 172197682026 ps
CPU time 92.87 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 250260 kb
Host smart-ad15ce15-342c-4e40-a005-9c7041827a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749214169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
749214169
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.188144680
Short name T979
Test name
Test status
Simulation time 1092844321 ps
CPU time 5.93 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:18 PM PDT 24
Peak memory 233256 kb
Host smart-fbd56e38-82fd-4dec-9748-e4ee52739cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188144680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.188144680
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1563430581
Short name T266
Test name
Test status
Simulation time 102582670 ps
CPU time 2.63 seconds
Started Jul 31 05:00:56 PM PDT 24
Finished Jul 31 05:00:59 PM PDT 24
Peak memory 225220 kb
Host smart-b8015a41-ea9d-4d52-bfb5-0684eca715b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563430581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1563430581
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1723183684
Short name T797
Test name
Test status
Simulation time 28075655 ps
CPU time 1.02 seconds
Started Jul 31 05:00:52 PM PDT 24
Finished Jul 31 05:00:53 PM PDT 24
Peak memory 218272 kb
Host smart-9c072b26-4982-49b2-9729-a4fea94cad6e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723183684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1723183684
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.627152798
Short name T793
Test name
Test status
Simulation time 233082992 ps
CPU time 2.37 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:03 PM PDT 24
Peak memory 225248 kb
Host smart-80d6c4d6-4f5b-40e6-8e01-58664c4cc154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627152798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
627152798
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.735268576
Short name T502
Test name
Test status
Simulation time 114559504 ps
CPU time 2.36 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:01:01 PM PDT 24
Peak memory 233056 kb
Host smart-73e79f71-dc46-4773-8197-579d7a558396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735268576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.735268576
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3649113935
Short name T737
Test name
Test status
Simulation time 8184740912 ps
CPU time 7.7 seconds
Started Jul 31 05:00:59 PM PDT 24
Finished Jul 31 05:01:07 PM PDT 24
Peak memory 219296 kb
Host smart-05cfd4c8-9be8-4b19-a6b8-592398768c0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3649113935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3649113935
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.634473253
Short name T70
Test name
Test status
Simulation time 111004093 ps
CPU time 1.1 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 235448 kb
Host smart-bc680f1d-1c62-4fa3-b0ca-5fc83fa34f6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634473253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.634473253
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.825314308
Short name T517
Test name
Test status
Simulation time 1809282985 ps
CPU time 10.95 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 225252 kb
Host smart-20d8d87b-ad7d-4079-a06f-b7aa8f72580b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825314308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.825314308
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3603040184
Short name T581
Test name
Test status
Simulation time 10660854911 ps
CPU time 21.65 seconds
Started Jul 31 05:00:51 PM PDT 24
Finished Jul 31 05:01:13 PM PDT 24
Peak memory 217012 kb
Host smart-4ed421f8-971c-4cf5-a0e4-421e2accc888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603040184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3603040184
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1838385315
Short name T383
Test name
Test status
Simulation time 3028947866 ps
CPU time 8.39 seconds
Started Jul 31 05:00:41 PM PDT 24
Finished Jul 31 05:00:49 PM PDT 24
Peak memory 216952 kb
Host smart-0413eb39-5ba4-4394-be9b-561882d43843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838385315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1838385315
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3723486452
Short name T748
Test name
Test status
Simulation time 100808388 ps
CPU time 1.85 seconds
Started Jul 31 05:00:46 PM PDT 24
Finished Jul 31 05:00:48 PM PDT 24
Peak memory 216864 kb
Host smart-c7bbd1c8-15a9-4bd1-be1d-19eef5fbf23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723486452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3723486452
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1575083959
Short name T713
Test name
Test status
Simulation time 162822464 ps
CPU time 0.87 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 206468 kb
Host smart-38038b15-a3ac-4b5d-92ba-988450cd0ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575083959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1575083959
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.896073012
Short name T875
Test name
Test status
Simulation time 5725511653 ps
CPU time 9.62 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 233400 kb
Host smart-6f2ce23f-02cd-4c7a-a612-e7c810a1e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896073012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.896073012
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2483358287
Short name T833
Test name
Test status
Simulation time 10898551 ps
CPU time 0.68 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:00:54 PM PDT 24
Peak memory 205816 kb
Host smart-49320f73-b8c0-4508-9040-168ecab13c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483358287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
483358287
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4117218625
Short name T586
Test name
Test status
Simulation time 4904621642 ps
CPU time 4.73 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 225252 kb
Host smart-67631971-594f-4366-a8f6-ae20cb52c754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117218625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4117218625
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.793257262
Short name T77
Test name
Test status
Simulation time 17755762 ps
CPU time 0.76 seconds
Started Jul 31 05:00:54 PM PDT 24
Finished Jul 31 05:00:55 PM PDT 24
Peak memory 206232 kb
Host smart-6db00a9b-5826-4c01-86b8-c44af70065b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793257262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.793257262
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.759590922
Short name T316
Test name
Test status
Simulation time 1033473559 ps
CPU time 18.27 seconds
Started Jul 31 05:01:08 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 241168 kb
Host smart-1164c17b-5554-420d-bfac-c1f6e68bd0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759590922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.759590922
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2189688045
Short name T575
Test name
Test status
Simulation time 106754702 ps
CPU time 2.16 seconds
Started Jul 31 05:00:57 PM PDT 24
Finished Jul 31 05:00:59 PM PDT 24
Peak memory 223600 kb
Host smart-16881c55-6c60-4262-817b-0692709be894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189688045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2189688045
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3554005331
Short name T131
Test name
Test status
Simulation time 800896546 ps
CPU time 14.75 seconds
Started Jul 31 05:01:10 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 240872 kb
Host smart-7103704c-b276-4786-8678-b1ff27d1af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554005331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3554005331
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2210458440
Short name T935
Test name
Test status
Simulation time 1057513916 ps
CPU time 3.52 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:09 PM PDT 24
Peak memory 233440 kb
Host smart-f498662a-ef27-4c6c-a3c5-c30c4fa70bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210458440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2210458440
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3138262305
Short name T238
Test name
Test status
Simulation time 6490875806 ps
CPU time 15.53 seconds
Started Jul 31 05:00:58 PM PDT 24
Finished Jul 31 05:01:14 PM PDT 24
Peak memory 233300 kb
Host smart-0254c7d3-fbef-44df-936d-95d908b73f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138262305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3138262305
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4263307447
Short name T6
Test name
Test status
Simulation time 1704918265 ps
CPU time 6.2 seconds
Started Jul 31 05:00:59 PM PDT 24
Finished Jul 31 05:01:05 PM PDT 24
Peak memory 222480 kb
Host smart-3bc909e5-d6c2-40a4-a478-87bd7ba6d4d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4263307447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4263307447
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4088937916
Short name T73
Test name
Test status
Simulation time 158798997 ps
CPU time 1.2 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:02 PM PDT 24
Peak memory 235484 kb
Host smart-bbb2c929-90ac-4183-94a2-9be91d409795
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088937916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4088937916
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3306753456
Short name T137
Test name
Test status
Simulation time 38328255 ps
CPU time 0.99 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 207088 kb
Host smart-c41d26b2-8e60-4d8d-8ae3-58807d25d749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306753456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3306753456
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1954578169
Short name T702
Test name
Test status
Simulation time 37367257456 ps
CPU time 29.47 seconds
Started Jul 31 05:01:04 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 218132 kb
Host smart-d458d462-f4c9-4a5f-8394-8f2cc2be02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954578169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1954578169
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1462061193
Short name T516
Test name
Test status
Simulation time 54245170 ps
CPU time 1.57 seconds
Started Jul 31 05:00:55 PM PDT 24
Finished Jul 31 05:00:57 PM PDT 24
Peak memory 216868 kb
Host smart-19fb96dc-dce5-4116-a4e6-a5cdf65a9f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462061193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1462061193
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.791474607
Short name T534
Test name
Test status
Simulation time 156079757 ps
CPU time 0.84 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:12 PM PDT 24
Peak memory 207396 kb
Host smart-fc2361cf-69b5-4148-a16d-146fc4c0b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791474607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.791474607
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2163529214
Short name T459
Test name
Test status
Simulation time 700427088 ps
CPU time 3.64 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:01:19 PM PDT 24
Peak memory 237292 kb
Host smart-0868d554-2b15-47dc-b603-994e05792722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163529214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2163529214
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1854137721
Short name T953
Test name
Test status
Simulation time 94000904 ps
CPU time 0.69 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 205784 kb
Host smart-8c5c3e9d-01db-4c80-8283-c5502041ab01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854137721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1854137721
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2532877619
Short name T779
Test name
Test status
Simulation time 653440933 ps
CPU time 3.01 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 225256 kb
Host smart-fb994f61-bf15-48ec-9e1d-669a69a73c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532877619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2532877619
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.59083526
Short name T348
Test name
Test status
Simulation time 30733907 ps
CPU time 0.81 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 206976 kb
Host smart-3be4af19-e9c1-48b3-9270-80195fa776cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59083526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.59083526
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1906515893
Short name T781
Test name
Test status
Simulation time 9439181789 ps
CPU time 98.92 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 254764 kb
Host smart-fbbf57e2-2c0a-4679-891c-62087cfb3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906515893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1906515893
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1196980593
Short name T519
Test name
Test status
Simulation time 27183531232 ps
CPU time 179.83 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 254572 kb
Host smart-14a6ddfe-e0b7-4f23-b956-668ab75cecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196980593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1196980593
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2084978185
Short name T196
Test name
Test status
Simulation time 7343536169 ps
CPU time 91.74 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 255600 kb
Host smart-4bead651-29b5-4251-8c5a-7a5a04af5172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084978185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2084978185
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1655031507
Short name T491
Test name
Test status
Simulation time 6905551438 ps
CPU time 25.34 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 239248 kb
Host smart-1a8357aa-656a-40ee-ba07-0763a49f4472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655031507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1655031507
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3660753191
Short name T518
Test name
Test status
Simulation time 16590497 ps
CPU time 0.75 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 216444 kb
Host smart-c4f593a1-4eed-4955-b7f2-5a1896950742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660753191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3660753191
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1323054928
Short name T95
Test name
Test status
Simulation time 1921010665 ps
CPU time 18.08 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 225140 kb
Host smart-cba8e183-b1cf-4f7a-ab19-729824be9da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323054928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1323054928
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1309140152
Short name T757
Test name
Test status
Simulation time 11025276108 ps
CPU time 58.39 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 233416 kb
Host smart-571123a9-8211-409e-8d94-c229c44b5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309140152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1309140152
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3664877233
Short name T1027
Test name
Test status
Simulation time 139173104 ps
CPU time 0.97 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 218312 kb
Host smart-282256bd-e75f-4f0f-9a9e-6a3813bfc628
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664877233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3664877233
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2567090958
Short name T942
Test name
Test status
Simulation time 1214523598 ps
CPU time 9.59 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 225176 kb
Host smart-0cd1d164-9f96-454d-a0e4-f4f7e64f4579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567090958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2567090958
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.205277173
Short name T419
Test name
Test status
Simulation time 942685118 ps
CPU time 5.58 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 233296 kb
Host smart-3784a6f0-1b1b-454f-80e9-e77e15249dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205277173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.205277173
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2832975438
Short name T166
Test name
Test status
Simulation time 211273463 ps
CPU time 3.01 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 220868 kb
Host smart-f94d0f18-a53f-41c9-b22c-29a10c3929b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832975438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2832975438
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3425720022
Short name T989
Test name
Test status
Simulation time 5407534082 ps
CPU time 27.11 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:55 PM PDT 24
Peak memory 225016 kb
Host smart-eeb6f1f8-ce58-44ea-b7ef-2d14ec864674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425720022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3425720022
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3371234410
Short name T882
Test name
Test status
Simulation time 19199951 ps
CPU time 0.74 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 206108 kb
Host smart-75d8f928-c2ab-49fb-8e7c-34cd6b2cbdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371234410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3371234410
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1607682893
Short name T56
Test name
Test status
Simulation time 3978225559 ps
CPU time 14.33 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 216956 kb
Host smart-c9d770e4-4a79-4fda-a38d-0294e1f4a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607682893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1607682893
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2900232267
Short name T544
Test name
Test status
Simulation time 194828172 ps
CPU time 2.55 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 216972 kb
Host smart-23803e48-327b-4162-bab0-82c2103dc962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900232267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2900232267
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.666342873
Short name T625
Test name
Test status
Simulation time 333079557 ps
CPU time 0.83 seconds
Started Jul 31 05:01:31 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 206480 kb
Host smart-e033342d-a78c-4e8e-9807-a64194b838e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666342873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.666342873
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2569075030
Short name T246
Test name
Test status
Simulation time 56893153 ps
CPU time 2.45 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 233352 kb
Host smart-41b65d35-4948-439a-becb-f89050948e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569075030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2569075030
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4118840355
Short name T959
Test name
Test status
Simulation time 14764022 ps
CPU time 0.7 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 205832 kb
Host smart-39daa0da-663c-4204-9cec-959546127cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118840355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4118840355
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.511882766
Short name T760
Test name
Test status
Simulation time 51095347 ps
CPU time 2.7 seconds
Started Jul 31 05:01:20 PM PDT 24
Finished Jul 31 05:01:23 PM PDT 24
Peak memory 233304 kb
Host smart-dca0d86b-df97-479f-942f-4539f346d153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511882766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.511882766
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1661542776
Short name T742
Test name
Test status
Simulation time 35857917 ps
CPU time 0.8 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 206980 kb
Host smart-e536f8bc-7f74-4d1f-931e-6570ad96f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661542776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1661542776
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1394889401
Short name T194
Test name
Test status
Simulation time 96508169464 ps
CPU time 213.49 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:05:04 PM PDT 24
Peak memory 249780 kb
Host smart-4ebfba3c-9c6b-4c95-b914-76b5ad3c071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394889401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1394889401
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2140256080
Short name T239
Test name
Test status
Simulation time 55204950622 ps
CPU time 150.91 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:04:03 PM PDT 24
Peak memory 251076 kb
Host smart-8a6c2a14-df1b-4ef7-ace8-d520b12c0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140256080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2140256080
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3430396153
Short name T975
Test name
Test status
Simulation time 11438307836 ps
CPU time 113.25 seconds
Started Jul 31 05:01:34 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 238656 kb
Host smart-e1fbf62f-35d0-4e6b-a4d1-88e610402dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430396153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3430396153
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3958142874
Short name T588
Test name
Test status
Simulation time 1137102037 ps
CPU time 13.44 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:41 PM PDT 24
Peak memory 233468 kb
Host smart-fc5eb2f4-d6b4-4e4b-ab5c-462106527afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958142874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3958142874
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1664920938
Short name T598
Test name
Test status
Simulation time 147810226 ps
CPU time 5.12 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 233288 kb
Host smart-5cf06f55-573d-4c19-ad64-d2ebdc6c5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664920938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1664920938
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2335329460
Short name T901
Test name
Test status
Simulation time 4363929794 ps
CPU time 44.48 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 241536 kb
Host smart-f871ebbc-ddd8-4ecd-811c-c1fdee2d7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335329460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2335329460
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1442138593
Short name T41
Test name
Test status
Simulation time 102783809 ps
CPU time 1.02 seconds
Started Jul 31 05:01:55 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 217172 kb
Host smart-bfbb7a4e-5442-460f-a784-2d6baa8517e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442138593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1442138593
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2554572490
Short name T545
Test name
Test status
Simulation time 7710543129 ps
CPU time 12.6 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 225264 kb
Host smart-220d615b-c9a6-4441-a096-a9ca3ff616b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554572490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2554572490
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.419002996
Short name T675
Test name
Test status
Simulation time 13776670024 ps
CPU time 25.99 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 234252 kb
Host smart-39be3292-2c38-4c5a-a194-59d8b2c4d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419002996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.419002996
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1955360195
Short name T687
Test name
Test status
Simulation time 2072459067 ps
CPU time 23.97 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:02:06 PM PDT 24
Peak memory 222048 kb
Host smart-419410b0-d115-4496-bec3-e5cad6ef6b87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955360195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1955360195
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2752847501
Short name T161
Test name
Test status
Simulation time 13781960351 ps
CPU time 202.31 seconds
Started Jul 31 05:01:34 PM PDT 24
Finished Jul 31 05:04:57 PM PDT 24
Peak memory 274404 kb
Host smart-75282ec0-e717-4e6c-88c4-2615a699f24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752847501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2752847501
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.723804124
Short name T652
Test name
Test status
Simulation time 13033474214 ps
CPU time 14.51 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 216916 kb
Host smart-dd1da556-d880-4e58-9c11-85b71c5f5d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723804124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.723804124
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2448156675
Short name T635
Test name
Test status
Simulation time 5661809940 ps
CPU time 17.4 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:49 PM PDT 24
Peak memory 216816 kb
Host smart-4e9be72a-6e23-49d7-9d2c-c8469c6e726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448156675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2448156675
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1910739195
Short name T890
Test name
Test status
Simulation time 360199576 ps
CPU time 1.89 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 216772 kb
Host smart-21d3a598-533f-46e8-abfe-7b2b966663b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910739195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1910739195
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.87250783
Short name T967
Test name
Test status
Simulation time 148973582 ps
CPU time 0.81 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:06 PM PDT 24
Peak memory 206544 kb
Host smart-3985042f-9c78-4e91-8d22-b8cdf106d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87250783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.87250783
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.764484906
Short name T672
Test name
Test status
Simulation time 1392939882 ps
CPU time 9.15 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 233432 kb
Host smart-af8928ba-874b-476f-ae01-ee0dfdc6c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764484906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.764484906
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2545215247
Short name T922
Test name
Test status
Simulation time 34003808 ps
CPU time 2.56 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 233248 kb
Host smart-d916bed2-d7c3-4d80-8384-2f33411b0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545215247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2545215247
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4174002923
Short name T542
Test name
Test status
Simulation time 19738092 ps
CPU time 0.76 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 206952 kb
Host smart-bbc3b50c-6a9b-4444-a1af-d458c2263360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174002923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4174002923
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.54900026
Short name T764
Test name
Test status
Simulation time 7057513408 ps
CPU time 27.35 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 250476 kb
Host smart-101480f7-7c2d-4a65-9db8-d2e6fc8822c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54900026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.54900026
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2512021267
Short name T223
Test name
Test status
Simulation time 7589137061 ps
CPU time 80.28 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:02:48 PM PDT 24
Peak memory 237840 kb
Host smart-f31d88f9-4ba3-46b0-8385-b5170f2927db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512021267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2512021267
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1604533408
Short name T466
Test name
Test status
Simulation time 4200931497 ps
CPU time 10.49 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 218320 kb
Host smart-51b1036d-ed1b-485e-a132-424ddb9ac369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604533408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1604533408
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2944891268
Short name T1020
Test name
Test status
Simulation time 35048952 ps
CPU time 2.65 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 233384 kb
Host smart-7d78e037-2846-459c-be01-78db14135ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944891268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2944891268
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2690309680
Short name T929
Test name
Test status
Simulation time 6160281953 ps
CPU time 47.98 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:02:30 PM PDT 24
Peak memory 240080 kb
Host smart-8c536b8f-8c71-4b00-83cb-0aa78e0f82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690309680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2690309680
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.324614660
Short name T249
Test name
Test status
Simulation time 1511024681 ps
CPU time 15.23 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 233276 kb
Host smart-1bab9d80-7bc3-4190-aed4-426cee1be06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324614660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.324614660
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1908614447
Short name T507
Test name
Test status
Simulation time 57300361 ps
CPU time 2.1 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 224516 kb
Host smart-81c7d625-726d-4feb-a1a8-088d1587d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908614447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1908614447
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3078635282
Short name T944
Test name
Test status
Simulation time 36888313 ps
CPU time 1.15 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 217060 kb
Host smart-dc3cd616-5a3d-4520-8e11-416abf398f7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078635282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3078635282
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2886480506
Short name T663
Test name
Test status
Simulation time 941065280 ps
CPU time 3.14 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 233284 kb
Host smart-f531b5dc-159c-4109-823e-31c2b0fa29ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886480506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2886480506
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3672835635
Short name T543
Test name
Test status
Simulation time 134759696 ps
CPU time 4.02 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 233280 kb
Host smart-0d7daef6-8668-4341-a992-e86dfacdf621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672835635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3672835635
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2994010261
Short name T379
Test name
Test status
Simulation time 2019222620 ps
CPU time 9.42 seconds
Started Jul 31 05:02:13 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 223468 kb
Host smart-90d359c0-1789-4949-923f-753ef7aabe01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994010261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2994010261
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3636043195
Short name T243
Test name
Test status
Simulation time 40151344129 ps
CPU time 109.15 seconds
Started Jul 31 05:01:31 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 251832 kb
Host smart-5aa1a6f9-5e5b-499c-8877-18c78907db5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636043195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3636043195
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1976735952
Short name T59
Test name
Test status
Simulation time 2651233473 ps
CPU time 11.88 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 217024 kb
Host smart-4e8250ec-999c-4727-aa77-8d74d587968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976735952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1976735952
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3935830659
Short name T676
Test name
Test status
Simulation time 6934163368 ps
CPU time 18.44 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 217048 kb
Host smart-dfb9c50f-5ac1-428f-95e2-97cd79fbb632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935830659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3935830659
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.638923533
Short name T486
Test name
Test status
Simulation time 193730311 ps
CPU time 1.13 seconds
Started Jul 31 05:01:34 PM PDT 24
Finished Jul 31 05:01:35 PM PDT 24
Peak memory 208412 kb
Host smart-f15377e1-229e-4866-bb44-39852573d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638923533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.638923533
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.146215718
Short name T352
Test name
Test status
Simulation time 43471128 ps
CPU time 0.8 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 206416 kb
Host smart-ff5dd539-31b0-43b4-adfd-c838c7285220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146215718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.146215718
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3578427686
Short name T956
Test name
Test status
Simulation time 272356929 ps
CPU time 7.16 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 241144 kb
Host smart-99212cd2-6dcd-45ae-812b-1f6d7558154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578427686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3578427686
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.667352840
Short name T659
Test name
Test status
Simulation time 19213152 ps
CPU time 0.72 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:41 PM PDT 24
Peak memory 205160 kb
Host smart-5f18e7b9-df70-4b92-96b9-7b8dc5514646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667352840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.667352840
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4077215967
Short name T866
Test name
Test status
Simulation time 4560422252 ps
CPU time 12.77 seconds
Started Jul 31 05:01:33 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 233296 kb
Host smart-b1a1d33b-3904-4ee2-a483-8990c68d0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077215967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4077215967
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2537731952
Short name T362
Test name
Test status
Simulation time 66945851 ps
CPU time 0.79 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 207008 kb
Host smart-a624a797-b84c-4dbc-8046-97425edb69c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537731952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2537731952
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3729402779
Short name T981
Test name
Test status
Simulation time 11739924404 ps
CPU time 41.38 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 256340 kb
Host smart-0f57150a-b2aa-4f21-9847-9c63fca9ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729402779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3729402779
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2342571820
Short name T589
Test name
Test status
Simulation time 2546693713 ps
CPU time 46.72 seconds
Started Jul 31 05:01:49 PM PDT 24
Finished Jul 31 05:02:36 PM PDT 24
Peak memory 236512 kb
Host smart-e1c6fafe-0a4d-4cb7-95ca-c6f4fbecf42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342571820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2342571820
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3104107411
Short name T405
Test name
Test status
Simulation time 7959817170 ps
CPU time 48.03 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 225280 kb
Host smart-f3b08bbb-2815-4dc9-9cc2-6c243795ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104107411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3104107411
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1613394359
Short name T315
Test name
Test status
Simulation time 584038985 ps
CPU time 16.6 seconds
Started Jul 31 05:01:34 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 238256 kb
Host smart-1a800c3c-13b5-44aa-b8cc-c83f1df1a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613394359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1613394359
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3840583646
Short name T302
Test name
Test status
Simulation time 14832435536 ps
CPU time 81.44 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 257528 kb
Host smart-b7ef4314-9692-4556-9950-33f93d1e604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840583646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3840583646
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.660851585
Short name T531
Test name
Test status
Simulation time 1849793324 ps
CPU time 8.35 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:44 PM PDT 24
Peak memory 225096 kb
Host smart-daeae824-eb01-49e5-9172-c3ce6cd4b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660851585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.660851585
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2962654157
Short name T873
Test name
Test status
Simulation time 1262580539 ps
CPU time 2.97 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:43 PM PDT 24
Peak memory 225064 kb
Host smart-06b78705-5f68-43cb-9cf5-4e7881d4c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962654157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2962654157
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3692004714
Short name T720
Test name
Test status
Simulation time 76258592 ps
CPU time 1.03 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 217024 kb
Host smart-489d608d-ced9-4443-8944-14dd485c9ac3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692004714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3692004714
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3894997369
Short name T427
Test name
Test status
Simulation time 4762450893 ps
CPU time 14.38 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 225072 kb
Host smart-12ef6312-f319-4665-8f68-a61564668618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894997369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3894997369
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3387337391
Short name T728
Test name
Test status
Simulation time 22869240023 ps
CPU time 20.59 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 233456 kb
Host smart-652c5846-daa7-4dc4-8616-8df73bcd3311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387337391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3387337391
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2361741474
Short name T651
Test name
Test status
Simulation time 11360332313 ps
CPU time 6.5 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 219432 kb
Host smart-213223d0-304d-4d23-8bfd-77f53ceb667d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2361741474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2361741474
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1295376161
Short name T591
Test name
Test status
Simulation time 4690798904 ps
CPU time 29.56 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:02:00 PM PDT 24
Peak memory 220968 kb
Host smart-ec90be97-d399-493c-8eda-83a961cc1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295376161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1295376161
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2281377396
Short name T790
Test name
Test status
Simulation time 4610650620 ps
CPU time 7.6 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 216996 kb
Host smart-fc8448cc-9c5d-4151-a82e-de44475ccc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281377396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2281377396
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3837299023
Short name T973
Test name
Test status
Simulation time 142763292 ps
CPU time 1.21 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 208428 kb
Host smart-a403fd08-f649-416c-98b8-794bddf1928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837299023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3837299023
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2550255629
Short name T614
Test name
Test status
Simulation time 98201529 ps
CPU time 0.85 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:41 PM PDT 24
Peak memory 207420 kb
Host smart-99fb2f6c-3778-4a0a-a5df-3d8b40543991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550255629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2550255629
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.354649454
Short name T554
Test name
Test status
Simulation time 357797225 ps
CPU time 2.97 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 225104 kb
Host smart-b4de0bde-2362-4078-a694-7ec9183b3cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354649454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.354649454
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1736984571
Short name T770
Test name
Test status
Simulation time 15609194 ps
CPU time 0.82 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 205672 kb
Host smart-688c897b-73b8-486a-9a5a-9a3ae809a8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736984571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1736984571
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4206547139
Short name T279
Test name
Test status
Simulation time 433035992 ps
CPU time 6.02 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 225244 kb
Host smart-7145b21f-84af-412c-ba68-22e115f45b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206547139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4206547139
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3443846233
Short name T340
Test name
Test status
Simulation time 63404435 ps
CPU time 0.79 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 206924 kb
Host smart-e5afc3b7-0eee-428a-902e-467ff20eb024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443846233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3443846233
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3039282426
Short name T327
Test name
Test status
Simulation time 11691995524 ps
CPU time 29.82 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 218308 kb
Host smart-207acefe-44bb-4c40-b0c9-8b667554589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039282426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3039282426
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2729954704
Short name T415
Test name
Test status
Simulation time 109000479978 ps
CPU time 217.67 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:05:17 PM PDT 24
Peak memory 266172 kb
Host smart-2aab4cee-063e-4537-9271-c27e884ed23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729954704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2729954704
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1405187803
Short name T719
Test name
Test status
Simulation time 2720254385 ps
CPU time 8.49 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 225180 kb
Host smart-2099aa38-2276-4514-b9a2-c3b3cf5532d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405187803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1405187803
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3818861793
Short name T409
Test name
Test status
Simulation time 453634937 ps
CPU time 5.43 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 233440 kb
Host smart-19cdee9a-7e8d-4ed9-b2ef-f050339c7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818861793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3818861793
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3887752047
Short name T898
Test name
Test status
Simulation time 2764757133 ps
CPU time 25.68 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 233464 kb
Host smart-4ea25fd2-2474-42d6-960a-d8aa03e3c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887752047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3887752047
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2764538433
Short name T1032
Test name
Test status
Simulation time 31462217 ps
CPU time 1.09 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 217120 kb
Host smart-526b2491-8b53-4087-908a-4d72262eb4f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764538433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2764538433
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1564340955
Short name T439
Test name
Test status
Simulation time 4032144164 ps
CPU time 14.14 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:02:07 PM PDT 24
Peak memory 238476 kb
Host smart-a62f8277-2b6d-45c5-bd63-91a915f7c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564340955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1564340955
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1225214231
Short name T590
Test name
Test status
Simulation time 9370638868 ps
CPU time 8.19 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:02:00 PM PDT 24
Peak memory 225212 kb
Host smart-a571717e-92ce-48ed-947f-81ada07fdbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225214231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1225214231
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4194120566
Short name T523
Test name
Test status
Simulation time 7269369829 ps
CPU time 6.71 seconds
Started Jul 31 05:01:49 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 219812 kb
Host smart-0ee1d50d-f0b3-459b-b49d-dbdae2396591
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4194120566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4194120566
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3157883493
Short name T999
Test name
Test status
Simulation time 72673435 ps
CPU time 1.15 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 208252 kb
Host smart-01cb5e65-25fe-497b-a65d-3b99bef8a2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157883493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3157883493
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4061375132
Short name T626
Test name
Test status
Simulation time 4677639164 ps
CPU time 22.15 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 216908 kb
Host smart-74f382d8-d82b-4b8c-b6ac-7614b4b32017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061375132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4061375132
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2579966027
Short name T946
Test name
Test status
Simulation time 31288306015 ps
CPU time 22.07 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 217992 kb
Host smart-5c570c14-99d5-4039-94a2-7fe0a3cbefb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579966027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2579966027
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3068136410
Short name T616
Test name
Test status
Simulation time 125726005 ps
CPU time 3.79 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 216996 kb
Host smart-b47ba59b-3f37-4c32-aaf2-6e060af49541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068136410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3068136410
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3420658886
Short name T444
Test name
Test status
Simulation time 65691861 ps
CPU time 0.81 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:53 PM PDT 24
Peak memory 206436 kb
Host smart-07b4eed3-f1fa-44f1-b60a-659cd9b0dba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420658886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3420658886
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4246418308
Short name T928
Test name
Test status
Simulation time 1877366892 ps
CPU time 11.82 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 225212 kb
Host smart-263fbcfd-f725-4f2c-848b-9b78bd43e458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246418308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4246418308
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1505911552
Short name T886
Test name
Test status
Simulation time 16654827 ps
CPU time 0.73 seconds
Started Jul 31 05:01:49 PM PDT 24
Finished Jul 31 05:01:49 PM PDT 24
Peak memory 205164 kb
Host smart-1ba02eaf-9471-47e7-950c-413c33623540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505911552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1505911552
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3576313778
Short name T9
Test name
Test status
Simulation time 145659306 ps
CPU time 2.08 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 224692 kb
Host smart-4c417f34-928c-4704-97f7-59adcbbc96f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576313778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3576313778
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2495765542
Short name T369
Test name
Test status
Simulation time 62703733 ps
CPU time 0.75 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 206252 kb
Host smart-9373d63e-0f96-4ffd-9bd4-106298213105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495765542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2495765542
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2395493617
Short name T803
Test name
Test status
Simulation time 3969808406 ps
CPU time 18.88 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 241744 kb
Host smart-635852b3-84f7-4681-b1c0-7b191eb0f804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395493617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2395493617
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4093640580
Short name T218
Test name
Test status
Simulation time 86665144703 ps
CPU time 230.25 seconds
Started Jul 31 05:01:45 PM PDT 24
Finished Jul 31 05:05:35 PM PDT 24
Peak memory 257816 kb
Host smart-efd2f8fd-81c3-4c7e-a2cb-d53b4490c751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093640580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4093640580
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1057595729
Short name T10
Test name
Test status
Simulation time 18341899022 ps
CPU time 46.94 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 218216 kb
Host smart-2b781ea9-2b04-4bea-9b6e-11d9d9a3f5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057595729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1057595729
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.717343584
Short name T374
Test name
Test status
Simulation time 207989686 ps
CPU time 3.25 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 225132 kb
Host smart-83ba2c7d-9413-4949-a27b-1953ea400434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717343584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.717343584
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1503462681
Short name T784
Test name
Test status
Simulation time 66855342705 ps
CPU time 232.83 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:05:34 PM PDT 24
Peak memory 253548 kb
Host smart-34bf6af1-c23b-423c-b771-f6aa49f68a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503462681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1503462681
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2047256569
Short name T1021
Test name
Test status
Simulation time 418345311 ps
CPU time 4.75 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 233384 kb
Host smart-e41fe2f8-c3be-44dc-9478-2a8728871a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047256569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2047256569
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3768051129
Short name T768
Test name
Test status
Simulation time 7064979261 ps
CPU time 60.76 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 240376 kb
Host smart-5a941d2a-315e-41ec-81ce-a5e884d96040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768051129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3768051129
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.792231334
Short name T458
Test name
Test status
Simulation time 16467432 ps
CPU time 1 seconds
Started Jul 31 05:01:45 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 218368 kb
Host smart-270f74db-61de-4878-a081-df8985e25b35
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792231334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.792231334
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3243983121
Short name T984
Test name
Test status
Simulation time 34166056 ps
CPU time 2.38 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 233344 kb
Host smart-ea8ffdeb-65f3-4637-84e3-507ca6596e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243983121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3243983121
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.161893843
Short name T704
Test name
Test status
Simulation time 4375176137 ps
CPU time 7.55 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 233372 kb
Host smart-5fb5e77d-e082-4b46-b8f4-b98f27da85dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161893843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.161893843
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3226504817
Short name T993
Test name
Test status
Simulation time 1635657874 ps
CPU time 7.31 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 220000 kb
Host smart-ff04df90-f6fa-4264-bba2-aa24970d0e89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226504817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3226504817
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4264184366
Short name T363
Test name
Test status
Simulation time 3455698664 ps
CPU time 18.35 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 217000 kb
Host smart-666912c4-29dd-41af-8687-4b6d5d00e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264184366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4264184366
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1218101893
Short name T923
Test name
Test status
Simulation time 28605742274 ps
CPU time 8.75 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:49 PM PDT 24
Peak memory 216856 kb
Host smart-ecbee952-e1a1-4727-9d30-b353189848cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218101893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1218101893
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.720734293
Short name T382
Test name
Test status
Simulation time 295643698 ps
CPU time 11.87 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 216752 kb
Host smart-b6c97537-2ce2-4599-a82b-deb0ed1738ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720734293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.720734293
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1322511104
Short name T681
Test name
Test status
Simulation time 165127698 ps
CPU time 0.8 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 206448 kb
Host smart-77824b9b-0407-4615-bc2c-f2c4e83bb7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322511104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1322511104
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1032332907
Short name T229
Test name
Test status
Simulation time 3878353612 ps
CPU time 17.32 seconds
Started Jul 31 05:01:49 PM PDT 24
Finished Jul 31 05:02:06 PM PDT 24
Peak memory 233408 kb
Host smart-10432ba4-afda-44f7-998f-82a30d372a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032332907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1032332907
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3995512105
Short name T759
Test name
Test status
Simulation time 68748208 ps
CPU time 0.72 seconds
Started Jul 31 05:01:33 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 205208 kb
Host smart-cb881fea-08d6-4b50-b74b-9d64da7b4f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995512105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3995512105
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2675023412
Short name T5
Test name
Test status
Simulation time 2506035314 ps
CPU time 18.04 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 225292 kb
Host smart-27dd1ee6-b6dc-408a-b680-6077b6dbcdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675023412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2675023412
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.388634386
Short name T915
Test name
Test status
Simulation time 45382094 ps
CPU time 0.75 seconds
Started Jul 31 05:01:46 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 206968 kb
Host smart-cc52d73b-6b03-4ead-a4d1-ed95c1967b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388634386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.388634386
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1467417536
Short name T524
Test name
Test status
Simulation time 5154921498 ps
CPU time 6.01 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 225248 kb
Host smart-07d3ec73-ae4f-4f03-8967-5144b419d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467417536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1467417536
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2028057951
Short name T301
Test name
Test status
Simulation time 24126256503 ps
CPU time 263.92 seconds
Started Jul 31 05:01:47 PM PDT 24
Finished Jul 31 05:06:11 PM PDT 24
Peak memory 273700 kb
Host smart-33d70382-061c-4648-a280-1f08ff59c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028057951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2028057951
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1045692198
Short name T1000
Test name
Test status
Simulation time 1057465434 ps
CPU time 17.4 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 234360 kb
Host smart-431a9b4c-e0c1-4c28-a897-52024d6773bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045692198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1045692198
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.532606209
Short name T774
Test name
Test status
Simulation time 5970910877 ps
CPU time 81.61 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:03:15 PM PDT 24
Peak memory 254332 kb
Host smart-ab06fee5-2747-4592-b384-cbb227cae47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532606209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.532606209
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3641441778
Short name T390
Test name
Test status
Simulation time 576604616 ps
CPU time 3.77 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 225052 kb
Host smart-471f087d-ac84-4506-a03b-9885596f4d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641441778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3641441778
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3795253352
Short name T862
Test name
Test status
Simulation time 218138817 ps
CPU time 4.33 seconds
Started Jul 31 05:01:31 PM PDT 24
Finished Jul 31 05:01:35 PM PDT 24
Peak memory 235788 kb
Host smart-ea90cc81-5213-44db-bd9e-72b648304018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795253352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3795253352
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1471445257
Short name T366
Test name
Test status
Simulation time 27530667 ps
CPU time 1.1 seconds
Started Jul 31 05:01:54 PM PDT 24
Finished Jul 31 05:01:55 PM PDT 24
Peak memory 217108 kb
Host smart-ac51ea18-0077-49e8-b08a-4d27b6e98c02
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471445257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1471445257
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2953424984
Short name T964
Test name
Test status
Simulation time 861826729 ps
CPU time 5.59 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:43 PM PDT 24
Peak memory 225208 kb
Host smart-3809c781-0be6-448e-991a-dd7ae3344064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953424984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2953424984
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1944237824
Short name T730
Test name
Test status
Simulation time 1120468970 ps
CPU time 7.43 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 225152 kb
Host smart-c70f7e62-0bb1-4138-ad93-19366a0f8074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944237824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1944237824
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1331827288
Short name T514
Test name
Test status
Simulation time 759946549 ps
CPU time 10.05 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 220704 kb
Host smart-d4faf7e0-f814-4f55-b5e7-2e8690002339
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331827288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1331827288
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3050350159
Short name T433
Test name
Test status
Simulation time 7887970144 ps
CPU time 40.42 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 216920 kb
Host smart-3d3851df-159f-4b9e-b238-a9b738531766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050350159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3050350159
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1196677546
Short name T911
Test name
Test status
Simulation time 1650994287 ps
CPU time 4.73 seconds
Started Jul 31 05:01:45 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 216832 kb
Host smart-9fafee21-408a-4972-a8f7-017eaa44ed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196677546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1196677546
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2725562266
Short name T414
Test name
Test status
Simulation time 695842564 ps
CPU time 3.55 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:10 PM PDT 24
Peak memory 216888 kb
Host smart-dfb2891f-3129-4be4-83ba-dbe7e707b288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725562266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2725562266
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2200966329
Short name T669
Test name
Test status
Simulation time 66020521 ps
CPU time 0.86 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:01:43 PM PDT 24
Peak memory 206568 kb
Host smart-529582a2-a472-40cb-a82f-a48faa8f9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200966329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2200966329
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.511512925
Short name T555
Test name
Test status
Simulation time 3107969000 ps
CPU time 6.6 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 233464 kb
Host smart-a5a125c1-fea4-4b21-9df9-aa200d123063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511512925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.511512925
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2838371053
Short name T998
Test name
Test status
Simulation time 39936875 ps
CPU time 0.7 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:02:00 PM PDT 24
Peak memory 205208 kb
Host smart-78ad6904-2816-4906-9fc3-286e4c566b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838371053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2838371053
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.982109350
Short name T703
Test name
Test status
Simulation time 68042759 ps
CPU time 2.75 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:03 PM PDT 24
Peak memory 233352 kb
Host smart-b8c224b5-2cb1-4927-b449-491e0b9e05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982109350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.982109350
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1204032156
Short name T789
Test name
Test status
Simulation time 19306997 ps
CPU time 0.75 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 207004 kb
Host smart-0c806eac-4cc1-4cbd-97e4-080b80069873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204032156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1204032156
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2786338685
Short name T971
Test name
Test status
Simulation time 24026297851 ps
CPU time 49.68 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 257428 kb
Host smart-df5be912-3f53-42c6-9395-599f71b5f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786338685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2786338685
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.204620789
Short name T326
Test name
Test status
Simulation time 561414600 ps
CPU time 10.17 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 220296 kb
Host smart-375b2b90-0bcf-45cf-9848-20c120fb0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204620789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.204620789
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.282052757
Short name T965
Test name
Test status
Simulation time 3875664555 ps
CPU time 98.98 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 265936 kb
Host smart-5d6a69fa-5754-4bdd-9518-090a13ba805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282052757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.282052757
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1825271389
Short name T863
Test name
Test status
Simulation time 1160495684 ps
CPU time 7.84 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 241496 kb
Host smart-92216c0c-3caf-43f0-9eb4-0407f7b3d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825271389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1825271389
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.527084346
Short name T692
Test name
Test status
Simulation time 8307516187 ps
CPU time 44.13 seconds
Started Jul 31 05:01:33 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 251156 kb
Host smart-e66aa2d6-a075-4191-ae4f-615c5f8af169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527084346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.527084346
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3207905998
Short name T881
Test name
Test status
Simulation time 427035309 ps
CPU time 3.39 seconds
Started Jul 31 05:01:56 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 225148 kb
Host smart-46adb7bb-f0b7-4b5b-99fc-3648be132f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207905998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3207905998
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2271059232
Short name T972
Test name
Test status
Simulation time 2271123636 ps
CPU time 24.4 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:30 PM PDT 24
Peak memory 225128 kb
Host smart-de409125-3ba7-48aa-9018-7ff6a21f0084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271059232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2271059232
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.488103414
Short name T40
Test name
Test status
Simulation time 23907346 ps
CPU time 1.03 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 217212 kb
Host smart-69738a13-1c28-4a16-985a-5151350fe793
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488103414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.488103414
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.766586218
Short name T275
Test name
Test status
Simulation time 1138479119 ps
CPU time 3.21 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:43 PM PDT 24
Peak memory 225220 kb
Host smart-4e97b09e-3cec-40bd-892f-4069a67d21ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766586218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.766586218
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.779952279
Short name T215
Test name
Test status
Simulation time 3147623919 ps
CPU time 9.03 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 225152 kb
Host smart-a22ebd34-47a9-40ec-90dd-bae5850c9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779952279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.779952279
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2674870359
Short name T356
Test name
Test status
Simulation time 11905131502 ps
CPU time 9.43 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:46 PM PDT 24
Peak memory 222396 kb
Host smart-158158e8-e7a8-4519-9211-1986fe2d2c77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674870359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2674870359
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3381938005
Short name T497
Test name
Test status
Simulation time 173029738 ps
CPU time 0.99 seconds
Started Jul 31 05:01:55 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 207384 kb
Host smart-3faf170a-bd45-4cae-b678-a876382fbece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381938005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3381938005
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1509549843
Short name T693
Test name
Test status
Simulation time 6377156327 ps
CPU time 11.21 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 216896 kb
Host smart-3d5c48dc-9197-4e5a-aaff-b682cd446e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509549843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1509549843
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1777686727
Short name T829
Test name
Test status
Simulation time 3149120632 ps
CPU time 9.87 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 216948 kb
Host smart-f7f580d5-565a-44d6-a305-c6f0863f0280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777686727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1777686727
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1714886903
Short name T615
Test name
Test status
Simulation time 108424418 ps
CPU time 1.14 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 216828 kb
Host smart-a5f22360-cd3a-4be3-b8ad-a5aa8b7b5a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714886903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1714886903
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2057376528
Short name T335
Test name
Test status
Simulation time 415847621 ps
CPU time 0.9 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 206444 kb
Host smart-b3283f63-4428-47d4-9c7a-5d86f93bf7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057376528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2057376528
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3857500554
Short name T938
Test name
Test status
Simulation time 16341590205 ps
CPU time 15.58 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 225176 kb
Host smart-78782764-c864-4494-9247-d2ba1a5522fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857500554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3857500554
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2099291173
Short name T505
Test name
Test status
Simulation time 14654639 ps
CPU time 0.75 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 206040 kb
Host smart-a3daa2e2-0b81-4b77-9a1d-c6f6e11e2c72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099291173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2099291173
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1765470979
Short name T76
Test name
Test status
Simulation time 210289239 ps
CPU time 2.35 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:02:07 PM PDT 24
Peak memory 225036 kb
Host smart-712ebc35-f7c9-4e45-9969-d4e70c507162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765470979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1765470979
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.789187376
Short name T133
Test name
Test status
Simulation time 104063595 ps
CPU time 0.74 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 207260 kb
Host smart-39e43833-0e74-4c07-8938-b6ad76961585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789187376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.789187376
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4248139723
Short name T241
Test name
Test status
Simulation time 49881737094 ps
CPU time 387.18 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:08:07 PM PDT 24
Peak memory 274144 kb
Host smart-c671e9a1-9e1c-43aa-b81c-8f6cfd52cf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248139723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4248139723
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4195054633
Short name T926
Test name
Test status
Simulation time 29848196659 ps
CPU time 280.45 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:06:38 PM PDT 24
Peak memory 252644 kb
Host smart-a8f9cf33-63a8-4629-bab3-2d20f1733f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195054633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4195054633
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3041646357
Short name T202
Test name
Test status
Simulation time 49103266795 ps
CPU time 439.54 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:09:20 PM PDT 24
Peak memory 254052 kb
Host smart-7c30aeaa-9162-4a5a-bb82-08b7c95bfb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041646357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3041646357
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3537539100
Short name T639
Test name
Test status
Simulation time 100937943 ps
CPU time 5.85 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:21 PM PDT 24
Peak memory 233264 kb
Host smart-3a2b6f50-7200-42ee-ac04-f648b13d81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537539100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3537539100
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.565694647
Short name T1024
Test name
Test status
Simulation time 678842891 ps
CPU time 4.04 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 218864 kb
Host smart-0ca47785-b434-4f24-a0d6-325a1a99327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565694647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.565694647
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3318395309
Short name T985
Test name
Test status
Simulation time 405484228 ps
CPU time 6.8 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 233332 kb
Host smart-7d3b0446-4ad7-4e1a-afe0-e28adcbd2243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318395309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3318395309
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.657924511
Short name T559
Test name
Test status
Simulation time 33531076 ps
CPU time 2.55 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:55 PM PDT 24
Peak memory 233032 kb
Host smart-d01f4aff-d2e8-40c8-a5e4-a2635c95bdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657924511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.657924511
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.562826910
Short name T483
Test name
Test status
Simulation time 15621915 ps
CPU time 1.03 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:01:49 PM PDT 24
Peak memory 217120 kb
Host smart-eac19c0e-6a5f-4c55-aee8-39b85ed77423
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562826910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.562826910
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4135783812
Short name T270
Test name
Test status
Simulation time 2005733998 ps
CPU time 9.21 seconds
Started Jul 31 05:01:33 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 233296 kb
Host smart-772b65b4-49d5-4e95-88a8-562d8e4c609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135783812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4135783812
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1190962800
Short name T871
Test name
Test status
Simulation time 2110810818 ps
CPU time 7.69 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 225192 kb
Host smart-20ab1ef7-684f-4b35-bf66-d164547e2b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190962800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1190962800
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3881960496
Short name T610
Test name
Test status
Simulation time 2134443682 ps
CPU time 12.88 seconds
Started Jul 31 05:02:02 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 222624 kb
Host smart-5f448852-0059-4694-b2a6-e54507ad1360
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881960496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3881960496
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1962193910
Short name T139
Test name
Test status
Simulation time 371478629621 ps
CPU time 254.46 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:06:12 PM PDT 24
Peak memory 253120 kb
Host smart-f43cff51-cb7f-48a4-ae17-07bfe02672a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962193910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1962193910
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2759202023
Short name T951
Test name
Test status
Simulation time 5947521190 ps
CPU time 34.78 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 217020 kb
Host smart-ef7f4d55-8264-415e-9810-f46ef3475ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759202023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2759202023
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2869119983
Short name T506
Test name
Test status
Simulation time 15961451561 ps
CPU time 18.48 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 217068 kb
Host smart-977031c0-1a38-48d7-aac2-68776d14208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869119983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2869119983
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1536617578
Short name T613
Test name
Test status
Simulation time 85089158 ps
CPU time 1.3 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 216828 kb
Host smart-84d22422-5c4b-4f91-9062-5e4ca681ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536617578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1536617578
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2407420182
Short name T609
Test name
Test status
Simulation time 144266053 ps
CPU time 0.82 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 206552 kb
Host smart-8e4564c7-c47b-42ff-a563-e86a6cdb2389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407420182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2407420182
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1077527875
Short name T259
Test name
Test status
Simulation time 6695778902 ps
CPU time 14.1 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 241256 kb
Host smart-ffaf03cd-d7d2-43ea-9099-2800713f0250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077527875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1077527875
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3284586526
Short name T567
Test name
Test status
Simulation time 80301894 ps
CPU time 0.73 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:01 PM PDT 24
Peak memory 205792 kb
Host smart-375cbbf6-e0ac-40b1-8c15-50c266b1007d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284586526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3284586526
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3942328661
Short name T806
Test name
Test status
Simulation time 291667193 ps
CPU time 2.5 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 225160 kb
Host smart-d577b336-eb74-4651-a7d5-ad7b3429cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942328661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3942328661
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4053421093
Short name T865
Test name
Test status
Simulation time 112830912 ps
CPU time 0.74 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 205896 kb
Host smart-14b9ae0a-23f4-4d20-b91c-6c6fa138ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053421093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4053421093
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3353350315
Short name T566
Test name
Test status
Simulation time 12885844 ps
CPU time 0.76 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 216316 kb
Host smart-306b166d-8d9f-46ff-bafd-60ab9cc0167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353350315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3353350315
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1148699674
Short name T714
Test name
Test status
Simulation time 19686284122 ps
CPU time 72.23 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:03:27 PM PDT 24
Peak memory 256404 kb
Host smart-f7249243-ab74-4aac-87db-de8ef559d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148699674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1148699674
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.105823389
Short name T456
Test name
Test status
Simulation time 34090254634 ps
CPU time 43.74 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 218160 kb
Host smart-a890de38-81a6-4a10-94ed-d0d955ad39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105823389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.105823389
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4126329945
Short name T318
Test name
Test status
Simulation time 767576290 ps
CPU time 8.36 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 233356 kb
Host smart-047554be-1d36-46a6-bab0-f47095177077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126329945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4126329945
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1078800067
Short name T1025
Test name
Test status
Simulation time 320358201236 ps
CPU time 374.66 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:08:06 PM PDT 24
Peak memory 250660 kb
Host smart-b356c729-432c-462e-a3dd-8ed82c98eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078800067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1078800067
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1607958691
Short name T664
Test name
Test status
Simulation time 461945507 ps
CPU time 3.69 seconds
Started Jul 31 05:01:46 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 233352 kb
Host smart-ae66b9b1-cd1d-43d6-a4f4-a7cff25a4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607958691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1607958691
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.290057340
Short name T511
Test name
Test status
Simulation time 691527999 ps
CPU time 10.39 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 240620 kb
Host smart-28dd99fc-41e7-4f9d-9841-5a909ebac3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290057340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.290057340
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4096698121
Short name T708
Test name
Test status
Simulation time 378316752 ps
CPU time 1.05 seconds
Started Jul 31 05:01:46 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 217168 kb
Host smart-07c48740-b699-47ee-b97c-ba6783c44758
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096698121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4096698121
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1355348911
Short name T226
Test name
Test status
Simulation time 15460830358 ps
CPU time 25.41 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:02:03 PM PDT 24
Peak memory 233992 kb
Host smart-563c6504-424a-4173-b09e-354699161e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355348911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1355348911
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4011612366
Short name T650
Test name
Test status
Simulation time 348633166 ps
CPU time 3.51 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 225104 kb
Host smart-48d3b472-c8b6-41de-ae94-403f28e1b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011612366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4011612366
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3909171163
Short name T818
Test name
Test status
Simulation time 232046330 ps
CPU time 4.54 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 223496 kb
Host smart-adacb5fe-4f80-4c4a-86f7-2ba4842fdf60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909171163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3909171163
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4268744766
Short name T394
Test name
Test status
Simulation time 3288398839 ps
CPU time 82.88 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:03:51 PM PDT 24
Peak memory 257960 kb
Host smart-06903607-2c00-4d70-9fc9-25dd9b3d378b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268744766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4268744766
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.664303844
Short name T834
Test name
Test status
Simulation time 377029630 ps
CPU time 5.09 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 216912 kb
Host smart-0786dbbd-672e-4e98-91c7-49526e142434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664303844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.664303844
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3669443941
Short name T587
Test name
Test status
Simulation time 15315965706 ps
CPU time 10.74 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 216916 kb
Host smart-35306769-9a39-4ee1-a7bf-f88f6bc36f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669443941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3669443941
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2789808219
Short name T417
Test name
Test status
Simulation time 11641972 ps
CPU time 0.7 seconds
Started Jul 31 05:01:55 PM PDT 24
Finished Jul 31 05:01:55 PM PDT 24
Peak memory 205956 kb
Host smart-54377c1e-44af-40d8-bcbe-621424cd1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789808219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2789808219
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2194484966
Short name T846
Test name
Test status
Simulation time 23318140 ps
CPU time 0.77 seconds
Started Jul 31 05:01:50 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 206568 kb
Host smart-21bc9cbc-4761-49a6-9edb-1df7f8dcf2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194484966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2194484966
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2476989030
Short name T476
Test name
Test status
Simulation time 1232507753 ps
CPU time 6.37 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:02:03 PM PDT 24
Peak memory 233336 kb
Host smart-66a3ee58-670f-4a99-bae0-637ac7e4e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476989030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2476989030
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3893168748
Short name T934
Test name
Test status
Simulation time 145949609 ps
CPU time 0.73 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 205636 kb
Host smart-fd430a49-1ba2-4755-a733-dcc00bb81494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893168748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
893168748
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.690250502
Short name T252
Test name
Test status
Simulation time 4859987675 ps
CPU time 15.19 seconds
Started Jul 31 05:01:07 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 233384 kb
Host smart-5361e506-b9ec-4f62-9147-d88614f25704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690250502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.690250502
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2978437644
Short name T986
Test name
Test status
Simulation time 14037609 ps
CPU time 0.76 seconds
Started Jul 31 05:01:01 PM PDT 24
Finished Jul 31 05:01:02 PM PDT 24
Peak memory 206032 kb
Host smart-f25109a3-ae07-4d60-912d-32af489cc340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978437644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2978437644
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.343261990
Short name T219
Test name
Test status
Simulation time 228184320221 ps
CPU time 199.74 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:04:32 PM PDT 24
Peak memory 253264 kb
Host smart-fed414df-073b-4a80-ad83-5bf2248aabab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343261990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.343261990
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3280487695
Short name T325
Test name
Test status
Simulation time 47299776266 ps
CPU time 133.4 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 249892 kb
Host smart-9bac19b4-1e82-4555-aa38-c3cd1d9ec9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280487695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3280487695
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1238100354
Short name T845
Test name
Test status
Simulation time 3380458691 ps
CPU time 51.25 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:02:06 PM PDT 24
Peak memory 249936 kb
Host smart-509eee2d-621b-4895-813c-972fe95cf4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238100354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1238100354
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1928648120
Short name T428
Test name
Test status
Simulation time 2471926690 ps
CPU time 30.8 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:36 PM PDT 24
Peak memory 233384 kb
Host smart-359c5caa-4306-4d5f-85dc-abe3cd816db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928648120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1928648120
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2013300976
Short name T310
Test name
Test status
Simulation time 59506561821 ps
CPU time 33.21 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 233364 kb
Host smart-d89f6eef-a424-410d-85a1-a0f80dabbb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013300976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2013300976
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.282211196
Short name T723
Test name
Test status
Simulation time 509851333 ps
CPU time 3.25 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:08 PM PDT 24
Peak memory 225120 kb
Host smart-6a9d3dcf-f0c7-4c36-94ff-8c4e6df9a653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282211196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.282211196
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3803461777
Short name T726
Test name
Test status
Simulation time 7387546323 ps
CPU time 14.9 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 233392 kb
Host smart-803065ea-a3c3-467b-a713-67b3255e61a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803461777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3803461777
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3194279006
Short name T339
Test name
Test status
Simulation time 101691077 ps
CPU time 1.16 seconds
Started Jul 31 05:01:14 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 218316 kb
Host smart-e603341a-2f54-4fa3-bef7-dad9cf64bfdd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194279006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3194279006
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2133087693
Short name T715
Test name
Test status
Simulation time 13485346432 ps
CPU time 16.04 seconds
Started Jul 31 05:01:21 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 241464 kb
Host smart-a5694175-8986-4ef5-815f-988f3c3e6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133087693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2133087693
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.840897764
Short name T440
Test name
Test status
Simulation time 157737475 ps
CPU time 3.17 seconds
Started Jul 31 05:01:02 PM PDT 24
Finished Jul 31 05:01:05 PM PDT 24
Peak memory 233496 kb
Host smart-c3fd227e-6c90-4309-af79-35044aa7b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840897764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.840897764
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2613801420
Short name T378
Test name
Test status
Simulation time 587455170 ps
CPU time 3.58 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 221128 kb
Host smart-4aeb1e75-3f3d-4e3a-994c-0b96524cc539
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2613801420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2613801420
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3457526854
Short name T72
Test name
Test status
Simulation time 1159643829 ps
CPU time 1.12 seconds
Started Jul 31 05:01:19 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 235464 kb
Host smart-9c4327b6-9803-4a07-a8da-32a1b182cc77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457526854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3457526854
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1987695290
Short name T134
Test name
Test status
Simulation time 2933353195 ps
CPU time 11.62 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 235608 kb
Host smart-147a269a-e1b2-42c1-8b07-01da4594daf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987695290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1987695290
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1911968323
Short name T831
Test name
Test status
Simulation time 4056997964 ps
CPU time 16.11 seconds
Started Jul 31 05:01:07 PM PDT 24
Finished Jul 31 05:01:23 PM PDT 24
Peak memory 217080 kb
Host smart-1f1524b1-ec80-46f0-bc9d-2158a037549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911968323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1911968323
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2361606733
Short name T914
Test name
Test status
Simulation time 2292020347 ps
CPU time 4.14 seconds
Started Jul 31 05:01:17 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 216876 kb
Host smart-1ff5b516-25f2-4a26-801b-84ec33bf6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361606733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2361606733
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3701048592
Short name T868
Test name
Test status
Simulation time 72092303 ps
CPU time 2.1 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:18 PM PDT 24
Peak memory 216836 kb
Host smart-c142b814-854e-4e50-b355-83a87effbe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701048592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3701048592
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2891292638
Short name T810
Test name
Test status
Simulation time 162558840 ps
CPU time 0.95 seconds
Started Jul 31 05:01:03 PM PDT 24
Finished Jul 31 05:01:04 PM PDT 24
Peak memory 206396 kb
Host smart-f86ced36-434d-4776-a6d6-f642c78cdc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891292638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2891292638
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.310800623
Short name T551
Test name
Test status
Simulation time 902842578 ps
CPU time 4.63 seconds
Started Jul 31 05:01:02 PM PDT 24
Finished Jul 31 05:01:07 PM PDT 24
Peak memory 225212 kb
Host smart-d9749a7a-d6e1-4537-99d2-3b8344c6e344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310800623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.310800623
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4121762930
Short name T864
Test name
Test status
Simulation time 54800203 ps
CPU time 0.69 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:07 PM PDT 24
Peak memory 205728 kb
Host smart-d1b03092-875c-4b6d-b334-aca339ab8db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121762930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4121762930
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1708625920
Short name T570
Test name
Test status
Simulation time 1008117740 ps
CPU time 3.99 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 233276 kb
Host smart-537527e7-748a-4788-9d52-e2cda4fbc2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708625920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1708625920
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1249831955
Short name T529
Test name
Test status
Simulation time 17154098 ps
CPU time 0.75 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 206224 kb
Host smart-e976ae78-83aa-43b9-abd3-82deca528418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249831955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1249831955
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1657791101
Short name T608
Test name
Test status
Simulation time 5925437068 ps
CPU time 55.93 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 262264 kb
Host smart-161c52b3-d7b2-4aa8-81f3-c3f6f59f9909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657791101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1657791101
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4236324568
Short name T880
Test name
Test status
Simulation time 17933714360 ps
CPU time 31.41 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:02:45 PM PDT 24
Peak memory 240188 kb
Host smart-10739a32-9b94-4b76-b742-087693fdff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236324568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4236324568
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.531672188
Short name T836
Test name
Test status
Simulation time 65271797414 ps
CPU time 86.09 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:03:05 PM PDT 24
Peak memory 249844 kb
Host smart-e973db47-f57d-4729-bbc7-d9379e0bf668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531672188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.531672188
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3742743969
Short name T167
Test name
Test status
Simulation time 663041455 ps
CPU time 5.72 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 225244 kb
Host smart-53fa6aac-646b-4b33-8817-e993c81be718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742743969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3742743969
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.21813104
Short name T756
Test name
Test status
Simulation time 11798582 ps
CPU time 0.77 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 216316 kb
Host smart-8a67acf8-5edd-4f79-9c6a-190c48db3c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21813104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.21813104
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1376932916
Short name T281
Test name
Test status
Simulation time 20288599215 ps
CPU time 14.69 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 233488 kb
Host smart-9ccebee8-f4eb-42ba-a60a-321e93244d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376932916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1376932916
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.100908682
Short name T232
Test name
Test status
Simulation time 12263969026 ps
CPU time 86.61 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 233460 kb
Host smart-0ea07a30-89fe-4b89-839d-a983e5c3f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100908682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.100908682
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2960268764
Short name T1015
Test name
Test status
Simulation time 1408287632 ps
CPU time 6.92 seconds
Started Jul 31 05:01:43 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 239692 kb
Host smart-84a03c1b-0ef5-4243-a485-5e42f57122ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960268764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2960268764
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.590531023
Short name T927
Test name
Test status
Simulation time 10778140379 ps
CPU time 10.13 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 225148 kb
Host smart-b2306950-8ae9-4c9b-b71f-608e12a57a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590531023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.590531023
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2469894920
Short name T550
Test name
Test status
Simulation time 188232654 ps
CPU time 3.78 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 220960 kb
Host smart-bfe53398-1508-4438-91e7-b67b56e026a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2469894920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2469894920
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3341851794
Short name T667
Test name
Test status
Simulation time 4930142119 ps
CPU time 36.78 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 225252 kb
Host smart-e44d64f9-16c9-4f08-9f14-3bf22f4570a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341851794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3341851794
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2675480140
Short name T634
Test name
Test status
Simulation time 50988163 ps
CPU time 0.71 seconds
Started Jul 31 05:01:55 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 206172 kb
Host smart-ba01edb2-10d5-43d6-adea-f41cbebe5266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675480140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2675480140
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2852969959
Short name T600
Test name
Test status
Simulation time 145959242 ps
CPU time 0.78 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:11 PM PDT 24
Peak memory 206112 kb
Host smart-7255a930-e73c-40b1-b518-b864961a8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852969959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2852969959
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1675301881
Short name T462
Test name
Test status
Simulation time 339183598 ps
CPU time 1.35 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 208624 kb
Host smart-3ecc4e67-804d-4d61-851d-1989c8d1e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675301881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1675301881
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3487044643
Short name T722
Test name
Test status
Simulation time 190915467 ps
CPU time 0.93 seconds
Started Jul 31 05:02:01 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 207452 kb
Host smart-e3e1874b-6349-46ed-bc24-1c6f025fe613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487044643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3487044643
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2072111455
Short name T473
Test name
Test status
Simulation time 8575030904 ps
CPU time 10.03 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 241616 kb
Host smart-c93c2bd2-432e-42b3-9b46-4c4b2b1daabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072111455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2072111455
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2379591844
Short name T527
Test name
Test status
Simulation time 12665800 ps
CPU time 0.7 seconds
Started Jul 31 05:01:45 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 206088 kb
Host smart-82fe7dea-03cd-4c43-b365-12e5cbfdd217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379591844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2379591844
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1109991768
Short name T282
Test name
Test status
Simulation time 683973427 ps
CPU time 9.45 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 233440 kb
Host smart-6b413f08-b01f-413a-ad5c-32377ae6d32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109991768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1109991768
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.764840643
Short name T679
Test name
Test status
Simulation time 15296970 ps
CPU time 0.81 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 206916 kb
Host smart-aff00f75-b6a9-4164-9a9c-1a3993f3f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764840643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.764840643
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4000868424
Short name T52
Test name
Test status
Simulation time 17159819626 ps
CPU time 146.12 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 241636 kb
Host smart-51b5ecf9-b30c-4170-8cd2-be724661266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000868424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4000868424
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1948140709
Short name T647
Test name
Test status
Simulation time 43461015585 ps
CPU time 33.79 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 218364 kb
Host smart-78bae9dd-f4a9-40a5-8751-f6aa95a90db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948140709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1948140709
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2928625398
Short name T313
Test name
Test status
Simulation time 266417948 ps
CPU time 7.2 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 225044 kb
Host smart-1c295701-1f27-484f-bb93-eaa296240562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928625398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2928625398
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3908647629
Short name T353
Test name
Test status
Simulation time 74169292 ps
CPU time 0.87 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:01 PM PDT 24
Peak memory 216632 kb
Host smart-a504f70f-758b-439a-b382-745baef2f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908647629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3908647629
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1026829993
Short name T686
Test name
Test status
Simulation time 366560226 ps
CPU time 3.2 seconds
Started Jul 31 05:01:38 PM PDT 24
Finished Jul 31 05:01:41 PM PDT 24
Peak memory 225244 kb
Host smart-e986be96-b904-424a-8edf-226c235aead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026829993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1026829993
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2243056314
Short name T265
Test name
Test status
Simulation time 68318209297 ps
CPU time 41.62 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 251804 kb
Host smart-4d1ec0f6-966e-443a-b3d0-8827d5934893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243056314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2243056314
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2913210878
Short name T292
Test name
Test status
Simulation time 1100615950 ps
CPU time 4.78 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:03 PM PDT 24
Peak memory 225068 kb
Host smart-4c9b606c-f155-4619-bf89-1433e67ff53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913210878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2913210878
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1045816637
Short name T255
Test name
Test status
Simulation time 2186606608 ps
CPU time 4.79 seconds
Started Jul 31 05:01:40 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 225224 kb
Host smart-14065f8a-ac70-4c56-b9fb-0756587df350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045816637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1045816637
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3830686298
Short name T812
Test name
Test status
Simulation time 102993381 ps
CPU time 4.34 seconds
Started Jul 31 05:01:53 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 220484 kb
Host smart-9cecacda-b5ba-468f-9ee6-862b8043e4c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830686298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3830686298
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.41399195
Short name T21
Test name
Test status
Simulation time 97123851 ps
CPU time 0.93 seconds
Started Jul 31 05:02:01 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 206336 kb
Host smart-5ab25a47-5f4c-4d9a-a275-85bd4539d273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41399195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.41399195
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.504550474
Short name T619
Test name
Test status
Simulation time 2301711741 ps
CPU time 9.3 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 217212 kb
Host smart-e769a6d5-4c67-4008-9d6f-bc6b3257e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504550474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.504550474
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1791090180
Short name T471
Test name
Test status
Simulation time 16167756028 ps
CPU time 22.52 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 217040 kb
Host smart-a86b27dd-69de-4817-8b25-6d85ceb48e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791090180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1791090180
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1370498005
Short name T765
Test name
Test status
Simulation time 99777468 ps
CPU time 1.38 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:01:44 PM PDT 24
Peak memory 216852 kb
Host smart-e9ed838c-264f-43f2-ac85-4f493fab4432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370498005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1370498005
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.439477734
Short name T465
Test name
Test status
Simulation time 26032027 ps
CPU time 0.82 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 206496 kb
Host smart-02016864-a69a-44b4-9eb2-103a42dc2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439477734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.439477734
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3780125117
Short name T192
Test name
Test status
Simulation time 453756925 ps
CPU time 7.32 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 233420 kb
Host smart-333131a4-f1d4-4434-9655-5c97209ba155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780125117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3780125117
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.99327907
Short name T334
Test name
Test status
Simulation time 148967914 ps
CPU time 0.7 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 205240 kb
Host smart-2ed2d73a-8012-4027-be8c-c448a34ed3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99327907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.99327907
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.274673003
Short name T263
Test name
Test status
Simulation time 229746269 ps
CPU time 4.17 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 225088 kb
Host smart-0d906509-3e95-4c13-89f0-23edba8302ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274673003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.274673003
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3399440764
Short name T344
Test name
Test status
Simulation time 15935610 ps
CPU time 0.88 seconds
Started Jul 31 05:01:47 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 207092 kb
Host smart-a8f92ad7-3a35-4ded-8e70-65881397b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399440764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3399440764
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.416978138
Short name T212
Test name
Test status
Simulation time 7774064778 ps
CPU time 111.11 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:03:51 PM PDT 24
Peak memory 254128 kb
Host smart-54535790-4683-412a-a4d3-b187a26ce03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416978138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.416978138
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1431219945
Short name T700
Test name
Test status
Simulation time 881123245 ps
CPU time 6.53 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 233388 kb
Host smart-66e80c61-bafb-4146-86a2-03dfe186aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431219945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1431219945
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2592036576
Short name T24
Test name
Test status
Simulation time 2095029256 ps
CPU time 19.49 seconds
Started Jul 31 05:01:41 PM PDT 24
Finished Jul 31 05:02:01 PM PDT 24
Peak memory 241484 kb
Host smart-c30c5753-85c9-49df-a936-d6b264e1975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592036576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2592036576
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.961571225
Short name T217
Test name
Test status
Simulation time 3730163849 ps
CPU time 32.33 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:02:32 PM PDT 24
Peak memory 219572 kb
Host smart-13d6ac3b-9d10-47db-bbd4-767912b14369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961571225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.961571225
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.116536260
Short name T423
Test name
Test status
Simulation time 15243965609 ps
CPU time 32.21 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 225332 kb
Host smart-615b89bf-b37c-4c4f-bc59-2cfad6ac6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116536260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.116536260
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.828246830
Short name T12
Test name
Test status
Simulation time 2073867216 ps
CPU time 10.37 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 225108 kb
Host smart-d0e3f877-624d-4252-a0b1-81c834cdf5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828246830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.828246830
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2910693282
Short name T597
Test name
Test status
Simulation time 5278098423 ps
CPU time 14.78 seconds
Started Jul 31 05:01:49 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 233364 kb
Host smart-a9b11fd0-4c3a-4b29-aed7-8a9dc8aae968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910693282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2910693282
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2881950116
Short name T841
Test name
Test status
Simulation time 149315934 ps
CPU time 4.07 seconds
Started Jul 31 05:02:13 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 223092 kb
Host smart-b7ade97f-8a05-4303-8206-6b543e4790d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881950116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2881950116
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3821864261
Short name T546
Test name
Test status
Simulation time 83227732 ps
CPU time 0.99 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 207252 kb
Host smart-f1c65b62-a015-4483-be0c-7315ef429122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821864261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3821864261
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.296003960
Short name T668
Test name
Test status
Simulation time 39051307 ps
CPU time 0.71 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:01:53 PM PDT 24
Peak memory 206020 kb
Host smart-3cf4232b-7d10-40a2-8be8-5812433dc497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296003960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.296003960
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3816046745
Short name T28
Test name
Test status
Simulation time 9701713861 ps
CPU time 9.72 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 216952 kb
Host smart-785771c6-6380-4e29-a097-75546368d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816046745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3816046745
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.902092400
Short name T745
Test name
Test status
Simulation time 685938266 ps
CPU time 1.39 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:01 PM PDT 24
Peak memory 216840 kb
Host smart-d22e739c-79e6-4b64-a158-d186eadcc2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902092400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.902092400
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1437413270
Short name T85
Test name
Test status
Simulation time 74006087 ps
CPU time 0.99 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 207592 kb
Host smart-ac7c8f33-d731-4dc8-a2b5-7c9e8c50a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437413270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1437413270
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1017846875
Short name T162
Test name
Test status
Simulation time 213836268 ps
CPU time 3.31 seconds
Started Jul 31 05:01:48 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 233308 kb
Host smart-dc6d4852-a3e8-4d7e-b834-cb8eb8c3d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017846875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1017846875
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1592529780
Short name T552
Test name
Test status
Simulation time 19010126 ps
CPU time 0.7 seconds
Started Jul 31 05:01:47 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 205856 kb
Host smart-51b71ec0-ccf1-4926-93a4-c3c419c1682e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592529780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1592529780
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4189455147
Short name T916
Test name
Test status
Simulation time 177860971 ps
CPU time 3.98 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 233260 kb
Host smart-8892fe25-21e5-4c44-ab92-0b16171dcf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189455147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4189455147
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1216774700
Short name T788
Test name
Test status
Simulation time 18789783 ps
CPU time 0.82 seconds
Started Jul 31 05:02:13 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 206888 kb
Host smart-2b783557-09c5-4a41-88ab-66cf6d0576b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216774700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1216774700
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.134537479
Short name T584
Test name
Test status
Simulation time 214889896444 ps
CPU time 92.32 seconds
Started Jul 31 05:01:52 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 249892 kb
Host smart-62b08c31-f4f2-46c8-9dc3-7102099dc611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134537479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.134537479
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.242312415
Short name T65
Test name
Test status
Simulation time 111272213047 ps
CPU time 313.23 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:07:21 PM PDT 24
Peak memory 271180 kb
Host smart-531a8524-e32a-455c-ab5e-078933f08c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242312415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.242312415
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2757153110
Short name T293
Test name
Test status
Simulation time 91673871513 ps
CPU time 739.83 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 272664 kb
Host smart-7bdffeed-481a-45f6-bb30-67abb5c2c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757153110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2757153110
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1619409642
Short name T431
Test name
Test status
Simulation time 1368793162 ps
CPU time 21.65 seconds
Started Jul 31 05:01:56 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 233472 kb
Host smart-d32e8ede-afc9-4db1-a83e-9232b18590c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619409642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1619409642
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1758365680
Short name T1017
Test name
Test status
Simulation time 28344118375 ps
CPU time 182.78 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:05:17 PM PDT 24
Peak memory 257508 kb
Host smart-d31021fe-f5c7-4ab7-8c8a-a5f3996e4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758365680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1758365680
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1403631481
Short name T248
Test name
Test status
Simulation time 13148422111 ps
CPU time 24.35 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 233336 kb
Host smart-fea2751e-df7a-44b9-846f-4b5479d352d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403631481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1403631481
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1671901354
Short name T920
Test name
Test status
Simulation time 404417459 ps
CPU time 6.73 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 233412 kb
Host smart-765d2155-000c-41c2-9fb6-3c89eb7d9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671901354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1671901354
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.455666063
Short name T762
Test name
Test status
Simulation time 1085733306 ps
CPU time 4.8 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:10 PM PDT 24
Peak memory 225096 kb
Host smart-e604b79f-2de2-4ffd-8e8a-056ad96e75f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455666063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.455666063
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1175098356
Short name T499
Test name
Test status
Simulation time 2453201587 ps
CPU time 8.3 seconds
Started Jul 31 05:02:02 PM PDT 24
Finished Jul 31 05:02:11 PM PDT 24
Peak memory 225320 kb
Host smart-d2a61d51-35ba-4835-a6d2-e648638fd58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175098356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1175098356
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.942225995
Short name T749
Test name
Test status
Simulation time 827630646 ps
CPU time 5.3 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 220504 kb
Host smart-2ea7a3eb-5db9-4979-bf9a-236e266903e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942225995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.942225995
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2675136436
Short name T172
Test name
Test status
Simulation time 3257515167 ps
CPU time 24.54 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:43 PM PDT 24
Peak memory 218472 kb
Host smart-a544d43a-bc21-4348-98aa-fb5100fdced0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675136436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2675136436
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1116206534
Short name T605
Test name
Test status
Simulation time 22067225911 ps
CPU time 35.99 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 217044 kb
Host smart-4a77f6ca-6270-4e7d-beb4-d9d3990e7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116206534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1116206534
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3270240116
Short name T392
Test name
Test status
Simulation time 17610695018 ps
CPU time 16.59 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 216912 kb
Host smart-93416cb4-5c86-4c6c-9a6d-294b0b08fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270240116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3270240116
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3808218610
Short name T795
Test name
Test status
Simulation time 11452226 ps
CPU time 0.69 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 205896 kb
Host smart-2c9f2587-2bc8-4fd4-a567-dfa8fe912bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808218610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3808218610
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2690635107
Short name T1010
Test name
Test status
Simulation time 57208030 ps
CPU time 0.84 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 206440 kb
Host smart-668e2b0a-28f5-4d7e-b641-afcfb7fea5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690635107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2690635107
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1599645452
Short name T286
Test name
Test status
Simulation time 1556391157 ps
CPU time 7.8 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 225188 kb
Host smart-3db013f6-26eb-4fa4-a986-a9a2707f32a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599645452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1599645452
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2259722387
Short name T976
Test name
Test status
Simulation time 10872064 ps
CPU time 0.73 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 205784 kb
Host smart-f5f4c519-96e2-4efc-a190-5371b8018459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259722387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2259722387
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.538214557
Short name T649
Test name
Test status
Simulation time 204686419 ps
CPU time 3.03 seconds
Started Jul 31 05:01:54 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 233420 kb
Host smart-3b53e552-9f66-435a-8c24-0690bcebae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538214557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.538214557
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3053187580
Short name T662
Test name
Test status
Simulation time 73052764 ps
CPU time 0.77 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:32 PM PDT 24
Peak memory 206972 kb
Host smart-60a5b35c-7f10-42fc-961d-13a376542c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053187580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3053187580
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3105482184
Short name T921
Test name
Test status
Simulation time 15590044378 ps
CPU time 133.7 seconds
Started Jul 31 05:02:07 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 257980 kb
Host smart-0f944bed-b10a-4b2b-b416-aea92f1006c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105482184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3105482184
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2227120079
Short name T8
Test name
Test status
Simulation time 20125838592 ps
CPU time 115.32 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 256596 kb
Host smart-e1d774e2-550f-4936-a761-b6ca43a9d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227120079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2227120079
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1228534191
Short name T254
Test name
Test status
Simulation time 275844206484 ps
CPU time 234.21 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:05:58 PM PDT 24
Peak memory 255316 kb
Host smart-c2bdf0ed-8b33-4ed7-8b05-04f6c37e1e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228534191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1228534191
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2968832715
Short name T149
Test name
Test status
Simulation time 408948277 ps
CPU time 12.32 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 233320 kb
Host smart-4040a2a2-d696-4018-845a-53f78d58d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968832715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2968832715
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1293604956
Short name T851
Test name
Test status
Simulation time 2561742874 ps
CPU time 41.51 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:03:01 PM PDT 24
Peak memory 255712 kb
Host smart-08a62229-56e4-4784-9da1-2428b701682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293604956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1293604956
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3590614545
Short name T251
Test name
Test status
Simulation time 260746538 ps
CPU time 3.29 seconds
Started Jul 31 05:02:00 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 233324 kb
Host smart-9da49a82-c584-452e-bdaf-9e3327202041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590614545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3590614545
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.246355438
Short name T858
Test name
Test status
Simulation time 134655737 ps
CPU time 2.5 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:01:44 PM PDT 24
Peak memory 233412 kb
Host smart-8b235c45-89f1-4dfe-8e7f-21024ac7ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246355438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.246355438
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.124910511
Short name T496
Test name
Test status
Simulation time 1901738452 ps
CPU time 10.02 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 233480 kb
Host smart-180ab013-153d-4515-b498-46b8ab71c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124910511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.124910511
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3505249393
Short name T808
Test name
Test status
Simulation time 34625342 ps
CPU time 2.48 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 233392 kb
Host smart-f5a5d9c1-79b3-49a8-a087-1fe0f122baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505249393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3505249393
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2297296200
Short name T684
Test name
Test status
Simulation time 1078530826 ps
CPU time 5.44 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 219340 kb
Host smart-c741a2fd-e352-44de-9e3a-c38ac5119888
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297296200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2297296200
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.113436917
Short name T838
Test name
Test status
Simulation time 377363709 ps
CPU time 1.06 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:06 PM PDT 24
Peak memory 208288 kb
Host smart-7b5f6c05-ecd8-412b-a823-3e5336f9141c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113436917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.113436917
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2392664375
Short name T322
Test name
Test status
Simulation time 30612412775 ps
CPU time 36.84 seconds
Started Jul 31 05:01:56 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 216880 kb
Host smart-b529c57e-7fed-4b37-b608-3533ecfe9cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392664375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2392664375
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3737988687
Short name T349
Test name
Test status
Simulation time 1485214954 ps
CPU time 8.09 seconds
Started Jul 31 05:01:56 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 217020 kb
Host smart-baee44c5-7d45-4799-9b92-a2e439d3f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737988687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3737988687
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.105594802
Short name T445
Test name
Test status
Simulation time 42918875 ps
CPU time 1.3 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 208640 kb
Host smart-741eea19-320f-4b05-b059-11eb61cbd3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105594802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.105594802
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2272617259
Short name T903
Test name
Test status
Simulation time 54826068 ps
CPU time 0.85 seconds
Started Jul 31 05:01:54 PM PDT 24
Finished Jul 31 05:01:55 PM PDT 24
Peak memory 206572 kb
Host smart-ddd23bcb-25ca-4d88-8116-0e9c505d0613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272617259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2272617259
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1281591735
Short name T460
Test name
Test status
Simulation time 126715643997 ps
CPU time 25.33 seconds
Started Jul 31 05:02:01 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 225476 kb
Host smart-c566a1ab-2b5e-4197-8331-84ca88ce61b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281591735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1281591735
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3842895395
Short name T974
Test name
Test status
Simulation time 11719948 ps
CPU time 0.74 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 205168 kb
Host smart-e6d0ffed-57fa-4e50-966a-01812aca92cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842895395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3842895395
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.186322334
Short name T474
Test name
Test status
Simulation time 33006959 ps
CPU time 2 seconds
Started Jul 31 05:01:59 PM PDT 24
Finished Jul 31 05:02:02 PM PDT 24
Peak memory 225048 kb
Host smart-65c395d7-aec0-43db-ab6d-59f5a5af5519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186322334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.186322334
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.50100517
Short name T798
Test name
Test status
Simulation time 46050692 ps
CPU time 0.75 seconds
Started Jul 31 05:01:57 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 206352 kb
Host smart-260b229c-a116-420a-82cc-819ee5f59ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50100517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.50100517
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3348452486
Short name T872
Test name
Test status
Simulation time 2077853951 ps
CPU time 22 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 249792 kb
Host smart-1544dd19-bab2-434c-9227-fc182b5d9333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348452486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3348452486
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2256085841
Short name T375
Test name
Test status
Simulation time 2015999266 ps
CPU time 11.35 seconds
Started Jul 31 05:02:01 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 225288 kb
Host smart-772a9759-96ae-4a5e-9c31-0664d2e004d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256085841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2256085841
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1118956287
Short name T1019
Test name
Test status
Simulation time 5960605190 ps
CPU time 61.3 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 249884 kb
Host smart-25b78150-09d7-4434-805e-7ff8f1951a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118956287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1118956287
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1265572266
Short name T826
Test name
Test status
Simulation time 185252882 ps
CPU time 5.18 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 230200 kb
Host smart-ce0a12da-7e81-4cdd-b612-7a93300a7422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265572266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1265572266
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.587196584
Short name T508
Test name
Test status
Simulation time 691713798 ps
CPU time 8.96 seconds
Started Jul 31 05:02:05 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 237996 kb
Host smart-222d2503-cbdf-40bf-8506-181e9e449da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587196584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.587196584
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3643921750
Short name T562
Test name
Test status
Simulation time 5708809700 ps
CPU time 7.66 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 233372 kb
Host smart-cb9d5859-013f-4335-a414-ada1f5db7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643921750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3643921750
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1592648526
Short name T96
Test name
Test status
Simulation time 7071237760 ps
CPU time 11.14 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 233392 kb
Host smart-a7270ae1-5f0c-40bb-bdf2-a400322f356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592648526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1592648526
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1730039910
Short name T782
Test name
Test status
Simulation time 12741298191 ps
CPU time 15.22 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 223732 kb
Host smart-2a0d5dee-41dd-4d28-bd09-da8af6c286f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1730039910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1730039910
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3602855667
Short name T680
Test name
Test status
Simulation time 89846149412 ps
CPU time 471.06 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:10:01 PM PDT 24
Peak memory 264516 kb
Host smart-f02e38ab-4bd3-4db9-8d6b-78bd5fd9300d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602855667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3602855667
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.219875444
Short name T387
Test name
Test status
Simulation time 433260403 ps
CPU time 2.02 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 217080 kb
Host smart-77dfbc6c-7d51-450d-adf1-8e13339a036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219875444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.219875444
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2524724901
Short name T504
Test name
Test status
Simulation time 471518495 ps
CPU time 3.52 seconds
Started Jul 31 05:02:01 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 216860 kb
Host smart-f72f714c-4969-4fab-913c-6ad36c4d0c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524724901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2524724901
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3685253176
Short name T792
Test name
Test status
Simulation time 213004115 ps
CPU time 1.91 seconds
Started Jul 31 05:02:07 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 216816 kb
Host smart-ff6c648d-5dde-41e3-ab2f-0c439f231e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685253176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3685253176
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.816700076
Short name T490
Test name
Test status
Simulation time 54357197 ps
CPU time 0.72 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:02:09 PM PDT 24
Peak memory 206380 kb
Host smart-dc1db8be-33b2-44ec-978f-870859f6b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816700076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.816700076
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2851098243
Short name T274
Test name
Test status
Simulation time 122730320 ps
CPU time 2.19 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 225088 kb
Host smart-5447a924-1263-484e-8c10-e52a21c1074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851098243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2851098243
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3218717329
Short name T983
Test name
Test status
Simulation time 18859452 ps
CPU time 0.73 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:17 PM PDT 24
Peak memory 205764 kb
Host smart-6339c7f0-25ef-4122-928a-96dbd27e6638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218717329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3218717329
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.268516976
Short name T961
Test name
Test status
Simulation time 487290940 ps
CPU time 6.95 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 233364 kb
Host smart-e06870f7-355b-4d6f-8947-73b9a7e92d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268516976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.268516976
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2932732576
Short name T931
Test name
Test status
Simulation time 16663219 ps
CPU time 0.79 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 206984 kb
Host smart-a59a6a43-7a9f-48db-b4bc-6c29fd671fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932732576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2932732576
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1239992070
Short name T815
Test name
Test status
Simulation time 2291205307 ps
CPU time 27.93 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 241028 kb
Host smart-05516f5f-af97-4ff0-a594-92f26a2d50f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239992070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1239992070
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1700016974
Short name T298
Test name
Test status
Simulation time 12721935982 ps
CPU time 73 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 256700 kb
Host smart-ea60ae59-2013-4214-899c-298b9309baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700016974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1700016974
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2264141084
Short name T165
Test name
Test status
Simulation time 1914656277 ps
CPU time 57.84 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 266060 kb
Host smart-f7b492cc-1822-4343-95fd-682c14cfb867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264141084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2264141084
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2848863991
Short name T583
Test name
Test status
Simulation time 1977259607 ps
CPU time 24.68 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 233420 kb
Host smart-e35658f1-9575-4ddc-b9ff-55d210243757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848863991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2848863991
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1149727731
Short name T839
Test name
Test status
Simulation time 9222307729 ps
CPU time 65.24 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 254108 kb
Host smart-60f54c7b-ecb7-42ce-a5f2-0c0451926128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149727731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1149727731
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4150574809
Short name T2
Test name
Test status
Simulation time 679085298 ps
CPU time 8.38 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 225220 kb
Host smart-e009a73a-98ee-44bd-8d9b-e1cc4b89713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150574809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4150574809
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.815391656
Short name T454
Test name
Test status
Simulation time 21756635332 ps
CPU time 84.08 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:03:32 PM PDT 24
Peak memory 249720 kb
Host smart-10ab961c-bdc0-4300-bbe5-9965f032f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815391656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.815391656
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3462456729
Short name T424
Test name
Test status
Simulation time 812719411 ps
CPU time 3.3 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 233304 kb
Host smart-3b3cecf0-daca-4962-86f2-439fdc408acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462456729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3462456729
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1127101065
Short name T913
Test name
Test status
Simulation time 3384808447 ps
CPU time 4.55 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 225208 kb
Host smart-60f0a1e4-0d12-47fd-b75c-69dfc350a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127101065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1127101065
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2688287346
Short name T738
Test name
Test status
Simulation time 145231276 ps
CPU time 4.69 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 222612 kb
Host smart-d4033031-5f3b-4e2e-b57b-84c557eefe1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2688287346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2688287346
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.372146713
Short name T278
Test name
Test status
Simulation time 117896429690 ps
CPU time 273.43 seconds
Started Jul 31 05:02:09 PM PDT 24
Finished Jul 31 05:06:42 PM PDT 24
Peak memory 249896 kb
Host smart-45819bd3-eb86-4a02-846c-95842ba86575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372146713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.372146713
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.434944626
Short name T579
Test name
Test status
Simulation time 11565112343 ps
CPU time 14.05 seconds
Started Jul 31 05:02:28 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 216952 kb
Host smart-9d179440-f91b-4dc4-80b3-0f7c7bd4d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434944626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.434944626
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3066051764
Short name T386
Test name
Test status
Simulation time 4576278495 ps
CPU time 8.5 seconds
Started Jul 31 05:02:07 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 216916 kb
Host smart-6a4dd5c4-7f85-4e09-b7c6-9256e5a5e7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066051764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3066051764
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.10378282
Short name T521
Test name
Test status
Simulation time 81836035 ps
CPU time 2.75 seconds
Started Jul 31 05:01:58 PM PDT 24
Finished Jul 31 05:02:01 PM PDT 24
Peak memory 216844 kb
Host smart-406d8ca5-d3e4-47d7-9e98-92e730194a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10378282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.10378282
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3672231255
Short name T408
Test name
Test status
Simulation time 12038729 ps
CPU time 0.69 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 205996 kb
Host smart-1ab1832d-d677-4424-bc75-e51254c69b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672231255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3672231255
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3539117923
Short name T820
Test name
Test status
Simulation time 3100290555 ps
CPU time 12.01 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 233732 kb
Host smart-870d7963-82bf-4d89-a079-57caba240451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539117923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3539117923
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2782958638
Short name T170
Test name
Test status
Simulation time 51119736 ps
CPU time 0.72 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 205684 kb
Host smart-ad7a1aca-6fdd-46cf-9663-831e443d163a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782958638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2782958638
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.703854426
Short name T261
Test name
Test status
Simulation time 1909454704 ps
CPU time 16.66 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 233364 kb
Host smart-82fd8a56-b5ce-498c-9038-a15b94fa0897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703854426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.703854426
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1604796864
Short name T848
Test name
Test status
Simulation time 19681183 ps
CPU time 0.79 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:04 PM PDT 24
Peak memory 207284 kb
Host smart-3baa438c-0f0b-4463-b4ac-14f8a60d9076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604796864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1604796864
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4130498526
Short name T295
Test name
Test status
Simulation time 6503805125 ps
CPU time 83.6 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 267072 kb
Host smart-32079bd7-7b22-4d99-89df-0834abd62ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130498526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4130498526
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.751683613
Short name T290
Test name
Test status
Simulation time 12299179588 ps
CPU time 77.88 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 250872 kb
Host smart-52fb27a7-7869-411b-bb1d-bd186241698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751683613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.751683613
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.859758944
Short name T541
Test name
Test status
Simulation time 42788333215 ps
CPU time 374.59 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:08:21 PM PDT 24
Peak memory 258088 kb
Host smart-0184e4a9-8afe-4279-aa32-aa83d5ac2bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859758944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.859758944
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3040823411
Short name T526
Test name
Test status
Simulation time 76877927 ps
CPU time 2.35 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 225116 kb
Host smart-88239626-9711-4a42-ba99-552f16d3ed9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040823411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3040823411
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1781346105
Short name T48
Test name
Test status
Simulation time 6612681361 ps
CPU time 47.52 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 250892 kb
Host smart-ed6ee50a-e3fd-4969-8b7c-fd76b17bf37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781346105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1781346105
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3608271272
Short name T578
Test name
Test status
Simulation time 572107365 ps
CPU time 3.21 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:21 PM PDT 24
Peak memory 225076 kb
Host smart-40803896-2186-4bc1-86d6-1a844e90fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608271272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3608271272
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2016949677
Short name T461
Test name
Test status
Simulation time 1061507994 ps
CPU time 5.5 seconds
Started Jul 31 05:02:03 PM PDT 24
Finished Jul 31 05:02:08 PM PDT 24
Peak memory 225076 kb
Host smart-b0a9cc20-de29-40b6-97d8-a3622d483552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016949677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2016949677
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3193906231
Short name T1014
Test name
Test status
Simulation time 171665861 ps
CPU time 2.4 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 232896 kb
Host smart-beaa6ce4-5dc4-4ac0-8ce3-544193e308d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193906231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3193906231
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3186631308
Short name T276
Test name
Test status
Simulation time 4791723525 ps
CPU time 14.8 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 234660 kb
Host smart-7e29144d-7faa-4e7f-aee4-92ceda300ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186631308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3186631308
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2334091372
Short name T37
Test name
Test status
Simulation time 200544144 ps
CPU time 4.56 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 223372 kb
Host smart-9a6f0937-0fd6-447a-b3c5-636314fa6b32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2334091372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2334091372
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1921167775
Short name T844
Test name
Test status
Simulation time 1469789980 ps
CPU time 9.51 seconds
Started Jul 31 05:02:06 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 216836 kb
Host smart-d7d0d56a-9cb7-48fd-91cb-3fac9a27b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921167775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1921167775
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3688110699
Short name T84
Test name
Test status
Simulation time 1412897039 ps
CPU time 1.6 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 207576 kb
Host smart-2196843c-656b-40a9-b6d9-7a2f3deee929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688110699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3688110699
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2789658887
Short name T805
Test name
Test status
Simulation time 24346519 ps
CPU time 1.02 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:02:05 PM PDT 24
Peak memory 207656 kb
Host smart-be1214d8-3875-4781-a620-408144ff0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789658887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2789658887
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.597113194
Short name T32
Test name
Test status
Simulation time 37030192 ps
CPU time 0.91 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:27 PM PDT 24
Peak memory 206520 kb
Host smart-9f464aa4-c233-46ff-a8ff-7400970e2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597113194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.597113194
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1358014098
Short name T530
Test name
Test status
Simulation time 2434925242 ps
CPU time 20.9 seconds
Started Jul 31 05:02:08 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 249456 kb
Host smart-16065757-36b0-4437-96a5-79b695af3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358014098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1358014098
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1342983189
Short name T472
Test name
Test status
Simulation time 97670025 ps
CPU time 0.72 seconds
Started Jul 31 05:02:02 PM PDT 24
Finished Jul 31 05:02:03 PM PDT 24
Peak memory 206140 kb
Host smart-b36b4e4c-3907-4282-a132-7468d4a0d142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342983189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1342983189
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.29937356
Short name T950
Test name
Test status
Simulation time 117691709 ps
CPU time 3.58 seconds
Started Jul 31 05:02:10 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 225164 kb
Host smart-6bed07cd-0787-4950-9edd-9893fe450ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29937356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.29937356
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4273154205
Short name T468
Test name
Test status
Simulation time 38891857 ps
CPU time 0.78 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 206776 kb
Host smart-87cc5c71-12ab-470a-906c-f5d4de391591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273154205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4273154205
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3649173396
Short name T297
Test name
Test status
Simulation time 22578890231 ps
CPU time 194.84 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:05:31 PM PDT 24
Peak memory 265360 kb
Host smart-77d17e19-d5df-4deb-bb3c-9ff5a9213ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649173396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3649173396
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1136051326
Short name T426
Test name
Test status
Simulation time 5717692625 ps
CPU time 37.94 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 241672 kb
Host smart-27391ff7-4a8c-426a-b3f1-31c2500dd4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136051326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1136051326
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.979754460
Short name T512
Test name
Test status
Simulation time 1702327298 ps
CPU time 23.12 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:43 PM PDT 24
Peak memory 251108 kb
Host smart-df11eccb-3449-4b65-b62f-481e7cdb572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979754460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.979754460
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.450962951
Short name T794
Test name
Test status
Simulation time 4943296905 ps
CPU time 15.02 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 233412 kb
Host smart-ac63b30a-28f6-4102-98e4-8064cfef07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450962951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.450962951
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1144459592
Short name T842
Test name
Test status
Simulation time 525837283 ps
CPU time 6.05 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 233280 kb
Host smart-ba0e64e6-c662-4d4e-9955-db89a3e7e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144459592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1144459592
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3794921495
Short name T389
Test name
Test status
Simulation time 93464001 ps
CPU time 2.13 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 224568 kb
Host smart-872f1868-7989-4e84-a640-c8ddc197dac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794921495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3794921495
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1144204621
Short name T285
Test name
Test status
Simulation time 797557423 ps
CPU time 4.79 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 233464 kb
Host smart-a19d9c8d-5c37-4e89-b984-b85c3691dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144204621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1144204621
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2352085151
Short name T905
Test name
Test status
Simulation time 19143027018 ps
CPU time 13.19 seconds
Started Jul 31 05:02:02 PM PDT 24
Finished Jul 31 05:02:15 PM PDT 24
Peak memory 223736 kb
Host smart-57219a1d-1682-453d-a968-a3ca113b9b27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352085151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2352085151
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2618450651
Short name T57
Test name
Test status
Simulation time 50080039908 ps
CPU time 29.59 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 225216 kb
Host smart-7f70f996-46d6-478b-95ef-8aa173fef5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618450651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2618450651
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2862188565
Short name T31
Test name
Test status
Simulation time 2651095512 ps
CPU time 15.58 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:36 PM PDT 24
Peak memory 217060 kb
Host smart-47011103-cb73-442c-b5c8-a24966c66ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862188565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2862188565
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2410392184
Short name T503
Test name
Test status
Simulation time 5296151224 ps
CPU time 13.34 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 216904 kb
Host smart-c8e258ff-7ffc-42c8-8862-205e15458722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410392184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2410392184
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.663509584
Short name T802
Test name
Test status
Simulation time 38010108 ps
CPU time 1.15 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 208560 kb
Host smart-e42798db-3ce4-480c-91a3-2e45cec0b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663509584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.663509584
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1388829392
Short name T477
Test name
Test status
Simulation time 11850619 ps
CPU time 0.73 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:21 PM PDT 24
Peak memory 206128 kb
Host smart-7ebd8d45-16a5-4836-a01b-bfe85e10e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388829392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1388829392
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1261316311
Short name T62
Test name
Test status
Simulation time 664579533 ps
CPU time 6.58 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 241364 kb
Host smart-c8ad15a9-94f3-40dc-b58a-c93e1104ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261316311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1261316311
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.481803181
Short name T23
Test name
Test status
Simulation time 12034352 ps
CPU time 0.67 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 205204 kb
Host smart-5c0dde19-0292-4758-8d24-a84bf6952e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481803181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.481803181
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2055938698
Short name T242
Test name
Test status
Simulation time 217336615 ps
CPU time 2.54 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 225184 kb
Host smart-b5dadf96-75a0-4709-832b-ededb3c0bcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055938698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2055938698
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1946979104
Short name T136
Test name
Test status
Simulation time 15675718 ps
CPU time 0.83 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 206892 kb
Host smart-ef467db9-cde6-4c5e-9153-1b4c608a5248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946979104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1946979104
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2971037797
Short name T766
Test name
Test status
Simulation time 66608016 ps
CPU time 0.78 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 216336 kb
Host smart-6e8a0ef2-f807-427b-974f-89155f693eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971037797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2971037797
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2527439968
Short name T561
Test name
Test status
Simulation time 49354410373 ps
CPU time 127.12 seconds
Started Jul 31 05:02:14 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 268988 kb
Host smart-fba58e9d-1d65-43cd-b2e8-0e2c0cec81b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527439968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2527439968
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2173960962
Short name T601
Test name
Test status
Simulation time 4435547506 ps
CPU time 29.94 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 240768 kb
Host smart-1e69355b-ad3f-4db1-9995-97e216702df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173960962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2173960962
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3097648536
Short name T677
Test name
Test status
Simulation time 1838805415 ps
CPU time 5.49 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 225116 kb
Host smart-9933cedb-dd70-4e80-a4c5-b2f131a12541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097648536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3097648536
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3830249980
Short name T832
Test name
Test status
Simulation time 29952069598 ps
CPU time 214.46 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:05:57 PM PDT 24
Peak memory 249948 kb
Host smart-545721ab-da92-4277-a082-46785d95e6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830249980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3830249980
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1873281817
Short name T717
Test name
Test status
Simulation time 30522284 ps
CPU time 1.88 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 224748 kb
Host smart-89c9e690-064f-4119-a0c0-c3b7d33509a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873281817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1873281817
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1262749782
Short name T706
Test name
Test status
Simulation time 429831541 ps
CPU time 10.03 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 240912 kb
Host smart-2a475327-988b-4d67-b375-126fffd2b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262749782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1262749782
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.648118846
Short name T272
Test name
Test status
Simulation time 6173120733 ps
CPU time 15.81 seconds
Started Jul 31 05:02:07 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 225196 kb
Host smart-05f6a8f7-af96-48b1-968d-1df24cc70b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648118846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.648118846
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3351916990
Short name T260
Test name
Test status
Simulation time 8090494519 ps
CPU time 12.35 seconds
Started Jul 31 05:02:04 PM PDT 24
Finished Jul 31 05:02:16 PM PDT 24
Peak memory 233516 kb
Host smart-eef53c3d-f279-468e-a2b2-d0cd05b6fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351916990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3351916990
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.226647147
Short name T354
Test name
Test status
Simulation time 3937681760 ps
CPU time 14.85 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 221180 kb
Host smart-9d300d65-88c7-48c8-a535-9072b16421d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226647147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.226647147
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2869914214
Short name T236
Test name
Test status
Simulation time 4502861039 ps
CPU time 88.59 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:03:49 PM PDT 24
Peak memory 258012 kb
Host smart-d484f01c-8265-4a5f-9fc2-d360c53e0f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869914214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2869914214
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3005509005
Short name T682
Test name
Test status
Simulation time 670787866 ps
CPU time 11.16 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 217160 kb
Host smart-72cd4512-7d32-44f5-a99d-1c017e8b44c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005509005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3005509005
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2542716637
Short name T580
Test name
Test status
Simulation time 756876382 ps
CPU time 6.16 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 216820 kb
Host smart-db5ffe00-fbab-4259-825f-a78916d48cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542716637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2542716637
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.633634448
Short name T816
Test name
Test status
Simulation time 141535060 ps
CPU time 5.28 seconds
Started Jul 31 05:02:07 PM PDT 24
Finished Jul 31 05:02:13 PM PDT 24
Peak memory 216756 kb
Host smart-e53cd830-a43f-41bd-8f46-17ef46ac74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633634448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.633634448
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2016841065
Short name T643
Test name
Test status
Simulation time 139057153 ps
CPU time 0.78 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 206432 kb
Host smart-004359e7-3959-40c7-9af7-4710369375a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016841065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2016841065
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2390787645
Short name T455
Test name
Test status
Simulation time 392430369 ps
CPU time 6.19 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 233284 kb
Host smart-a9f10ff1-4196-4290-8b58-19d278c62a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390787645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2390787645
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3585837514
Short name T498
Test name
Test status
Simulation time 11269348 ps
CPU time 0.7 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 205100 kb
Host smart-6c0cff14-d930-4b74-8271-de9c102c18a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585837514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
585837514
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4079168184
Short name T734
Test name
Test status
Simulation time 204424200 ps
CPU time 3.2 seconds
Started Jul 31 05:05:29 PM PDT 24
Finished Jul 31 05:05:32 PM PDT 24
Peak memory 233428 kb
Host smart-048a6748-0568-4087-8cd4-4a43a02a2ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079168184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4079168184
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3253949158
Short name T443
Test name
Test status
Simulation time 40563963 ps
CPU time 0.76 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:23 PM PDT 24
Peak memory 207316 kb
Host smart-9ad3141e-5a04-4488-b942-740b8b6e4150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253949158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3253949158
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2513810417
Short name T201
Test name
Test status
Simulation time 1696696754 ps
CPU time 41.58 seconds
Started Jul 31 05:01:17 PM PDT 24
Finished Jul 31 05:01:58 PM PDT 24
Peak memory 255992 kb
Host smart-49aac3c4-954c-409c-ae3e-bd9957ff0c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513810417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2513810417
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.357788670
Short name T495
Test name
Test status
Simulation time 6200721704 ps
CPU time 28.51 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:53 PM PDT 24
Peak memory 218132 kb
Host smart-a8f5faed-486f-4ce2-a937-a26577f2edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357788670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.357788670
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1220700426
Short name T1005
Test name
Test status
Simulation time 14571503298 ps
CPU time 77.3 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 249828 kb
Host smart-98a6b07d-bf20-4569-bf5a-b025cd08f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220700426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1220700426
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.537487118
Short name T168
Test name
Test status
Simulation time 965876548 ps
CPU time 11.7 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 234424 kb
Host smart-8c28baf3-2b5c-443f-9995-578abb0ac219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537487118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.537487118
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1226509642
Short name T303
Test name
Test status
Simulation time 13888586984 ps
CPU time 92.37 seconds
Started Jul 31 05:00:53 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 249768 kb
Host smart-5962d33d-308c-48b5-bac0-7e5e66c4757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226509642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1226509642
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.609165267
Short name T205
Test name
Test status
Simulation time 4532487387 ps
CPU time 12.09 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 233396 kb
Host smart-bc28937f-0439-4184-a6a4-9662454eb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609165267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.609165267
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2267662301
Short name T992
Test name
Test status
Simulation time 28631870 ps
CPU time 2.09 seconds
Started Jul 31 05:01:06 PM PDT 24
Finished Jul 31 05:01:08 PM PDT 24
Peak memory 223616 kb
Host smart-c52c79a6-a671-4465-80ea-9db292229ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267662301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2267662301
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2201837208
Short name T694
Test name
Test status
Simulation time 27445477 ps
CPU time 1.05 seconds
Started Jul 31 05:01:14 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 218352 kb
Host smart-e38b4747-7644-4085-9552-5c399edf7460
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201837208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2201837208
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.60507730
Short name T884
Test name
Test status
Simulation time 66092376 ps
CPU time 2.55 seconds
Started Jul 31 05:01:07 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 233016 kb
Host smart-a0009a18-144a-4870-839d-89451880828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60507730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.60507730
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1236942571
Short name T859
Test name
Test status
Simulation time 445915553 ps
CPU time 4.93 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:18 PM PDT 24
Peak memory 233288 kb
Host smart-c7a6f3bb-36bd-4901-aa45-e4cb9cddcfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236942571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1236942571
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3561273059
Short name T412
Test name
Test status
Simulation time 4090582312 ps
CPU time 14.67 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 223620 kb
Host smart-82b9519f-668c-4f43-abbd-54ed307c625c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561273059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3561273059
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.830964611
Short name T71
Test name
Test status
Simulation time 709812550 ps
CPU time 1.19 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 235476 kb
Host smart-d69ab829-b73a-4bfa-b10f-864068b6877e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830964611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.830964611
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1466731880
Short name T17
Test name
Test status
Simulation time 3040848727 ps
CPU time 23.05 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 218324 kb
Host smart-41cd06a6-1761-4271-9836-8ec1576618f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466731880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1466731880
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4003435212
Short name T446
Test name
Test status
Simulation time 9276405432 ps
CPU time 29.76 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:35 PM PDT 24
Peak memory 217020 kb
Host smart-b15c8f74-3650-45f8-8159-12b10b5c1893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003435212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4003435212
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.403122320
Short name T357
Test name
Test status
Simulation time 19620765 ps
CPU time 0.68 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 206040 kb
Host smart-f5d90afd-dacf-4944-a23e-01b9f355cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403122320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.403122320
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2302810468
Short name T796
Test name
Test status
Simulation time 152258279 ps
CPU time 1.21 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:10 PM PDT 24
Peak memory 208184 kb
Host smart-85042bd6-40a2-434c-90a0-c81155a30264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302810468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2302810468
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3462705554
Short name T978
Test name
Test status
Simulation time 272526424 ps
CPU time 1.02 seconds
Started Jul 31 05:01:02 PM PDT 24
Finished Jul 31 05:01:03 PM PDT 24
Peak memory 206560 kb
Host smart-1ab79a2e-b972-4e9d-a205-5d0a64636930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462705554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3462705554
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1012183458
Short name T235
Test name
Test status
Simulation time 140352767 ps
CPU time 3 seconds
Started Jul 31 05:01:18 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 225140 kb
Host smart-2e6a1eab-2e43-4273-89eb-7df667563afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012183458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1012183458
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3284608063
Short name T933
Test name
Test status
Simulation time 14860276 ps
CPU time 0.7 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 205876 kb
Host smart-929401f1-e86c-440a-8dc7-07c7b215bfd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284608063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3284608063
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.428048498
Short name T1012
Test name
Test status
Simulation time 166398034 ps
CPU time 2.85 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 225148 kb
Host smart-4da22c22-543b-42cc-87d8-f85a8c1580cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428048498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.428048498
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.825355711
Short name T341
Test name
Test status
Simulation time 17655290 ps
CPU time 0.75 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 205876 kb
Host smart-8b166f38-2710-45e5-93da-646862f79b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825355711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.825355711
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3839461077
Short name T233
Test name
Test status
Simulation time 5057566449 ps
CPU time 34.04 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 221904 kb
Host smart-bfb26b2b-a7f9-47cd-8b41-9598ef4c33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839461077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3839461077
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1384768933
Short name T319
Test name
Test status
Simulation time 8875985405 ps
CPU time 23.41 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 218248 kb
Host smart-05f558a2-85d7-47f0-a062-3e96d041b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384768933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1384768933
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1936207811
Short name T987
Test name
Test status
Simulation time 32083159589 ps
CPU time 325.37 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:07:45 PM PDT 24
Peak memory 258000 kb
Host smart-a5d5ec51-acf0-473c-bcb1-a55e9abc3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936207811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1936207811
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1713236727
Short name T573
Test name
Test status
Simulation time 190285657 ps
CPU time 5.91 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 233440 kb
Host smart-0e4c29a1-c50e-44f9-85a3-802a3402e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713236727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1713236727
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2356400767
Short name T775
Test name
Test status
Simulation time 2562821693 ps
CPU time 30 seconds
Started Jul 31 05:02:29 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 253680 kb
Host smart-2fbd3305-1047-47fa-a958-b3d5c4bfd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356400767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2356400767
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.801896140
Short name T273
Test name
Test status
Simulation time 1921230000 ps
CPU time 19.9 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:37 PM PDT 24
Peak memory 225164 kb
Host smart-c9315768-3326-4714-a0d0-fcb915010763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801896140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.801896140
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1657577532
Short name T751
Test name
Test status
Simulation time 34925000 ps
CPU time 2.54 seconds
Started Jul 31 05:02:12 PM PDT 24
Finished Jul 31 05:02:14 PM PDT 24
Peak memory 233384 kb
Host smart-835488ae-c492-413a-b76f-e419b877bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657577532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1657577532
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3055382610
Short name T599
Test name
Test status
Simulation time 439224922 ps
CPU time 7.96 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 233388 kb
Host smart-1adbbfb2-a7f9-4ac3-aad0-6b7afe49755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055382610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3055382610
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3090501935
Short name T222
Test name
Test status
Simulation time 11179231384 ps
CPU time 12.23 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 233468 kb
Host smart-136eb153-a847-4629-a608-fcf090357583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090501935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3090501935
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3388742099
Short name T656
Test name
Test status
Simulation time 4590754444 ps
CPU time 10.99 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:30 PM PDT 24
Peak memory 223824 kb
Host smart-fa648b1e-211f-4770-aa85-ce4191c43ea8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388742099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3388742099
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.660904135
Short name T699
Test name
Test status
Simulation time 2639167685 ps
CPU time 32.71 seconds
Started Jul 31 05:02:11 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 218668 kb
Host smart-ed66d166-cea3-4cd5-8ca3-66081e60b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660904135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.660904135
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3680502513
Short name T811
Test name
Test status
Simulation time 17413136550 ps
CPU time 13.8 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 217012 kb
Host smart-88901523-f7a9-493c-b80e-f36a880c30a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680502513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3680502513
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2532957936
Short name T373
Test name
Test status
Simulation time 28083638 ps
CPU time 1.95 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 216980 kb
Host smart-ef90bec4-dfdb-4a08-8363-ac3a24536acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532957936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2532957936
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.561251266
Short name T963
Test name
Test status
Simulation time 162347334 ps
CPU time 0.83 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 206424 kb
Host smart-54f30fcd-bbec-471a-b962-0826882b1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561251266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.561251266
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1082732009
Short name T480
Test name
Test status
Simulation time 7035308540 ps
CPU time 5.49 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 233400 kb
Host smart-4377a0ac-6e3a-4cdf-ba89-ca5d8652f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082732009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1082732009
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3212386664
Short name T787
Test name
Test status
Simulation time 40500490 ps
CPU time 0.73 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 206076 kb
Host smart-4dfcff1b-78a3-41a8-a925-d14db1aa2020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212386664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3212386664
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1388068944
Short name T729
Test name
Test status
Simulation time 549458974 ps
CPU time 2.73 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 225080 kb
Host smart-f65f2e82-30f4-4c2b-aa17-f70ef72c916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388068944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1388068944
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2782314039
Short name T617
Test name
Test status
Simulation time 146031026 ps
CPU time 0.75 seconds
Started Jul 31 05:02:36 PM PDT 24
Finished Jul 31 05:02:37 PM PDT 24
Peak memory 205960 kb
Host smart-b4481651-6c27-4d9b-a313-e3d296a5c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782314039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2782314039
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3425656985
Short name T646
Test name
Test status
Simulation time 13813478 ps
CPU time 0.73 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 216392 kb
Host smart-cbe57e5f-b82b-4648-ae7e-e359e800c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425656985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3425656985
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1221192035
Short name T761
Test name
Test status
Simulation time 36959955113 ps
CPU time 60.68 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 224604 kb
Host smart-c6aba87a-f988-4a64-8d85-0c8bf91150ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221192035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1221192035
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4011970768
Short name T791
Test name
Test status
Simulation time 4086066695 ps
CPU time 58.71 seconds
Started Jul 31 05:02:29 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 254644 kb
Host smart-6d81329d-d258-42da-831c-0a015489aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011970768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4011970768
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2516075693
Short name T977
Test name
Test status
Simulation time 1552177964 ps
CPU time 11.74 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 249880 kb
Host smart-8a332a15-541a-4325-a57e-fda6bd2032be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516075693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2516075693
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.54722688
Short name T164
Test name
Test status
Simulation time 2360149463 ps
CPU time 23.96 seconds
Started Jul 31 05:02:27 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 249680 kb
Host smart-5023bc8c-10ba-49f7-a3db-987ac61515c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54722688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.54722688
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3981491255
Short name T407
Test name
Test status
Simulation time 2685274677 ps
CPU time 20.16 seconds
Started Jul 31 05:02:29 PM PDT 24
Finished Jul 31 05:02:49 PM PDT 24
Peak memory 225304 kb
Host smart-fbe01c65-d284-46fc-8eee-80f71a2c40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981491255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3981491255
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3244657461
Short name T930
Test name
Test status
Simulation time 16946967675 ps
CPU time 30.98 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 233308 kb
Host smart-52208b97-ef33-4f78-a31b-9f288a1f27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244657461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3244657461
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2746602986
Short name T807
Test name
Test status
Simulation time 600724844 ps
CPU time 5.57 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 233376 kb
Host smart-af578a0f-5927-4b7a-af6f-c02e0ceaa355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746602986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2746602986
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1899068771
Short name T203
Test name
Test status
Simulation time 1263613249 ps
CPU time 4.45 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 233360 kb
Host smart-8daacb71-f987-4829-a9e8-31eedfd71cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899068771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1899068771
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2762373281
Short name T481
Test name
Test status
Simulation time 102485622 ps
CPU time 3.88 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 219540 kb
Host smart-202e5acc-c970-4d90-a214-159724d2f4a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2762373281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2762373281
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.272370892
Short name T488
Test name
Test status
Simulation time 1137478947 ps
CPU time 10.51 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 216944 kb
Host smart-09340fbb-119f-4247-bcb5-a8a8e0397f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272370892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.272370892
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4275278547
Short name T398
Test name
Test status
Simulation time 12784078042 ps
CPU time 10.02 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 217072 kb
Host smart-c2613a0d-1983-4a68-94a2-dde7c15d36cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275278547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4275278547
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1409818345
Short name T776
Test name
Test status
Simulation time 45764370 ps
CPU time 1.26 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 216880 kb
Host smart-1f79f85a-0a64-4373-8d6b-e284b1d8b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409818345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1409818345
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2313154312
Short name T336
Test name
Test status
Simulation time 21133669 ps
CPU time 0.74 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 206528 kb
Host smart-36642a13-da2c-43b8-94a6-48b216628646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313154312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2313154312
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.508513534
Short name T532
Test name
Test status
Simulation time 126495708 ps
CPU time 2.95 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 225140 kb
Host smart-11a7c5a6-bb3a-4a53-b80e-5a6ed74658ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508513534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.508513534
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1998229190
Short name T969
Test name
Test status
Simulation time 36993984 ps
CPU time 0.69 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 205724 kb
Host smart-70cb3dfd-3526-4572-98f0-ddfd4586cb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998229190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1998229190
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2730897792
Short name T391
Test name
Test status
Simulation time 206054805 ps
CPU time 3.52 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 233316 kb
Host smart-6e35d80b-abd4-4cde-9799-87c577f29107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730897792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2730897792
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1252651687
Short name T410
Test name
Test status
Simulation time 20759475 ps
CPU time 0.78 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 207284 kb
Host smart-6a0c3446-1da3-4d7b-bb05-9dd2475b6f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252651687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1252651687
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4072615902
Short name T623
Test name
Test status
Simulation time 58973007230 ps
CPU time 69.97 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 252316 kb
Host smart-b105f046-878d-4eb6-a57b-b31176a912cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072615902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4072615902
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1824082730
Short name T174
Test name
Test status
Simulation time 67547597841 ps
CPU time 174.28 seconds
Started Jul 31 05:03:00 PM PDT 24
Finished Jul 31 05:05:54 PM PDT 24
Peak memory 257988 kb
Host smart-2085caa3-a346-4dce-afcd-3e1ba244ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824082730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1824082730
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.860483490
Short name T44
Test name
Test status
Simulation time 171852642391 ps
CPU time 80.45 seconds
Started Jul 31 05:02:24 PM PDT 24
Finished Jul 31 05:03:45 PM PDT 24
Peak memory 233516 kb
Host smart-759aa3fb-207b-43e7-9b8c-13f87eab0162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860483490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.860483490
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.381086180
Short name T14
Test name
Test status
Simulation time 1633961016 ps
CPU time 7.6 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 249716 kb
Host smart-a4c6826b-7ea9-45ed-8545-3eb35f2679bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381086180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.381086180
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3895989136
Short name T94
Test name
Test status
Simulation time 13368238199 ps
CPU time 115.66 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 249812 kb
Host smart-ac0342c5-2f70-4998-a5fa-63c6c5e7adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895989136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3895989136
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3038240885
Short name T727
Test name
Test status
Simulation time 4155269442 ps
CPU time 18.29 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 233368 kb
Host smart-80966137-3041-4b1b-9a93-07e1302a2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038240885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3038240885
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.570484721
Short name T225
Test name
Test status
Simulation time 1227474958 ps
CPU time 18.69 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 233448 kb
Host smart-9671f16f-c8c6-419d-b61f-5bbcfbd93c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570484721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.570484721
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3152835201
Short name T447
Test name
Test status
Simulation time 717358871 ps
CPU time 5.1 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 233356 kb
Host smart-0d66516b-b92d-4536-96e9-a7ea373c2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152835201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3152835201
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3446541265
Short name T195
Test name
Test status
Simulation time 35680533335 ps
CPU time 29 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:56 PM PDT 24
Peak memory 233400 kb
Host smart-530dad42-eb76-4251-bc8d-5ef3ac8e0a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446541265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3446541265
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1765915097
Short name T710
Test name
Test status
Simulation time 873188850 ps
CPU time 10.54 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 219484 kb
Host smart-70e5291d-45fb-430b-b810-c0dc477b0dea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765915097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1765915097
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2604918457
Short name T154
Test name
Test status
Simulation time 42488133 ps
CPU time 0.87 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 207064 kb
Host smart-30b12b24-d547-452e-afde-c075ab74b991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604918457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2604918457
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.434554674
Short name T725
Test name
Test status
Simulation time 9076775918 ps
CPU time 14.69 seconds
Started Jul 31 05:02:25 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 220960 kb
Host smart-6baa23df-a6f0-426e-be4d-64656c92aca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434554674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.434554674
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.846744133
Short name T435
Test name
Test status
Simulation time 255583734 ps
CPU time 2.49 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 216856 kb
Host smart-3fab036f-5a6f-4e0e-bf76-17663d99ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846744133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.846744133
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3634415866
Short name T896
Test name
Test status
Simulation time 605283456 ps
CPU time 2.49 seconds
Started Jul 31 05:02:15 PM PDT 24
Finished Jul 31 05:02:18 PM PDT 24
Peak memory 216808 kb
Host smart-1af2f29a-b908-4fc5-a938-db0a9df02d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634415866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3634415866
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2086676690
Short name T691
Test name
Test status
Simulation time 50781270 ps
CPU time 0.69 seconds
Started Jul 31 05:02:37 PM PDT 24
Finished Jul 31 05:02:37 PM PDT 24
Peak memory 206032 kb
Host smart-d458e318-3296-48de-9728-7a46abef5aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086676690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2086676690
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2697488093
Short name T685
Test name
Test status
Simulation time 942175115 ps
CPU time 8.36 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:27 PM PDT 24
Peak memory 241664 kb
Host smart-60f0b73b-182a-4deb-95f0-3140f64a4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697488093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2697488093
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.582610068
Short name T622
Test name
Test status
Simulation time 34028670 ps
CPU time 0.72 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 205752 kb
Host smart-4d53ada6-44b1-4ffe-a42e-cdba2e0a190b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582610068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.582610068
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.659204288
Short name T603
Test name
Test status
Simulation time 74325737 ps
CPU time 2.63 seconds
Started Jul 31 05:02:44 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 225136 kb
Host smart-36179cad-89b2-4aab-b0b2-418036a70edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659204288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.659204288
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2290686266
Short name T343
Test name
Test status
Simulation time 62855525 ps
CPU time 0.8 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 207160 kb
Host smart-c1c66c5d-c5f1-439e-afb5-b060a851699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290686266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2290686266
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1831953439
Short name T739
Test name
Test status
Simulation time 19299538847 ps
CPU time 158.23 seconds
Started Jul 31 05:02:35 PM PDT 24
Finished Jul 31 05:05:14 PM PDT 24
Peak memory 257536 kb
Host smart-cbf0dfd5-ef89-4a81-a3d0-3ae0e7c622f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831953439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1831953439
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4047914720
Short name T300
Test name
Test status
Simulation time 248172154783 ps
CPU time 548.51 seconds
Started Jul 31 05:02:35 PM PDT 24
Finished Jul 31 05:11:43 PM PDT 24
Peak memory 265920 kb
Host smart-4d91f027-9af2-484a-a547-dcbf1271892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047914720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4047914720
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4109867238
Short name T736
Test name
Test status
Simulation time 1444164472 ps
CPU time 16.37 seconds
Started Jul 31 05:02:16 PM PDT 24
Finished Jul 31 05:02:32 PM PDT 24
Peak memory 239548 kb
Host smart-42f78ee0-d5cd-405e-a61c-f9f6d49a504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109867238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4109867238
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4226791742
Short name T741
Test name
Test status
Simulation time 4679263322 ps
CPU time 25.44 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 241556 kb
Host smart-db88a9d7-5616-49b7-b777-0618139b2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226791742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4226791742
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4195131814
Short name T628
Test name
Test status
Simulation time 490783671 ps
CPU time 5.79 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:56 PM PDT 24
Peak memory 225088 kb
Host smart-d84bc8b9-2c73-41f3-be70-e6128e3dc697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195131814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4195131814
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2846184315
Short name T230
Test name
Test status
Simulation time 25228549351 ps
CPU time 49.92 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 233464 kb
Host smart-47114815-7716-49ff-8e74-f9e44cac5c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846184315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2846184315
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3690115676
Short name T494
Test name
Test status
Simulation time 2919258775 ps
CPU time 3.09 seconds
Started Jul 31 05:02:43 PM PDT 24
Finished Jul 31 05:02:46 PM PDT 24
Peak memory 233384 kb
Host smart-5cef74f2-762f-4628-a8fe-331569d3cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690115676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3690115676
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3407642187
Short name T707
Test name
Test status
Simulation time 17187195454 ps
CPU time 12.91 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 233372 kb
Host smart-25b13d8f-e8fe-427f-86b3-96483d34b55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407642187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3407642187
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2469326806
Short name T478
Test name
Test status
Simulation time 927314043 ps
CPU time 4.46 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 223140 kb
Host smart-9fbd9c13-1b6f-4722-b265-cb316433d9fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2469326806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2469326806
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1770083734
Short name T34
Test name
Test status
Simulation time 16536326337 ps
CPU time 130.32 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:04:40 PM PDT 24
Peak memory 266864 kb
Host smart-ef2d2bf4-fe3e-4f8d-acc9-28ca281d0b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770083734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1770083734
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.320960353
Short name T604
Test name
Test status
Simulation time 290672191 ps
CPU time 2.59 seconds
Started Jul 31 05:02:29 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 217104 kb
Host smart-674f5284-5e86-4a64-b6e7-125481bb8ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320960353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.320960353
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3200379609
Short name T365
Test name
Test status
Simulation time 619326244 ps
CPU time 4.67 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 216912 kb
Host smart-49babe10-5976-4642-b790-b81c00719ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200379609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3200379609
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2040028158
Short name T902
Test name
Test status
Simulation time 185928674 ps
CPU time 2.47 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 216860 kb
Host smart-b8bd683b-78d2-4db3-a357-621d7d8b3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040028158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2040028158
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1169517728
Short name T87
Test name
Test status
Simulation time 45844429 ps
CPU time 0.71 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 206468 kb
Host smart-b9b399c6-19f0-4f38-bc15-eae60f37498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169517728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1169517728
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3014520690
Short name T244
Test name
Test status
Simulation time 4975182986 ps
CPU time 17.18 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 225112 kb
Host smart-9f4d6f84-6470-4afa-a401-aa48b25326a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014520690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3014520690
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4006794496
Short name T402
Test name
Test status
Simulation time 37408873 ps
CPU time 0.71 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 205724 kb
Host smart-2fae4cac-51a7-4f7e-91fb-0adadea88fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006794496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4006794496
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4184061020
Short name T89
Test name
Test status
Simulation time 114730980 ps
CPU time 3.67 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:37 PM PDT 24
Peak memory 233340 kb
Host smart-5d5323fe-4675-4643-9957-f648e69e48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184061020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4184061020
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.863648389
Short name T337
Test name
Test status
Simulation time 14852802 ps
CPU time 0.76 seconds
Started Jul 31 05:02:23 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 205888 kb
Host smart-0d45a85f-707c-405e-82da-03153ef1b387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863648389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.863648389
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2343214227
Short name T305
Test name
Test status
Simulation time 34971802010 ps
CPU time 74.65 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 252908 kb
Host smart-73d50ddd-fda1-4962-97c9-2ca4e97fccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343214227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2343214227
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2356630089
Short name T657
Test name
Test status
Simulation time 7678583260 ps
CPU time 86.57 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 256036 kb
Host smart-e8ed7965-f55f-4aaa-8a7f-7c5c398fd79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356630089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2356630089
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3645188642
Short name T317
Test name
Test status
Simulation time 580962444 ps
CPU time 8.95 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 225112 kb
Host smart-440a08c3-a695-465c-b10a-56ee3c0b25ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645188642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3645188642
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2077438342
Short name T701
Test name
Test status
Simulation time 28391140228 ps
CPU time 118.78 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 240448 kb
Host smart-5d89e62b-cb12-4128-90e3-a5e8e617cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077438342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2077438342
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1191102874
Short name T758
Test name
Test status
Simulation time 356981014 ps
CPU time 4.84 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:25 PM PDT 24
Peak memory 225296 kb
Host smart-48e5dbc5-67e7-4613-93a2-a1d793d30094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191102874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1191102874
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3680311896
Short name T93
Test name
Test status
Simulation time 991121463 ps
CPU time 10.2 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 225280 kb
Host smart-58bd6d75-aeb9-4f5e-a83b-8e72035fb14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680311896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3680311896
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3199193500
Short name T268
Test name
Test status
Simulation time 3709598580 ps
CPU time 9.2 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 225324 kb
Host smart-c4356e97-25f5-4733-8dfb-b9bd7692f08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199193500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3199193500
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4226683389
Short name T582
Test name
Test status
Simulation time 243171867 ps
CPU time 3.41 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 220784 kb
Host smart-8d19a5e5-0bd0-419c-9075-ee333ecb273f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4226683389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4226683389
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.645701357
Short name T320
Test name
Test status
Simulation time 646407453 ps
CPU time 10 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:43 PM PDT 24
Peak memory 220400 kb
Host smart-f0aa0b56-bb98-4ba2-9673-f1ea6538981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645701357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.645701357
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1349772100
Short name T908
Test name
Test status
Simulation time 948990370 ps
CPU time 3.09 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 216684 kb
Host smart-27b804e9-acc4-4661-9dda-c7c21d99f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349772100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1349772100
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3357889341
Short name T432
Test name
Test status
Simulation time 84997970 ps
CPU time 1.94 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 216904 kb
Host smart-871aac42-5140-4c28-ad0d-7f9c0a71bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357889341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3357889341
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3847208201
Short name T618
Test name
Test status
Simulation time 29513844 ps
CPU time 0.72 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 206440 kb
Host smart-06bf0aac-2599-4ec6-896b-36e0b85f2f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847208201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3847208201
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1643260691
Short name T370
Test name
Test status
Simulation time 3073752839 ps
CPU time 8.34 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 233456 kb
Host smart-0fde0245-7228-4947-bc19-2007f13ae41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643260691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1643260691
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3873279643
Short name T869
Test name
Test status
Simulation time 104442177 ps
CPU time 0.7 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 205712 kb
Host smart-77b85891-ab6c-43b0-9355-ece5cbf3add5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873279643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3873279643
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3378520005
Short name T1028
Test name
Test status
Simulation time 716176778 ps
CPU time 6.68 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 225144 kb
Host smart-5a907315-ab3d-4898-b7d5-67a16a69290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378520005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3378520005
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3028211270
Short name T678
Test name
Test status
Simulation time 57187911 ps
CPU time 0.75 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 206944 kb
Host smart-c052fb07-2b03-49b5-826a-0888e010b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028211270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3028211270
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1842195846
Short name T367
Test name
Test status
Simulation time 6221254972 ps
CPU time 43.28 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 241984 kb
Host smart-c429cce3-2c47-49a0-a74d-504b35683000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842195846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1842195846
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1867888807
Short name T169
Test name
Test status
Simulation time 27755263796 ps
CPU time 251.98 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:06:38 PM PDT 24
Peak memory 250856 kb
Host smart-fd2f9e4d-0df4-4efa-8797-0174b0c9af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867888807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1867888807
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2794095042
Short name T291
Test name
Test status
Simulation time 104569486846 ps
CPU time 281.33 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:07:31 PM PDT 24
Peak memory 250472 kb
Host smart-0744f8f6-2466-4cdb-a324-e145657d3f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794095042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2794095042
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1953637681
Short name T705
Test name
Test status
Simulation time 1435711273 ps
CPU time 19.97 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:03:13 PM PDT 24
Peak memory 234956 kb
Host smart-c0dfdb8e-7938-4645-a035-f168be6c2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953637681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1953637681
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1650062259
Short name T91
Test name
Test status
Simulation time 29463440865 ps
CPU time 261.3 seconds
Started Jul 31 05:02:18 PM PDT 24
Finished Jul 31 05:06:39 PM PDT 24
Peak memory 256716 kb
Host smart-8fbc4004-4bf8-47d8-8585-11aa9fc97179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650062259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1650062259
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3044392588
Short name T200
Test name
Test status
Simulation time 5495450201 ps
CPU time 15.88 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:48 PM PDT 24
Peak memory 225272 kb
Host smart-d11da7d3-fc70-4e9f-83fd-22afa1e5c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044392588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3044392588
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1559941623
Short name T744
Test name
Test status
Simulation time 1578681781 ps
CPU time 7.06 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 233284 kb
Host smart-63d3088e-4312-4289-abc8-3516d9fd7205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559941623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1559941623
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3002005026
Short name T771
Test name
Test status
Simulation time 8170893618 ps
CPU time 10.24 seconds
Started Jul 31 05:02:25 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 233500 kb
Host smart-4dbf16a9-62d3-4e93-966f-e7a00dfe2308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002005026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3002005026
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3834063478
Short name T769
Test name
Test status
Simulation time 220122754 ps
CPU time 2.82 seconds
Started Jul 31 05:02:42 PM PDT 24
Finished Jul 31 05:02:45 PM PDT 24
Peak memory 233496 kb
Host smart-3f28914c-0886-4278-be47-50ac16997469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834063478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3834063478
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4073910703
Short name T396
Test name
Test status
Simulation time 1983972707 ps
CPU time 6.43 seconds
Started Jul 31 05:02:17 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 223884 kb
Host smart-fc166903-1745-407d-bc58-5121a08b3637
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4073910703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4073910703
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.95852887
Short name T388
Test name
Test status
Simulation time 127968785 ps
CPU time 0.81 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 206352 kb
Host smart-4019eb2c-0e56-4e1f-b8be-7474e3d9eb4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95852887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.95852887
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2630392031
Short name T932
Test name
Test status
Simulation time 3307542592 ps
CPU time 8.04 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:27 PM PDT 24
Peak memory 216932 kb
Host smart-4411c231-b748-4d8d-8d3b-5e0db0f1c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630392031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2630392031
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.69943333
Short name T29
Test name
Test status
Simulation time 7352824273 ps
CPU time 18.93 seconds
Started Jul 31 05:02:28 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 216888 kb
Host smart-9fc31acf-eff7-49e4-99e0-6129769211d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69943333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.69943333
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2574672032
Short name T558
Test name
Test status
Simulation time 466344042 ps
CPU time 2.48 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 216824 kb
Host smart-3e3bc7a5-3ffd-43d5-9f45-a41ce1455e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574672032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2574672032
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1912798665
Short name T804
Test name
Test status
Simulation time 40452549 ps
CPU time 0.68 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:31 PM PDT 24
Peak memory 206048 kb
Host smart-6aab2819-ea47-4fac-ae8d-f09e6c412356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912798665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1912798665
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.860370022
Short name T574
Test name
Test status
Simulation time 14382053724 ps
CPU time 8.89 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 233456 kb
Host smart-46d33ad0-d7d2-4d7a-93b9-58ee36a0f10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860370022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.860370022
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.878923688
Short name T861
Test name
Test status
Simulation time 22338747 ps
CPU time 0.72 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 205684 kb
Host smart-88c30627-1ccd-490f-b92c-a0786b8da753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878923688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.878923688
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1174256062
Short name T533
Test name
Test status
Simulation time 7045461313 ps
CPU time 33.08 seconds
Started Jul 31 05:02:37 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 225264 kb
Host smart-840e83df-da9b-4c2c-96a9-3fd30eccd825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174256062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1174256062
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4257192563
Short name T995
Test name
Test status
Simulation time 18821472 ps
CPU time 0.78 seconds
Started Jul 31 05:02:39 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 206920 kb
Host smart-53740a55-6e04-45b2-b480-c8fb50845136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257192563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4257192563
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2350103037
Short name T420
Test name
Test status
Simulation time 2374373621 ps
CPU time 33.46 seconds
Started Jul 31 05:02:36 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 249820 kb
Host smart-9f37d26d-6411-4463-b6a9-eb964893604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350103037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2350103037
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3684606653
Short name T49
Test name
Test status
Simulation time 4130902434 ps
CPU time 20.04 seconds
Started Jul 31 05:02:42 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 225296 kb
Host smart-39e0c7bf-07e8-4f10-ba1a-f31459e64a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684606653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3684606653
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.687420595
Short name T60
Test name
Test status
Simulation time 5812198014 ps
CPU time 119.55 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 259472 kb
Host smart-971fa614-7d3b-4418-884e-50bb5a47b457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687420595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.687420595
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1671686737
Short name T416
Test name
Test status
Simulation time 5204800352 ps
CPU time 57.12 seconds
Started Jul 31 05:02:35 PM PDT 24
Finished Jul 31 05:03:32 PM PDT 24
Peak memory 233504 kb
Host smart-34138782-f4cf-4a60-997e-176e4dac392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671686737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1671686737
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1771706374
Short name T453
Test name
Test status
Simulation time 705839307 ps
CPU time 12.22 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 241568 kb
Host smart-728cb403-8826-44a8-9468-c61dd6986da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771706374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1771706374
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1114803136
Short name T630
Test name
Test status
Simulation time 200896085 ps
CPU time 2.86 seconds
Started Jul 31 05:02:22 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 233156 kb
Host smart-2cec6a26-0bc8-48c0-82b9-0e971630e1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114803136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1114803136
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2774917552
Short name T690
Test name
Test status
Simulation time 306010676 ps
CPU time 3.39 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 233304 kb
Host smart-6881b4df-f523-4f8d-864b-9c8f65d1424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774917552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2774917552
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3744353857
Short name T304
Test name
Test status
Simulation time 10519858692 ps
CPU time 8.72 seconds
Started Jul 31 05:02:19 PM PDT 24
Finished Jul 31 05:02:28 PM PDT 24
Peak memory 225180 kb
Host smart-19ed0f3d-5a3a-4caa-9b68-c5f612d1f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744353857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3744353857
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2280723531
Short name T206
Test name
Test status
Simulation time 698459639 ps
CPU time 5.65 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 225252 kb
Host smart-087fcd20-f40a-47bf-ab55-f957a1592a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280723531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2280723531
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2667173015
Short name T148
Test name
Test status
Simulation time 6363417419 ps
CPU time 7.85 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 223944 kb
Host smart-335f76ba-29e8-4531-8c48-6f89ffd290c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2667173015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2667173015
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4115419985
Short name T296
Test name
Test status
Simulation time 49645072939 ps
CPU time 333.56 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:08:26 PM PDT 24
Peak memory 286672 kb
Host smart-afaec622-1c10-4d04-8075-1f7aa2d7ad40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115419985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4115419985
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2237653589
Short name T434
Test name
Test status
Simulation time 55514216 ps
CPU time 0.75 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 206068 kb
Host smart-85160ff1-8b4f-41ae-bdba-dd27533dd9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237653589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2237653589
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1899807099
Short name T855
Test name
Test status
Simulation time 5856665894 ps
CPU time 19.49 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:03:05 PM PDT 24
Peak memory 216968 kb
Host smart-ff8b9922-498b-4f86-a31a-54ff895f0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899807099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1899807099
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1482273687
Short name T854
Test name
Test status
Simulation time 62100349 ps
CPU time 1.15 seconds
Started Jul 31 05:02:21 PM PDT 24
Finished Jul 31 05:02:22 PM PDT 24
Peak memory 208188 kb
Host smart-8cfc8e3f-995d-4622-9c2c-4b52b2915565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482273687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1482273687
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2066736278
Short name T86
Test name
Test status
Simulation time 14934678 ps
CPU time 0.71 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:20 PM PDT 24
Peak memory 206568 kb
Host smart-0ca0f0af-e20d-498c-8502-b086d9ede53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066736278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2066736278
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2097305208
Short name T1013
Test name
Test status
Simulation time 164697568 ps
CPU time 2.57 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 233428 kb
Host smart-752f2cd3-e085-4eda-ab8f-5bc0565c3cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097305208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2097305208
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.155602900
Short name T783
Test name
Test status
Simulation time 35123510 ps
CPU time 0.73 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 205208 kb
Host smart-a8e73d79-e5b7-47cc-be28-a8fc8c375419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155602900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.155602900
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3147463008
Short name T404
Test name
Test status
Simulation time 821261175 ps
CPU time 5.42 seconds
Started Jul 31 05:02:39 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 233308 kb
Host smart-d7c5d0c7-9aeb-47ed-b527-bae80a4f5184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147463008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3147463008
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1611664994
Short name T627
Test name
Test status
Simulation time 33915313 ps
CPU time 0.77 seconds
Started Jul 31 05:02:26 PM PDT 24
Finished Jul 31 05:02:27 PM PDT 24
Peak memory 207364 kb
Host smart-fdf8d823-7ec9-4642-8d10-fc11ea748437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611664994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1611664994
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3586673813
Short name T262
Test name
Test status
Simulation time 2237575914 ps
CPU time 38.56 seconds
Started Jul 31 05:02:28 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 240748 kb
Host smart-62e8c0d4-1a7b-4dc1-9e00-c64f4fd267bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586673813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3586673813
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1497771078
Short name T631
Test name
Test status
Simulation time 1621354629 ps
CPU time 19.18 seconds
Started Jul 31 05:02:44 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 237564 kb
Host smart-356a4118-20e4-48c7-9854-d8606da320a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497771078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1497771078
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2572690745
Short name T633
Test name
Test status
Simulation time 11980605725 ps
CPU time 60.96 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:04:05 PM PDT 24
Peak memory 252764 kb
Host smart-2957a996-3123-4fba-8a99-7504722d9a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572690745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2572690745
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3813148122
Short name T899
Test name
Test status
Simulation time 322744417 ps
CPU time 6.33 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 233308 kb
Host smart-3228d308-ec0f-4563-b9c3-f9936673a732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813148122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3813148122
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.397487965
Short name T308
Test name
Test status
Simulation time 14453796904 ps
CPU time 99.19 seconds
Started Jul 31 05:02:43 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 255776 kb
Host smart-7f8c7f68-91d8-42ae-be76-2a32c2c94470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397487965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.397487965
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4158073002
Short name T240
Test name
Test status
Simulation time 1508263514 ps
CPU time 14.91 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:02:56 PM PDT 24
Peak memory 233364 kb
Host smart-afbbcf65-36a0-40ac-a31c-3a23074abeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158073002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4158073002
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.823230242
Short name T221
Test name
Test status
Simulation time 2863572001 ps
CPU time 14.82 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:03:05 PM PDT 24
Peak memory 225184 kb
Host smart-c8d0e232-61b6-469f-8136-18d35bc7b5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823230242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.823230242
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1910879469
Short name T696
Test name
Test status
Simulation time 1010275308 ps
CPU time 3.03 seconds
Started Jul 31 05:02:42 PM PDT 24
Finished Jul 31 05:02:45 PM PDT 24
Peak memory 233364 kb
Host smart-470986c9-7fd6-4d8a-a38f-810d8c249190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910879469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1910879469
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3488120732
Short name T253
Test name
Test status
Simulation time 1776058973 ps
CPU time 7.67 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 233420 kb
Host smart-14dff9bd-2dad-463f-b45e-09a9dbeecba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488120732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3488120732
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1351446433
Short name T421
Test name
Test status
Simulation time 113616807 ps
CPU time 3.76 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:45 PM PDT 24
Peak memory 220088 kb
Host smart-598a0fc2-07dc-434a-bdf6-5bfde9661eba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1351446433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1351446433
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3843055430
Short name T213
Test name
Test status
Simulation time 399017583379 ps
CPU time 850.71 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:16:59 PM PDT 24
Peak memory 266332 kb
Host smart-7f7bc050-3aae-4408-a289-c0b23e90ba7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843055430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3843055430
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4090853548
Short name T763
Test name
Test status
Simulation time 18946610 ps
CPU time 0.73 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:36 PM PDT 24
Peak memory 206064 kb
Host smart-6143faa0-5adf-464d-a7da-d229e6160853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090853548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4090853548
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.205884321
Short name T380
Test name
Test status
Simulation time 17794956 ps
CPU time 0.7 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:02:34 PM PDT 24
Peak memory 206176 kb
Host smart-b8fc5516-bacc-4ec8-85b1-00a03e0f9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205884321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.205884321
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.506570198
Short name T61
Test name
Test status
Simulation time 370615370 ps
CPU time 1.47 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:02:48 PM PDT 24
Peak memory 216552 kb
Host smart-99116860-a4ca-43a8-8501-fc19d15b65a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506570198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.506570198
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.801846526
Short name T917
Test name
Test status
Simulation time 31476845 ps
CPU time 0.86 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 206448 kb
Host smart-a2473434-e773-4938-a07c-b5da7406d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801846526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.801846526
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4126914423
Short name T958
Test name
Test status
Simulation time 1726976986 ps
CPU time 8.91 seconds
Started Jul 31 05:02:30 PM PDT 24
Finished Jul 31 05:02:39 PM PDT 24
Peak memory 233436 kb
Host smart-ce026932-e4fc-46ca-ad96-cb471953615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126914423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4126914423
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1860277369
Short name T413
Test name
Test status
Simulation time 88229817 ps
CPU time 0.71 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 205268 kb
Host smart-6f3c8aec-fac3-4151-9cb6-96b878526f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860277369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1860277369
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4135316497
Short name T889
Test name
Test status
Simulation time 788474684 ps
CPU time 4.19 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:02:36 PM PDT 24
Peak memory 225204 kb
Host smart-f34754a4-7ece-4372-8ff9-8a71bb4e0176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135316497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4135316497
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4156366903
Short name T549
Test name
Test status
Simulation time 46628024 ps
CPU time 0.79 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 207312 kb
Host smart-96bcc3d1-4dd2-4be6-b1b0-a5b9a6cfcfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156366903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4156366903
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.666794937
Short name T624
Test name
Test status
Simulation time 40988648 ps
CPU time 0.88 seconds
Started Jul 31 05:02:36 PM PDT 24
Finished Jul 31 05:02:37 PM PDT 24
Peak memory 216700 kb
Host smart-ed4b7d48-ff10-4109-85d8-c8e4fbd69609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666794937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.666794937
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1229553251
Short name T312
Test name
Test status
Simulation time 215787673845 ps
CPU time 415.51 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:09:29 PM PDT 24
Peak memory 271004 kb
Host smart-4dc56a2e-be17-4511-be62-bdfaf530fc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229553251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1229553251
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3902501334
Short name T919
Test name
Test status
Simulation time 24694567107 ps
CPU time 108.73 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:04:43 PM PDT 24
Peak memory 258100 kb
Host smart-d9f77cd3-fc63-4a80-864b-1ffd0a9cf243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902501334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3902501334
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.579456853
Short name T1003
Test name
Test status
Simulation time 260367160 ps
CPU time 3.65 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:24 PM PDT 24
Peak memory 235004 kb
Host smart-404748fc-226d-42a9-9610-9fa008f67544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579456853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.579456853
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1723048122
Short name T970
Test name
Test status
Simulation time 29081810542 ps
CPU time 205.61 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:06:07 PM PDT 24
Peak memory 249788 kb
Host smart-32e66b86-6b5b-4985-9497-d0039d493b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723048122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1723048122
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2020450513
Short name T90
Test name
Test status
Simulation time 4180253386 ps
CPU time 24.17 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 233220 kb
Host smart-0631b4fa-0b9b-4601-83dc-cf3f3236cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020450513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2020450513
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2861391536
Short name T452
Test name
Test status
Simulation time 376683673 ps
CPU time 3.87 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:02:49 PM PDT 24
Peak memory 233460 kb
Host smart-34cf6369-1f9f-4b56-b01d-ddad90741279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861391536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2861391536
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2909951185
Short name T1007
Test name
Test status
Simulation time 2839780421 ps
CPU time 8.45 seconds
Started Jul 31 05:02:20 PM PDT 24
Finished Jul 31 05:02:29 PM PDT 24
Peak memory 233484 kb
Host smart-232b4c60-16ed-45a4-8be7-60aaa1299ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909951185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2909951185
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3970134064
Short name T469
Test name
Test status
Simulation time 4281137886 ps
CPU time 12.84 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:02:58 PM PDT 24
Peak memory 233536 kb
Host smart-cf4b3eca-1988-4de5-a758-1c2432fff327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970134064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3970134064
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3468142173
Short name T359
Test name
Test status
Simulation time 2190334154 ps
CPU time 17.74 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 220484 kb
Host smart-6ee34fa4-47bd-4488-afbd-8c6f8652d41d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3468142173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3468142173
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1280469887
Short name T912
Test name
Test status
Simulation time 81891164 ps
CPU time 0.95 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:02:49 PM PDT 24
Peak memory 207372 kb
Host smart-32dd972d-97ab-4cbe-9965-1345d688f18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280469887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1280469887
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2333508399
Short name T966
Test name
Test status
Simulation time 3334191200 ps
CPU time 24.39 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 217004 kb
Host smart-df8b032b-be3b-460b-8f18-ac322041316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333508399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2333508399
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3821742229
Short name T464
Test name
Test status
Simulation time 830952439 ps
CPU time 5.36 seconds
Started Jul 31 05:02:37 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 216808 kb
Host smart-b3ec0d65-ffc8-4fd1-a885-5017405fa2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821742229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3821742229
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1098400663
Short name T785
Test name
Test status
Simulation time 28383111 ps
CPU time 0.85 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 207140 kb
Host smart-1dc0f34b-defa-4da9-bc7b-b193d7776d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098400663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1098400663
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1683906820
Short name T381
Test name
Test status
Simulation time 104116575 ps
CPU time 1.01 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 207608 kb
Host smart-0af9a8b9-c8d2-4693-bd09-44f0d209abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683906820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1683906820
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3449687698
Short name T26
Test name
Test status
Simulation time 3597791230 ps
CPU time 4.97 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 225204 kb
Host smart-aae82e2c-e982-4c6e-b6ec-958cecd93655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449687698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3449687698
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1834905366
Short name T666
Test name
Test status
Simulation time 24863504 ps
CPU time 0.77 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 205680 kb
Host smart-383d0c93-481c-41c6-a4ef-37d13367ad26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834905366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1834905366
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2479258899
Short name T280
Test name
Test status
Simulation time 1773092025 ps
CPU time 16.48 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:03:05 PM PDT 24
Peak memory 233212 kb
Host smart-e15d7f62-56d7-40eb-949a-e0415b9b0958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479258899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2479258899
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1285724443
Short name T828
Test name
Test status
Simulation time 19630995 ps
CPU time 0.81 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 206916 kb
Host smart-32efc021-c47e-4fc8-a481-0c2fd99b7316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285724443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1285724443
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1791833413
Short name T990
Test name
Test status
Simulation time 28966266 ps
CPU time 0.79 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 216392 kb
Host smart-234eaf36-ffb3-4276-ab71-aba6fae49f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791833413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1791833413
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.33481549
Short name T817
Test name
Test status
Simulation time 20572720954 ps
CPU time 150.78 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:05:09 PM PDT 24
Peak memory 225404 kb
Host smart-7c34c895-f42b-4256-a4f6-3459d0db2764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33481549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.33481549
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1082345588
Short name T607
Test name
Test status
Simulation time 244149051302 ps
CPU time 348.41 seconds
Started Jul 31 05:02:36 PM PDT 24
Finished Jul 31 05:08:25 PM PDT 24
Peak memory 257812 kb
Host smart-1bbf0195-2791-41e6-acfd-bdcf9bfd5404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082345588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1082345588
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2919562978
Short name T673
Test name
Test status
Simulation time 665358110 ps
CPU time 13.62 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 241680 kb
Host smart-cf823abf-75ba-41f4-99cd-e9bf4e69e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919562978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2919562978
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.113810433
Short name T665
Test name
Test status
Simulation time 902612979 ps
CPU time 10.73 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 233336 kb
Host smart-d7f44142-37f5-405a-9c8a-30ca416b38e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113810433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.113810433
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3114306261
Short name T724
Test name
Test status
Simulation time 782627279 ps
CPU time 6.56 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 225140 kb
Host smart-389f7d9e-23a8-4ab2-879a-e9062d68cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114306261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3114306261
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4003193869
Short name T939
Test name
Test status
Simulation time 970118030 ps
CPU time 19.4 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 239852 kb
Host smart-36e0e406-e84c-4add-a4ed-023dcc388b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003193869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4003193869
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2879683404
Short name T277
Test name
Test status
Simulation time 381431993 ps
CPU time 2.58 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 225068 kb
Host smart-dd10e2f1-2e3d-4472-8017-b82037f1f326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879683404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2879683404
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2843496888
Short name T522
Test name
Test status
Simulation time 3920320749 ps
CPU time 11.97 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 225160 kb
Host smart-b2e08987-d6dc-4046-8412-d482d4245367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843496888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2843496888
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1047534727
Short name T852
Test name
Test status
Simulation time 2294425805 ps
CPU time 6.44 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 223840 kb
Host smart-dd7c699f-b5c5-4c3b-b870-523d0370aa06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1047534727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1047534727
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3292697465
Short name T158
Test name
Test status
Simulation time 207183138796 ps
CPU time 526.95 seconds
Started Jul 31 05:02:39 PM PDT 24
Finished Jul 31 05:11:26 PM PDT 24
Peak memory 266312 kb
Host smart-6a3868cb-94c9-4e0f-bb58-4dfef828d983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292697465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3292697465
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2905674774
Short name T539
Test name
Test status
Simulation time 27460990295 ps
CPU time 28.07 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 217016 kb
Host smart-3cf9989c-36e2-49af-a9ba-248609f0d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905674774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2905674774
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.363135970
Short name T1022
Test name
Test status
Simulation time 7139222881 ps
CPU time 21.93 seconds
Started Jul 31 05:02:57 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 216928 kb
Host smart-f6eda2fb-8644-4a4f-9985-04ad0fa00270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363135970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.363135970
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1605678483
Short name T42
Test name
Test status
Simulation time 134966439 ps
CPU time 1.23 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 216644 kb
Host smart-50a7b46c-b352-4a98-8121-aa959f92149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605678483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1605678483
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1649018814
Short name T1016
Test name
Test status
Simulation time 243371934 ps
CPU time 1 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 207468 kb
Host smart-bf0d0041-7d9c-40fb-8485-f8378fd72bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649018814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1649018814
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1112068708
Short name T660
Test name
Test status
Simulation time 17687598657 ps
CPU time 23.39 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 252172 kb
Host smart-e237899a-a629-41b8-84c3-1dd95fe35507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112068708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1112068708
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1723531906
Short name T907
Test name
Test status
Simulation time 19249119 ps
CPU time 0.71 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:12 PM PDT 24
Peak memory 206108 kb
Host smart-c5a8cb95-d6a9-48f6-b7ee-a43dbb2a5036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723531906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
723531906
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2714919443
Short name T537
Test name
Test status
Simulation time 668933191 ps
CPU time 4.44 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 225288 kb
Host smart-6012374a-fd04-470d-9665-4cd4383ed174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714919443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2714919443
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4162604917
Short name T571
Test name
Test status
Simulation time 25897392 ps
CPU time 0.83 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:27 PM PDT 24
Peak memory 206888 kb
Host smart-e0ef63a1-87ba-48c2-a3c6-97e8b03a8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162604917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4162604917
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4076435374
Short name T638
Test name
Test status
Simulation time 238485762260 ps
CPU time 113.23 seconds
Started Jul 31 05:01:17 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 249884 kb
Host smart-aad05660-aff6-467d-9002-c53ccecf37a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076435374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4076435374
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1999601731
Short name T996
Test name
Test status
Simulation time 30610703379 ps
CPU time 122.61 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 258124 kb
Host smart-9d768cc0-301b-4a5a-adc5-b268320b2bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999601731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1999601731
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2809747193
Short name T997
Test name
Test status
Simulation time 216783953 ps
CPU time 4.35 seconds
Started Jul 31 05:01:11 PM PDT 24
Finished Jul 31 05:01:15 PM PDT 24
Peak memory 234396 kb
Host smart-2b050891-c81d-453c-baa2-24383b693652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809747193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2809747193
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2150999070
Short name T661
Test name
Test status
Simulation time 2072016152 ps
CPU time 35.5 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:02:00 PM PDT 24
Peak memory 249688 kb
Host smart-287a44d8-74ef-4a9a-ae18-7a205c5e9b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150999070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2150999070
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4245738663
Short name T824
Test name
Test status
Simulation time 1143244525 ps
CPU time 5.84 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 225260 kb
Host smart-a85eb96d-b38e-4a3b-8545-20b49ea31efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245738663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4245738663
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1635837542
Short name T538
Test name
Test status
Simulation time 6890916088 ps
CPU time 19.6 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:36 PM PDT 24
Peak memory 238680 kb
Host smart-179d7451-3f8b-4017-84f8-320bc6e26454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635837542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1635837542
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.854690398
Short name T952
Test name
Test status
Simulation time 18620873 ps
CPU time 1.01 seconds
Started Jul 31 05:01:05 PM PDT 24
Finished Jul 31 05:01:06 PM PDT 24
Peak memory 217116 kb
Host smart-6f3d2ecf-f864-4570-8ed3-b736b299ec66
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854690398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.854690398
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2909891195
Short name T422
Test name
Test status
Simulation time 30731158 ps
CPU time 1.98 seconds
Started Jul 31 05:01:02 PM PDT 24
Finished Jul 31 05:01:04 PM PDT 24
Peak memory 223712 kb
Host smart-ae98a225-68b5-4eca-bf5a-683b95909150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909891195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2909891195
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.280162993
Short name T384
Test name
Test status
Simulation time 549336614 ps
CPU time 5.89 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:19 PM PDT 24
Peak memory 233264 kb
Host smart-5c5c5a1d-2178-4107-b13b-55b3670148a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280162993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.280162993
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.245930717
Short name T346
Test name
Test status
Simulation time 90505762 ps
CPU time 3.91 seconds
Started Jul 31 05:01:18 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 222896 kb
Host smart-98d8e7e0-314e-4b15-a5c1-5da1ea27dd9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=245930717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.245930717
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2616784370
Short name T18
Test name
Test status
Simulation time 186662976 ps
CPU time 1.02 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:14 PM PDT 24
Peak memory 207992 kb
Host smart-48fcfdb1-6ee4-49e4-9386-4813b601c59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616784370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2616784370
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.283909515
Short name T892
Test name
Test status
Simulation time 4399945405 ps
CPU time 28.96 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 217092 kb
Host smart-d573d869-30d3-40e7-9f89-5ec4a5b84c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283909515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.283909515
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3519155187
Short name T74
Test name
Test status
Simulation time 8961286607 ps
CPU time 13.98 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 216908 kb
Host smart-a011b738-f967-4220-b9a5-57883602007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519155187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3519155187
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1506278143
Short name T564
Test name
Test status
Simulation time 276384609 ps
CPU time 1.76 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:18 PM PDT 24
Peak memory 216840 kb
Host smart-b56cada0-63e2-402a-87de-c0880c00f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506278143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1506278143
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1291647888
Short name T786
Test name
Test status
Simulation time 346571481 ps
CPU time 0.92 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 206764 kb
Host smart-b188b1ab-c151-40ea-8b18-3f29eb10fc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291647888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1291647888
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3372624740
Short name T132
Test name
Test status
Simulation time 18690746090 ps
CPU time 25.91 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:01:35 PM PDT 24
Peak memory 233536 kb
Host smart-f88eba1c-4b5f-4d24-9f44-6a085182ccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372624740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3372624740
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1902342339
Short name T475
Test name
Test status
Simulation time 11989667 ps
CPU time 0.73 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 205260 kb
Host smart-b4f01970-acfd-4cce-82bd-6e8b40ffdfaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902342339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1902342339
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2170340005
Short name T451
Test name
Test status
Simulation time 6654640247 ps
CPU time 4.85 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 225208 kb
Host smart-64fce475-ce84-4b6a-ae77-87c894ed34b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170340005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2170340005
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.843766838
Short name T773
Test name
Test status
Simulation time 37202795 ps
CPU time 0.78 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 206912 kb
Host smart-827dd50e-4cbd-4803-900e-1fe06cb5ac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843766838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.843766838
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4268059866
Short name T237
Test name
Test status
Simulation time 16468512123 ps
CPU time 74.9 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:04:10 PM PDT 24
Peak memory 241880 kb
Host smart-4cb44c3b-8631-4689-bd03-2be45976405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268059866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4268059866
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4118731211
Short name T960
Test name
Test status
Simulation time 21293892933 ps
CPU time 89.34 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 267848 kb
Host smart-c93fc19a-71bf-4c35-83b8-ab85dbbeedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118731211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4118731211
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1471296182
Short name T850
Test name
Test status
Simulation time 2408090341 ps
CPU time 50.06 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 238396 kb
Host smart-87258af6-d67f-4f81-a11b-85d30fea34b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471296182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1471296182
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2767148368
Short name T980
Test name
Test status
Simulation time 276863686 ps
CPU time 6.8 seconds
Started Jul 31 05:03:00 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 235576 kb
Host smart-dec5c13b-92d9-4bff-9d27-31c9daaec892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767148368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2767148368
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.412321683
Short name T695
Test name
Test status
Simulation time 5356373926 ps
CPU time 42.9 seconds
Started Jul 31 05:02:32 PM PDT 24
Finished Jul 31 05:03:15 PM PDT 24
Peak memory 241552 kb
Host smart-2a4a146c-f808-46b8-8358-d4939ff729eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412321683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.412321683
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.812764980
Short name T548
Test name
Test status
Simulation time 978184119 ps
CPU time 7.66 seconds
Started Jul 31 05:02:43 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 225140 kb
Host smart-0c844db8-9100-4abb-9f6a-303819ca6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812764980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.812764980
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2291576509
Short name T418
Test name
Test status
Simulation time 106739000 ps
CPU time 1.94 seconds
Started Jul 31 05:02:40 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 223680 kb
Host smart-b5dc7c6f-5030-4a03-99df-872e85f96cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291576509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2291576509
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2648394816
Short name T721
Test name
Test status
Simulation time 159280605 ps
CPU time 2.72 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 225164 kb
Host smart-48cbd35c-7ccf-41ec-ad9d-260d30e89fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648394816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2648394816
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.699010028
Short name T1018
Test name
Test status
Simulation time 1269641012 ps
CPU time 4.69 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:02:58 PM PDT 24
Peak memory 233468 kb
Host smart-a4f962cc-9ddd-4ae9-9b18-b32f7e6d73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699010028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.699010028
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1070929028
Short name T819
Test name
Test status
Simulation time 83300915 ps
CPU time 3.81 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 223040 kb
Host smart-c640885e-5019-4571-a1f6-d33debb27fd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1070929028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1070929028
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4023636792
Short name T1026
Test name
Test status
Simulation time 26659499882 ps
CPU time 248.25 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:07:00 PM PDT 24
Peak memory 253808 kb
Host smart-2aa98df9-5b45-4cee-a396-85ce6fb2cecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023636792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4023636792
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1622956603
Short name T66
Test name
Test status
Simulation time 2614296233 ps
CPU time 9.14 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 217192 kb
Host smart-e62d5ed6-efcb-4cd5-adf1-d8cd65204cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622956603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1622956603
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2999111518
Short name T406
Test name
Test status
Simulation time 2407894141 ps
CPU time 7.82 seconds
Started Jul 31 05:02:34 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 216844 kb
Host smart-ee1915ba-0fdf-4bff-8e7b-6982481a4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999111518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2999111518
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3748421041
Short name T324
Test name
Test status
Simulation time 526673665 ps
CPU time 10.17 seconds
Started Jul 31 05:02:44 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 216768 kb
Host smart-6f955f65-993c-481b-8734-ae7f566b02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748421041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3748421041
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.350152528
Short name T847
Test name
Test status
Simulation time 28735424 ps
CPU time 0.71 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:02:46 PM PDT 24
Peak memory 206404 kb
Host smart-a6887a3b-0d39-42b4-9528-5edfad59408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350152528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.350152528
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3329719878
Short name T606
Test name
Test status
Simulation time 249152590 ps
CPU time 2.25 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:02:49 PM PDT 24
Peak memory 233128 kb
Host smart-55a7bbe5-7c7f-4ae2-9e8f-6c03ce8a5d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329719878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3329719878
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4080087303
Short name T654
Test name
Test status
Simulation time 12850439 ps
CPU time 0.72 seconds
Started Jul 31 05:02:46 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 205732 kb
Host smart-2e86e99b-cd93-4f96-86c9-8c36f68b5428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080087303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4080087303
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3757854438
Short name T397
Test name
Test status
Simulation time 57572122 ps
CPU time 2.23 seconds
Started Jul 31 05:03:05 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 233380 kb
Host smart-adf40a5a-1677-4caf-9ad4-cd3d45a45906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757854438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3757854438
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1435054679
Short name T358
Test name
Test status
Simulation time 13603906 ps
CPU time 0.78 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:50 PM PDT 24
Peak memory 207032 kb
Host smart-81faa614-647b-4ed7-b394-6eb6451247b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435054679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1435054679
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3792610614
Short name T271
Test name
Test status
Simulation time 36433766815 ps
CPU time 273.52 seconds
Started Jul 31 05:02:40 PM PDT 24
Finished Jul 31 05:07:13 PM PDT 24
Peak memory 255264 kb
Host smart-49cd254a-5e50-4fb4-b2f7-bbf9268337d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792610614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3792610614
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.293766156
Short name T189
Test name
Test status
Simulation time 11290981326 ps
CPU time 43.66 seconds
Started Jul 31 05:02:45 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 241660 kb
Host smart-b9723686-930e-4b1c-bf39-9d8e1f948c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293766156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.293766156
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2925116260
Short name T51
Test name
Test status
Simulation time 35395360755 ps
CPU time 345.33 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:08:38 PM PDT 24
Peak memory 265732 kb
Host smart-35df9ab2-991c-4f60-a0e0-058829b42057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925116260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2925116260
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2459191957
Short name T563
Test name
Test status
Simulation time 1718907534 ps
CPU time 22.65 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:03:13 PM PDT 24
Peak memory 237700 kb
Host smart-a70487f5-0a81-40b6-9d1d-459b93c99f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459191957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2459191957
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1221469611
Short name T947
Test name
Test status
Simulation time 7518155295 ps
CPU time 42.46 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 253036 kb
Host smart-d65ffcb8-cdae-445a-b48e-4eb58c2063e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221469611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1221469611
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2182181764
Short name T104
Test name
Test status
Simulation time 334834355 ps
CPU time 4.44 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 225176 kb
Host smart-e28764b6-d120-4913-b07f-5a0b638faeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182181764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2182181764
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2544711414
Short name T231
Test name
Test status
Simulation time 333559621051 ps
CPU time 193.25 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:06:02 PM PDT 24
Peak memory 240712 kb
Host smart-cb6185e4-e244-48c3-ba7b-8f9247e7f724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544711414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2544711414
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3055194822
Short name T289
Test name
Test status
Simulation time 195359212 ps
CPU time 2.9 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 225088 kb
Host smart-230f3bc5-ea57-463b-80c5-2df30bcb173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055194822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3055194822
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1937361019
Short name T940
Test name
Test status
Simulation time 1837097082 ps
CPU time 3.96 seconds
Started Jul 31 05:03:05 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 233332 kb
Host smart-f00563d6-6fca-4475-aac5-3f4b3adbbb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937361019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1937361019
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3043104098
Short name T360
Test name
Test status
Simulation time 615491423 ps
CPU time 7.62 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 222404 kb
Host smart-fbdf8c23-63c9-48a6-bd20-9ccfeb1cece9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3043104098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3043104098
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4062289894
Short name T467
Test name
Test status
Simulation time 7253987227 ps
CPU time 24.2 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:18 PM PDT 24
Peak memory 216788 kb
Host smart-bac750f6-fe4f-400e-9334-6d00dc6d09dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062289894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4062289894
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.697519587
Short name T333
Test name
Test status
Simulation time 2981440657 ps
CPU time 6.29 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:56 PM PDT 24
Peak memory 217028 kb
Host smart-164dcb3c-ab8b-4be3-a5a2-bf9cc0f4ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697519587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.697519587
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2719097587
Short name T894
Test name
Test status
Simulation time 276173769 ps
CPU time 2.98 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 216956 kb
Host smart-0946bbd4-acc0-43e3-bec9-5b3a4521b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719097587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2719097587
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1503931051
Short name T515
Test name
Test status
Simulation time 13960904 ps
CPU time 0.7 seconds
Started Jul 31 05:02:39 PM PDT 24
Finished Jul 31 05:02:40 PM PDT 24
Peak memory 205792 kb
Host smart-f2fdfcb6-b43c-480b-a21f-8e591f50681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503931051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1503931051
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3954067578
Short name T645
Test name
Test status
Simulation time 9869608723 ps
CPU time 29.57 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:03:17 PM PDT 24
Peak memory 233364 kb
Host smart-f64cc0d7-bcc9-4651-9ac9-416007298fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954067578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3954067578
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2984772046
Short name T853
Test name
Test status
Simulation time 22122372 ps
CPU time 0.75 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 206072 kb
Host smart-e700194b-3ca5-45f6-b78e-b2485b923cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984772046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2984772046
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2520633405
Short name T191
Test name
Test status
Simulation time 222986118 ps
CPU time 3.18 seconds
Started Jul 31 05:02:43 PM PDT 24
Finished Jul 31 05:02:46 PM PDT 24
Peak memory 225056 kb
Host smart-a973a9dc-1877-494f-bec4-670513fa229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520633405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2520633405
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3228675770
Short name T813
Test name
Test status
Simulation time 19050171 ps
CPU time 0.73 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:02:49 PM PDT 24
Peak memory 205908 kb
Host smart-47debe7e-e183-41dc-8f63-9dae10830c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228675770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3228675770
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4177418925
Short name T750
Test name
Test status
Simulation time 4805259941 ps
CPU time 99.21 seconds
Started Jul 31 05:02:42 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 257600 kb
Host smart-db6f5840-70c5-4366-b41e-db93501ba3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177418925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4177418925
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2116796981
Short name T670
Test name
Test status
Simulation time 48293354575 ps
CPU time 89.88 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:04:17 PM PDT 24
Peak memory 249764 kb
Host smart-3ff8aca2-7898-45ba-adb8-a43fe3a1df32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116796981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2116796981
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2990557674
Short name T492
Test name
Test status
Simulation time 6953617276 ps
CPU time 23.56 seconds
Started Jul 31 05:02:36 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 241548 kb
Host smart-dca948ca-a5ca-4f5a-b3c2-eb96b6943d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990557674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2990557674
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3726718021
Short name T227
Test name
Test status
Simulation time 5918205864 ps
CPU time 78.07 seconds
Started Jul 31 05:02:33 PM PDT 24
Finished Jul 31 05:03:51 PM PDT 24
Peak memory 255256 kb
Host smart-09ce3f88-30cf-47a4-81d8-8889b746c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726718021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3726718021
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3498040525
Short name T629
Test name
Test status
Simulation time 1167210651 ps
CPU time 15.39 seconds
Started Jul 31 05:02:40 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 225276 kb
Host smart-c8d9ef0d-6e70-4840-b292-eb575fd1b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498040525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3498040525
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.237855519
Short name T827
Test name
Test status
Simulation time 76795258 ps
CPU time 2.11 seconds
Started Jul 31 05:02:39 PM PDT 24
Finished Jul 31 05:02:42 PM PDT 24
Peak memory 224168 kb
Host smart-a95e8b0b-4bac-4a6d-838e-b69df418ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237855519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.237855519
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2533176340
Short name T753
Test name
Test status
Simulation time 503284740 ps
CPU time 3.64 seconds
Started Jul 31 05:02:31 PM PDT 24
Finished Jul 31 05:02:35 PM PDT 24
Peak memory 233256 kb
Host smart-f3e3ca38-befc-4dd2-aa62-30f8e54c02eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533176340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2533176340
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.411408399
Short name T689
Test name
Test status
Simulation time 640030951 ps
CPU time 3.72 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 225104 kb
Host smart-54fe64b5-f636-43ca-98ba-c0aa28537aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411408399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.411408399
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.295420161
Short name T712
Test name
Test status
Simulation time 3687930163 ps
CPU time 7.09 seconds
Started Jul 31 05:02:56 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 224832 kb
Host smart-3f16f33a-7111-4c0e-8aee-5e429c17100e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=295420161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.295420161
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1280611724
Short name T735
Test name
Test status
Simulation time 240522356 ps
CPU time 0.9 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:02:48 PM PDT 24
Peak memory 206984 kb
Host smart-037dea59-f443-4942-8ba7-0940ac08c611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280611724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1280611724
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.986056150
Short name T457
Test name
Test status
Simulation time 1678908060 ps
CPU time 11.89 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 216912 kb
Host smart-550d78a1-cedf-43b5-a8cf-83499a79bd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986056150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.986056150
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1884821907
Short name T924
Test name
Test status
Simulation time 936282616 ps
CPU time 4.99 seconds
Started Jul 31 05:02:38 PM PDT 24
Finished Jul 31 05:02:43 PM PDT 24
Peak memory 216852 kb
Host smart-dd868703-de50-4246-a507-304c7532efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884821907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1884821907
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1129660423
Short name T830
Test name
Test status
Simulation time 64293951 ps
CPU time 1.4 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 216940 kb
Host smart-9060d304-7eb4-47bd-9e98-95d658e47c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129660423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1129660423
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2611624292
Short name T411
Test name
Test status
Simulation time 19289432 ps
CPU time 0.73 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:52 PM PDT 24
Peak memory 206492 kb
Host smart-1ab06d6e-ad7c-49a7-a33c-7738b8a81856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611624292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2611624292
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3907960528
Short name T345
Test name
Test status
Simulation time 50224649 ps
CPU time 2.14 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:02:58 PM PDT 24
Peak memory 225272 kb
Host smart-a0164029-2c4e-4c2e-aeac-caa79a361d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907960528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3907960528
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1266397221
Short name T1011
Test name
Test status
Simulation time 25158640 ps
CPU time 0.74 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 205164 kb
Host smart-75d93336-3950-413f-8d16-0395d118596e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266397221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1266397221
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1198736294
Short name T520
Test name
Test status
Simulation time 377928039 ps
CPU time 3.45 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:02:58 PM PDT 24
Peak memory 233268 kb
Host smart-179b4918-300a-48b5-b73c-0e73b1abb647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198736294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1198736294
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1863865831
Short name T342
Test name
Test status
Simulation time 19431455 ps
CPU time 0.76 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 206312 kb
Host smart-a4812c70-cd9a-4df0-990c-2510bc911a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863865831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1863865831
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1288970005
Short name T361
Test name
Test status
Simulation time 7524847625 ps
CPU time 80.78 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 249844 kb
Host smart-fc301215-0b2b-4c58-8fdc-1549c558e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288970005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1288970005
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2874967065
Short name T209
Test name
Test status
Simulation time 18196686818 ps
CPU time 77.86 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:04:10 PM PDT 24
Peak memory 233564 kb
Host smart-9b9e455a-2a95-43bd-a403-d8c81da81ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874967065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2874967065
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3541786879
Short name T988
Test name
Test status
Simulation time 7816549585 ps
CPU time 33.16 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 237124 kb
Host smart-84b4d2bd-2051-457b-9515-d9fbf4e179a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541786879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3541786879
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1248460412
Short name T849
Test name
Test status
Simulation time 102118366239 ps
CPU time 169.16 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:05:50 PM PDT 24
Peak memory 249716 kb
Host smart-95c640c7-9d30-435f-9b16-c7f0bcd2f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248460412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1248460412
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1184197371
Short name T258
Test name
Test status
Simulation time 596905105 ps
CPU time 4.94 seconds
Started Jul 31 05:02:42 PM PDT 24
Finished Jul 31 05:02:47 PM PDT 24
Peak memory 228620 kb
Host smart-1261beed-65a2-4f7d-a484-1e5f3b6a575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184197371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1184197371
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2477699114
Short name T88
Test name
Test status
Simulation time 1824710125 ps
CPU time 9.38 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 233388 kb
Host smart-a5ac1760-5988-4b6e-9f9d-54b73aa2d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477699114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2477699114
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1118268036
Short name T50
Test name
Test status
Simulation time 5360441734 ps
CPU time 17.96 seconds
Started Jul 31 05:02:56 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 240976 kb
Host smart-c91ee18a-7b02-4f91-ada7-cdab955412b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118268036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1118268036
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.104746604
Short name T709
Test name
Test status
Simulation time 321967886 ps
CPU time 2.23 seconds
Started Jul 31 05:02:51 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 225092 kb
Host smart-cf52feef-d0a3-455f-90ff-c1b6b1ab462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104746604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.104746604
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1979877872
Short name T150
Test name
Test status
Simulation time 1946718274 ps
CPU time 15.34 seconds
Started Jul 31 05:02:56 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 223052 kb
Host smart-5fe37b36-a131-48bf-9be5-9781ccb5bc46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979877872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1979877872
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2397438217
Short name T20
Test name
Test status
Simulation time 2757254838 ps
CPU time 27.79 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:35 PM PDT 24
Peak memory 233504 kb
Host smart-4e96b88a-d4ee-4f8c-a2dc-50c0bd1f11a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397438217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2397438217
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2620196928
Short name T329
Test name
Test status
Simulation time 1869614831 ps
CPU time 9.09 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 220264 kb
Host smart-8da6b9ab-f003-42c9-8f4d-2a0852da9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620196928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2620196928
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1989890849
Short name T592
Test name
Test status
Simulation time 6055844453 ps
CPU time 8.13 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 216980 kb
Host smart-42b5caa0-192d-4551-8d73-0d0dd3b4aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989890849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1989890849
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3311426053
Short name T777
Test name
Test status
Simulation time 64189923 ps
CPU time 1.71 seconds
Started Jul 31 05:02:57 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 216920 kb
Host smart-36f47855-d7ad-4dd3-8e8b-ac0d208b144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311426053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3311426053
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3411528432
Short name T430
Test name
Test status
Simulation time 31218291 ps
CPU time 0.88 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 207564 kb
Host smart-92276246-8054-4e2d-b3b8-c40af039e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411528432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3411528432
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.925351071
Short name T210
Test name
Test status
Simulation time 26917000580 ps
CPU time 12.21 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 233480 kb
Host smart-0d8b4f9a-3409-462e-8463-3b5554680b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925351071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.925351071
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2703926182
Short name T612
Test name
Test status
Simulation time 23683956 ps
CPU time 0.75 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 206088 kb
Host smart-ea72db9d-4dfd-4458-ac02-cd1b03a9ecab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703926182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2703926182
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4180460295
Short name T257
Test name
Test status
Simulation time 31206557 ps
CPU time 2.16 seconds
Started Jul 31 05:02:49 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 225040 kb
Host smart-fe72184c-5173-4e2e-82fa-4861f9feb495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180460295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4180460295
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2043672204
Short name T595
Test name
Test status
Simulation time 52881482 ps
CPU time 0.75 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:02:53 PM PDT 24
Peak memory 206912 kb
Host smart-30af7003-d482-4453-933e-63f670ec2743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043672204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2043672204
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2790043158
Short name T879
Test name
Test status
Simulation time 47421156047 ps
CPU time 157.73 seconds
Started Jul 31 05:02:52 PM PDT 24
Finished Jul 31 05:05:30 PM PDT 24
Peak memory 252984 kb
Host smart-ce642a4d-d493-4ccf-a028-00c5704b11ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790043158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2790043158
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2231079299
Short name T955
Test name
Test status
Simulation time 15238529033 ps
CPU time 151.41 seconds
Started Jul 31 05:02:47 PM PDT 24
Finished Jul 31 05:05:18 PM PDT 24
Peak memory 251200 kb
Host smart-5b5ede24-2d3f-43cc-bf51-56dd6edb5b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231079299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2231079299
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3989569463
Short name T53
Test name
Test status
Simulation time 5183612038 ps
CPU time 34.21 seconds
Started Jul 31 05:03:00 PM PDT 24
Finished Jul 31 05:03:34 PM PDT 24
Peak memory 234488 kb
Host smart-4f1d2398-5e50-4126-824c-a1007d0a356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989569463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3989569463
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3866668318
Short name T500
Test name
Test status
Simulation time 135627390 ps
CPU time 5.47 seconds
Started Jul 31 05:02:55 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 236856 kb
Host smart-bb9fbfbe-51cc-4c5b-95b3-4fb29a6f19ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866668318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3866668318
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.654240827
Short name T288
Test name
Test status
Simulation time 215963312651 ps
CPU time 365.39 seconds
Started Jul 31 05:02:48 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 265432 kb
Host smart-b7ef834d-956a-46e3-bed8-d90ca4683b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654240827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.654240827
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3304795659
Short name T577
Test name
Test status
Simulation time 20640659512 ps
CPU time 15.02 seconds
Started Jul 31 05:02:44 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 233504 kb
Host smart-6ef2909b-9982-4395-9ee1-8595e1bb9b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304795659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3304795659
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3496701687
Short name T256
Test name
Test status
Simulation time 391627695 ps
CPU time 7.83 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:03:01 PM PDT 24
Peak memory 233384 kb
Host smart-857ac97b-3c99-4d8b-8212-a1c6573fb75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496701687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3496701687
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.69102183
Short name T780
Test name
Test status
Simulation time 13024647884 ps
CPU time 8.96 seconds
Started Jul 31 05:02:57 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 233276 kb
Host smart-1638e4a1-ed29-4fc2-9ee2-e7183799c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69102183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.69102183
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.539259596
Short name T207
Test name
Test status
Simulation time 2971659578 ps
CPU time 10.77 seconds
Started Jul 31 05:03:03 PM PDT 24
Finished Jul 31 05:03:13 PM PDT 24
Peak memory 233424 kb
Host smart-f5559afb-1ceb-4786-b66f-039c42b727ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539259596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.539259596
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3670186350
Short name T377
Test name
Test status
Simulation time 504173580 ps
CPU time 4.05 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 223716 kb
Host smart-44d73abf-fd2e-46d5-8acf-d39410ceea1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3670186350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3670186350
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3984217293
Short name T602
Test name
Test status
Simulation time 7057128814 ps
CPU time 28.34 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 217068 kb
Host smart-41c67e57-fa7e-43ec-b91d-c241ee9faa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984217293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3984217293
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2555038100
Short name T437
Test name
Test status
Simulation time 7739052772 ps
CPU time 7.3 seconds
Started Jul 31 05:02:59 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 217056 kb
Host smart-6198359a-ab3f-4aa0-ac9a-49a8e0e95ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555038100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2555038100
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3713223439
Short name T364
Test name
Test status
Simulation time 87895987 ps
CPU time 1.3 seconds
Started Jul 31 05:02:50 PM PDT 24
Finished Jul 31 05:02:51 PM PDT 24
Peak memory 216820 kb
Host smart-aebc2495-a6f8-4d3d-b463-c2dcbf91c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713223439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3713223439
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.765972375
Short name T338
Test name
Test status
Simulation time 24685497 ps
CPU time 0.75 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 206568 kb
Host smart-e2df06ab-d9d5-4e58-98fc-548ccee8d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765972375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.765972375
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3135859785
Short name T743
Test name
Test status
Simulation time 149885454 ps
CPU time 2.2 seconds
Started Jul 31 05:02:41 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 232948 kb
Host smart-446819b2-d711-460d-a28f-90f7e3693e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135859785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3135859785
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.681513872
Short name T640
Test name
Test status
Simulation time 14198974 ps
CPU time 0.7 seconds
Started Jul 31 05:02:59 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 205168 kb
Host smart-b3250176-b668-4367-ab28-d2f6a3af1a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681513872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.681513872
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3977631495
Short name T283
Test name
Test status
Simulation time 1648725556 ps
CPU time 15.21 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 233296 kb
Host smart-b75f9b7e-4cdf-4aa3-89cb-75fe1faa1b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977631495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3977631495
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.285593479
Short name T821
Test name
Test status
Simulation time 13294444 ps
CPU time 0.8 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 207012 kb
Host smart-9d6b32ff-c840-44fd-b65b-9f2c74ec3ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285593479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.285593479
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1166595693
Short name T63
Test name
Test status
Simulation time 520364884 ps
CPU time 9.83 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 234428 kb
Host smart-cd09af5d-1aa6-4a7d-aa85-75c50b0ef6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166595693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1166595693
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.600252447
Short name T593
Test name
Test status
Simulation time 5064175808 ps
CPU time 52.79 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:47 PM PDT 24
Peak memory 241604 kb
Host smart-92071b20-04fc-4ecd-a19e-ce79efebda7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600252447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.600252447
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2919516594
Short name T918
Test name
Test status
Simulation time 37433602487 ps
CPU time 269.35 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:07:31 PM PDT 24
Peak memory 266308 kb
Host smart-59dd9f72-c7d9-4a4f-bef7-395fbb5ca908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919516594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2919516594
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3191074988
Short name T941
Test name
Test status
Simulation time 259351035 ps
CPU time 6.89 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 233296 kb
Host smart-ddda6819-7b29-43f3-9321-31f82f6a01b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191074988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3191074988
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2017589706
Short name T43
Test name
Test status
Simulation time 2935246765 ps
CPU time 60.22 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 253596 kb
Host smart-ce746645-6a26-4053-8c60-1c1d27cf1e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017589706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2017589706
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4280505802
Short name T835
Test name
Test status
Simulation time 528735721 ps
CPU time 6.08 seconds
Started Jul 31 05:03:09 PM PDT 24
Finished Jul 31 05:03:15 PM PDT 24
Peak memory 225088 kb
Host smart-3bcf1e43-2efb-4740-b0cb-8f5a57266945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280505802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4280505802
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1224944030
Short name T13
Test name
Test status
Simulation time 2397846195 ps
CPU time 23.25 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:33 PM PDT 24
Peak memory 233380 kb
Host smart-221575cb-ba43-4af8-99f5-f11775d3c226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224944030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1224944030
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2740413024
Short name T436
Test name
Test status
Simulation time 34617145 ps
CPU time 2.28 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 232976 kb
Host smart-84ee5377-cf64-4d3c-b557-ad2f8a59a779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740413024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2740413024
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.688243931
Short name T874
Test name
Test status
Simulation time 1379765054 ps
CPU time 6.21 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:16 PM PDT 24
Peak memory 233472 kb
Host smart-9d547b93-0254-42de-b14b-accd7715640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688243931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.688243931
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3160835886
Short name T716
Test name
Test status
Simulation time 584549841 ps
CPU time 3.58 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 219456 kb
Host smart-24b412b5-be3c-458d-bcbe-5f4f50ea06fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160835886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3160835886
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3967403385
Short name T697
Test name
Test status
Simulation time 3759425271 ps
CPU time 19.19 seconds
Started Jul 31 05:02:56 PM PDT 24
Finished Jul 31 05:03:16 PM PDT 24
Peak memory 216864 kb
Host smart-d7606b42-af20-440b-9037-bd146392c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967403385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3967403385
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2709656972
Short name T632
Test name
Test status
Simulation time 11256404 ps
CPU time 0.69 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 206164 kb
Host smart-b5a8e568-b9a1-41aa-8b06-09f88804b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709656972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2709656972
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1749286127
Short name T767
Test name
Test status
Simulation time 81631866 ps
CPU time 0.86 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 207500 kb
Host smart-12a3baa4-1cf3-45a3-afad-4cfebbe6302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749286127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1749286127
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.683136200
Short name T671
Test name
Test status
Simulation time 43895125 ps
CPU time 0.78 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 206476 kb
Host smart-33b0388e-1407-49bd-9baf-39973382e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683136200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.683136200
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1612177813
Short name T733
Test name
Test status
Simulation time 1462462636 ps
CPU time 5.61 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 225100 kb
Host smart-f410bcaa-c0e4-44aa-b20c-95d872101d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612177813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1612177813
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.478364589
Short name T525
Test name
Test status
Simulation time 14895800 ps
CPU time 0.77 seconds
Started Jul 31 05:02:57 PM PDT 24
Finished Jul 31 05:02:58 PM PDT 24
Peak memory 205156 kb
Host smart-b386a83d-d862-4f18-8bb1-e4f640fc2029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478364589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.478364589
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3444735076
Short name T400
Test name
Test status
Simulation time 36887373 ps
CPU time 2.24 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 233004 kb
Host smart-8e921064-efb5-4adb-ba66-efbbad6201a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444735076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3444735076
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3461329607
Short name T535
Test name
Test status
Simulation time 37428296 ps
CPU time 0.7 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:02:59 PM PDT 24
Peak memory 206360 kb
Host smart-2969324c-cbda-403e-b5d5-67a5e459e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461329607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3461329607
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1099646938
Short name T557
Test name
Test status
Simulation time 57559735298 ps
CPU time 84.49 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 236644 kb
Host smart-accd2c23-2640-4297-be1e-9bc2a42102e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099646938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1099646938
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.884858981
Short name T138
Test name
Test status
Simulation time 16572119590 ps
CPU time 97.74 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:04:38 PM PDT 24
Peak memory 267844 kb
Host smart-4987d3b3-82ba-4dd1-b5b6-33e820d08c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884858981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.884858981
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1063937057
Short name T307
Test name
Test status
Simulation time 7046599906 ps
CPU time 117.98 seconds
Started Jul 31 05:02:59 PM PDT 24
Finished Jul 31 05:04:57 PM PDT 24
Peak memory 262392 kb
Host smart-3f657540-7fc3-4e05-a1d1-7f1235f83bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063937057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1063937057
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2257504981
Short name T1004
Test name
Test status
Simulation time 705919977 ps
CPU time 14.02 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 224968 kb
Host smart-ddde3c33-73a1-464c-91ce-1abd0e2afd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257504981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2257504981
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.206141673
Short name T653
Test name
Test status
Simulation time 18774466311 ps
CPU time 61.1 seconds
Started Jul 31 05:03:09 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 249756 kb
Host smart-52c14b70-dc16-4542-af02-89b1cd317f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206141673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.206141673
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2830144800
Short name T220
Test name
Test status
Simulation time 289821053 ps
CPU time 5.93 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:17 PM PDT 24
Peak memory 233508 kb
Host smart-600de3c2-c99d-434d-8450-6b502b38ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830144800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2830144800
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1926278233
Short name T245
Test name
Test status
Simulation time 5888173530 ps
CPU time 47.43 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:03:45 PM PDT 24
Peak memory 225268 kb
Host smart-6d5c25cc-5521-4895-920c-a04329ca7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926278233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1926278233
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1466485286
Short name T103
Test name
Test status
Simulation time 282954257 ps
CPU time 2.11 seconds
Started Jul 31 05:02:58 PM PDT 24
Finished Jul 31 05:03:00 PM PDT 24
Peak memory 224444 kb
Host smart-e25f386d-06fd-41c9-be00-47b4a8592060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466485286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1466485286
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3429768145
Short name T801
Test name
Test status
Simulation time 1378537006 ps
CPU time 11.07 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:13 PM PDT 24
Peak memory 240140 kb
Host smart-77e44ae2-3f6a-4f3e-b108-d0dc2e12f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429768145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3429768145
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1256089359
Short name T372
Test name
Test status
Simulation time 517906640 ps
CPU time 4.08 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 220892 kb
Host smart-7d2f95c2-f7ce-461a-ab39-988aa4a68528
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1256089359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1256089359
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1945029541
Short name T140
Test name
Test status
Simulation time 34816688425 ps
CPU time 173.6 seconds
Started Jul 31 05:03:01 PM PDT 24
Finished Jul 31 05:05:55 PM PDT 24
Peak memory 255028 kb
Host smart-ac83f4de-5df6-4131-a94f-9b114c2b1f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945029541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1945029541
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1312480809
Short name T860
Test name
Test status
Simulation time 13971121 ps
CPU time 0.71 seconds
Started Jul 31 05:02:53 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 206056 kb
Host smart-4d9ced97-5ea1-45c6-a21e-a0120a2ae9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312480809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1312480809
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2090691675
Short name T885
Test name
Test status
Simulation time 894716670 ps
CPU time 1.88 seconds
Started Jul 31 05:03:05 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 208548 kb
Host smart-c15accc9-04c1-4976-aa18-e2b0501c52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090691675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2090691675
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1775200275
Short name T321
Test name
Test status
Simulation time 61242633 ps
CPU time 1.75 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 216972 kb
Host smart-63adf167-222c-403c-b7c9-076d313b7fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775200275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1775200275
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3531818449
Short name T485
Test name
Test status
Simulation time 46857050 ps
CPU time 0.81 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 206504 kb
Host smart-931d4e2b-dbab-4613-b10b-d985844bab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531818449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3531818449
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1735272742
Short name T648
Test name
Test status
Simulation time 633446191 ps
CPU time 5.45 seconds
Started Jul 31 05:02:56 PM PDT 24
Finished Jul 31 05:03:02 PM PDT 24
Peak memory 233280 kb
Host smart-0282821f-eb42-4cc8-8d11-a44fcf75559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735272742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1735272742
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.575494426
Short name T906
Test name
Test status
Simulation time 122827338 ps
CPU time 0.73 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 205764 kb
Host smart-d362883f-c622-419b-8a02-ad1b6f1a0ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575494426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.575494426
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1093800640
Short name T982
Test name
Test status
Simulation time 405837158 ps
CPU time 3.49 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 233276 kb
Host smart-d9e59337-1cd5-4b0e-9186-51fe4f396c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093800640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1093800640
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2036975479
Short name T877
Test name
Test status
Simulation time 52261456 ps
CPU time 0.76 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 207012 kb
Host smart-a1b6cf2e-0085-4377-b106-a7257197199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036975479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2036975479
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4212004892
Short name T1006
Test name
Test status
Simulation time 138645994505 ps
CPU time 167.4 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:05:54 PM PDT 24
Peak memory 254556 kb
Host smart-f7bb967b-023e-4a76-8bba-66dc00fc1cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212004892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4212004892
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1874166149
Short name T311
Test name
Test status
Simulation time 29215069158 ps
CPU time 68.17 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 243404 kb
Host smart-6026a48a-7455-4a08-832f-46c7e185de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874166149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1874166149
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3885626560
Short name T897
Test name
Test status
Simulation time 58809787381 ps
CPU time 116.52 seconds
Started Jul 31 05:03:05 PM PDT 24
Finished Jul 31 05:05:02 PM PDT 24
Peak memory 249848 kb
Host smart-ca8baa42-a983-4394-a58f-b225d69e58d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885626560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3885626560
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3327076250
Short name T856
Test name
Test status
Simulation time 881588078 ps
CPU time 12.3 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 233356 kb
Host smart-f6a76efd-8385-4d0c-a8aa-fc3f3f043cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327076250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3327076250
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.160099162
Short name T190
Test name
Test status
Simulation time 80708567713 ps
CPU time 134.06 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:05:22 PM PDT 24
Peak memory 255084 kb
Host smart-6192dd46-1677-4a0e-bfe4-4eb44ff7c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160099162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.160099162
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3710974206
Short name T247
Test name
Test status
Simulation time 1252424210 ps
CPU time 6.19 seconds
Started Jul 31 05:02:57 PM PDT 24
Finished Jul 31 05:03:03 PM PDT 24
Peak memory 233408 kb
Host smart-4d5dcd93-246d-4bfc-8075-c391bfd61388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710974206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3710974206
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.526653681
Short name T948
Test name
Test status
Simulation time 18071888602 ps
CPU time 108.84 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:04:59 PM PDT 24
Peak memory 250796 kb
Host smart-46d52209-41c5-4c53-b197-89a9ddc91546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526653681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.526653681
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2023237977
Short name T199
Test name
Test status
Simulation time 75343313920 ps
CPU time 15.71 seconds
Started Jul 31 05:03:04 PM PDT 24
Finished Jul 31 05:03:20 PM PDT 24
Peak memory 241608 kb
Host smart-77b4892a-4d2d-49b5-8e7a-c2bfd9c3849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023237977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2023237977
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.109453594
Short name T509
Test name
Test status
Simulation time 29741566811 ps
CPU time 23.25 seconds
Started Jul 31 05:03:27 PM PDT 24
Finished Jul 31 05:03:50 PM PDT 24
Peak memory 241248 kb
Host smart-0c8330e9-8209-4d99-8098-f87589b3369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109453594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.109453594
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3326474180
Short name T837
Test name
Test status
Simulation time 147069873 ps
CPU time 4.57 seconds
Started Jul 31 05:03:02 PM PDT 24
Finished Jul 31 05:03:07 PM PDT 24
Peak memory 223624 kb
Host smart-6a5f117e-38b4-4fec-b5e3-be8c5b9a4dae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3326474180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3326474180
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2950501905
Short name T173
Test name
Test status
Simulation time 64331131 ps
CPU time 0.9 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 207172 kb
Host smart-43a0409e-5369-4b3f-80b0-4f79ea1bad38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950501905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2950501905
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1273219723
Short name T925
Test name
Test status
Simulation time 2090759546 ps
CPU time 20.75 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 220380 kb
Host smart-409782a3-c33c-402d-ab17-2608fc497fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273219723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1273219723
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1479919154
Short name T936
Test name
Test status
Simulation time 816737242 ps
CPU time 5.61 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:15 PM PDT 24
Peak memory 216892 kb
Host smart-a3ea2fb3-d61b-421e-a86a-e0ea853963b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479919154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1479919154
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3568608478
Short name T893
Test name
Test status
Simulation time 50343998 ps
CPU time 0.87 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 206564 kb
Host smart-b807606c-78d2-4bef-b105-ec6065a10921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568608478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3568608478
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1233675743
Short name T910
Test name
Test status
Simulation time 168104293 ps
CPU time 0.89 seconds
Started Jul 31 05:02:54 PM PDT 24
Finished Jul 31 05:02:55 PM PDT 24
Peak memory 207404 kb
Host smart-4efe9f22-8766-4ae1-b5c1-ec687f5944ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233675743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1233675743
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4051033040
Short name T284
Test name
Test status
Simulation time 34675293682 ps
CPU time 9.2 seconds
Started Jul 31 05:02:59 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 233404 kb
Host smart-c93b7de2-c212-416b-8661-250244c46b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051033040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4051033040
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2305154960
Short name T68
Test name
Test status
Simulation time 15973176 ps
CPU time 0.72 seconds
Started Jul 31 05:03:19 PM PDT 24
Finished Jul 31 05:03:20 PM PDT 24
Peak memory 206072 kb
Host smart-d093f2d1-9447-4b19-997d-83ceea33a6f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305154960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2305154960
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4103334502
Short name T641
Test name
Test status
Simulation time 134938644 ps
CPU time 3.51 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:18 PM PDT 24
Peak memory 233404 kb
Host smart-97847e1e-2f02-46bd-a162-6a4e2df70a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103334502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4103334502
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1125377828
Short name T547
Test name
Test status
Simulation time 14590897 ps
CPU time 0.76 seconds
Started Jul 31 05:03:05 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 207004 kb
Host smart-ce107f89-0e43-49ec-b0be-ededf1b9692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125377828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1125377828
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2870618034
Short name T376
Test name
Test status
Simulation time 72549142 ps
CPU time 0.81 seconds
Started Jul 31 05:03:00 PM PDT 24
Finished Jul 31 05:03:01 PM PDT 24
Peak memory 216676 kb
Host smart-094c6f1d-6fab-45be-be4c-7fcb82cc884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870618034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2870618034
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2735485266
Short name T809
Test name
Test status
Simulation time 6599577714 ps
CPU time 113.16 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:05:06 PM PDT 24
Peak memory 267236 kb
Host smart-03fe6d83-decc-4260-8509-eb002f8bce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735485266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2735485266
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3679772462
Short name T611
Test name
Test status
Simulation time 26857552605 ps
CPU time 106.12 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:04:58 PM PDT 24
Peak memory 266380 kb
Host smart-a5db1310-6273-42ce-9374-4f4334fc44e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679772462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3679772462
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2946269856
Short name T945
Test name
Test status
Simulation time 231163670 ps
CPU time 4.86 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 235944 kb
Host smart-fea383d0-bad6-48f1-818d-195d22c9e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946269856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2946269856
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.10205856
Short name T621
Test name
Test status
Simulation time 6420767386 ps
CPU time 33.38 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:40 PM PDT 24
Peak memory 252120 kb
Host smart-32960f8a-ceeb-4a93-89b3-00c707c48fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10205856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.10205856
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1982166010
Short name T823
Test name
Test status
Simulation time 2800528215 ps
CPU time 29.5 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 233436 kb
Host smart-d289167c-a0a2-4d03-9e7d-b0e77d87e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982166010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1982166010
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3202205117
Short name T814
Test name
Test status
Simulation time 279639936 ps
CPU time 4.31 seconds
Started Jul 31 05:02:59 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 225200 kb
Host smart-b323ce8b-2782-48b8-9938-043f5963fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202205117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3202205117
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.963089762
Short name T878
Test name
Test status
Simulation time 1780127151 ps
CPU time 4.4 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 225172 kb
Host smart-ca21f8de-0f35-4651-9a1f-7c53082f39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963089762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.963089762
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.21537346
Short name T540
Test name
Test status
Simulation time 937928549 ps
CPU time 3.97 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 233428 kb
Host smart-eb495236-1f1d-403e-a91a-7edefca15fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21537346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.21537346
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1472170180
Short name T351
Test name
Test status
Simulation time 90158295 ps
CPU time 3.52 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 223104 kb
Host smart-10043d43-3097-4ad2-a7ad-541f1f115bb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472170180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1472170180
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2979249110
Short name T157
Test name
Test status
Simulation time 13590572829 ps
CPU time 79.33 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:04:25 PM PDT 24
Peak memory 266900 kb
Host smart-c1f1188e-db4c-470f-b556-4bbf6ca3879a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979249110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2979249110
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2572113556
Short name T891
Test name
Test status
Simulation time 3263207516 ps
CPU time 13.86 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 217212 kb
Host smart-e271cbc3-0d1b-449b-879b-970f63299a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572113556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2572113556
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2887632868
Short name T1009
Test name
Test status
Simulation time 1067252617 ps
CPU time 1.61 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 208476 kb
Host smart-4de52eb6-af64-46e8-bf67-4c851efaf49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887632868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2887632868
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3489269108
Short name T484
Test name
Test status
Simulation time 219722197 ps
CPU time 1.34 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:09 PM PDT 24
Peak memory 216960 kb
Host smart-acddf510-999a-4202-8201-501f1163c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489269108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3489269108
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1782781312
Short name T393
Test name
Test status
Simulation time 15823174 ps
CPU time 0.72 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:12 PM PDT 24
Peak memory 206408 kb
Host smart-64f571bb-9032-447a-94fc-48e6a5c4f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782781312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1782781312
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1643598430
Short name T636
Test name
Test status
Simulation time 22787239195 ps
CPU time 15.76 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 233424 kb
Host smart-afc7176e-db9a-4895-bb26-8067a249c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643598430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1643598430
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3037104669
Short name T450
Test name
Test status
Simulation time 52261903 ps
CPU time 0.76 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:08 PM PDT 24
Peak memory 205160 kb
Host smart-30cffd37-8b98-4b44-a1f4-8c6660608b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037104669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3037104669
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3075805664
Short name T637
Test name
Test status
Simulation time 120454053 ps
CPU time 2.57 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:15 PM PDT 24
Peak memory 233236 kb
Host smart-f0a213ee-89fa-4186-a0e8-aa6bcd673c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075805664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3075805664
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.833094029
Short name T429
Test name
Test status
Simulation time 17672431 ps
CPU time 0.78 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:18 PM PDT 24
Peak memory 207000 kb
Host smart-5eb8eda2-6fa2-48ee-86d5-78efdf3ce0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833094029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.833094029
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2605770968
Short name T674
Test name
Test status
Simulation time 2583141325 ps
CPU time 46.59 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:58 PM PDT 24
Peak memory 249608 kb
Host smart-e710d8bf-514a-4be1-a295-504f4d0aa0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605770968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2605770968
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2121273610
Short name T772
Test name
Test status
Simulation time 1203588229 ps
CPU time 16.69 seconds
Started Jul 31 05:03:06 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 218204 kb
Host smart-6cfa9ae5-2164-4aad-b62c-1876806e6188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121273610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2121273610
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.582483066
Short name T799
Test name
Test status
Simulation time 1548298288 ps
CPU time 27.18 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:43 PM PDT 24
Peak memory 225128 kb
Host smart-444487a6-e469-4a91-a32e-5428e5af36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582483066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.582483066
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1616581113
Short name T658
Test name
Test status
Simulation time 52280264597 ps
CPU time 119.03 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:05:12 PM PDT 24
Peak memory 251564 kb
Host smart-1afae07f-cfb6-4139-a5c9-ae73dc29096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616581113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1616581113
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1854697528
Short name T536
Test name
Test status
Simulation time 45414498994 ps
CPU time 21.21 seconds
Started Jul 31 05:03:03 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 233380 kb
Host smart-cd55d410-6972-46f2-8f43-27432aa501d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854697528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1854697528
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2625136122
Short name T943
Test name
Test status
Simulation time 117075455 ps
CPU time 2.59 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 232968 kb
Host smart-30848a33-9647-4c33-8508-5680ff2dbed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625136122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2625136122
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3594399409
Short name T822
Test name
Test status
Simulation time 92157102 ps
CPU time 3.43 seconds
Started Jul 31 05:03:07 PM PDT 24
Finished Jul 31 05:03:11 PM PDT 24
Peak memory 232944 kb
Host smart-7ec9bbd0-469a-452d-bb24-b6c766bf5bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594399409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3594399409
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.577915559
Short name T904
Test name
Test status
Simulation time 44922694271 ps
CPU time 36.07 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 241204 kb
Host smart-e5740d08-3fc3-4613-9bce-172d477cc468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577915559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.577915559
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.470965788
Short name T501
Test name
Test status
Simulation time 177504180 ps
CPU time 3.76 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 223112 kb
Host smart-d531ff35-472d-444e-97d3-67c1fede62e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=470965788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.470965788
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1639763858
Short name T155
Test name
Test status
Simulation time 43997935967 ps
CPU time 189.93 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:06:18 PM PDT 24
Peak memory 262412 kb
Host smart-57bcb005-d9a4-4627-8165-04c45fa0e369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639763858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1639763858
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.42558651
Short name T30
Test name
Test status
Simulation time 40173875769 ps
CPU time 37.51 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:56 PM PDT 24
Peak memory 216908 kb
Host smart-2a342202-0756-49af-b30d-6d5b28e7dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42558651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.42558651
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.486960323
Short name T888
Test name
Test status
Simulation time 469605301 ps
CPU time 2.31 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:36 PM PDT 24
Peak memory 217024 kb
Host smart-40b85947-cd90-4709-b763-2ba2336bcacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486960323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.486960323
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1902669212
Short name T347
Test name
Test status
Simulation time 988379735 ps
CPU time 1.46 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:10 PM PDT 24
Peak memory 216852 kb
Host smart-51bb305b-26d4-47c4-8e47-856f4d5903b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902669212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1902669212
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2770620778
Short name T800
Test name
Test status
Simulation time 22725781 ps
CPU time 0.68 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:14 PM PDT 24
Peak memory 206496 kb
Host smart-bdfad41e-4407-4ca3-9e29-dac16f487e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770620778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2770620778
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.994724697
Short name T510
Test name
Test status
Simulation time 57301097706 ps
CPU time 11.69 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 233352 kb
Host smart-3077ab5f-633e-4df0-a1c1-d5e8cd928d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994724697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.994724697
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.254243375
Short name T1002
Test name
Test status
Simulation time 13505364 ps
CPU time 0.71 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 205856 kb
Host smart-420c66c4-6a13-4d04-9370-d0470037926f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254243375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.254243375
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.639055548
Short name T448
Test name
Test status
Simulation time 1013799640 ps
CPU time 12.11 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:01:56 PM PDT 24
Peak memory 225288 kb
Host smart-520bd520-e670-4568-8ef9-3b5077ce462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639055548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.639055548
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2051440903
Short name T442
Test name
Test status
Simulation time 83610563 ps
CPU time 0.79 seconds
Started Jul 31 05:01:21 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 207068 kb
Host smart-a48cadfc-fd1a-4a88-b876-ad1472703aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051440903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2051440903
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3174393310
Short name T1029
Test name
Test status
Simulation time 24583687600 ps
CPU time 81.75 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:02:46 PM PDT 24
Peak memory 249884 kb
Host smart-0ab19c71-3a72-4120-a462-66b8013f9c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174393310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3174393310
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3033101681
Short name T163
Test name
Test status
Simulation time 36894542318 ps
CPU time 324.05 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:06:54 PM PDT 24
Peak memory 267344 kb
Host smart-7662a62a-2489-43c2-b291-83ef90c2fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033101681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3033101681
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2958474137
Short name T740
Test name
Test status
Simulation time 30279824635 ps
CPU time 74.25 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:02:38 PM PDT 24
Peak memory 252128 kb
Host smart-0e64d61b-fe60-49c4-b952-969a77272ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958474137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2958474137
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2252041937
Short name T46
Test name
Test status
Simulation time 2191707678 ps
CPU time 18.04 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:43 PM PDT 24
Peak memory 233424 kb
Host smart-b593297b-b576-4b15-b5fa-969c95b49e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252041937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2252041937
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3120145856
Short name T188
Test name
Test status
Simulation time 49708730905 ps
CPU time 92.93 seconds
Started Jul 31 05:01:21 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 241580 kb
Host smart-522606e2-9f6c-4142-ae9b-f94403e73c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120145856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3120145856
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1152752134
Short name T399
Test name
Test status
Simulation time 870142981 ps
CPU time 10.64 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 233292 kb
Host smart-706be5f3-8ea7-47e0-872c-8a01a5e2f349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152752134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1152752134
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2424877621
Short name T1033
Test name
Test status
Simulation time 5979660284 ps
CPU time 35.31 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:52 PM PDT 24
Peak memory 225204 kb
Host smart-6ba29271-1e62-4910-9f7f-c1caf04590d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424877621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2424877621
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3347976491
Short name T1001
Test name
Test status
Simulation time 34552735 ps
CPU time 1.04 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:13 PM PDT 24
Peak memory 217116 kb
Host smart-e8f1250e-deb5-48d2-8816-f774a173f2c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347976491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3347976491
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2257210911
Short name T991
Test name
Test status
Simulation time 1501083641 ps
CPU time 9.03 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:36 PM PDT 24
Peak memory 225256 kb
Host smart-89e13785-db41-4031-aec4-586317596aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257210911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2257210911
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.587625092
Short name T355
Test name
Test status
Simulation time 362907693 ps
CPU time 2.27 seconds
Started Jul 31 05:01:13 PM PDT 24
Finished Jul 31 05:01:16 PM PDT 24
Peak memory 223636 kb
Host smart-625a618b-6868-4b8f-8065-4229c3b178c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587625092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.587625092
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2095795946
Short name T747
Test name
Test status
Simulation time 1482201792 ps
CPU time 4.74 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 219888 kb
Host smart-04091acf-991b-4dac-9f50-833bfb690d25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2095795946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2095795946
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1955583129
Short name T160
Test name
Test status
Simulation time 27331517981 ps
CPU time 190.84 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 249848 kb
Host smart-2c0b1619-3da4-494a-b057-f3348d2b88bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955583129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1955583129
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2320792535
Short name T395
Test name
Test status
Simulation time 1649372337 ps
CPU time 26.22 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 217248 kb
Host smart-0d495335-bcba-4ae7-9add-cc5e6c440023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320792535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2320792535
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1747462584
Short name T401
Test name
Test status
Simulation time 5945421192 ps
CPU time 5.66 seconds
Started Jul 31 05:01:16 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 216916 kb
Host smart-0166ca35-00c2-4da8-9b2f-15a78fe8142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747462584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1747462584
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.278503902
Short name T962
Test name
Test status
Simulation time 403597639 ps
CPU time 4.3 seconds
Started Jul 31 05:01:18 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 216896 kb
Host smart-f664c100-0260-43da-ae19-c2434cb69637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278503902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.278503902
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.623888158
Short name T752
Test name
Test status
Simulation time 79947227 ps
CPU time 0.98 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:25 PM PDT 24
Peak memory 207452 kb
Host smart-d88c5ac9-7cfc-4a6d-9545-4feb7824af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623888158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.623888158
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.828130888
Short name T568
Test name
Test status
Simulation time 51297511 ps
CPU time 2.51 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:25 PM PDT 24
Peak memory 233388 kb
Host smart-11270d1c-5ef9-499c-94c5-8e5d86312725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828130888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.828130888
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2280446285
Short name T479
Test name
Test status
Simulation time 15407242 ps
CPU time 0.75 seconds
Started Jul 31 05:01:20 PM PDT 24
Finished Jul 31 05:01:21 PM PDT 24
Peak memory 205852 kb
Host smart-265162e2-9b05-488a-ad3f-cc2d9ba2473b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280446285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
280446285
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.207742694
Short name T840
Test name
Test status
Simulation time 232587711 ps
CPU time 4.9 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 233304 kb
Host smart-3af0465d-52e5-4707-b7dd-aade93e9e105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207742694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.207742694
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1616178226
Short name T493
Test name
Test status
Simulation time 23501575 ps
CPU time 0.77 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 207028 kb
Host smart-67136db2-08d5-4447-b32a-bc320b641ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616178226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1616178226
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1093897784
Short name T843
Test name
Test status
Simulation time 15573965872 ps
CPU time 106.22 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 249644 kb
Host smart-192acbd6-0f0c-4a25-a5c5-58c362664302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093897784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1093897784
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4158146613
Short name T323
Test name
Test status
Simulation time 30578604647 ps
CPU time 31.37 seconds
Started Jul 31 05:01:20 PM PDT 24
Finished Jul 31 05:01:51 PM PDT 24
Peak memory 218536 kb
Host smart-2d02569c-9f13-46de-b3ca-4436da6ec02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158146613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4158146613
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4218573295
Short name T489
Test name
Test status
Simulation time 16847135368 ps
CPU time 151.7 seconds
Started Jul 31 05:01:42 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 266324 kb
Host smart-53a0228c-9f02-4796-a38e-c78cfd00ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218573295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4218573295
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3647518435
Short name T683
Test name
Test status
Simulation time 143881447 ps
CPU time 5.22 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 221936 kb
Host smart-121f4d78-e76d-4ed9-8453-10849530f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647518435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3647518435
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.207223867
Short name T234
Test name
Test status
Simulation time 5593171342 ps
CPU time 13.96 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 225184 kb
Host smart-c7d0d80a-be78-4e42-9c16-318b90253ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207223867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.207223867
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3830734267
Short name T463
Test name
Test status
Simulation time 961123321 ps
CPU time 7.57 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 241504 kb
Host smart-a8da35cd-dafc-46ef-a89c-667649722c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830734267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3830734267
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4070354141
Short name T39
Test name
Test status
Simulation time 24552214 ps
CPU time 1.05 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 217216 kb
Host smart-6e00ae2e-cf2f-48ed-baba-b6b9d9f696db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070354141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4070354141
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2335820118
Short name T576
Test name
Test status
Simulation time 2227974670 ps
CPU time 4.07 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 233496 kb
Host smart-15ff5bcc-08c0-45db-a38d-9f0e9f0bc3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335820118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2335820118
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3248742287
Short name T731
Test name
Test status
Simulation time 884102479 ps
CPU time 5.61 seconds
Started Jul 31 05:01:19 PM PDT 24
Finished Jul 31 05:01:25 PM PDT 24
Peak memory 233332 kb
Host smart-967e37eb-be48-4ea5-8f00-aa9e47c07137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248742287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3248742287
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2552358648
Short name T146
Test name
Test status
Simulation time 5242908500 ps
CPU time 10.17 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:38 PM PDT 24
Peak memory 219428 kb
Host smart-e03e5745-4b9a-497a-9dbc-53a87d28cf09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552358648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2552358648
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1862949907
Short name T438
Test name
Test status
Simulation time 183542539 ps
CPU time 1 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:01:40 PM PDT 24
Peak memory 207352 kb
Host smart-37722171-a6b4-4a29-acd3-0e67dbe1a42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862949907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1862949907
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3764119084
Short name T328
Test name
Test status
Simulation time 24302225122 ps
CPU time 37.13 seconds
Started Jul 31 05:01:20 PM PDT 24
Finished Jul 31 05:01:57 PM PDT 24
Peak memory 217000 kb
Host smart-b9721258-7476-41d5-bd60-64ad93561f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764119084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3764119084
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3251387287
Short name T900
Test name
Test status
Simulation time 2400831614 ps
CPU time 2.29 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 208540 kb
Host smart-bd0a2c6a-91bc-43d7-a12c-93a0f253391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251387287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3251387287
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.60679030
Short name T487
Test name
Test status
Simulation time 20515215 ps
CPU time 0.68 seconds
Started Jul 31 05:01:21 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 206100 kb
Host smart-62273221-759d-4fdf-a195-a5e4502ddca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60679030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.60679030
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2280039673
Short name T482
Test name
Test status
Simulation time 35287063 ps
CPU time 0.8 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 206392 kb
Host smart-0baf4e30-7831-4493-ba62-03e27da3e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280039673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2280039673
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1270323969
Short name T250
Test name
Test status
Simulation time 264986996 ps
CPU time 2.99 seconds
Started Jul 31 05:01:39 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 225208 kb
Host smart-8004ae77-1c42-424d-b34c-d30ea85c2c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270323969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1270323969
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.720560986
Short name T528
Test name
Test status
Simulation time 13532375 ps
CPU time 0.7 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 205272 kb
Host smart-52d197b2-2b21-4f68-87e4-78a15e55f757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720560986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.720560986
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2698174152
Short name T732
Test name
Test status
Simulation time 309014930 ps
CPU time 3.06 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 225160 kb
Host smart-3a5027b0-ee21-4c67-8856-d1a4a2f0a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698174152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2698174152
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3253447144
Short name T441
Test name
Test status
Simulation time 37191809 ps
CPU time 0.77 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 206932 kb
Host smart-1cc666e2-e7c6-406a-8f2d-ea8bfdde73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253447144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3253447144
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3283950608
Short name T287
Test name
Test status
Simulation time 183293339065 ps
CPU time 209.15 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:04:55 PM PDT 24
Peak memory 258092 kb
Host smart-c28c5d11-1912-456a-a0bd-d24e721f9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283950608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3283950608
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1794803759
Short name T968
Test name
Test status
Simulation time 3873394467 ps
CPU time 57.4 seconds
Started Jul 31 05:01:21 PM PDT 24
Finished Jul 31 05:02:19 PM PDT 24
Peak memory 245720 kb
Host smart-37e179f3-ca20-4d46-852c-d240e941d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794803759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1794803759
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3773082006
Short name T425
Test name
Test status
Simulation time 28528825504 ps
CPU time 98.02 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:03:06 PM PDT 24
Peak memory 250880 kb
Host smart-163c6c3f-45f3-400b-9279-db96401c75e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773082006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3773082006
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3653925422
Short name T513
Test name
Test status
Simulation time 1521797193 ps
CPU time 10.4 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 249548 kb
Host smart-8dca759b-5e36-4550-8969-0ea602175cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653925422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3653925422
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3426675529
Short name T698
Test name
Test status
Simulation time 25459359854 ps
CPU time 80.45 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:02:44 PM PDT 24
Peak memory 254596 kb
Host smart-ef92bbe6-fb79-444b-8e89-689f6ad02cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426675529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3426675529
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2064486941
Short name T909
Test name
Test status
Simulation time 19392392776 ps
CPU time 22.64 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:48 PM PDT 24
Peak memory 233384 kb
Host smart-e88a158d-63d2-4a90-b7f0-7c0bc7509445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064486941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2064486941
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3187687183
Short name T368
Test name
Test status
Simulation time 260561447 ps
CPU time 6.37 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 241340 kb
Host smart-4d8a21dc-f68b-477a-b954-7a8d5b85baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187687183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3187687183
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3995757483
Short name T642
Test name
Test status
Simulation time 14471069 ps
CPU time 0.99 seconds
Started Jul 31 05:01:25 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 217072 kb
Host smart-36cf68a5-03d7-43f0-a365-48137b0ded39
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995757483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3995757483
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.915075918
Short name T937
Test name
Test status
Simulation time 166427574 ps
CPU time 2.84 seconds
Started Jul 31 05:01:31 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 233312 kb
Host smart-df2d5a17-bba7-4b42-a0e1-79853ce05ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915075918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
915075918
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.212090401
Short name T949
Test name
Test status
Simulation time 7429437637 ps
CPU time 9.45 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:39 PM PDT 24
Peak memory 233476 kb
Host smart-28b42b90-acbe-48f5-97b7-a65f23f53a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212090401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.212090401
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2929643295
Short name T957
Test name
Test status
Simulation time 84259806 ps
CPU time 3.41 seconds
Started Jul 31 05:01:15 PM PDT 24
Finished Jul 31 05:01:19 PM PDT 24
Peak memory 219728 kb
Host smart-1b982a4f-d61b-45a1-ade2-bee43b354503
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2929643295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2929643295
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1180918276
Short name T620
Test name
Test status
Simulation time 57599059402 ps
CPU time 617.74 seconds
Started Jul 31 05:01:09 PM PDT 24
Finished Jul 31 05:11:27 PM PDT 24
Peak memory 274372 kb
Host smart-8d3d7e2a-d7c9-4aca-95b3-17e8afae7db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180918276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1180918276
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3368508751
Short name T825
Test name
Test status
Simulation time 11611866330 ps
CPU time 11.66 seconds
Started Jul 31 05:01:33 PM PDT 24
Finished Jul 31 05:01:44 PM PDT 24
Peak memory 217016 kb
Host smart-499aa8cb-3ae5-44c6-a94d-f2986cba1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368508751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3368508751
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1438680315
Short name T876
Test name
Test status
Simulation time 34387077910 ps
CPU time 24.48 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:54 PM PDT 24
Peak memory 216824 kb
Host smart-8aa211ef-3268-4512-820c-f1541bacc1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438680315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1438680315
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.453684378
Short name T857
Test name
Test status
Simulation time 42248515 ps
CPU time 1.5 seconds
Started Jul 31 05:01:12 PM PDT 24
Finished Jul 31 05:01:14 PM PDT 24
Peak memory 216876 kb
Host smart-1cd904f3-d103-40cd-8bb9-8b3a5bd7e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453684378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.453684378
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2754264923
Short name T754
Test name
Test status
Simulation time 39262274 ps
CPU time 0.7 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 206564 kb
Host smart-03788b45-7a3f-4603-80d8-373b78ecc5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754264923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2754264923
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1694147307
Short name T135
Test name
Test status
Simulation time 2607333031 ps
CPU time 7.46 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:36 PM PDT 24
Peak memory 233492 kb
Host smart-05bc772e-8e0f-4d2f-b8d6-fbe8fb016236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694147307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1694147307
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3948230225
Short name T470
Test name
Test status
Simulation time 29716693 ps
CPU time 0.7 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 205280 kb
Host smart-a6141fa4-1a79-4fa8-9408-888db12b5611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948230225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
948230225
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3556440471
Short name T594
Test name
Test status
Simulation time 584436420 ps
CPU time 3.69 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 225148 kb
Host smart-cb29c2cc-1471-4c84-a44e-229b49d8fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556440471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3556440471
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1989763978
Short name T350
Test name
Test status
Simulation time 57692152 ps
CPU time 0.76 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:27 PM PDT 24
Peak memory 207272 kb
Host smart-c3955930-7b9b-4822-8358-fb84806b5018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989763978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1989763978
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2736751269
Short name T269
Test name
Test status
Simulation time 3774396057 ps
CPU time 25.62 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:50 PM PDT 24
Peak memory 241632 kb
Host smart-9fdc10b3-c60b-444b-9888-df1abef53448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736751269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2736751269
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.731816202
Short name T309
Test name
Test status
Simulation time 59672250808 ps
CPU time 490.12 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:09:41 PM PDT 24
Peak memory 273008 kb
Host smart-f4b599b9-d986-4e4b-a2a8-82000a626c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731816202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.731816202
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2990233246
Short name T54
Test name
Test status
Simulation time 50902632067 ps
CPU time 236.54 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:05:26 PM PDT 24
Peak memory 256776 kb
Host smart-78094a99-8d68-4b3b-9d28-fe30f7eb79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990233246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2990233246
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1115383300
Short name T1023
Test name
Test status
Simulation time 168732209 ps
CPU time 4.21 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:26 PM PDT 24
Peak memory 225128 kb
Host smart-4f24038a-e01f-4401-8483-774ce776d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115383300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1115383300
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3400629678
Short name T755
Test name
Test status
Simulation time 31150230459 ps
CPU time 113.56 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:03:16 PM PDT 24
Peak memory 252504 kb
Host smart-ae38f570-6431-49a2-865d-e0d6cd2a60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400629678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3400629678
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.347374158
Short name T572
Test name
Test status
Simulation time 10922256613 ps
CPU time 9.23 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:37 PM PDT 24
Peak memory 233444 kb
Host smart-0639607c-bad5-4afe-b843-32ae19fd17b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347374158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.347374158
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.375925939
Short name T711
Test name
Test status
Simulation time 6569931243 ps
CPU time 10.07 seconds
Started Jul 31 05:01:37 PM PDT 24
Finished Jul 31 05:01:47 PM PDT 24
Peak memory 241440 kb
Host smart-1480f9f0-3298-4b8d-878d-3ba84468d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375925939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.375925939
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2479692717
Short name T718
Test name
Test status
Simulation time 22120803 ps
CPU time 1.03 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:23 PM PDT 24
Peak memory 218368 kb
Host smart-bd019239-b405-4fc2-9858-07a6a573953c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479692717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2479692717
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3591443676
Short name T655
Test name
Test status
Simulation time 12814372498 ps
CPU time 11.41 seconds
Started Jul 31 05:01:20 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 233492 kb
Host smart-c5601c30-c4c2-4e9e-ab5d-547279ea16dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591443676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3591443676
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1274443107
Short name T332
Test name
Test status
Simulation time 118775918 ps
CPU time 2.13 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:24 PM PDT 24
Peak memory 232888 kb
Host smart-869c0963-8b51-4024-a936-f78b7c431b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274443107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1274443107
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4119401886
Short name T45
Test name
Test status
Simulation time 201186999 ps
CPU time 4 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 223540 kb
Host smart-8de2f4b4-834f-46da-9bdb-5b9b13d89d0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119401886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4119401886
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2913637890
Short name T159
Test name
Test status
Simulation time 927609839 ps
CPU time 17.68 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:42 PM PDT 24
Peak memory 240696 kb
Host smart-acc2c59e-d455-41e7-9f79-47fbd8e7dee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913637890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2913637890
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.488386791
Short name T644
Test name
Test status
Simulation time 755238850 ps
CPU time 7.77 seconds
Started Jul 31 05:01:51 PM PDT 24
Finished Jul 31 05:01:59 PM PDT 24
Peak memory 216980 kb
Host smart-f1100b03-03a7-47b5-9b33-eed7e883be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488386791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.488386791
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.881894775
Short name T78
Test name
Test status
Simulation time 13546109 ps
CPU time 0.71 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 206128 kb
Host smart-c0a759d0-ace3-4070-a54f-61b546f2d849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881894775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.881894775
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2088684679
Short name T3
Test name
Test status
Simulation time 49539984 ps
CPU time 0.71 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 206560 kb
Host smart-e4804993-85f2-46f5-9ea6-bffa2fab4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088684679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2088684679
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.136690248
Short name T994
Test name
Test status
Simulation time 71277138 ps
CPU time 0.75 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:28 PM PDT 24
Peak memory 206476 kb
Host smart-10e178c2-f1de-4c59-ba2d-f4b3c4a6860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136690248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.136690248
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3049011653
Short name T264
Test name
Test status
Simulation time 3532332452 ps
CPU time 8.13 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:36 PM PDT 24
Peak memory 225112 kb
Host smart-830ba8c9-e6b8-427d-ad1a-6129ad91a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049011653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3049011653
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2020329534
Short name T596
Test name
Test status
Simulation time 18220670 ps
CPU time 0.71 seconds
Started Jul 31 05:01:44 PM PDT 24
Finished Jul 31 05:01:45 PM PDT 24
Peak memory 205204 kb
Host smart-5ddd1b72-ab5c-412f-a093-2fb534ccd6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020329534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
020329534
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2056859954
Short name T887
Test name
Test status
Simulation time 52558450 ps
CPU time 1.98 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 224364 kb
Host smart-48f25a84-162b-4bf2-809e-1febbeb46064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056859954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2056859954
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2281545981
Short name T1008
Test name
Test status
Simulation time 43772934 ps
CPU time 0.75 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 205984 kb
Host smart-22036226-1686-426b-920e-f4f34c8cb8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281545981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2281545981
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4232741942
Short name T11
Test name
Test status
Simulation time 5159683375 ps
CPU time 69.94 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:02:33 PM PDT 24
Peak memory 249816 kb
Host smart-82f708ab-373e-4a6b-867c-59ac3a6e99b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232741942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4232741942
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2529430719
Short name T688
Test name
Test status
Simulation time 18269670664 ps
CPU time 206.64 seconds
Started Jul 31 05:01:30 PM PDT 24
Finished Jul 31 05:04:57 PM PDT 24
Peak memory 255908 kb
Host smart-01cb42dd-a031-476a-8ecf-9cc4f6849ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529430719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2529430719
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3012735969
Short name T1031
Test name
Test status
Simulation time 33264005425 ps
CPU time 78.38 seconds
Started Jul 31 05:01:36 PM PDT 24
Finished Jul 31 05:02:54 PM PDT 24
Peak memory 243472 kb
Host smart-3714a5f9-1a4a-4c95-81f0-d06446e7361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012735969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3012735969
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3434660251
Short name T147
Test name
Test status
Simulation time 649757874 ps
CPU time 6.66 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:31 PM PDT 24
Peak memory 233464 kb
Host smart-c93be513-72ef-4da5-9b76-60fec9a25fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434660251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3434660251
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2376079426
Short name T64
Test name
Test status
Simulation time 4064038034 ps
CPU time 41.35 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:02:07 PM PDT 24
Peak memory 257464 kb
Host smart-bf8cbb10-701b-40c5-ac70-57b8d9dcf563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376079426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2376079426
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3218109197
Short name T895
Test name
Test status
Simulation time 68279901 ps
CPU time 2.04 seconds
Started Jul 31 05:01:32 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 225156 kb
Host smart-2bd73d36-fcde-4e21-99c1-2e9ce34a73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218109197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3218109197
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2118706095
Short name T371
Test name
Test status
Simulation time 778872706 ps
CPU time 11.88 seconds
Started Jul 31 05:01:23 PM PDT 24
Finished Jul 31 05:01:35 PM PDT 24
Peak memory 233312 kb
Host smart-6d8a78fd-4906-43fa-987a-3eb621b548d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118706095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2118706095
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.179777831
Short name T954
Test name
Test status
Simulation time 113129130 ps
CPU time 1.03 seconds
Started Jul 31 05:01:28 PM PDT 24
Finished Jul 31 05:01:29 PM PDT 24
Peak memory 218396 kb
Host smart-9e04f9c8-50f6-457f-9176-0f86a69c6491
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179777831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.179777831
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1118935990
Short name T58
Test name
Test status
Simulation time 448375247 ps
CPU time 5.87 seconds
Started Jul 31 05:01:35 PM PDT 24
Finished Jul 31 05:01:41 PM PDT 24
Peak memory 225052 kb
Host smart-436034e2-c050-4a9e-966c-b1e4a19727c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118935990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1118935990
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3782016181
Short name T331
Test name
Test status
Simulation time 72137400 ps
CPU time 2.21 seconds
Started Jul 31 05:01:27 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 224240 kb
Host smart-d6f23592-bc4d-4ec3-aadc-9b2bf341a5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782016181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3782016181
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.724847060
Short name T449
Test name
Test status
Simulation time 5900990316 ps
CPU time 9.92 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 219436 kb
Host smart-23ba7d21-96db-4a97-ae5f-1e6d53c74ad5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=724847060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.724847060
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.154374011
Short name T560
Test name
Test status
Simulation time 7970520963 ps
CPU time 48.89 seconds
Started Jul 31 05:01:34 PM PDT 24
Finished Jul 31 05:02:23 PM PDT 24
Peak memory 249876 kb
Host smart-d9694fbf-5b27-4b72-b60b-d2c63bce1606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154374011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.154374011
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.134314306
Short name T565
Test name
Test status
Simulation time 1629802547 ps
CPU time 8.4 seconds
Started Jul 31 05:01:22 PM PDT 24
Finished Jul 31 05:01:30 PM PDT 24
Peak memory 216860 kb
Host smart-87195e67-49fb-4edf-b013-f819449c8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134314306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.134314306
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1204142698
Short name T569
Test name
Test status
Simulation time 1020401720 ps
CPU time 4.23 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:33 PM PDT 24
Peak memory 216992 kb
Host smart-61a573db-353c-47b5-96cb-4c211a7a7126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204142698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1204142698
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.347096938
Short name T33
Test name
Test status
Simulation time 27623229 ps
CPU time 0.72 seconds
Started Jul 31 05:01:24 PM PDT 24
Finished Jul 31 05:01:25 PM PDT 24
Peak memory 206556 kb
Host smart-a0dfea9c-8814-4c7d-87ce-9f1419acc7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347096938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.347096938
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1771188948
Short name T778
Test name
Test status
Simulation time 97041072 ps
CPU time 0.77 seconds
Started Jul 31 05:01:26 PM PDT 24
Finished Jul 31 05:01:27 PM PDT 24
Peak memory 206464 kb
Host smart-6e3d1547-ba45-4bca-8a89-d9a79681a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771188948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1771188948
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3185031448
Short name T867
Test name
Test status
Simulation time 843517205 ps
CPU time 4.69 seconds
Started Jul 31 05:01:29 PM PDT 24
Finished Jul 31 05:01:34 PM PDT 24
Peak memory 233256 kb
Host smart-6d49c0d8-dda8-4c78-911f-34d06f6dce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185031448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3185031448
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%