Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2233424	1			T1	1		T2	2706		T3	1
all_values[1]	2233424	1			T1	1		T2	2706		T3	1
all_values[2]	2233424	1			T1	1		T2	2706		T3	1
all_values[3]	2233424	1			T1	1		T2	2706		T3	1
all_values[4]	2233424	1			T1	1		T2	2706		T3	1
all_values[5]	2233424	1			T1	1		T2	2706		T3	1
all_values[6]	2233424	1			T1	1		T2	2706		T3	1
all_values[7]	2233424	1			T1	1		T2	2706		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17398289

1

T1

8

T2

21648

T3

8

auto[1]

469103

1

T13

25

T17

79

T18

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17840699

1

T1

8

T2

21647

T3

8

auto[1]

26693

1

T2

1

T9

28

T13

444

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2104801	1			T1	1		T2	2705		T3	1
all_values[0]	auto[0]	auto[1]	11557	1			T2	1		T9	14		T13	192
all_values[0]	auto[1]	auto[0]	115834	1			T13	1		T17	1		T18	7
all_values[0]	auto[1]	auto[1]	1232	1			T13	2		T17	4		T18	5
all_values[1]	auto[0]	auto[0]	2162869	1			T1	1		T2	2706		T3	1
all_values[1]	auto[0]	auto[1]	7700	1			T9	14		T13	190		T23	80
all_values[1]	auto[1]	auto[0]	62373	1			T13	2		T17	3		T18	3
all_values[1]	auto[1]	auto[1]	482	1			T13	3		T17	4		T18	2
all_values[2]	auto[0]	auto[0]	2194238	1			T1	1		T2	2706		T3	1
all_values[2]	auto[0]	auto[1]	3364	1			T13	41		T23	49		T30	5
all_values[2]	auto[1]	auto[0]	35536	1			T13	1		T17	8		T18	7
all_values[2]	auto[1]	auto[1]	286	1			T13	2		T17	5		T18	5
all_values[3]	auto[0]	auto[0]	2211179	1			T1	1		T2	2706		T3	1
all_values[3]	auto[0]	auto[1]	195	1			T18	3		T19	5		T21	6
all_values[3]	auto[1]	auto[0]	21855	1			T13	2		T17	7		T18	1
all_values[3]	auto[1]	auto[1]	195	1			T13	2		T17	4		T18	2
all_values[4]	auto[0]	auto[0]	2184519	1			T1	1		T2	2706		T3	1
all_values[4]	auto[0]	auto[1]	212	1			T13	3		T17	4		T18	1
all_values[4]	auto[1]	auto[0]	48471	1			T13	1		T17	3		T18	5
all_values[4]	auto[1]	auto[1]	222	1			T17	3		T18	6		T19	4
all_values[5]	auto[0]	auto[0]	2182628	1			T1	1		T2	2706		T3	1
all_values[5]	auto[0]	auto[1]	191	1			T13	1		T17	1		T18	2
all_values[5]	auto[1]	auto[0]	50404	1			T13	1		T17	8		T18	5
all_values[5]	auto[1]	auto[1]	201	1			T17	5		T18	3		T19	3
all_values[6]	auto[0]	auto[0]	2169812	1			T1	1		T2	2706		T3	1
all_values[6]	auto[0]	auto[1]	222	1			T13	1		T17	1		T18	6
all_values[6]	auto[1]	auto[0]	63180	1			T13	1		T17	9		T18	5
all_values[6]	auto[1]	auto[1]	210	1			T13	3		T17	4		T18	1
all_values[7]	auto[0]	auto[0]	2164597	1			T1	1		T2	2706		T3	1
all_values[7]	auto[0]	auto[1]	205	1			T13	1		T17	4		T18	2
all_values[7]	auto[1]	auto[0]	68403	1			T13	1		T17	5		T18	8
all_values[7]	auto[1]	auto[1]	219	1			T13	3		T17	6		T18	6