Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38786	1			T1	2		T2	5		T6	2
auto[SpiFlashAddrCfg]	7944	1			T2	8		T8	10		T9	9
auto[SpiFlashAddr3b]	9260	1			T2	4		T8	7		T9	10
auto[SpiFlashAddr4b]	7989	1			T2	4		T8	10		T9	15

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36376

1

T1

2

T2

8

T6

2

auto[1]

27603

1

T2

13

T8

22

T9

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33918

1

T1

2

T2

9

T8

25

auto[1]

30061

1

T2

12

T6

2

T8

27

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43552	1			T1	2		T2	7		T6	2
values[1]	1145	1			T8	1		T10	4		T13	5
values[2]	1549	1			T2	1		T8	4		T9	1
values[3]	1448	1			T2	2		T8	1		T9	1
values[4]	1502	1			T8	3		T9	1		T10	9
values[5]	1560	1			T2	1		T8	2		T9	2
values[6]	1482	1			T9	3		T10	3		T13	7
values[7]	1499	1			T2	1		T9	1		T10	4
values[8]	10242	1			T2	9		T8	12		T9	15

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32564

1

T1

2

T2

21

T6

2

auto[1]

31415

1

T9

64

T13

240

T23

181

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60541

1

T1

2

T2

21

T6

2

write

3438

1

T8

1

T9

10

T10

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19914

1

T1

2

T2

13

T8

20

valids[0x1]

44065

1

T2

8

T6

2

T8

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1586	1			T2	1		T8	1		T9	1
internal_process_ops[0x5a]	1648	1			T8	1		T9	1		T10	3
internal_process_ops[0x05]	24257	1			T2	3		T8	15		T9	5
internal_process_ops[0x35]	1637	1			T6	2		T8	2		T9	1
internal_process_ops[0x15]	1574	1			T9	1		T10	4		T13	5
internal_process_ops[0x03]	1044	1			T2	1		T8	4		T10	4
internal_process_ops[0x0b]	1101	1			T2	1		T8	3		T9	2
internal_process_ops[0x3b]	987	1			T2	2		T8	1		T10	5
internal_process_ops[0x6b]	1037	1			T8	2		T9	1		T10	5
internal_process_ops[0xbb]	1073	1			T2	1		T8	1		T10	7
internal_process_ops[0xeb]	1013	1			T2	1		T8	2		T10	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62295

1

T1

2

T2

21

T6

2

auto[1]

1684

1

T8

1

T9

5

T10

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61448

1

T1

2

T2

20

T6

2

auto[1]

2531

1

T2

1

T8

3

T9

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11366

1

T1

2

T2

1

T6

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7236

1

T2

4

T8

6

T10

54

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2072

1

T2

4

T8

1

T10

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1848

1

T2

4

T8

9

T10

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2422

1

T2

2

T8

4

T10

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2093

1

T2

2

T8

2

T10

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2042

1

T2

1

T8

5

T10

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1834

1

T2

3

T8

5

T10

25

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

127

1

T42

4

T33

2

T73

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T10

1

T42

7

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

110

1

T45

4

T41

4

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

112

1

T10

1

T42

4

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T27

2

T45

1

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

84

1

T39

2

T42

1

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T10

3

T48

1

T15

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T39

1

T42

1

T33

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T33

3

T45

3

T47

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

94

1

T8

1

T45

1

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T42

1

T33

1

T45

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

118

1

T10

3

T39

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

123

1

T10

4

T42

2

T33

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

87

1

T10

2

T41

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

78

1

T10

1

T33

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

118

1

T10

2

T39

1

T41

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11524

1

T9

25

T13

56

T23

62

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7746

1

T9

3

T13

74

T23

18

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1634

1

T9

4

T13

6

T23

18

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1564

1

T9

2

T13

19

T23

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1920

1

T9

6

T13

11

T23

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1962

1

T9

1

T13

19

T23

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1640

1

T9

6

T13

15

T23

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1638

1

T9

7

T13

19

T23

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

138

1

T13

1

T30

6

T49

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T9

2

T13

1

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

108

1

T13

3

T30

1

T75

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T23

2

T30

2

T49

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

113

1

T9

1

T30

3

T49

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

98

1

T13

1

T23

3

T170

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T13

3

T23

1

T49

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

122

1

T9

2

T75

1

T90

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T9

1

T23

3

T49

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T9

1

T13

1

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

108

1

T9

1

T49

1

T171

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

128

1

T23

1

T30

2

T172

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

142

1

T9

2

T13

2

T49

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T13

2

T49

1

T75

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

85

1

T13

4

T76

3

T139

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T13

3

T30

5

T75

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3959	1			T1	2		T2	2		T8	7
auto[0]	values[0]	valids[0x1]	17570	1			T2	5		T6	2		T8	22
auto[0]	values[1]	valids[0x1]	573	1			T8	1		T10	4		T39	3
auto[0]	values[2]	valids[0x0]	566	1			T2	1		T8	1		T10	7
auto[0]	values[2]	valids[0x1]	300	1			T8	3		T10	1		T39	4
auto[0]	values[3]	valids[0x0]	524	1			T2	2		T10	3		T39	5
auto[0]	values[3]	valids[0x1]	261	1			T8	1		T10	5		T39	10
auto[0]	values[4]	valids[0x0]	504	1			T8	3		T10	5		T39	5
auto[0]	values[4]	valids[0x1]	301	1			T10	4		T40	2		T39	6
auto[0]	values[5]	valids[0x0]	567	1			T8	1		T10	3		T39	9
auto[0]	values[5]	valids[0x1]	317	1			T2	1		T8	1		T10	5
auto[0]	values[6]	valids[0x0]	514	1			T10	2		T40	4		T39	5
auto[0]	values[6]	valids[0x1]	291	1			T10	1		T39	6		T42	1
auto[0]	values[7]	valids[0x0]	518	1			T10	2		T11	4		T39	8
auto[0]	values[7]	valids[0x1]	278	1			T2	1		T10	2		T39	8
auto[0]	values[8]	valids[0x0]	3368	1			T2	8		T8	8		T10	31
auto[0]	values[8]	valids[0x1]	2153	1			T2	1		T8	4		T10	20
auto[1]	values[0]	valids[0x0]	4182	1			T9	16		T13	33		T23	38
auto[1]	values[0]	valids[0x1]	17841	1			T9	24		T13	118		T23	62
auto[1]	values[1]	valids[0x1]	572	1			T13	5		T23	4		T30	4
auto[1]	values[2]	valids[0x0]	419	1			T9	1		T13	3		T23	4
auto[1]	values[2]	valids[0x1]	264	1			T13	2		T23	3		T30	3
auto[1]	values[3]	valids[0x0]	387	1			T13	4		T23	12		T30	4
auto[1]	values[3]	valids[0x1]	276	1			T9	1		T23	3		T30	5
auto[1]	values[4]	valids[0x0]	423	1			T23	2		T30	3		T49	2
auto[1]	values[4]	valids[0x1]	274	1			T9	1		T13	3		T30	3
auto[1]	values[5]	valids[0x0]	390	1			T9	1		T13	1		T23	2
auto[1]	values[5]	valids[0x1]	286	1			T9	1		T13	5		T23	3
auto[1]	values[6]	valids[0x0]	384	1			T13	1		T23	1		T30	4
auto[1]	values[6]	valids[0x1]	293	1			T9	3		T13	6		T23	2
auto[1]	values[7]	valids[0x0]	440	1			T13	6		T30	3		T49	2
auto[1]	values[7]	valids[0x1]	263	1			T9	1		T13	2		T23	1
auto[1]	values[8]	valids[0x0]	2769	1			T9	11		T13	30		T23	20
auto[1]	values[8]	valids[0x1]	1952	1			T9	4		T13	21		T23	24