Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3354762

1

T1

1425

T2

2631

T6

622

auto[1]

33610

1

T2

1

T8

12

T9

4

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

861480

1

T1

1425

T2

9

T6

110

auto[1]

2526892

1

T2

2623

T6

512

T8

4093

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	655312	1			T1	47		T2	5		T6	122
auto[524288:1048575]	366824	1			T1	3		T9	4		T10	582
auto[1048576:1572863]	386466	1			T1	171		T6	243		T8	3
auto[1572864:2097151]	397599	1			T1	399		T6	257		T9	1
auto[2097152:2621439]	426705	1			T1	154		T8	1		T10	2
auto[2621440:3145727]	388474	1			T1	467		T8	133		T10	3381
auto[3145728:3670015]	401578	1			T1	130		T10	2298		T13	22
auto[3670016:4194303]	365414	1			T1	54		T2	2627		T8	12

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2561320

1

T1

70

T2

2632

T6

514

auto[1]

827052

1

T1

1355

T6

108

T8

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2899062

1

T1

1425

T2

2632

T6

622

auto[1]

489310

1

T8

133

T9

3

T10

596

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	171547	1			T1	47		T2	3		T6	108
auto[0]	auto[0]	auto[0:524287]	auto[1]	416902	1			T2	1		T6	14		T8	3953
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	59702	1			T1	3		T9	2		T10	12
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	243724	1			T9	1		T10	520		T13	274
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	109032	1			T1	171		T6	1		T8	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	208334	1			T6	242		T8	1		T9	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	99821	1			T1	399		T6	1		T9	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	220220	1			T6	256		T10	2172		T13	2049
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	123871	1			T1	154		T8	1		T10	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	250034	1			T13	3264		T30	281		T39	2256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105577	1			T1	467		T8	1		T10	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	236655	1			T10	3367		T13	2		T24	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	89409	1			T1	130		T10	6		T13	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	257479	1			T10	2268		T13	1		T23	774
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84235	1			T1	54		T2	5		T8	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	195698	1			T2	2622		T8	1		T9	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	3581	1			T8	1		T39	4		T42	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	58145	1			T9	3		T23	606		T33	899
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2661	1			T10	2		T23	2		T49	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56829	1			T23	513		T49	2		T33	2472
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1591	1			T28	10		T39	24		T49	26
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	63011	1			T49	1809		T75	1		T170	768
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2323	1			T23	2		T28	10		T30	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	71286	1			T13	579		T23	1		T30	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1260	1			T10	1		T13	2		T30	9
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47810	1			T30	516		T33	384		T41	2566
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	805	1			T8	2		T13	1		T28	172
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	41599	1			T8	129		T13	1		T172	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	548	1			T13	5		T42	2		T49	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49722	1			T13	2		T42	733		T45	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1432	1			T10	3		T13	1		T23	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	79919	1			T10	582		T23	1		T49	899
auto[1]	auto[0]	auto[0:524287]	auto[0]	599	1			T2	1		T10	2		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3744	1			T10	27		T13	12		T30	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	439	1			T9	1		T10	5		T23	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2415	1			T10	43		T49	75		T33	51
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	369	1			T8	1		T30	1		T49	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3475	1			T30	10		T33	133		T75	13
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	404	1			T23	4		T30	2		T42	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2841	1			T23	4		T30	26		T42	78
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	371	1			T13	5		T42	4		T49	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2793	1			T13	19		T42	115		T75	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	389	1			T10	2		T13	2		T30	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2575	1			T10	7		T13	7		T42	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	407	1			T10	2		T13	1		T23	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2538	1			T10	22		T23	2		T33	33
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	386	1			T8	1		T9	2		T10	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3077	1			T8	9		T9	1		T10	17
auto[1]	auto[1]	auto[0:524287]	auto[0]	89	1			T33	3		T48	1		T15	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	705	1			T33	60		T48	24		T15	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	118	1			T23	1		T33	1		T195	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	936	1			T23	4		T33	12		T76	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	84	1			T75	1		T227	3		T76	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	570	1			T75	4		T76	20		T217	21
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	115	1			T23	1		T41	2		T227	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	589	1			T23	1		T41	57		T200	34
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	75	1			T30	4		T41	2		T172	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	491	1			T30	18		T41	42		T172	19
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	58	1			T8	1		T13	1		T48	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	816	1			T13	5		T48	39		T15	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	85	1			T13	2		T75	1		T47	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1390	1			T13	4		T75	1		T15	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	97	1			T10	1		T23	1		T49	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	570	1			T10	7		T49	5		T202	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2054597	1			T1	70		T2	2631		T6	514
auto[0]	auto[0]	auto[1]	817643	1			T1	1355		T6	108		T8	1
auto[0]	auto[1]	auto[0]	473872	1			T8	132		T9	3		T10	587
auto[0]	auto[1]	auto[1]	8650	1			T10	1		T28	19		T30	3
auto[1]	auto[0]	auto[0]	26199	1			T2	1		T8	11		T9	4
auto[1]	auto[0]	auto[1]	623	1			T10	5		T13	1		T23	2
auto[1]	auto[1]	auto[0]	6652	1			T8	1		T10	7		T13	12
auto[1]	auto[1]	auto[1]	136	1			T10	1		T30	2		T41	1