Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2233424	1			T1	1		T2	2706		T3	1
all_pins[1]	2233424	1			T1	1		T2	2706		T3	1
all_pins[2]	2233424	1			T1	1		T2	2706		T3	1
all_pins[3]	2233424	1			T1	1		T2	2706		T3	1
all_pins[4]	2233424	1			T1	1		T2	2706		T3	1
all_pins[5]	2233424	1			T1	1		T2	2706		T3	1
all_pins[6]	2233424	1			T1	1		T2	2706		T3	1
all_pins[7]	2233424	1			T1	1		T2	2706		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17800005	1			T1	8		T2	21648		T3	8
values[0x1]	67387	1			T13	15		T17	35		T18	30
transitions[0x0=>0x1]	66594	1			T13	5		T17	28		T18	23
transitions[0x1=>0x0]	66608	1			T13	6		T17	28		T18	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2232112	1			T1	1		T2	2706		T3	1
all_pins[0]	values[0x1]	1312	1			T13	2		T17	4		T18	5
all_pins[0]	transitions[0x0=>0x1]	970	1			T17	4		T18	4		T19	1
all_pins[0]	transitions[0x1=>0x0]	161	1			T13	1		T17	4		T18	1
all_pins[1]	values[0x0]	2232921	1			T1	1		T2	2706		T3	1
all_pins[1]	values[0x1]	503	1			T13	3		T17	4		T18	2
all_pins[1]	transitions[0x0=>0x1]	401	1			T13	1		T17	2		T18	1
all_pins[1]	transitions[0x1=>0x0]	192	1			T17	3		T18	4		T19	1
all_pins[2]	values[0x0]	2233130	1			T1	1		T2	2706		T3	1
all_pins[2]	values[0x1]	294	1			T13	2		T17	5		T18	5
all_pins[2]	transitions[0x0=>0x1]	232	1			T17	5		T18	4		T19	1
all_pins[2]	transitions[0x1=>0x0]	133	1			T17	4		T18	1		T19	2
all_pins[3]	values[0x0]	2233229	1			T1	1		T2	2706		T3	1
all_pins[3]	values[0x1]	195	1			T13	2		T17	4		T18	2
all_pins[3]	transitions[0x0=>0x1]	141	1			T13	2		T17	3		T18	2
all_pins[3]	transitions[0x1=>0x0]	168	1			T17	2		T18	6		T19	2
all_pins[4]	values[0x0]	2233202	1			T1	1		T2	2706		T3	1
all_pins[4]	values[0x1]	222	1			T17	3		T18	6		T19	4
all_pins[4]	transitions[0x0=>0x1]	158	1			T17	3		T18	4		T19	2
all_pins[4]	transitions[0x1=>0x0]	1533	1			T17	5		T18	1		T19	1
all_pins[5]	values[0x0]	2231827	1			T1	1		T2	2706		T3	1
all_pins[5]	values[0x1]	1597	1			T17	5		T18	3		T19	3
all_pins[5]	transitions[0x0=>0x1]	1547	1			T17	3		T18	2		T19	3
all_pins[5]	transitions[0x1=>0x0]	62995	1			T13	3		T17	2		T20	1
all_pins[6]	values[0x0]	2170379	1			T1	1		T2	2706		T3	1
all_pins[6]	values[0x1]	63045	1			T13	3		T17	4		T18	1
all_pins[6]	transitions[0x0=>0x1]	62999	1			T13	1		T17	3		T18	1
all_pins[6]	transitions[0x1=>0x0]	173	1			T13	1		T17	5		T18	6
all_pins[7]	values[0x0]	2233205	1			T1	1		T2	2706		T3	1
all_pins[7]	values[0x1]	219	1			T13	3		T17	6		T18	6
all_pins[7]	transitions[0x0=>0x1]	146	1			T13	1		T17	5		T18	5
all_pins[7]	transitions[0x1=>0x0]	1253	1			T13	1		T17	3		T18	4