Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18738

1

T1

2

T2

8

T6

2

auto[1]

13826

1

T2

13

T8

22

T10

122

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4037	1			T27	4		T39	60		T69	8
values[1]	3717	1			T10	57		T39	40		T119	16
values[2]	4264	1			T2	21		T10	40		T28	20
values[3]	3707	1			T10	20		T39	20		T42	81
values[4]	4137	1			T8	20		T224	20		T45	90
values[5]	4394	1			T8	32		T10	73		T39	40
values[6]	4190	1			T10	107		T24	22		T39	20
values[7]	4118	1			T1	2		T6	2		T11	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3882	1			T8	20		T10	24		T39	40
values[1]	3709	1			T6	2		T39	80		T92	18
values[2]	4347	1			T42	20		T33	93		T73	18
values[3]	4546	1			T40	20		T39	40		T84	8
values[4]	3985	1			T1	2		T2	21		T10	20
values[5]	3555	1			T10	95		T27	4		T39	20
values[6]	4722	1			T10	130		T11	10		T28	20
values[7]	3818	1			T8	32		T10	28		T24	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	172	1			T39	26		T47	12		T32	10
auto[0]	values[0]	values[1]	300	1			T39	11		T47	12		T200	16
auto[0]	values[0]	values[2]	334	1			T33	66		T41	15		T77	20
auto[0]	values[0]	values[3]	291	1			T236	20		T186	10		T237	2
auto[0]	values[0]	values[4]	171	1			T33	15		T45	12		T47	11
auto[0]	values[0]	values[5]	272	1			T27	4		T70	2		T47	14
auto[0]	values[0]	values[6]	307	1			T33	11		T218	22		T202	11
auto[0]	values[0]	values[7]	300	1			T47	8		T195	29		T17	15
auto[0]	values[1]	values[0]	233	1			T15	13		T238	26		T200	12
auto[0]	values[1]	values[1]	163	1			T39	14		T227	8		T20	7
auto[0]	values[1]	values[2]	231	1			T239	66		T77	20		T205	11
auto[0]	values[1]	values[3]	366	1			T45	10		T48	11		T15	28
auto[0]	values[1]	values[4]	297	1			T119	16		T33	20		T217	11
auto[0]	values[1]	values[5]	176	1			T39	16		T33	7		T43	14
auto[0]	values[1]	values[6]	304	1			T10	9		T48	19		T195	14
auto[0]	values[1]	values[7]	176	1			T19	10		T190	30		T240	8
auto[0]	values[2]	values[0]	316	1			T42	73		T48	13		T217	34
auto[0]	values[2]	values[1]	220	1			T39	10		T42	10		T44	16
auto[0]	values[2]	values[2]	586	1			T33	5		T73	18		T235	128
auto[0]	values[2]	values[3]	203	1			T39	17		T84	8		T44	14
auto[0]	values[2]	values[4]	424	1			T2	8		T195	18		T217	9
auto[0]	values[2]	values[5]	188	1			T10	16		T200	13		T186	10
auto[0]	values[2]	values[6]	516	1			T28	20		T42	5		T47	14
auto[0]	values[2]	values[7]	124	1			T39	13		T45	17		T195	11
auto[0]	values[3]	values[0]	166	1			T42	9		T195	9		T203	10
auto[0]	values[3]	values[1]	334	1			T47	6		T60	13		T17	10
auto[0]	values[3]	values[2]	313	1			T45	6		T41	10		T241	8
auto[0]	values[3]	values[3]	157	1			T242	4		T48	73		T220	15
auto[0]	values[3]	values[4]	140	1			T10	12		T195	11		T186	9
auto[0]	values[3]	values[5]	168	1			T33	11		T201	10		T15	8
auto[0]	values[3]	values[6]	216	1			T39	16		T47	13		T44	13
auto[0]	values[3]	values[7]	353	1			T42	15		T47	11		T202	14
auto[0]	values[4]	values[0]	251	1			T8	10		T44	19		T195	13
auto[0]	values[4]	values[1]	303	1			T48	14		T44	14		T182	14
auto[0]	values[4]	values[2]	425	1			T45	12		T186	12		T189	25
auto[0]	values[4]	values[3]	342	1			T45	21		T41	94		T227	13
auto[0]	values[4]	values[4]	334	1			T224	20		T182	13		T54	16
auto[0]	values[4]	values[5]	233	1			T45	14		T48	33		T243	2
auto[0]	values[4]	values[6]	214	1			T74	2		T91	9		T220	14
auto[0]	values[4]	values[7]	246	1			T200	8		T50	23		T162	15
auto[0]	values[5]	values[0]	407	1			T48	9		T200	12		T202	16
auto[0]	values[5]	values[1]	304	1			T39	12		T200	20		T162	34
auto[0]	values[5]	values[2]	242	1			T42	11		T48	56		T186	27
auto[0]	values[5]	values[3]	317	1			T212	32		T195	45		T200	9
auto[0]	values[5]	values[4]	162	1			T217	12		T244	12		T223	11
auto[0]	values[5]	values[5]	457	1			T47	11		T44	12		T217	13
auto[0]	values[5]	values[6]	427	1			T10	59		T39	12		T45	6
auto[0]	values[5]	values[7]	249	1			T8	20		T47	13		T245	2
auto[0]	values[6]	values[0]	282	1			T10	13		T77	28		T189	60
auto[0]	values[6]	values[1]	295	1			T92	18		T45	23		T44	9
auto[0]	values[6]	values[2]	156	1			T41	7		T246	6		T186	14
auto[0]	values[6]	values[3]	451	1			T47	20		T48	22		T189	76
auto[0]	values[6]	values[4]	241	1			T200	7		T202	10		T247	4
auto[0]	values[6]	values[5]	229	1			T10	46		T217	20		T189	16
auto[0]	values[6]	values[6]	513	1			T39	8		T42	14		T93	18
auto[0]	values[6]	values[7]	389	1			T10	20		T24	22		T220	12
auto[0]	values[7]	values[0]	324	1			T42	24		T33	10		T248	4
auto[0]	values[7]	values[1]	282	1			T6	2		T33	18		T15	18
auto[0]	values[7]	values[2]	502	1			T249	16		T195	12		T91	12
auto[0]	values[7]	values[3]	427	1			T15	15		T202	11		T229	41
auto[0]	values[7]	values[4]	344	1			T1	2		T42	166		T32	45
auto[0]	values[7]	values[5]	427	1			T33	5		T182	9		T17	53
auto[0]	values[7]	values[6]	245	1			T11	10		T42	9		T15	11
auto[0]	values[7]	values[7]	201	1			T33	10		T206	16		T198	8
auto[1]	values[0]	values[0]	187	1			T39	14		T47	10		T32	11
auto[1]	values[0]	values[1]	214	1			T39	9		T47	10		T200	10
auto[1]	values[0]	values[2]	223	1			T33	5		T41	5		T77	10
auto[1]	values[0]	values[3]	467	1			T186	10		T203	90		T221	12
auto[1]	values[0]	values[4]	197	1			T33	68		T45	8		T47	17
auto[1]	values[0]	values[5]	119	1			T47	8		T162	14		T250	7
auto[1]	values[0]	values[6]	211	1			T69	8		T33	30		T202	14
auto[1]	values[0]	values[7]	272	1			T47	13		T195	12		T17	5
auto[1]	values[1]	values[0]	182	1			T15	7		T200	8		T202	32
auto[1]	values[1]	values[1]	161	1			T39	6		T227	12		T20	18
auto[1]	values[1]	values[2]	72	1			T77	7		T205	9		T51	11
auto[1]	values[1]	values[3]	217	1			T45	11		T48	9		T15	19
auto[1]	values[1]	values[4]	307	1			T33	12		T217	9		T50	8
auto[1]	values[1]	values[5]	138	1			T39	4		T33	13		T43	6
auto[1]	values[1]	values[6]	354	1			T10	48		T48	6		T195	6
auto[1]	values[1]	values[7]	340	1			T19	10		T190	5		T197	9
auto[1]	values[2]	values[0]	146	1			T42	5		T48	7		T217	9
auto[1]	values[2]	values[1]	147	1			T39	10		T42	10		T44	4
auto[1]	values[2]	values[2]	245	1			T33	17		T17	9		T189	4
auto[1]	values[2]	values[3]	164	1			T39	23		T44	6		T209	5
auto[1]	values[2]	values[4]	518	1			T2	13		T195	6		T251	2
auto[1]	values[2]	values[5]	167	1			T10	24		T200	9		T186	10
auto[1]	values[2]	values[6]	199	1			T42	28		T47	7		T252	12
auto[1]	values[2]	values[7]	101	1			T39	7		T45	6		T195	12
auto[1]	values[3]	values[0]	255	1			T42	52		T195	11		T203	63
auto[1]	values[3]	values[1]	254	1			T47	14		T60	7		T17	11
auto[1]	values[3]	values[2]	328	1			T45	14		T41	214		T200	7
auto[1]	values[3]	values[3]	73	1			T48	10		T220	5		T253	15
auto[1]	values[3]	values[4]	101	1			T10	8		T195	10		T186	11
auto[1]	values[3]	values[5]	179	1			T33	45		T15	15		T195	19
auto[1]	values[3]	values[6]	451	1			T39	4		T47	7		T44	20
auto[1]	values[3]	values[7]	219	1			T42	5		T47	10		T202	11
auto[1]	values[4]	values[0]	129	1			T8	10		T44	5		T195	12
auto[1]	values[4]	values[1]	283	1			T48	30		T44	6		T182	6
auto[1]	values[4]	values[2]	203	1			T45	8		T186	8		T189	15
auto[1]	values[4]	values[3]	362	1			T45	25		T41	3		T227	7
auto[1]	values[4]	values[4]	268	1			T182	7		T55	14		T77	81
auto[1]	values[4]	values[5]	136	1			T45	10		T48	10		T203	7
auto[1]	values[4]	values[6]	139	1			T91	11		T220	6		T223	9
auto[1]	values[4]	values[7]	269	1			T200	33		T50	5		T162	5
auto[1]	values[5]	values[0]	441	1			T48	15		T200	8		T202	5
auto[1]	values[5]	values[1]	99	1			T39	8		T200	5		T162	9
auto[1]	values[5]	values[2]	124	1			T42	9		T48	9		T186	13
auto[1]	values[5]	values[3]	223	1			T195	6		T200	61		T209	13
auto[1]	values[5]	values[4]	173	1			T217	31		T223	60		T254	16
auto[1]	values[5]	values[5]	334	1			T47	10		T44	8		T217	7
auto[1]	values[5]	values[6]	227	1			T10	14		T39	8		T45	14
auto[1]	values[5]	values[7]	208	1			T8	12		T47	7		T15	12
auto[1]	values[6]	values[0]	264	1			T10	11		T77	8		T189	14
auto[1]	values[6]	values[1]	169	1			T45	18		T44	14		T186	10
auto[1]	values[6]	values[2]	92	1			T41	13		T186	6		T197	14
auto[1]	values[6]	values[3]	317	1			T47	5		T48	26		T59	24
auto[1]	values[6]	values[4]	162	1			T200	21		T202	12		T190	15
auto[1]	values[6]	values[5]	202	1			T10	9		T217	4		T189	44
auto[1]	values[6]	values[6]	260	1			T39	12		T42	6		T33	7
auto[1]	values[6]	values[7]	168	1			T10	8		T220	8		T196	4
auto[1]	values[7]	values[0]	127	1			T42	4		T33	10		T48	11
auto[1]	values[7]	values[1]	181	1			T33	2		T15	9		T200	11
auto[1]	values[7]	values[2]	271	1			T195	33		T91	8		T77	9
auto[1]	values[7]	values[3]	169	1			T40	20		T15	10		T202	9
auto[1]	values[7]	values[4]	146	1			T42	13		T255	18		T32	8
auto[1]	values[7]	values[5]	130	1			T33	15		T182	11		T17	12
auto[1]	values[7]	values[6]	139	1			T42	11		T15	9		T200	10
auto[1]	values[7]	values[7]	203	1			T33	10		T198	22		T256	9