Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	421	1			T10	6		T11	2		T39	11
auto[ReadAddrCrossIntoMailbox]	251	1			T39	4		T42	1		T33	1
auto[ReadAddrCrossOutOfMailbox]	296	1			T2	1		T10	4		T39	5
auto[ReadAddrCrossAllMailbox]	184	1			T10	3		T39	8		T42	2
auto[ReadAddrOutsideMailbox]	3456	1			T2	5		T8	13		T10	22

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255

1

T2

1

T8

11

T10

17

auto[1]

2353

1

T2

5

T8

2

T10

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	780	1			T2	1		T8	4		T10	4
read_ops[0x0b]	820	1			T2	1		T8	3		T10	9
read_ops[0x3b]	719	1			T2	2		T8	1		T10	5
read_ops[0x6b]	757	1			T8	2		T10	5		T39	5
read_ops[0xbb]	784	1			T2	1		T8	1		T10	7
read_ops[0xeb]	748	1			T2	1		T8	2		T10	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T39	3		T33	1		T241	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T42	1		T33	2		T241	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T45	1		T195	1		T200	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T46	1		T47	2		T257	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T10	1		T47	1		T44	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T2	1		T47	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T39	1		T45	1		T15	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T47	1		T19	1		T240	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T8	4		T11	1		T40	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	322	1			T10	3		T11	1		T40	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T33	2		T200	1		T17	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T10	2		T39	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T46	2		T195	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T39	1		T202	1		T77	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T39	2		T47	1		T48	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T10	3		T39	2		T33	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T39	1		T195	1		T258	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T10	1		T39	1		T186	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T2	1		T8	3		T10	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T10	1		T11	2		T39	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T33	1		T46	1		T47	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T10	1		T39	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T15	1		T44	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T39	2		T186	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T42	1		T70	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T42	1		T70	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T47	1		T44	1		T220	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T10	1		T39	3		T42	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T10	2		T40	2		T39	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T2	2		T8	1		T10	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T10	1		T18	1		T209	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T39	1		T33	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T45	1		T48	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T39	1		T47	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T189	1		T190	2		T220	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T42	1		T189	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T39	1		T47	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T45	1		T195	1		T91	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T8	2		T92	1		T42	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T10	4		T39	2		T92	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T10	2		T39	2		T47	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T39	2		T33	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T47	1		T186	1		T77	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T33	1		T45	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T42	1		T46	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T39	1		T44	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T42	1		T47	1		T48	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T10	1		T202	2		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T10	4		T39	2		T224	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T2	1		T8	1		T39	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T11	1		T39	1		T45	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T11	1		T48	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	10	1			T41	1		T15	1		T77	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T42	1		T45	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T45	1		T195	1		T186	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T48	1		T189	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T47	1		T195	1		T190	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T39	1		T33	2		T189	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T8	2		T10	5		T11	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	257	1			T2	1		T11	1		T39	2