Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4664	1			T2	21		T6	2		T119	16
values[1]	3618	1			T1	2		T8	32		T10	132
values[2]	4445	1			T10	40		T39	60		T92	18
values[3]	4358	1			T39	80		T42	227		T93	18
values[4]	3411	1			T10	52		T33	61		T41	20
values[5]	3795	1			T8	20		T39	40		T42	20
values[6]	3850	1			T69	8		T73	18		T45	40
values[7]	4423	1			T10	73		T11	10		T27	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4468	1			T39	40		T42	38		T84	8
values[1]	3375	1			T8	20		T10	156		T39	20
values[2]	4600	1			T39	20		T92	18		T42	138
values[3]	4188	1			T1	2		T11	10		T39	40
values[4]	4199	1			T2	21		T10	60		T39	20
values[5]	4454	1			T6	2		T8	32		T10	57
values[6]	3914	1			T10	24		T24	22		T39	40
values[7]	3366	1			T40	20		T39	40		T42	202

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31755

1

T1

2

T2

21

T6

2

auto[1]

809

1

T8

1

T10

9

T39

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	686	1			T33	83		T195	23		T77	22
auto[0]	values[0]	values[1]	528	1			T195	26		T186	20		T202	25
auto[0]	values[0]	values[2]	793	1			T42	20		T33	155		T47	25
auto[0]	values[0]	values[3]	500	1			T202	20		T77	42		T18	24
auto[0]	values[0]	values[4]	415	1			T2	21		T33	20		T189	20
auto[0]	values[0]	values[5]	437	1			T6	2		T119	16		T33	20
auto[0]	values[0]	values[6]	512	1			T195	20		T186	19		T59	24
auto[0]	values[0]	values[7]	678	1			T42	59		T47	20		T44	20
auto[0]	values[1]	values[0]	405	1			T182	20		T19	20		T259	51
auto[0]	values[1]	values[1]	301	1			T10	51		T48	20		T200	28
auto[0]	values[1]	values[2]	463	1			T70	2		T227	20		T202	23
auto[0]	values[1]	values[3]	450	1			T1	2		T39	20		T248	4
auto[0]	values[1]	values[4]	451	1			T10	20		T260	4		T182	20
auto[0]	values[1]	values[5]	526	1			T8	31		T10	54		T19	20
auto[0]	values[1]	values[6]	694	1			T24	22		T224	20		T42	52
auto[0]	values[1]	values[7]	225	1			T40	20		T39	20		T195	49
auto[0]	values[2]	values[0]	623	1			T39	20		T84	8		T261	10
auto[0]	values[2]	values[1]	459	1			T47	21		T50	26		T17	20
auto[0]	values[2]	values[2]	565	1			T92	18		T42	17		T33	20
auto[0]	values[2]	values[3]	499	1			T249	16		T17	21		T32	20
auto[0]	values[2]	values[4]	710	1			T10	40		T235	128		T15	20
auto[0]	values[2]	values[5]	807	1			T39	19		T45	21		T200	38
auto[0]	values[2]	values[6]	448	1			T200	25		T17	65		T143	4
auto[0]	values[2]	values[7]	228	1			T39	20		T60	20		T262	34
auto[0]	values[3]	values[0]	418	1			T42	36		T48	24		T77	20
auto[0]	values[3]	values[1]	440	1			T42	18		T15	24		T212	32
auto[0]	values[3]	values[2]	654	1			T39	20		T33	53		T74	2
auto[0]	values[3]	values[3]	685	1			T93	18		T33	71		T41	223
auto[0]	values[3]	values[4]	598	1			T39	20		T42	27		T33	32
auto[0]	values[3]	values[5]	336	1			T39	19		T77	27		T263	16
auto[0]	values[3]	values[6]	364	1			T39	20		T45	21		T15	26
auto[0]	values[3]	values[7]	769	1			T42	138		T43	20		T200	68
auto[0]	values[4]	values[0]	372	1			T41	18		T44	20		T200	20
auto[0]	values[4]	values[1]	279	1			T10	26		T15	22		T17	20
auto[0]	values[4]	values[2]	359	1			T44	20		T195	39		T182	20
auto[0]	values[4]	values[3]	356	1			T186	18		T77	36		T209	40
auto[0]	values[4]	values[4]	506	1			T33	20		T15	24		T162	20
auto[0]	values[4]	values[5]	865	1			T33	40		T241	8		T48	44
auto[0]	values[4]	values[6]	325	1			T10	24		T245	2		T44	24
auto[0]	values[4]	values[7]	277	1			T44	31		T182	20		T264	24
auto[0]	values[5]	values[0]	564	1			T45	20		T41	17		T47	20
auto[0]	values[5]	values[1]	361	1			T8	20		T39	20		T45	24
auto[0]	values[5]	values[2]	561	1			T42	20		T33	22		T45	20
auto[0]	values[5]	values[3]	499	1			T60	19		T202	22		T237	2
auto[0]	values[5]	values[4]	532	1			T15	20		T195	23		T217	19
auto[0]	values[5]	values[5]	415	1			T252	12		T205	20		T265	10
auto[0]	values[5]	values[6]	592	1			T39	20		T47	26		T44	22
auto[0]	values[5]	values[7]	195	1			T47	20		T266	22		T232	19
auto[0]	values[6]	values[0]	591	1			T48	19		T217	86		T162	20
auto[0]	values[6]	values[1]	577	1			T195	21		T200	20		T251	2
auto[0]	values[6]	values[2]	349	1			T45	20		T242	4		T44	21
auto[0]	values[6]	values[3]	437	1			T45	20		T47	20		T17	24
auto[0]	values[6]	values[4]	418	1			T17	23		T209	22		T32	72
auto[0]	values[6]	values[5]	419	1			T73	18		T47	21		T182	19
auto[0]	values[6]	values[6]	466	1			T69	8		T46	30		T195	27
auto[0]	values[6]	values[7]	486	1			T205	20		T190	39		T196	24
auto[0]	values[7]	values[0]	692	1			T39	17		T47	43		T48	42
auto[0]	values[7]	values[1]	327	1			T10	73		T45	20		T189	85
auto[0]	values[7]	values[2]	751	1			T42	78		T202	44		T189	20
auto[0]	values[7]	values[3]	663	1			T11	10		T39	20		T47	38
auto[0]	values[7]	values[4]	463	1			T33	19		T202	20		T189	23
auto[0]	values[7]	values[5]	546	1			T27	4		T28	20		T45	20
auto[0]	values[7]	values[6]	419	1			T48	98		T227	17		T195	43
auto[0]	values[7]	values[7]	426	1			T186	19		T77	58		T243	2
auto[1]	values[0]	values[0]	19	1			T77	2		T198	1		T267	2
auto[1]	values[0]	values[1]	13	1			T77	1		T18	2		T162	2
auto[1]	values[0]	values[2]	8	1			T91	1		T202	1		T268	1
auto[1]	values[0]	values[3]	20	1			T77	1		T269	4		T270	1
auto[1]	values[0]	values[4]	10	1			T190	1		T191	1		T223	2
auto[1]	values[0]	values[5]	5	1			T271	1		T272	1		T273	2
auto[1]	values[0]	values[6]	17	1			T186	1		T191	2		T51	1
auto[1]	values[0]	values[7]	23	1			T42	2		T195	3		T203	5
auto[1]	values[1]	values[0]	6	1			T145	1		T274	3		T275	2
auto[1]	values[1]	values[1]	25	1			T10	4		T190	1		T203	1
auto[1]	values[1]	values[2]	12	1			T202	2		T77	2		T276	2
auto[1]	values[1]	values[3]	12	1			T15	1		T223	1		T277	2
auto[1]	values[1]	values[4]	18	1			T55	6		T18	2		T191	2
auto[1]	values[1]	values[5]	12	1			T8	1		T10	3		T278	2
auto[1]	values[1]	values[6]	11	1			T42	1		T202	1		T209	3
auto[1]	values[1]	values[7]	7	1			T195	2		T77	1		T225	3
auto[1]	values[2]	values[0]	16	1			T209	3		T210	1		T164	1
auto[1]	values[2]	values[1]	17	1			T50	2		T190	1		T162	4
auto[1]	values[2]	values[2]	15	1			T42	3		T48	5		T20	1
auto[1]	values[2]	values[3]	5	1			T232	1		T163	1		T279	1
auto[1]	values[2]	values[4]	10	1			T200	1		T77	2		T189	2
auto[1]	values[2]	values[5]	28	1			T39	1		T45	2		T200	3
auto[1]	values[2]	values[6]	10	1			T205	5		T197	2		T198	1
auto[1]	values[2]	values[7]	5	1			T280	1		T281	2		T282	2
auto[1]	values[3]	values[0]	14	1			T42	2		T48	1		T221	1
auto[1]	values[3]	values[1]	11	1			T42	2		T15	1		T267	3
auto[1]	values[3]	values[2]	17	1			T33	3		T48	1		T250	3
auto[1]	values[3]	values[3]	10	1			T41	1		T186	1		T193	1
auto[1]	values[3]	values[4]	10	1			T42	1		T45	1		T48	2
auto[1]	values[3]	values[5]	5	1			T39	1		T193	1		T283	1
auto[1]	values[3]	values[6]	8	1			T15	1		T217	3		T209	1
auto[1]	values[3]	values[7]	19	1			T42	3		T200	2		T18	3
auto[1]	values[4]	values[0]	8	1			T41	2		T221	1		T211	1
auto[1]	values[4]	values[1]	8	1			T10	2		T15	1		T220	1
auto[1]	values[4]	values[2]	8	1			T195	2		T284	1		T274	1
auto[1]	values[4]	values[3]	9	1			T186	2		T209	1		T203	1
auto[1]	values[4]	values[4]	11	1			T15	2		T250	1		T262	1
auto[1]	values[4]	values[5]	14	1			T33	1		T182	1		T250	1
auto[1]	values[4]	values[6]	9	1			T186	3		T196	1		T279	3
auto[1]	values[4]	values[7]	5	1			T44	2		T164	1		T285	2
auto[1]	values[5]	values[0]	13	1			T41	3		T47	1		T163	1
auto[1]	values[5]	values[1]	2	1			T162	1		T283	1		-	-
auto[1]	values[5]	values[2]	12	1			T198	1		T215	1		T193	3
auto[1]	values[5]	values[3]	15	1			T60	2		T286	2		T262	1
auto[1]	values[5]	values[4]	14	1			T195	2		T217	1		T209	1
auto[1]	values[5]	values[5]	4	1			T265	2		T198	1		T163	1
auto[1]	values[5]	values[6]	12	1			T47	2		T287	2		T279	2
auto[1]	values[5]	values[7]	4	1			T232	1		T267	2		T259	1
auto[1]	values[6]	values[0]	14	1			T48	1		T217	1		T198	4
auto[1]	values[6]	values[1]	19	1			T220	2		T255	2		T267	1
auto[1]	values[6]	values[2]	11	1			T44	2		T189	3		T288	2
auto[1]	values[6]	values[3]	10	1			T47	2		T17	1		T232	2
auto[1]	values[6]	values[4]	19	1			T17	1		T209	1		T164	5
auto[1]	values[6]	values[5]	11	1			T182	1		T189	1		T250	1
auto[1]	values[6]	values[6]	11	1			T46	1		T195	1		T164	1
auto[1]	values[6]	values[7]	12	1			T190	1		T196	1		T221	1
auto[1]	values[7]	values[0]	27	1			T39	3		T47	1		T48	1
auto[1]	values[7]	values[1]	8	1			T189	2		T289	4		T272	1
auto[1]	values[7]	values[2]	22	1			T202	3		T197	6		T279	2
auto[1]	values[7]	values[3]	18	1			T47	3		T200	1		T77	1
auto[1]	values[7]	values[4]	14	1			T33	1		T202	1		T197	5
auto[1]	values[7]	values[5]	24	1			T45	1		T41	6		T186	3
auto[1]	values[7]	values[6]	16	1			T48	3		T227	3		T195	2
auto[1]	values[7]	values[7]	7	1			T186	1		T278	3		T259	1