Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	878	1			T13	4		T17	14		T18	14
all_values[1]	878	1			T13	4		T17	14		T18	14
all_values[2]	878	1			T13	4		T17	14		T18	14
all_values[3]	878	1			T13	4		T17	14		T18	14
all_values[4]	878	1			T13	4		T17	14		T18	14
all_values[5]	878	1			T13	4		T17	14		T18	14
all_values[6]	878	1			T13	4		T17	14		T18	14
all_values[7]	878	1			T13	4		T17	14		T18	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3668

1

T13

17

T17

46

T18

49

auto[1]

3356

1

T13

15

T17

66

T18

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2722

1

T13

8

T17

39

T18

48

auto[1]

4302

1

T13

24

T17

73

T18

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4005

1

T13

19

T17

61

T18

73

auto[1]

3019

1

T13

13

T17

51

T18

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	171	1			T17	5		T18	2		T19	2
all_values[0]	auto[0]	auto[0]	auto[1]	92	1			T13	1		T21	2		T162	3
all_values[0]	auto[0]	auto[1]	auto[0]	126	1			T17	1		T18	5		T19	5
all_values[0]	auto[0]	auto[1]	auto[1]	108	1			T13	1		T17	1		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T13	2		T17	3		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	188	1			T17	4		T18	6		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T17	2		T18	4		T20	2
all_values[1]	auto[0]	auto[0]	auto[1]	103	1			T17	2		T18	3		T19	3
all_values[1]	auto[0]	auto[1]	auto[0]	144	1			T13	1		T17	1		T18	2
all_values[1]	auto[0]	auto[1]	auto[1]	98	1			T13	1		T17	4		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T17	3		T18	2		T19	3
all_values[1]	auto[1]	auto[1]	auto[1]	180	1			T13	2		T17	2		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T13	1		T17	1		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T17	1		T18	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	155	1			T17	3		T18	4		T19	1
all_values[2]	auto[0]	auto[1]	auto[1]	101	1			T13	1		T17	3		T18	3
all_values[2]	auto[1]	auto[0]	auto[1]	167	1			T13	2		T17	3		T18	4
all_values[2]	auto[1]	auto[1]	auto[1]	221	1			T17	3		T18	1		T19	3
all_values[3]	auto[0]	auto[0]	auto[0]	184	1			T13	1		T17	2		T18	5
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T18	2		T19	2		T21	2
all_values[3]	auto[0]	auto[1]	auto[0]	178	1			T13	1		T17	5		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T13	1		T17	2		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T13	1		T17	1		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	162	1			T17	4		T18	1		T19	2
all_values[4]	auto[0]	auto[0]	auto[0]	180	1			T17	3		T18	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T13	2		T17	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T13	1		T18	5		T21	6
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T17	1		T18	4		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T13	1		T17	7		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	182	1			T17	2		T18	3		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	259	1			T13	2		T17	2		T18	3
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T13	1		T17	6		T18	6
all_values[5]	auto[1]	auto[0]	auto[1]	208	1			T13	1		T18	2		T19	3
all_values[5]	auto[1]	auto[1]	auto[1]	184	1			T17	6		T18	3		T19	3
all_values[6]	auto[0]	auto[0]	auto[0]	183	1			T17	1		T18	3		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	101	1			T17	2		T18	5		T19	3
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T17	5		T18	2		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T13	2		T17	1		T21	2
all_values[6]	auto[1]	auto[0]	auto[1]	200	1			T13	1		T17	3		T18	2
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T13	1		T17	2		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	181	1			T20	4		T21	2		T162	2
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T13	1		T17	2		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T17	2		T18	3		T20	5
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T13	1		T17	2		T18	3
all_values[7]	auto[1]	auto[0]	auto[1]	216	1			T13	1		T17	2		T18	2
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T13	1		T17	6		T18	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal