Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1772

1

T2

4

T3

10

T4

3

auto[1]

1733

1

T2

8

T3

14

T4

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1816

1

T2

12

T8

1

T9

17

auto[1]

1689

1

T3

24

T4

4

T23

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2833

1

T2

8

T3

24

T4

4

auto[1]

672

1

T2

4

T9

5

T13

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	708	1			T2	1		T3	5		T4	1
valid[1]	722	1			T2	3		T3	7		T9	4
valid[2]	698	1			T2	2		T3	8		T4	1
valid[3]	720	1			T2	5		T3	1		T4	1
valid[4]	657	1			T2	1		T3	3		T4	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	114	1			T9	1		T13	1		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T3	4		T4	1		T82	4
auto[0]	auto[0]	valid[1]	auto[0]	118	1			T2	1		T9	2		T13	1
auto[0]	auto[0]	valid[1]	auto[1]	177	1			T3	3		T23	2		T31	1
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T9	3		T13	1		T23	1
auto[0]	auto[0]	valid[2]	auto[1]	161	1			T3	3		T82	5		T83	1
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T45	1		T75	1		T46	2
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T4	1		T23	1		T82	3
auto[0]	auto[0]	valid[4]	auto[0]	108	1			T9	1		T13	4		T46	1
auto[0]	auto[0]	valid[4]	auto[1]	157	1			T4	1		T82	3		T310	3
auto[0]	auto[1]	valid[0]	auto[0]	105	1			T299	1		T171	2		T15	3
auto[0]	auto[1]	valid[0]	auto[1]	176	1			T3	1		T23	1		T30	2
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T2	1		T9	1		T30	1
auto[0]	auto[1]	valid[1]	auto[1]	154	1			T3	4		T82	4		T83	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T2	1		T8	1		T9	2
auto[0]	auto[1]	valid[2]	auto[1]	195	1			T3	5		T4	1		T23	1
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T2	4		T31	1		T75	3
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T3	1		T23	1		T82	3
auto[0]	auto[1]	valid[4]	auto[0]	122	1			T2	1		T9	2		T13	2
auto[0]	auto[1]	valid[4]	auto[1]	146	1			T3	3		T82	9		T310	6
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T2	1		T31	1		T45	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T2	1		T9	1		T23	2
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T2	1		T13	1		T30	1
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T45	3		T47	2		T43	1
auto[1]	auto[0]	valid[4]	auto[0]	65	1			T13	2		T299	1		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T9	2		T13	1		T46	1
auto[1]	auto[1]	valid[1]	auto[0]	61	1			T13	1		T33	1		T75	1
auto[1]	auto[1]	valid[2]	auto[0]	48	1			T23	1		T200	1		T50	1
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T2	1		T9	2		T23	2
auto[1]	auto[1]	valid[4]	auto[0]	59	1			T15	1		T44	1		T303	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal