Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44153

1

T2

162

T7

14

T8

46

auto[1]

17376

1

T3

301

T4

26

T23

110

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45387

1

T2

117

T3

301

T4

26

auto[1]

16142

1

T2

45

T7

9

T8

11

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31694	1			T2	82		T3	155		T4	12
others[1]	5296	1			T2	12		T3	24		T4	1
others[2]	5132	1			T2	17		T3	23		T4	3
others[3]	5803	1			T2	18		T3	30		T4	7
interest[1]	3358	1			T2	8		T3	20		T8	4
interest[4]	20639	1			T2	55		T3	88		T4	10
interest[64]	10246	1			T2	25		T3	49		T4	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14385	1			T2	63		T7	3		T8	21
auto[0]	auto[0]	others[1]	2492	1			T2	7		T8	1		T9	25
auto[0]	auto[0]	others[2]	2369	1			T2	12		T9	24		T13	23
auto[0]	auto[0]	others[3]	2608	1			T2	11		T7	2		T8	2
auto[0]	auto[0]	interest[1]	1514	1			T2	5		T8	3		T9	11
auto[0]	auto[0]	interest[4]	9262	1			T2	44		T7	1		T8	18
auto[0]	auto[0]	interest[64]	4643	1			T2	19		T8	8		T9	58
auto[0]	auto[1]	others[0]	9021	1			T3	155		T4	12		T23	60
auto[0]	auto[1]	others[1]	1415	1			T3	24		T4	1		T23	6
auto[0]	auto[1]	others[2]	1399	1			T3	23		T4	3		T23	5
auto[0]	auto[1]	others[3]	1665	1			T3	30		T4	7		T23	16
auto[0]	auto[1]	interest[1]	940	1			T3	20		T23	8		T30	2
auto[0]	auto[1]	interest[4]	5933	1			T3	88		T4	10		T23	35
auto[0]	auto[1]	interest[64]	2936	1			T3	49		T4	3		T23	15
auto[1]	auto[0]	others[0]	8288	1			T2	19		T7	8		T8	6
auto[1]	auto[0]	others[1]	1389	1			T2	5		T8	3		T9	21
auto[1]	auto[0]	others[2]	1364	1			T2	5		T9	14		T13	6
auto[1]	auto[0]	others[3]	1530	1			T2	7		T9	13		T13	13
auto[1]	auto[0]	interest[1]	904	1			T2	3		T8	1		T9	7
auto[1]	auto[0]	interest[4]	5444	1			T2	11		T7	6		T8	5
auto[1]	auto[0]	interest[64]	2667	1			T2	6		T7	1		T8	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal