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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T124 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2569879320 Aug 02 04:40:45 PM PDT 24 Aug 02 04:40:53 PM PDT 24 109260648 ps
T148 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1275326958 Aug 02 04:41:37 PM PDT 24 Aug 02 04:41:40 PM PDT 24 93005877 ps
T113 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2929958705 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:23 PM PDT 24 144736280 ps
T125 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4041433537 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:22 PM PDT 24 25957222 ps
T1041 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3167861618 Aug 02 04:41:40 PM PDT 24 Aug 02 04:41:48 PM PDT 24 583988009 ps
T1042 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2352036082 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 34817192 ps
T1043 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.912723485 Aug 02 04:41:57 PM PDT 24 Aug 02 04:41:58 PM PDT 24 25020382 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4285661134 Aug 02 04:41:01 PM PDT 24 Aug 02 04:41:37 PM PDT 24 8993601143 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2994623625 Aug 02 04:40:53 PM PDT 24 Aug 02 04:41:15 PM PDT 24 1531680864 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.383164537 Aug 02 04:41:40 PM PDT 24 Aug 02 04:41:41 PM PDT 24 39128763 ps
T1046 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2559691213 Aug 02 04:41:57 PM PDT 24 Aug 02 04:41:58 PM PDT 24 53518028 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4093182303 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:08 PM PDT 24 106956074 ps
T103 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.18559737 Aug 02 04:41:23 PM PDT 24 Aug 02 04:41:25 PM PDT 24 90754001 ps
T1048 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1599345712 Aug 02 04:41:49 PM PDT 24 Aug 02 04:41:49 PM PDT 24 16470000 ps
T178 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2442350153 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:39 PM PDT 24 554436148 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.90150170 Aug 02 04:41:47 PM PDT 24 Aug 02 04:41:52 PM PDT 24 817618426 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.828787515 Aug 02 04:40:51 PM PDT 24 Aug 02 04:40:53 PM PDT 24 90150013 ps
T128 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1584818126 Aug 02 04:41:11 PM PDT 24 Aug 02 04:41:14 PM PDT 24 38182662 ps
T1049 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2454218070 Aug 02 04:41:51 PM PDT 24 Aug 02 04:41:51 PM PDT 24 13172347 ps
T1050 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2959224641 Aug 02 04:41:59 PM PDT 24 Aug 02 04:42:00 PM PDT 24 16937985 ps
T157 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1861541675 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:54 PM PDT 24 508323105 ps
T134 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1183252976 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:39 PM PDT 24 106230910 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2642123393 Aug 02 04:41:52 PM PDT 24 Aug 02 04:41:53 PM PDT 24 11990528 ps
T1052 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2705514555 Aug 02 04:41:49 PM PDT 24 Aug 02 04:41:50 PM PDT 24 38443696 ps
T104 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3780517659 Aug 02 04:40:38 PM PDT 24 Aug 02 04:40:41 PM PDT 24 565532325 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3596037120 Aug 02 04:40:46 PM PDT 24 Aug 02 04:40:46 PM PDT 24 10800169 ps
T1054 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3616773156 Aug 02 04:41:37 PM PDT 24 Aug 02 04:41:41 PM PDT 24 288385254 ps
T1055 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.659468529 Aug 02 04:41:41 PM PDT 24 Aug 02 04:41:45 PM PDT 24 106383481 ps
T109 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1673056364 Aug 02 04:41:10 PM PDT 24 Aug 02 04:41:12 PM PDT 24 75296693 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2448804600 Aug 02 04:40:54 PM PDT 24 Aug 02 04:40:55 PM PDT 24 38784912 ps
T158 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.114384125 Aug 02 04:41:05 PM PDT 24 Aug 02 04:41:27 PM PDT 24 1073746824 ps
T1057 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.480655663 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:49 PM PDT 24 26149133 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3494821867 Aug 02 04:40:49 PM PDT 24 Aug 02 04:40:50 PM PDT 24 13299809 ps
T106 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.614377571 Aug 02 04:41:40 PM PDT 24 Aug 02 04:41:43 PM PDT 24 149176590 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.16484944 Aug 02 04:41:04 PM PDT 24 Aug 02 04:41:30 PM PDT 24 4829092758 ps
T1059 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.842888561 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 13553757 ps
T1060 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1340431022 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:40 PM PDT 24 14791223 ps
T1061 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1365387253 Aug 02 04:41:54 PM PDT 24 Aug 02 04:41:55 PM PDT 24 45967588 ps
T1062 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3152663845 Aug 02 04:41:21 PM PDT 24 Aug 02 04:41:22 PM PDT 24 17749631 ps
T159 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3638208580 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:42 PM PDT 24 404355711 ps
T160 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3294350771 Aug 02 04:41:49 PM PDT 24 Aug 02 04:41:50 PM PDT 24 45646838 ps
T1063 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2185607857 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:51 PM PDT 24 11820919 ps
T1064 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.413978352 Aug 02 04:41:31 PM PDT 24 Aug 02 04:41:34 PM PDT 24 105164462 ps
T129 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.976907769 Aug 02 04:41:34 PM PDT 24 Aug 02 04:41:35 PM PDT 24 136341796 ps
T1065 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.178705362 Aug 02 04:41:29 PM PDT 24 Aug 02 04:41:30 PM PDT 24 22627873 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4251331388 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:53 PM PDT 24 41360241 ps
T1067 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.856995972 Aug 02 04:41:10 PM PDT 24 Aug 02 04:41:11 PM PDT 24 23087315 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1890558688 Aug 02 04:41:04 PM PDT 24 Aug 02 04:41:08 PM PDT 24 503996916 ps
T105 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2229336614 Aug 02 04:41:04 PM PDT 24 Aug 02 04:41:09 PM PDT 24 275545374 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2009921511 Aug 02 04:41:29 PM PDT 24 Aug 02 04:41:33 PM PDT 24 156393386 ps
T1070 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.58482554 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:51 PM PDT 24 50355439 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2886904571 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:51 PM PDT 24 158035030 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4086192229 Aug 02 04:41:08 PM PDT 24 Aug 02 04:41:10 PM PDT 24 121515305 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1158170152 Aug 02 04:40:46 PM PDT 24 Aug 02 04:41:10 PM PDT 24 5033658926 ps
T108 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.546118475 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:41 PM PDT 24 190672452 ps
T130 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4293650886 Aug 02 04:41:12 PM PDT 24 Aug 02 04:41:43 PM PDT 24 548509965 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2238045325 Aug 02 04:41:19 PM PDT 24 Aug 02 04:41:24 PM PDT 24 169253913 ps
T161 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1056167304 Aug 02 04:41:34 PM PDT 24 Aug 02 04:41:37 PM PDT 24 626585629 ps
T179 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2064458343 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:45 PM PDT 24 608935628 ps
T1074 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2220404803 Aug 02 04:41:22 PM PDT 24 Aug 02 04:41:23 PM PDT 24 27045780 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2615614497 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:56 PM PDT 24 120014799 ps
T132 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4007963127 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:04 PM PDT 24 94174087 ps
T1075 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4130831604 Aug 02 04:41:33 PM PDT 24 Aug 02 04:41:34 PM PDT 24 67226894 ps
T180 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1296190928 Aug 02 04:41:33 PM PDT 24 Aug 02 04:41:52 PM PDT 24 3255676364 ps
T110 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3658358359 Aug 02 04:41:21 PM PDT 24 Aug 02 04:41:27 PM PDT 24 218013348 ps
T111 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.44033595 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:57 PM PDT 24 603700758 ps
T133 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3533095964 Aug 02 04:41:31 PM PDT 24 Aug 02 04:41:33 PM PDT 24 79443775 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4107695155 Aug 02 04:40:54 PM PDT 24 Aug 02 04:40:57 PM PDT 24 355268451 ps
T79 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.95290376 Aug 02 04:41:04 PM PDT 24 Aug 02 04:41:06 PM PDT 24 38091203 ps
T1077 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3287990974 Aug 02 04:41:49 PM PDT 24 Aug 02 04:41:53 PM PDT 24 206286128 ps
T174 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.8264755 Aug 02 04:41:50 PM PDT 24 Aug 02 04:42:12 PM PDT 24 955137105 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.39510302 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:03 PM PDT 24 87271036 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2525889300 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:34 PM PDT 24 177206859 ps
T1079 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2809587981 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:34 PM PDT 24 95446774 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1579535259 Aug 02 04:40:45 PM PDT 24 Aug 02 04:40:47 PM PDT 24 50613580 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2441640566 Aug 02 04:41:11 PM PDT 24 Aug 02 04:41:13 PM PDT 24 93874158 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3259836892 Aug 02 04:40:51 PM PDT 24 Aug 02 04:40:52 PM PDT 24 138218342 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3192818834 Aug 02 04:41:09 PM PDT 24 Aug 02 04:41:11 PM PDT 24 771064255 ps
T1084 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2863231784 Aug 02 04:41:21 PM PDT 24 Aug 02 04:41:24 PM PDT 24 81034124 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.239630015 Aug 02 04:40:55 PM PDT 24 Aug 02 04:40:56 PM PDT 24 102040994 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.796817827 Aug 02 04:40:54 PM PDT 24 Aug 02 04:40:55 PM PDT 24 21379513 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.461004438 Aug 02 04:41:10 PM PDT 24 Aug 02 04:41:11 PM PDT 24 143573657 ps
T1087 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1470249120 Aug 02 04:42:01 PM PDT 24 Aug 02 04:42:02 PM PDT 24 17054562 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2602740675 Aug 02 04:41:12 PM PDT 24 Aug 02 04:41:26 PM PDT 24 211481391 ps
T1089 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2473332473 Aug 02 04:40:46 PM PDT 24 Aug 02 04:40:46 PM PDT 24 17857714 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.323235167 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:19 PM PDT 24 791185860 ps
T1091 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2149088598 Aug 02 04:41:33 PM PDT 24 Aug 02 04:41:35 PM PDT 24 180410978 ps
T1092 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.366594578 Aug 02 04:41:47 PM PDT 24 Aug 02 04:41:47 PM PDT 24 34124386 ps
T1093 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2631141806 Aug 02 04:41:31 PM PDT 24 Aug 02 04:41:32 PM PDT 24 185914875 ps
T1094 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.981689912 Aug 02 04:41:10 PM PDT 24 Aug 02 04:41:14 PM PDT 24 622369905 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2248460055 Aug 02 04:40:49 PM PDT 24 Aug 02 04:40:53 PM PDT 24 68780762 ps
T1096 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4228823922 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:48 PM PDT 24 15023581 ps
T1097 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3036838656 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:41 PM PDT 24 28115006 ps
T175 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2656516445 Aug 02 04:40:49 PM PDT 24 Aug 02 04:40:57 PM PDT 24 1563760158 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1366154435 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:55 PM PDT 24 69002783 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3078158711 Aug 02 04:41:04 PM PDT 24 Aug 02 04:41:05 PM PDT 24 14545384 ps
T1100 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1293505943 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:49 PM PDT 24 242181046 ps
T1101 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.739889322 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:34 PM PDT 24 267589544 ps
T181 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1850588357 Aug 02 04:41:19 PM PDT 24 Aug 02 04:41:27 PM PDT 24 1297392754 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2658867994 Aug 02 04:41:05 PM PDT 24 Aug 02 04:41:08 PM PDT 24 167971130 ps
T1103 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1002639234 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:51 PM PDT 24 12044329 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2459341029 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:55 PM PDT 24 298763145 ps
T1105 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2945068843 Aug 02 04:41:47 PM PDT 24 Aug 02 04:41:48 PM PDT 24 28186598 ps
T176 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3148434341 Aug 02 04:41:21 PM PDT 24 Aug 02 04:41:34 PM PDT 24 204687331 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.426745656 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:22 PM PDT 24 34337049 ps
T1107 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2590506492 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:51 PM PDT 24 97555607 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1247090034 Aug 02 04:40:53 PM PDT 24 Aug 02 04:41:17 PM PDT 24 3218913425 ps
T1109 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3994324612 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:41 PM PDT 24 170088573 ps
T1110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2989504340 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:22 PM PDT 24 33138258 ps
T1111 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2351405275 Aug 02 04:41:31 PM PDT 24 Aug 02 04:41:36 PM PDT 24 1323329425 ps
T1112 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3081049386 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:51 PM PDT 24 26427789 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3404349893 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:04 PM PDT 24 111483116 ps
T1114 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4208630296 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 61219096 ps
T1115 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.979173883 Aug 02 04:41:23 PM PDT 24 Aug 02 04:41:26 PM PDT 24 44251753 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.848006114 Aug 02 04:40:53 PM PDT 24 Aug 02 04:40:54 PM PDT 24 214274030 ps
T1117 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2618379997 Aug 02 04:41:13 PM PDT 24 Aug 02 04:41:17 PM PDT 24 618677555 ps
T1118 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2058549649 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:21 PM PDT 24 17423641 ps
T1119 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3461186709 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 44259479 ps
T1120 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1691691287 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:54 PM PDT 24 558300082 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.213967817 Aug 02 04:41:31 PM PDT 24 Aug 02 04:41:35 PM PDT 24 388180180 ps
T1122 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3994871883 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:35 PM PDT 24 41688245 ps
T1123 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1832569899 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:43 PM PDT 24 169231739 ps
T1124 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2807500249 Aug 02 04:41:46 PM PDT 24 Aug 02 04:41:47 PM PDT 24 16060147 ps
T173 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3242115374 Aug 02 04:41:33 PM PDT 24 Aug 02 04:41:37 PM PDT 24 504432979 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.849859833 Aug 02 04:41:23 PM PDT 24 Aug 02 04:41:26 PM PDT 24 113753754 ps
T1126 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3079584205 Aug 02 04:41:23 PM PDT 24 Aug 02 04:41:26 PM PDT 24 131696262 ps
T1127 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.685635515 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:39 PM PDT 24 17575116 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.189332727 Aug 02 04:41:32 PM PDT 24 Aug 02 04:41:34 PM PDT 24 72281509 ps
T1129 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3964659087 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:24 PM PDT 24 347271577 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2487176970 Aug 02 04:41:33 PM PDT 24 Aug 02 04:41:33 PM PDT 24 24678821 ps
T1131 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3471106123 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 75401875 ps
T1132 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4183253068 Aug 02 04:40:45 PM PDT 24 Aug 02 04:40:49 PM PDT 24 57972532 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1823349986 Aug 02 04:41:13 PM PDT 24 Aug 02 04:41:15 PM PDT 24 161817260 ps
T1134 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.924618917 Aug 02 04:41:12 PM PDT 24 Aug 02 04:41:14 PM PDT 24 29727533 ps
T1135 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2657510637 Aug 02 04:41:50 PM PDT 24 Aug 02 04:41:50 PM PDT 24 51080931 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.453383196 Aug 02 04:41:02 PM PDT 24 Aug 02 04:41:03 PM PDT 24 32524331 ps
T1137 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2581143822 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:49 PM PDT 24 52723106 ps
T1138 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2208033401 Aug 02 04:41:21 PM PDT 24 Aug 02 04:41:22 PM PDT 24 47140264 ps
T1139 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2174436547 Aug 02 04:41:48 PM PDT 24 Aug 02 04:41:49 PM PDT 24 21887768 ps
T1140 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.56432964 Aug 02 04:41:51 PM PDT 24 Aug 02 04:41:52 PM PDT 24 14696382 ps
T1141 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3351873037 Aug 02 04:41:47 PM PDT 24 Aug 02 04:41:48 PM PDT 24 47873680 ps
T1142 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1175601455 Aug 02 04:41:34 PM PDT 24 Aug 02 04:41:35 PM PDT 24 29397860 ps
T1143 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2068912690 Aug 02 04:41:01 PM PDT 24 Aug 02 04:41:02 PM PDT 24 39822842 ps
T1144 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.484881529 Aug 02 04:41:38 PM PDT 24 Aug 02 04:41:42 PM PDT 24 157139265 ps
T1145 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4250399853 Aug 02 04:41:39 PM PDT 24 Aug 02 04:41:41 PM PDT 24 351817114 ps
T1146 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1440978117 Aug 02 04:41:47 PM PDT 24 Aug 02 04:42:06 PM PDT 24 294887549 ps
T1147 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2383206489 Aug 02 04:41:11 PM PDT 24 Aug 02 04:41:12 PM PDT 24 18379435 ps
T1148 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4009112509 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 111964671 ps
T1149 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3197421100 Aug 02 04:41:34 PM PDT 24 Aug 02 04:41:41 PM PDT 24 116279610 ps
T1150 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.146977760 Aug 02 04:41:20 PM PDT 24 Aug 02 04:41:23 PM PDT 24 95227117 ps

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4030956678
Short name T8
Test name
Test status
Simulation time 44011435338 ps
CPU time 38.37 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 239256 kb
Host smart-7ea7a6a1-9d73-4d39-aa82-ac8adbcf2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030956678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4030956678
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2389043896
Short name T45
Test name
Test status
Simulation time 41151234608 ps
CPU time 399.14 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:50:27 PM PDT 24
Peak memory 265856 kb
Host smart-b73c0180-d103-4e8a-9696-c5af133956fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389043896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2389043896
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.907084936
Short name T13
Test name
Test status
Simulation time 22294398311 ps
CPU time 98.42 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 257456 kb
Host smart-6a1a54e9-350e-4989-a78a-9e0ac371dc52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907084936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.907084936
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1045780569
Short name T94
Test name
Test status
Simulation time 707043188 ps
CPU time 14.51 seconds
Started Aug 02 04:41:11 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 215516 kb
Host smart-c82c6be7-75af-476e-8e20-e591d7856405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045780569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1045780569
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4177261468
Short name T77
Test name
Test status
Simulation time 38942091758 ps
CPU time 160.27 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 267272 kb
Host smart-20b798d5-5513-4e10-bd46-88792511c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177261468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4177261468
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2442444872
Short name T47
Test name
Test status
Simulation time 116197740096 ps
CPU time 589.36 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:55:18 PM PDT 24
Peak memory 265636 kb
Host smart-e403f04f-fbbe-45bc-b5e3-b1cccab82fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442444872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2442444872
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.80120000
Short name T65
Test name
Test status
Simulation time 16716848 ps
CPU time 0.79 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 216548 kb
Host smart-f97d2fd9-7006-4ca2-b6cf-f7c0c0f85d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80120000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.80120000
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1108409427
Short name T18
Test name
Test status
Simulation time 11475834293 ps
CPU time 62.37 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:46:34 PM PDT 24
Peak memory 254936 kb
Host smart-cebaf026-009d-49c2-95e2-0114a835a25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108409427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1108409427
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2050110706
Short name T15
Test name
Test status
Simulation time 248789345675 ps
CPU time 613.05 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:53:44 PM PDT 24
Peak memory 271508 kb
Host smart-df336e66-eb2e-40f2-ae96-9d92f3ef88b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050110706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2050110706
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3270004811
Short name T33
Test name
Test status
Simulation time 21590455115 ps
CPU time 88.89 seconds
Started Aug 02 04:46:07 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 268212 kb
Host smart-7ada947b-2b56-44b0-9a27-b7ddd622d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270004811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3270004811
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3244715113
Short name T14
Test name
Test status
Simulation time 35578152 ps
CPU time 0.92 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:49 PM PDT 24
Peak memory 235512 kb
Host smart-1b842bf8-e089-4cce-9a2f-c693ee3b0bf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244715113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3244715113
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3417255012
Short name T189
Test name
Test status
Simulation time 8806162688 ps
CPU time 90.6 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 266028 kb
Host smart-d84325ef-4fcf-4a4b-a821-37916ad7e75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417255012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3417255012
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2230482505
Short name T149
Test name
Test status
Simulation time 5391240334 ps
CPU time 20.97 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:21 PM PDT 24
Peak memory 225316 kb
Host smart-0b1301b9-dd2f-4dc3-8399-e1410e0583ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230482505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2230482505
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3830537854
Short name T200
Test name
Test status
Simulation time 56521029590 ps
CPU time 126.25 seconds
Started Aug 02 04:44:09 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 264636 kb
Host smart-5259cc99-9715-441f-9c16-cd611f65b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830537854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3830537854
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4063061761
Short name T146
Test name
Test status
Simulation time 246720463481 ps
CPU time 532.55 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:52:32 PM PDT 24
Peak memory 290792 kb
Host smart-82a837ba-06a7-47ca-b59a-4be015525f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063061761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4063061761
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.555788201
Short name T98
Test name
Test status
Simulation time 2002330733 ps
CPU time 5.59 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:44 PM PDT 24
Peak memory 215560 kb
Host smart-91363a15-c207-4d3d-ba92-c401fd762e92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555788201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.555788201
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2569879320
Short name T124
Test name
Test status
Simulation time 109260648 ps
CPU time 7.79 seconds
Started Aug 02 04:40:45 PM PDT 24
Finished Aug 02 04:40:53 PM PDT 24
Peak memory 215460 kb
Host smart-3073f85a-6c91-44ad-8408-dd00f3faeaae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569879320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2569879320
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1193408034
Short name T193
Test name
Test status
Simulation time 47363700835 ps
CPU time 187.62 seconds
Started Aug 02 04:43:18 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 268248 kb
Host smart-89625517-3100-4baa-9196-ca172789ddf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193408034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1193408034
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3421536976
Short name T20
Test name
Test status
Simulation time 33521743626 ps
CPU time 314.65 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:50:12 PM PDT 24
Peak memory 267300 kb
Host smart-06f66cf6-53e8-40d8-b8bd-7e4b11774613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421536976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3421536976
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2214561596
Short name T186
Test name
Test status
Simulation time 62506692569 ps
CPU time 318.4 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 257496 kb
Host smart-40a6e377-c9ee-4884-943c-0c3a4d2698bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214561596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2214561596
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.880487165
Short name T358
Test name
Test status
Simulation time 50511202 ps
CPU time 1.11 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 217012 kb
Host smart-a40c6e2b-be15-4639-9a1a-b44b0ae1ef52
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880487165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.880487165
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.469853901
Short name T222
Test name
Test status
Simulation time 53474390470 ps
CPU time 534.52 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:51:50 PM PDT 24
Peak memory 256208 kb
Host smart-e357fca0-7335-472d-9ff6-54381a9dc20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469853901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.469853901
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2838856588
Short name T182
Test name
Test status
Simulation time 113803719196 ps
CPU time 198.31 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:48:51 PM PDT 24
Peak memory 253088 kb
Host smart-4d872151-ea1a-46b4-9ecd-0c3ed68a2ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838856588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2838856588
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3336481279
Short name T75
Test name
Test status
Simulation time 14110173415 ps
CPU time 72.79 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:44:51 PM PDT 24
Peak memory 250284 kb
Host smart-cf3e849b-6ed6-4911-991c-a01fdcb90658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336481279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3336481279
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3054196588
Short name T39
Test name
Test status
Simulation time 9700987409 ps
CPU time 122.28 seconds
Started Aug 02 04:44:45 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 239704 kb
Host smart-4d06d34a-cff5-4bfd-9438-517904f723b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054196588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3054196588
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2495219746
Short name T50
Test name
Test status
Simulation time 35029045740 ps
CPU time 84.48 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 256016 kb
Host smart-8a2e556e-d8a7-428b-a912-eeb96311d441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495219746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2495219746
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3840501298
Short name T223
Test name
Test status
Simulation time 24376039227 ps
CPU time 95.64 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 251952 kb
Host smart-df57f0c0-f92f-4ebd-b9e4-a6d828ece6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840501298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3840501298
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3976099702
Short name T57
Test name
Test status
Simulation time 38615451 ps
CPU time 0.66 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 205668 kb
Host smart-61a59f5c-eea8-4a87-8a0c-dd5a0227c398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976099702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3976099702
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2248460055
Short name T1095
Test name
Test status
Simulation time 68780762 ps
CPU time 4.17 seconds
Started Aug 02 04:40:49 PM PDT 24
Finished Aug 02 04:40:53 PM PDT 24
Peak memory 216612 kb
Host smart-8f092789-7a5a-4ca2-82df-969cf94873ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248460055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
248460055
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3529463220
Short name T99
Test name
Test status
Simulation time 778472990 ps
CPU time 11.42 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:44 PM PDT 24
Peak memory 215524 kb
Host smart-b361a30d-5c4c-4d18-92e5-1f20e050c54e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529463220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3529463220
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.916892282
Short name T279
Test name
Test status
Simulation time 235632399718 ps
CPU time 404.67 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:51:19 PM PDT 24
Peak memory 255400 kb
Host smart-84f060fc-4809-4b4f-bfd9-e1ce6aa87cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916892282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.916892282
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.188477684
Short name T164
Test name
Test status
Simulation time 111867682912 ps
CPU time 218.63 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 257996 kb
Host smart-83c65eef-fe6f-49b8-8cec-37be1407c673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188477684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.188477684
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.134769759
Short name T292
Test name
Test status
Simulation time 567527583 ps
CPU time 16.33 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 225128 kb
Host smart-f012d921-b0e2-4c25-9e89-fe5578e8900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134769759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.134769759
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.652081893
Short name T171
Test name
Test status
Simulation time 39238975830 ps
CPU time 60.07 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:45:04 PM PDT 24
Peak memory 252092 kb
Host smart-ebb9d070-6e96-45ae-951e-823249abd7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652081893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.652081893
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3178310449
Short name T1023
Test name
Test status
Simulation time 35600544099 ps
CPU time 381.17 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:50:53 PM PDT 24
Peak memory 265088 kb
Host smart-5a3f619f-297f-498d-94d3-13d5c652f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178310449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3178310449
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1673071379
Short name T23
Test name
Test status
Simulation time 26092450719 ps
CPU time 234.99 seconds
Started Aug 02 04:44:47 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 250228 kb
Host smart-9c71f452-e022-4ec8-b3e0-1777181e5cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673071379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1673071379
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2121471734
Short name T272
Test name
Test status
Simulation time 2964696839 ps
CPU time 73.64 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 249772 kb
Host smart-0f58bc92-8935-4c65-919e-010216de13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121471734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2121471734
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1488963415
Short name T259
Test name
Test status
Simulation time 68119847824 ps
CPU time 176.12 seconds
Started Aug 02 04:44:14 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 274388 kb
Host smart-403e9b04-90bd-4cd8-bf23-df91ae6d2c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488963415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1488963415
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3973022014
Short name T145
Test name
Test status
Simulation time 19640983418 ps
CPU time 136.53 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 282156 kb
Host smart-15feea52-28bf-487c-a608-c43e9af14002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973022014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3973022014
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3593187113
Short name T87
Test name
Test status
Simulation time 81474828 ps
CPU time 2.61 seconds
Started Aug 02 04:43:41 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 233276 kb
Host smart-f0f0da42-a8a8-4f8a-b1de-a0ffdf16f8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593187113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3593187113
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2656516445
Short name T175
Test name
Test status
Simulation time 1563760158 ps
CPU time 7.92 seconds
Started Aug 02 04:40:49 PM PDT 24
Finished Aug 02 04:40:57 PM PDT 24
Peak memory 216244 kb
Host smart-4a7156e7-c186-4d6c-b900-82c3199e764a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656516445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2656516445
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1296190928
Short name T180
Test name
Test status
Simulation time 3255676364 ps
CPU time 18.65 seconds
Started Aug 02 04:41:33 PM PDT 24
Finished Aug 02 04:41:52 PM PDT 24
Peak memory 216072 kb
Host smart-ff570062-5b9e-482d-9bd3-55565b91311d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296190928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1296190928
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2089400714
Short name T823
Test name
Test status
Simulation time 1065134164 ps
CPU time 20.85 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:44:14 PM PDT 24
Peak memory 237192 kb
Host smart-5099ecab-2844-433c-b486-8f98b816fcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089400714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2089400714
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3381702502
Short name T311
Test name
Test status
Simulation time 5077020035 ps
CPU time 13.36 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:43:28 PM PDT 24
Peak memory 217000 kb
Host smart-ed04a513-b539-4e14-a5aa-89f53056b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381702502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3381702502
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.431726816
Short name T280
Test name
Test status
Simulation time 49602176721 ps
CPU time 138.82 seconds
Started Aug 02 04:43:45 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 265900 kb
Host smart-8b15ce05-ca5a-487e-8710-1e0c44dd5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431726816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.431726816
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3150017843
Short name T165
Test name
Test status
Simulation time 85096350832 ps
CPU time 402.59 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:50:22 PM PDT 24
Peak memory 258044 kb
Host smart-1b30a144-0064-4412-be31-a91499b78f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150017843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3150017843
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2859963781
Short name T163
Test name
Test status
Simulation time 3194841528 ps
CPU time 63.54 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 249824 kb
Host smart-52b72f56-4aaf-4819-bc38-2907adee390a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859963781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2859963781
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.452457951
Short name T91
Test name
Test status
Simulation time 10967874776 ps
CPU time 73.7 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:45:47 PM PDT 24
Peak memory 249824 kb
Host smart-312a2263-adca-443e-96d7-bca6bbd2e6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452457951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.452457951
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.328041205
Short name T162
Test name
Test status
Simulation time 9606722864 ps
CPU time 123.28 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 252288 kb
Host smart-db806af1-f980-4b9c-9d28-cbd6e6ce3cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328041205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.328041205
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4085540430
Short name T102
Test name
Test status
Simulation time 272813410 ps
CPU time 3.45 seconds
Started Aug 02 04:41:34 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 215584 kb
Host smart-34a74d59-053d-47ec-9c5c-76a5370034ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085540430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4085540430
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1793892320
Short name T213
Test name
Test status
Simulation time 5512355224 ps
CPU time 36.2 seconds
Started Aug 02 04:43:15 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 249848 kb
Host smart-df939200-4947-4c9f-abbf-8154bebdef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793892320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1793892320
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2941683725
Short name T78
Test name
Test status
Simulation time 293133189 ps
CPU time 1.14 seconds
Started Aug 02 04:40:44 PM PDT 24
Finished Aug 02 04:40:45 PM PDT 24
Peak memory 216404 kb
Host smart-266350c1-2ead-49dd-bd25-5755ff290c44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941683725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2941683725
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1158170152
Short name T1073
Test name
Test status
Simulation time 5033658926 ps
CPU time 24.25 seconds
Started Aug 02 04:40:46 PM PDT 24
Finished Aug 02 04:41:10 PM PDT 24
Peak memory 207368 kb
Host smart-ce96d43a-36d3-4dbc-9363-5f26a01eecb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158170152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1158170152
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1579535259
Short name T1080
Test name
Test status
Simulation time 50613580 ps
CPU time 1.75 seconds
Started Aug 02 04:40:45 PM PDT 24
Finished Aug 02 04:40:47 PM PDT 24
Peak memory 215436 kb
Host smart-68149f13-d56b-4a50-a23e-96440129da19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579535259 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1579535259
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3259836892
Short name T1082
Test name
Test status
Simulation time 138218342 ps
CPU time 1.29 seconds
Started Aug 02 04:40:51 PM PDT 24
Finished Aug 02 04:40:52 PM PDT 24
Peak memory 215472 kb
Host smart-2d290c7b-e5c3-4dcf-9030-6ce0cca3db21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259836892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
259836892
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.555598067
Short name T1037
Test name
Test status
Simulation time 86471711 ps
CPU time 0.72 seconds
Started Aug 02 04:40:43 PM PDT 24
Finished Aug 02 04:40:43 PM PDT 24
Peak memory 203872 kb
Host smart-2af6b782-4848-42be-9f08-189f5e89ad6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555598067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.555598067
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2176463367
Short name T123
Test name
Test status
Simulation time 315673806 ps
CPU time 1.73 seconds
Started Aug 02 04:40:44 PM PDT 24
Finished Aug 02 04:40:46 PM PDT 24
Peak memory 215424 kb
Host smart-59d5c7df-318f-43b7-81dd-2aa61eb15a7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176463367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2176463367
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3494821867
Short name T1058
Test name
Test status
Simulation time 13299809 ps
CPU time 0.66 seconds
Started Aug 02 04:40:49 PM PDT 24
Finished Aug 02 04:40:50 PM PDT 24
Peak memory 203940 kb
Host smart-63d8dea7-816a-4181-9eff-ce8460692958
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494821867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3494821867
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4183253068
Short name T1132
Test name
Test status
Simulation time 57972532 ps
CPU time 3.66 seconds
Started Aug 02 04:40:45 PM PDT 24
Finished Aug 02 04:40:49 PM PDT 24
Peak memory 207076 kb
Host smart-178a3f3d-e710-4f3d-99f2-3f9b3c542d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183253068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4183253068
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3780517659
Short name T104
Test name
Test status
Simulation time 565532325 ps
CPU time 2.64 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:40:41 PM PDT 24
Peak memory 215600 kb
Host smart-bcf8e197-967f-461a-a68e-5af46b968bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780517659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
780517659
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4090634723
Short name T116
Test name
Test status
Simulation time 459131249 ps
CPU time 6.84 seconds
Started Aug 02 04:40:36 PM PDT 24
Finished Aug 02 04:40:43 PM PDT 24
Peak memory 215476 kb
Host smart-5a14002a-624c-43c6-b7ce-fc4bee7a666d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090634723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4090634723
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1247090034
Short name T1108
Test name
Test status
Simulation time 3218913425 ps
CPU time 23.79 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:41:17 PM PDT 24
Peak memory 215560 kb
Host smart-d048c98f-a4fb-4cbb-932d-1bd535912fb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247090034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1247090034
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2994623625
Short name T1044
Test name
Test status
Simulation time 1531680864 ps
CPU time 21.94 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:41:15 PM PDT 24
Peak memory 207104 kb
Host smart-3d501370-7044-4007-b99b-4c31ac2f5044
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994623625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2994623625
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.796817827
Short name T1085
Test name
Test status
Simulation time 21379513 ps
CPU time 0.92 seconds
Started Aug 02 04:40:54 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 207052 kb
Host smart-ebfa273d-b0be-4b62-a723-901b58cd2dd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796817827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.796817827
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4107695155
Short name T1076
Test name
Test status
Simulation time 355268451 ps
CPU time 2.67 seconds
Started Aug 02 04:40:54 PM PDT 24
Finished Aug 02 04:40:57 PM PDT 24
Peak memory 217092 kb
Host smart-e9a46e50-5103-47cd-b236-2e12c7db15b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107695155 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4107695155
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.848006114
Short name T1116
Test name
Test status
Simulation time 214274030 ps
CPU time 1.34 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:54 PM PDT 24
Peak memory 215372 kb
Host smart-dc410e77-39ba-445f-b54b-8d178a80533b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848006114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.848006114
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2473332473
Short name T1089
Test name
Test status
Simulation time 17857714 ps
CPU time 0.73 seconds
Started Aug 02 04:40:46 PM PDT 24
Finished Aug 02 04:40:46 PM PDT 24
Peak memory 204176 kb
Host smart-a9e4a6c0-3ca0-4296-ba75-5484494d6fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473332473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
473332473
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.828787515
Short name T127
Test name
Test status
Simulation time 90150013 ps
CPU time 1.84 seconds
Started Aug 02 04:40:51 PM PDT 24
Finished Aug 02 04:40:53 PM PDT 24
Peak memory 215388 kb
Host smart-9448723e-8ae0-410c-972a-bc665bbc572e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828787515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.828787515
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3596037120
Short name T1053
Test name
Test status
Simulation time 10800169 ps
CPU time 0.67 seconds
Started Aug 02 04:40:46 PM PDT 24
Finished Aug 02 04:40:46 PM PDT 24
Peak memory 204100 kb
Host smart-429a915b-a456-4ee5-a02f-62d203f9f8a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596037120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3596037120
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2459341029
Short name T1104
Test name
Test status
Simulation time 298763145 ps
CPU time 1.72 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 215452 kb
Host smart-d0d1fbd6-86c2-477f-8a2e-644c288fa4b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459341029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2459341029
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3994871883
Short name T1122
Test name
Test status
Simulation time 41688245 ps
CPU time 2.57 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 216524 kb
Host smart-5523220d-b8f9-42eb-96fd-7fdb6f59a77d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994871883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3994871883
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2149088598
Short name T1091
Test name
Test status
Simulation time 180410978 ps
CPU time 1.75 seconds
Started Aug 02 04:41:33 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 207256 kb
Host smart-5408f85c-5d1f-4cde-847b-df3a704de9cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149088598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2149088598
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.178705362
Short name T1065
Test name
Test status
Simulation time 22627873 ps
CPU time 0.71 seconds
Started Aug 02 04:41:29 PM PDT 24
Finished Aug 02 04:41:30 PM PDT 24
Peak memory 203852 kb
Host smart-cd458103-1bdb-42d1-ac2a-32691ada49c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178705362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.178705362
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.213967817
Short name T1121
Test name
Test status
Simulation time 388180180 ps
CPU time 4.1 seconds
Started Aug 02 04:41:31 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 215372 kb
Host smart-814e4acc-38d5-4672-b7f0-d7acf7bef026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213967817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.213967817
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3658358359
Short name T110
Test name
Test status
Simulation time 218013348 ps
CPU time 6.32 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:27 PM PDT 24
Peak memory 215728 kb
Host smart-cc0705a9-86b3-4c38-a602-ecc560d043c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658358359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3658358359
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2809587981
Short name T1079
Test name
Test status
Simulation time 95446774 ps
CPU time 2.08 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 216440 kb
Host smart-c90c9405-63e1-4ea3-9fb4-8fbd20bff2ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809587981 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2809587981
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.739889322
Short name T1101
Test name
Test status
Simulation time 267589544 ps
CPU time 1.92 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 215416 kb
Host smart-ee53c653-6faa-4d4d-a6e8-6a6f78a778b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739889322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.739889322
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1175601455
Short name T1142
Test name
Test status
Simulation time 29397860 ps
CPU time 0.73 seconds
Started Aug 02 04:41:34 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 204168 kb
Host smart-1e80f6ee-b1fa-41ec-b922-781c6439ce33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175601455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1175601455
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2009921511
Short name T1069
Test name
Test status
Simulation time 156393386 ps
CPU time 3.81 seconds
Started Aug 02 04:41:29 PM PDT 24
Finished Aug 02 04:41:33 PM PDT 24
Peak memory 215096 kb
Host smart-401475aa-ff66-455e-9a4b-9c92c58f1f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009921511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2009921511
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.189332727
Short name T1128
Test name
Test status
Simulation time 72281509 ps
CPU time 2.39 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 216564 kb
Host smart-8bf30c43-ef47-4102-a225-75f1b894b7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189332727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.189332727
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3197421100
Short name T1149
Test name
Test status
Simulation time 116279610 ps
CPU time 6.35 seconds
Started Aug 02 04:41:34 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 215528 kb
Host smart-7b5b8ba4-ebe1-4594-a6e0-9f98f4ca9901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197421100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3197421100
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1056167304
Short name T161
Test name
Test status
Simulation time 626585629 ps
CPU time 3.81 seconds
Started Aug 02 04:41:34 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 217260 kb
Host smart-887e781c-c063-45a3-9a0c-64bd19703514
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056167304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1056167304
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3533095964
Short name T133
Test name
Test status
Simulation time 79443775 ps
CPU time 1.82 seconds
Started Aug 02 04:41:31 PM PDT 24
Finished Aug 02 04:41:33 PM PDT 24
Peak memory 215392 kb
Host smart-ddc0239e-6fed-45f4-a31e-8eb74ddf98e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533095964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3533095964
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2487176970
Short name T1130
Test name
Test status
Simulation time 24678821 ps
CPU time 0.73 seconds
Started Aug 02 04:41:33 PM PDT 24
Finished Aug 02 04:41:33 PM PDT 24
Peak memory 203892 kb
Host smart-65765305-4251-413f-9fa0-1cb86c335497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487176970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2487176970
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2351405275
Short name T1111
Test name
Test status
Simulation time 1323329425 ps
CPU time 4.3 seconds
Started Aug 02 04:41:31 PM PDT 24
Finished Aug 02 04:41:36 PM PDT 24
Peak memory 215484 kb
Host smart-e61eb435-9d20-4364-8568-ab90533af226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351405275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2351405275
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2525889300
Short name T1078
Test name
Test status
Simulation time 177206859 ps
CPU time 2.44 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 217888 kb
Host smart-a33bca0e-0f00-40b5-a7d0-214442ff58a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525889300 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2525889300
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.976907769
Short name T129
Test name
Test status
Simulation time 136341796 ps
CPU time 1.16 seconds
Started Aug 02 04:41:34 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 207244 kb
Host smart-c400e0c6-2853-4614-bcca-effab701b24f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976907769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.976907769
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4130831604
Short name T1075
Test name
Test status
Simulation time 67226894 ps
CPU time 0.7 seconds
Started Aug 02 04:41:33 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 203816 kb
Host smart-1380a2d4-de2a-4ef6-8d66-a9d8123ea9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130831604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4130831604
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.413978352
Short name T1064
Test name
Test status
Simulation time 105164462 ps
CPU time 2.87 seconds
Started Aug 02 04:41:31 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 215372 kb
Host smart-d178621a-9bc7-47a3-99dd-6aaebbc0a460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413978352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.413978352
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2631141806
Short name T1093
Test name
Test status
Simulation time 185914875 ps
CPU time 1.55 seconds
Started Aug 02 04:41:31 PM PDT 24
Finished Aug 02 04:41:32 PM PDT 24
Peak memory 216680 kb
Host smart-70616b0c-1904-4c3c-933f-20af841082c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631141806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2631141806
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2442350153
Short name T178
Test name
Test status
Simulation time 554436148 ps
CPU time 6.63 seconds
Started Aug 02 04:41:32 PM PDT 24
Finished Aug 02 04:41:39 PM PDT 24
Peak memory 215736 kb
Host smart-9db25d3c-2b78-4221-a8da-b78d28268e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442350153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2442350153
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.584253034
Short name T96
Test name
Test status
Simulation time 179290846 ps
CPU time 3.89 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:42 PM PDT 24
Peak memory 218228 kb
Host smart-aaebf7cb-7619-4646-86c9-f6fe665f65a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584253034 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.584253034
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1370241580
Short name T122
Test name
Test status
Simulation time 63607548 ps
CPU time 1.9 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:40 PM PDT 24
Peak memory 215380 kb
Host smart-89f49246-5561-4033-96ad-e21a4aef7cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370241580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1370241580
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.685635515
Short name T1127
Test name
Test status
Simulation time 17575116 ps
CPU time 0.73 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:39 PM PDT 24
Peak memory 203852 kb
Host smart-622dd73a-dc9f-4342-bca5-a66b304ab835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685635515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.685635515
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1275326958
Short name T148
Test name
Test status
Simulation time 93005877 ps
CPU time 2.65 seconds
Started Aug 02 04:41:37 PM PDT 24
Finished Aug 02 04:41:40 PM PDT 24
Peak memory 215420 kb
Host smart-c3d41f71-c513-4161-8ec4-6de9812954a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275326958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1275326958
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3242115374
Short name T173
Test name
Test status
Simulation time 504432979 ps
CPU time 4.26 seconds
Started Aug 02 04:41:33 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 215756 kb
Host smart-88be2625-0afa-4502-ae63-3884256c66d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242115374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3242115374
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3167861618
Short name T1041
Test name
Test status
Simulation time 583988009 ps
CPU time 8.26 seconds
Started Aug 02 04:41:40 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 215164 kb
Host smart-1f9fc362-6de9-41d0-819c-b8058d469f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167861618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3167861618
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.659468529
Short name T1055
Test name
Test status
Simulation time 106383481 ps
CPU time 3.93 seconds
Started Aug 02 04:41:41 PM PDT 24
Finished Aug 02 04:41:45 PM PDT 24
Peak memory 217100 kb
Host smart-d58e8230-77cd-4aa5-96f0-bb609464550c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659468529 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.659468529
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3036838656
Short name T1097
Test name
Test status
Simulation time 28115006 ps
CPU time 1.73 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 215100 kb
Host smart-2baa2619-c1ab-422f-94bb-6285c059d36e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036838656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3036838656
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.424321328
Short name T1040
Test name
Test status
Simulation time 19692553 ps
CPU time 0.68 seconds
Started Aug 02 04:41:37 PM PDT 24
Finished Aug 02 04:41:38 PM PDT 24
Peak memory 203736 kb
Host smart-2b018480-9871-4d9e-9550-f187347138cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424321328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.424321328
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3994324612
Short name T1109
Test name
Test status
Simulation time 170088573 ps
CPU time 2.86 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 215392 kb
Host smart-d7439ed8-7526-495c-9aa0-9261d55fb0d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994324612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3994324612
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3110861937
Short name T100
Test name
Test status
Simulation time 2490722451 ps
CPU time 14.51 seconds
Started Aug 02 04:41:37 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 215520 kb
Host smart-7b4f7a81-d552-4c73-9aa2-20fd503ce3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110861937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3110861937
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1832569899
Short name T1123
Test name
Test status
Simulation time 169231739 ps
CPU time 4.07 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:43 PM PDT 24
Peak memory 217252 kb
Host smart-f4084355-9d7a-458c-a6a4-3b42c4680ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832569899 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1832569899
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4250399853
Short name T1145
Test name
Test status
Simulation time 351817114 ps
CPU time 1.19 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 206900 kb
Host smart-66c77ae8-bf36-469c-932d-91d9e800df91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250399853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4250399853
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1340431022
Short name T1060
Test name
Test status
Simulation time 14791223 ps
CPU time 0.73 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:40 PM PDT 24
Peak memory 204060 kb
Host smart-67e51fa9-c84f-4267-81cb-9c1fdea2cc55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340431022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1340431022
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.484881529
Short name T1144
Test name
Test status
Simulation time 157139265 ps
CPU time 4.4 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:42 PM PDT 24
Peak memory 215388 kb
Host smart-7ff63ff6-aabc-4fe4-a469-c0a93156ce6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484881529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.484881529
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.546118475
Short name T108
Test name
Test status
Simulation time 190672452 ps
CPU time 2.9 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 216600 kb
Host smart-1e0844fe-a519-4a24-8977-47162babe84f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546118475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.546118475
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2064458343
Short name T179
Test name
Test status
Simulation time 608935628 ps
CPU time 6.41 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:45 PM PDT 24
Peak memory 215348 kb
Host smart-4c3c05f1-2225-403d-b75f-c92302b6a97b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064458343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2064458343
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3638208580
Short name T159
Test name
Test status
Simulation time 404355711 ps
CPU time 2.63 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:42 PM PDT 24
Peak memory 215588 kb
Host smart-5d016560-511e-46a7-9599-9f478771e42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638208580 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3638208580
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1183252976
Short name T134
Test name
Test status
Simulation time 106230910 ps
CPU time 1.15 seconds
Started Aug 02 04:41:38 PM PDT 24
Finished Aug 02 04:41:39 PM PDT 24
Peak memory 215436 kb
Host smart-5274480d-f022-4a10-b9e8-88b4856f53dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183252976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1183252976
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.383164537
Short name T1045
Test name
Test status
Simulation time 39128763 ps
CPU time 0.73 seconds
Started Aug 02 04:41:40 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 203892 kb
Host smart-3f3ce674-222b-4878-ad64-b970e5544974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383164537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.383164537
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3616773156
Short name T1054
Test name
Test status
Simulation time 288385254 ps
CPU time 3.64 seconds
Started Aug 02 04:41:37 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 215404 kb
Host smart-2e3fc7fd-217d-4de3-aa9e-7d7904936c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616773156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3616773156
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.614377571
Short name T106
Test name
Test status
Simulation time 149176590 ps
CPU time 2.59 seconds
Started Aug 02 04:41:40 PM PDT 24
Finished Aug 02 04:41:43 PM PDT 24
Peak memory 215648 kb
Host smart-43b50073-920a-425c-8eff-ffce45d7c247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614377571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.614377571
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1691691287
Short name T1120
Test name
Test status
Simulation time 558300082 ps
CPU time 14.36 seconds
Started Aug 02 04:41:39 PM PDT 24
Finished Aug 02 04:41:54 PM PDT 24
Peak memory 216676 kb
Host smart-c8cd7e26-9518-4fb4-80ab-e8365a363132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691691287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1691691287
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1861541675
Short name T157
Test name
Test status
Simulation time 508323105 ps
CPU time 3.63 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:54 PM PDT 24
Peak memory 217428 kb
Host smart-28192ad6-2a96-44fa-8770-04408b16ff28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861541675 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1861541675
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3294350771
Short name T160
Test name
Test status
Simulation time 45646838 ps
CPU time 1.43 seconds
Started Aug 02 04:41:49 PM PDT 24
Finished Aug 02 04:41:50 PM PDT 24
Peak memory 207352 kb
Host smart-aef742e8-5c68-4dcd-8a89-849dabf198e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294350771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3294350771
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1293505943
Short name T1100
Test name
Test status
Simulation time 242181046 ps
CPU time 0.76 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 204276 kb
Host smart-6878a63f-fc43-4224-b4cc-72368ba092d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293505943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1293505943
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.90150170
Short name T156
Test name
Test status
Simulation time 817618426 ps
CPU time 4.3 seconds
Started Aug 02 04:41:47 PM PDT 24
Finished Aug 02 04:41:52 PM PDT 24
Peak memory 215372 kb
Host smart-28188347-f04a-4e3c-956e-36045ea895df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90150170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sp
i_device_same_csr_outstanding.90150170
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3334457832
Short name T101
Test name
Test status
Simulation time 93294809 ps
CPU time 2.85 seconds
Started Aug 02 04:41:41 PM PDT 24
Finished Aug 02 04:41:44 PM PDT 24
Peak memory 215600 kb
Host smart-92c67942-a7d5-49a9-baaf-2e4999e5842b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334457832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3334457832
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1440978117
Short name T1146
Test name
Test status
Simulation time 294887549 ps
CPU time 18.31 seconds
Started Aug 02 04:41:47 PM PDT 24
Finished Aug 02 04:42:06 PM PDT 24
Peak memory 215576 kb
Host smart-d81d0d02-d061-4cf3-9a84-e96fc4ede56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440978117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1440978117
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4163567414
Short name T112
Test name
Test status
Simulation time 47583141 ps
CPU time 1.76 seconds
Started Aug 02 04:41:54 PM PDT 24
Finished Aug 02 04:41:56 PM PDT 24
Peak memory 216412 kb
Host smart-97e369d4-c2ca-4fd2-997b-27099e796b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163567414 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4163567414
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2590506492
Short name T1107
Test name
Test status
Simulation time 97555607 ps
CPU time 2.74 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 215296 kb
Host smart-b220853d-7d34-48ee-b47f-c7aaabc4b61a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590506492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2590506492
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2642123393
Short name T1051
Test name
Test status
Simulation time 11990528 ps
CPU time 0.73 seconds
Started Aug 02 04:41:52 PM PDT 24
Finished Aug 02 04:41:53 PM PDT 24
Peak memory 203920 kb
Host smart-af02045d-3ec5-46c4-ba61-c42d9baef270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642123393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2642123393
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2886904571
Short name T1071
Test name
Test status
Simulation time 158035030 ps
CPU time 2.8 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 215424 kb
Host smart-6fe466c4-d405-485b-85a4-f1e7069d5d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886904571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2886904571
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3287990974
Short name T1077
Test name
Test status
Simulation time 206286128 ps
CPU time 3.48 seconds
Started Aug 02 04:41:49 PM PDT 24
Finished Aug 02 04:41:53 PM PDT 24
Peak memory 215592 kb
Host smart-041367f9-2bf1-4d92-8e14-eb8d4a5a6895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287990974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3287990974
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.8264755
Short name T174
Test name
Test status
Simulation time 955137105 ps
CPU time 20.88 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 223516 kb
Host smart-0be02828-7377-48a1-bc10-444c5f4c4f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8264755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_t
l_intg_err.8264755
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.114384125
Short name T158
Test name
Test status
Simulation time 1073746824 ps
CPU time 21.84 seconds
Started Aug 02 04:41:05 PM PDT 24
Finished Aug 02 04:41:27 PM PDT 24
Peak memory 207192 kb
Host smart-1c94b444-f3fe-411f-8028-9cc642860323
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114384125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.114384125
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4285661134
Short name T126
Test name
Test status
Simulation time 8993601143 ps
CPU time 36.22 seconds
Started Aug 02 04:41:01 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 207216 kb
Host smart-f9533872-a36e-4914-8b94-fa3af5f24170
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285661134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4285661134
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.239630015
Short name T81
Test name
Test status
Simulation time 102040994 ps
CPU time 1.01 seconds
Started Aug 02 04:40:55 PM PDT 24
Finished Aug 02 04:40:56 PM PDT 24
Peak memory 206944 kb
Host smart-7af0bafe-5ed1-4854-b673-003fb3740626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239630015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.239630015
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4086192229
Short name T1072
Test name
Test status
Simulation time 121515305 ps
CPU time 1.84 seconds
Started Aug 02 04:41:08 PM PDT 24
Finished Aug 02 04:41:10 PM PDT 24
Peak memory 216448 kb
Host smart-eb3323d1-4125-4b27-a9a5-e52dba5d114b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086192229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4086192229
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2615614497
Short name T131
Test name
Test status
Simulation time 120014799 ps
CPU time 2.79 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:56 PM PDT 24
Peak memory 215524 kb
Host smart-876012fd-28bc-41ab-880f-4497cbfba70f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615614497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
615614497
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4251331388
Short name T1066
Test name
Test status
Simulation time 41360241 ps
CPU time 0.76 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:53 PM PDT 24
Peak memory 203880 kb
Host smart-45110420-a5f0-4df7-a501-0d6be88d683d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251331388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
251331388
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1366154435
Short name T1098
Test name
Test status
Simulation time 69002783 ps
CPU time 2.1 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 215420 kb
Host smart-9a09ca37-732b-4f03-a3e0-b28519de3a7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366154435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1366154435
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2448804600
Short name T1056
Test name
Test status
Simulation time 38784912 ps
CPU time 0.66 seconds
Started Aug 02 04:40:54 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 203748 kb
Host smart-762e9b5d-e86d-4c6c-8861-d0fd7fc7e3c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448804600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2448804600
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2658867994
Short name T1102
Test name
Test status
Simulation time 167971130 ps
CPU time 2.94 seconds
Started Aug 02 04:41:05 PM PDT 24
Finished Aug 02 04:41:08 PM PDT 24
Peak memory 215340 kb
Host smart-a2047906-6604-45dd-aa64-d4e915e9d688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658867994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2658867994
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.44033595
Short name T111
Test name
Test status
Simulation time 603700758 ps
CPU time 4.56 seconds
Started Aug 02 04:40:53 PM PDT 24
Finished Aug 02 04:40:57 PM PDT 24
Peak memory 215760 kb
Host smart-71d12278-17dc-45d1-85f6-912f00501591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44033595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.44033595
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2620075796
Short name T114
Test name
Test status
Simulation time 513378969 ps
CPU time 13.23 seconds
Started Aug 02 04:40:52 PM PDT 24
Finished Aug 02 04:41:05 PM PDT 24
Peak memory 215340 kb
Host smart-88a7ce2f-aa49-4ee0-92cf-ebc5853d078c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620075796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2620075796
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2454218070
Short name T1049
Test name
Test status
Simulation time 13172347 ps
CPU time 0.69 seconds
Started Aug 02 04:41:51 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 203868 kb
Host smart-57546a4b-fa61-4587-916c-af80eb621961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454218070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2454218070
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.366594578
Short name T1092
Test name
Test status
Simulation time 34124386 ps
CPU time 0.69 seconds
Started Aug 02 04:41:47 PM PDT 24
Finished Aug 02 04:41:47 PM PDT 24
Peak memory 204144 kb
Host smart-46021db1-c9fc-46c3-9cc7-f2733a216df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366594578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.366594578
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.56432964
Short name T1140
Test name
Test status
Simulation time 14696382 ps
CPU time 0.75 seconds
Started Aug 02 04:41:51 PM PDT 24
Finished Aug 02 04:41:52 PM PDT 24
Peak memory 203824 kb
Host smart-7abda9ae-5c96-436a-8fc3-2f58a9afcb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56432964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.56432964
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2174436547
Short name T1139
Test name
Test status
Simulation time 21887768 ps
CPU time 0.68 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 203804 kb
Host smart-af6d19da-df81-4f98-83fa-280c81a9d4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174436547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2174436547
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2705514555
Short name T1052
Test name
Test status
Simulation time 38443696 ps
CPU time 0.76 seconds
Started Aug 02 04:41:49 PM PDT 24
Finished Aug 02 04:41:50 PM PDT 24
Peak memory 203892 kb
Host smart-1caced42-aa67-48b8-a703-e7cfd4970f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705514555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2705514555
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.58482554
Short name T1070
Test name
Test status
Simulation time 50355439 ps
CPU time 0.75 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 203888 kb
Host smart-566a1043-7046-488e-93d1-fb6eb638a3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58482554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.58482554
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3030886381
Short name T1038
Test name
Test status
Simulation time 55660245 ps
CPU time 0.7 seconds
Started Aug 02 04:41:51 PM PDT 24
Finished Aug 02 04:41:52 PM PDT 24
Peak memory 203832 kb
Host smart-ebadd52c-cf63-4b0a-b667-8f280f1d43fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030886381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3030886381
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2185607857
Short name T1063
Test name
Test status
Simulation time 11820919 ps
CPU time 0.75 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 204220 kb
Host smart-896f807b-c6a0-47c8-9370-2577fb82d79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185607857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2185607857
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2807500249
Short name T1124
Test name
Test status
Simulation time 16060147 ps
CPU time 0.77 seconds
Started Aug 02 04:41:46 PM PDT 24
Finished Aug 02 04:41:47 PM PDT 24
Peak memory 203904 kb
Host smart-bbdbdf57-8515-42a5-8063-a44fedfdf1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807500249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2807500249
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2945068843
Short name T1105
Test name
Test status
Simulation time 28186598 ps
CPU time 0.69 seconds
Started Aug 02 04:41:47 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 203924 kb
Host smart-11a01609-3966-4122-914b-cee8e767d39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945068843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2945068843
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.323235167
Short name T1090
Test name
Test status
Simulation time 791185860 ps
CPU time 16.46 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:19 PM PDT 24
Peak memory 215336 kb
Host smart-2802e211-f4ba-4b32-99e6-2f95ca4770a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323235167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.323235167
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.16484944
Short name T135
Test name
Test status
Simulation time 4829092758 ps
CPU time 25.82 seconds
Started Aug 02 04:41:04 PM PDT 24
Finished Aug 02 04:41:30 PM PDT 24
Peak memory 207260 kb
Host smart-9e0ec834-4b75-4f63-b5e9-28f02e25cdc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16484944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
bit_bash.16484944
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.39510302
Short name T80
Test name
Test status
Simulation time 87271036 ps
CPU time 0.94 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:03 PM PDT 24
Peak memory 207136 kb
Host smart-a2186f88-7ba8-4700-875d-400328c18843
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39510302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.39510302
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1890558688
Short name T1068
Test name
Test status
Simulation time 503996916 ps
CPU time 3.83 seconds
Started Aug 02 04:41:04 PM PDT 24
Finished Aug 02 04:41:08 PM PDT 24
Peak memory 217164 kb
Host smart-cc4320c5-5687-44d9-9f19-cf4d6ec9d11c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890558688 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1890558688
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4007963127
Short name T132
Test name
Test status
Simulation time 94174087 ps
CPU time 2.39 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:04 PM PDT 24
Peak memory 207172 kb
Host smart-d9e63a69-406c-4062-8934-5cfc7f7afdc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007963127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
007963127
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.453383196
Short name T1136
Test name
Test status
Simulation time 32524331 ps
CPU time 0.72 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:03 PM PDT 24
Peak memory 203884 kb
Host smart-6b3aa7b1-245c-456b-a811-2f1ef944c620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453383196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.453383196
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1963523683
Short name T121
Test name
Test status
Simulation time 184393449 ps
CPU time 1.39 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:03 PM PDT 24
Peak memory 215408 kb
Host smart-4960e89d-b36d-4997-b11d-bcd317891b55
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963523683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1963523683
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2068912690
Short name T1143
Test name
Test status
Simulation time 39822842 ps
CPU time 0.67 seconds
Started Aug 02 04:41:01 PM PDT 24
Finished Aug 02 04:41:02 PM PDT 24
Peak memory 203824 kb
Host smart-2883fdb8-d471-4f79-a691-27d79398dc2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068912690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2068912690
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3192818834
Short name T1083
Test name
Test status
Simulation time 771064255 ps
CPU time 1.84 seconds
Started Aug 02 04:41:09 PM PDT 24
Finished Aug 02 04:41:11 PM PDT 24
Peak memory 207148 kb
Host smart-2b5eb662-73e7-491a-9008-bc23d6ddf73a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192818834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3192818834
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2229336614
Short name T105
Test name
Test status
Simulation time 275545374 ps
CPU time 4.78 seconds
Started Aug 02 04:41:04 PM PDT 24
Finished Aug 02 04:41:09 PM PDT 24
Peak memory 215888 kb
Host smart-b8f6b526-96de-4e50-b71c-b501e2d5fcde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229336614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
229336614
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4093182303
Short name T1047
Test name
Test status
Simulation time 106956074 ps
CPU time 6.27 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:08 PM PDT 24
Peak memory 215416 kb
Host smart-7db3b4b6-96b5-4774-9488-34d8c86a1549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093182303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4093182303
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1365387253
Short name T1061
Test name
Test status
Simulation time 45967588 ps
CPU time 0.76 seconds
Started Aug 02 04:41:54 PM PDT 24
Finished Aug 02 04:41:55 PM PDT 24
Peak memory 204144 kb
Host smart-399b4a4a-15a4-461f-92a9-a21de18abda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365387253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1365387253
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1599345712
Short name T1048
Test name
Test status
Simulation time 16470000 ps
CPU time 0.72 seconds
Started Aug 02 04:41:49 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 203804 kb
Host smart-5cd8db07-0455-447b-89d0-79ec78b154c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599345712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1599345712
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3081049386
Short name T1112
Test name
Test status
Simulation time 26427789 ps
CPU time 0.75 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 203940 kb
Host smart-0504b53b-f867-4e32-8f8d-8e7e59ef7e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081049386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3081049386
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2657510637
Short name T1135
Test name
Test status
Simulation time 51080931 ps
CPU time 0.74 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:50 PM PDT 24
Peak memory 203836 kb
Host smart-a035b737-d62e-4f19-bac2-4ccf9be9587a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657510637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2657510637
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1002639234
Short name T1103
Test name
Test status
Simulation time 12044329 ps
CPU time 0.69 seconds
Started Aug 02 04:41:50 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 203844 kb
Host smart-75706a61-f876-428e-aadb-221ffe72abf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002639234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1002639234
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4228823922
Short name T1096
Test name
Test status
Simulation time 15023581 ps
CPU time 0.73 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 204216 kb
Host smart-53a6e869-4258-46f3-9a2c-3b5a712ba53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228823922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4228823922
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2581143822
Short name T1137
Test name
Test status
Simulation time 52723106 ps
CPU time 0.7 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 203900 kb
Host smart-c95179c9-25b0-4fbd-beaf-c7d02ed1cb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581143822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2581143822
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.480655663
Short name T1057
Test name
Test status
Simulation time 26149133 ps
CPU time 0.69 seconds
Started Aug 02 04:41:48 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 203780 kb
Host smart-ac0f0d10-5bc2-415c-b468-b1a38aad018a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480655663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.480655663
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3351873037
Short name T1141
Test name
Test status
Simulation time 47873680 ps
CPU time 0.74 seconds
Started Aug 02 04:41:47 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 203900 kb
Host smart-a21ff81d-f586-42a9-915b-c934dea3858c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351873037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3351873037
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.912723485
Short name T1043
Test name
Test status
Simulation time 25020382 ps
CPU time 0.7 seconds
Started Aug 02 04:41:57 PM PDT 24
Finished Aug 02 04:41:58 PM PDT 24
Peak memory 203832 kb
Host smart-08ebe850-7e86-4c3e-a4a7-2da266bbeadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912723485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.912723485
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2602740675
Short name T1088
Test name
Test status
Simulation time 211481391 ps
CPU time 14.25 seconds
Started Aug 02 04:41:12 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 215324 kb
Host smart-b0187d25-2ffc-4719-821f-ade09616e145
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602740675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2602740675
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4293650886
Short name T130
Test name
Test status
Simulation time 548509965 ps
CPU time 31.07 seconds
Started Aug 02 04:41:12 PM PDT 24
Finished Aug 02 04:41:43 PM PDT 24
Peak memory 207320 kb
Host smart-c965e949-c295-4aff-add4-6a07ebfc551f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293650886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4293650886
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.95290376
Short name T79
Test name
Test status
Simulation time 38091203 ps
CPU time 1.21 seconds
Started Aug 02 04:41:04 PM PDT 24
Finished Aug 02 04:41:06 PM PDT 24
Peak memory 216496 kb
Host smart-93a73a30-756b-493d-85de-b9834fc5e181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95290376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.95290376
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2618379997
Short name T1117
Test name
Test status
Simulation time 618677555 ps
CPU time 3.7 seconds
Started Aug 02 04:41:13 PM PDT 24
Finished Aug 02 04:41:17 PM PDT 24
Peak memory 217136 kb
Host smart-9a1668b4-c00a-47f6-8637-1be374e3ee20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618379997 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2618379997
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.461004438
Short name T1086
Test name
Test status
Simulation time 143573657 ps
CPU time 1.31 seconds
Started Aug 02 04:41:10 PM PDT 24
Finished Aug 02 04:41:11 PM PDT 24
Peak memory 207140 kb
Host smart-59616adb-072f-4307-8231-4bd0557cb27d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461004438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.461004438
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3078158711
Short name T1099
Test name
Test status
Simulation time 14545384 ps
CPU time 0.76 seconds
Started Aug 02 04:41:04 PM PDT 24
Finished Aug 02 04:41:05 PM PDT 24
Peak memory 203884 kb
Host smart-cf24eca5-dcc0-4d49-b6a8-0640958f9b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078158711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
078158711
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.687804528
Short name T120
Test name
Test status
Simulation time 17958004 ps
CPU time 1.29 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:03 PM PDT 24
Peak memory 215500 kb
Host smart-8f52f11a-11e6-4113-9653-688c645f5fb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687804528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.687804528
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4063889123
Short name T1036
Test name
Test status
Simulation time 83405701 ps
CPU time 0.66 seconds
Started Aug 02 04:41:01 PM PDT 24
Finished Aug 02 04:41:02 PM PDT 24
Peak memory 203796 kb
Host smart-cb8d0f52-dd65-4e8b-819a-ed1eaac8934c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063889123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4063889123
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2441640566
Short name T1081
Test name
Test status
Simulation time 93874158 ps
CPU time 1.69 seconds
Started Aug 02 04:41:11 PM PDT 24
Finished Aug 02 04:41:13 PM PDT 24
Peak memory 215304 kb
Host smart-a7e9fbe7-e321-411a-aa8e-bd8f594601fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441640566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2441640566
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3404349893
Short name T1113
Test name
Test status
Simulation time 111483116 ps
CPU time 1.8 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:04 PM PDT 24
Peak memory 215556 kb
Host smart-5f3a9748-5887-416d-8ea3-0aadcb90bd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404349893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
404349893
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1756913922
Short name T177
Test name
Test status
Simulation time 409578131 ps
CPU time 12.64 seconds
Started Aug 02 04:41:02 PM PDT 24
Finished Aug 02 04:41:14 PM PDT 24
Peak memory 215336 kb
Host smart-80c84856-4694-48a0-85b6-9a52c0d29636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756913922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1756913922
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4208630296
Short name T1114
Test name
Test status
Simulation time 61219096 ps
CPU time 0.75 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 204228 kb
Host smart-df25621c-7903-4791-9d56-7f7084659f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208630296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4208630296
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2383038427
Short name T1039
Test name
Test status
Simulation time 46462875 ps
CPU time 0.74 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 203900 kb
Host smart-b30992c2-1c9f-4a2f-99f1-ccb5bf317f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383038427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2383038427
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2352036082
Short name T1042
Test name
Test status
Simulation time 34817192 ps
CPU time 0.73 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 203928 kb
Host smart-194a3ff2-4a4c-4c83-bc57-1fc850119ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352036082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2352036082
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2959224641
Short name T1050
Test name
Test status
Simulation time 16937985 ps
CPU time 0.78 seconds
Started Aug 02 04:41:59 PM PDT 24
Finished Aug 02 04:42:00 PM PDT 24
Peak memory 203852 kb
Host smart-3a63ef9e-4cd3-404a-8d05-40addc357d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959224641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2959224641
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3461186709
Short name T1119
Test name
Test status
Simulation time 44259479 ps
CPU time 0.75 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 203864 kb
Host smart-4e7d1327-9b8b-4ce8-acd1-df0b904e593c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461186709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3461186709
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.842888561
Short name T1059
Test name
Test status
Simulation time 13553757 ps
CPU time 0.76 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 204212 kb
Host smart-0339f68a-a6d6-4793-8a56-9df96a4cf32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842888561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.842888561
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3471106123
Short name T1131
Test name
Test status
Simulation time 75401875 ps
CPU time 0.74 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 203840 kb
Host smart-aa1bcc12-8d54-4552-b335-76d98bd779ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471106123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3471106123
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4009112509
Short name T1148
Test name
Test status
Simulation time 111964671 ps
CPU time 0.72 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 203904 kb
Host smart-716cc5b7-7d5d-4648-9244-3e1804dcd27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009112509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4009112509
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2559691213
Short name T1046
Test name
Test status
Simulation time 53518028 ps
CPU time 0.68 seconds
Started Aug 02 04:41:57 PM PDT 24
Finished Aug 02 04:41:58 PM PDT 24
Peak memory 204228 kb
Host smart-fc11c719-5c02-4e97-b458-d92d054e04e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559691213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2559691213
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1470249120
Short name T1087
Test name
Test status
Simulation time 17054562 ps
CPU time 0.84 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:02 PM PDT 24
Peak memory 203808 kb
Host smart-051ef662-5463-435e-88cb-096779266c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470249120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1470249120
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.924618917
Short name T1134
Test name
Test status
Simulation time 29727533 ps
CPU time 1.98 seconds
Started Aug 02 04:41:12 PM PDT 24
Finished Aug 02 04:41:14 PM PDT 24
Peak memory 215508 kb
Host smart-c948b6e4-d0e1-472f-a117-255733cac87b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924618917 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.924618917
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1584818126
Short name T128
Test name
Test status
Simulation time 38182662 ps
CPU time 2.26 seconds
Started Aug 02 04:41:11 PM PDT 24
Finished Aug 02 04:41:14 PM PDT 24
Peak memory 215300 kb
Host smart-76fc0976-4c9c-4c2c-be1d-36a0da4e67c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584818126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
584818126
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2383206489
Short name T1147
Test name
Test status
Simulation time 18379435 ps
CPU time 0.73 seconds
Started Aug 02 04:41:11 PM PDT 24
Finished Aug 02 04:41:12 PM PDT 24
Peak memory 203852 kb
Host smart-8f3df477-d94c-45f7-938b-c227b79b6172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383206489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
383206489
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1823349986
Short name T1133
Test name
Test status
Simulation time 161817260 ps
CPU time 1.84 seconds
Started Aug 02 04:41:13 PM PDT 24
Finished Aug 02 04:41:15 PM PDT 24
Peak memory 215460 kb
Host smart-b329f2f4-9f96-4171-aa40-76a5e1417f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823349986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1823349986
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.981689912
Short name T1094
Test name
Test status
Simulation time 622369905 ps
CPU time 4.07 seconds
Started Aug 02 04:41:10 PM PDT 24
Finished Aug 02 04:41:14 PM PDT 24
Peak memory 215524 kb
Host smart-0376eff0-8f5f-4f95-9198-639527d75db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981689912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.981689912
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3323709835
Short name T95
Test name
Test status
Simulation time 3741735399 ps
CPU time 21.38 seconds
Started Aug 02 04:41:11 PM PDT 24
Finished Aug 02 04:41:32 PM PDT 24
Peak memory 215556 kb
Host smart-932e37a4-03c6-44e9-88d3-146775feb476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323709835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3323709835
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2083080424
Short name T115
Test name
Test status
Simulation time 240556654 ps
CPU time 1.85 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 216496 kb
Host smart-605add70-34e6-41cf-abeb-3c257642a6b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083080424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2083080424
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4041433537
Short name T125
Test name
Test status
Simulation time 25957222 ps
CPU time 1.19 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 207248 kb
Host smart-0317829e-04b9-404c-abac-c03d85de0858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041433537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
041433537
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.856995972
Short name T1067
Test name
Test status
Simulation time 23087315 ps
CPU time 0.78 seconds
Started Aug 02 04:41:10 PM PDT 24
Finished Aug 02 04:41:11 PM PDT 24
Peak memory 203540 kb
Host smart-b61a7d78-6903-4bce-9648-0316d57d3a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856995972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.856995972
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3079584205
Short name T1126
Test name
Test status
Simulation time 131696262 ps
CPU time 2.94 seconds
Started Aug 02 04:41:23 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 215396 kb
Host smart-7f8ef44c-8524-4131-807e-83f6963e1cb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079584205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3079584205
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1673056364
Short name T109
Test name
Test status
Simulation time 75296693 ps
CPU time 2.25 seconds
Started Aug 02 04:41:10 PM PDT 24
Finished Aug 02 04:41:12 PM PDT 24
Peak memory 215700 kb
Host smart-e2a76dc4-dc6c-4a3a-8dd5-d62ae42dcfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673056364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
673056364
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2208033401
Short name T1138
Test name
Test status
Simulation time 47140264 ps
CPU time 1.63 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 215492 kb
Host smart-8128a031-6fa0-4cbf-993a-36b0749644dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208033401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2208033401
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.426745656
Short name T1106
Test name
Test status
Simulation time 34337049 ps
CPU time 2.31 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 215364 kb
Host smart-dbabbe63-cce6-4716-97cb-93aadb945b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426745656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.426745656
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3152663845
Short name T1062
Test name
Test status
Simulation time 17749631 ps
CPU time 0.74 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 203836 kb
Host smart-dc532093-8f57-4d5d-b527-4ea2f031d90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152663845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
152663845
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2863231784
Short name T1084
Test name
Test status
Simulation time 81034124 ps
CPU time 2.64 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:24 PM PDT 24
Peak memory 215488 kb
Host smart-c10ae512-6a8e-47a3-8343-adfd7bf89a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863231784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2863231784
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2989504340
Short name T1110
Test name
Test status
Simulation time 33138258 ps
CPU time 1.89 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 215648 kb
Host smart-f2d5d82c-ad63-47fe-93b7-e99b6e6b53a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989504340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
989504340
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3148434341
Short name T176
Test name
Test status
Simulation time 204687331 ps
CPU time 12.81 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:34 PM PDT 24
Peak memory 215432 kb
Host smart-1a62f99f-c869-44bd-b081-1b5cccd51135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148434341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3148434341
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2929958705
Short name T113
Test name
Test status
Simulation time 144736280 ps
CPU time 2.65 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 217584 kb
Host smart-6c7ab0c2-2f36-45f7-9307-c583583f714f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929958705 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2929958705
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.849859833
Short name T1125
Test name
Test status
Simulation time 113753754 ps
CPU time 2.62 seconds
Started Aug 02 04:41:23 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 215400 kb
Host smart-b7b3ab9c-33d1-4e63-9b78-2984cd76a517
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849859833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.849859833
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2058549649
Short name T1118
Test name
Test status
Simulation time 17423641 ps
CPU time 0.76 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:21 PM PDT 24
Peak memory 204252 kb
Host smart-556d7967-050d-4605-8d6a-25349daea64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058549649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
058549649
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3964659087
Short name T1129
Test name
Test status
Simulation time 347271577 ps
CPU time 3.85 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:24 PM PDT 24
Peak memory 215880 kb
Host smart-3f68a7c9-7444-48bf-9ff9-a3e21e053b7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964659087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3964659087
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2238045325
Short name T107
Test name
Test status
Simulation time 169253913 ps
CPU time 4.28 seconds
Started Aug 02 04:41:19 PM PDT 24
Finished Aug 02 04:41:24 PM PDT 24
Peak memory 215624 kb
Host smart-20a658fe-bab7-4b74-b429-821a6dc4817d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238045325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
238045325
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1850588357
Short name T181
Test name
Test status
Simulation time 1297392754 ps
CPU time 7.38 seconds
Started Aug 02 04:41:19 PM PDT 24
Finished Aug 02 04:41:27 PM PDT 24
Peak memory 215468 kb
Host smart-90a7307c-d761-4d40-8604-77ceee4bfb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850588357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1850588357
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2037991211
Short name T97
Test name
Test status
Simulation time 87544446 ps
CPU time 1.63 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:22 PM PDT 24
Peak memory 215472 kb
Host smart-bd87104b-e832-458d-add4-30f2bf26f417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037991211 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2037991211
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.146977760
Short name T1150
Test name
Test status
Simulation time 95227117 ps
CPU time 2.64 seconds
Started Aug 02 04:41:20 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 207344 kb
Host smart-dcf93ad0-f02f-4a91-bba9-71ed72eb1989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146977760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.146977760
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2220404803
Short name T1074
Test name
Test status
Simulation time 27045780 ps
CPU time 0.75 seconds
Started Aug 02 04:41:22 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 203892 kb
Host smart-41fd6ebd-e92f-431e-a11c-79851ff29362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220404803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
220404803
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.979173883
Short name T1115
Test name
Test status
Simulation time 44251753 ps
CPU time 2.53 seconds
Started Aug 02 04:41:23 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 215340 kb
Host smart-a871995d-794b-4096-8148-7ca040466684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979173883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.979173883
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.18559737
Short name T103
Test name
Test status
Simulation time 90754001 ps
CPU time 2.36 seconds
Started Aug 02 04:41:23 PM PDT 24
Finished Aug 02 04:41:25 PM PDT 24
Peak memory 215612 kb
Host smart-0783aff2-3727-4f8f-9f7a-f437ed8aa886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.18559737
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.732781001
Short name T117
Test name
Test status
Simulation time 738615688 ps
CPU time 12.48 seconds
Started Aug 02 04:41:21 PM PDT 24
Finished Aug 02 04:41:33 PM PDT 24
Peak memory 215776 kb
Host smart-67db3e5e-bc7b-455f-b937-61651c82b9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732781001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.732781001
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.656053735
Short name T482
Test name
Test status
Simulation time 37577219 ps
CPU time 0.7 seconds
Started Aug 02 04:42:45 PM PDT 24
Finished Aug 02 04:42:46 PM PDT 24
Peak memory 205724 kb
Host smart-fde270e4-cb25-4fa0-b760-37d5433ebd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656053735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.656053735
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.696401196
Short name T628
Test name
Test status
Simulation time 1058311910 ps
CPU time 5.52 seconds
Started Aug 02 04:42:40 PM PDT 24
Finished Aug 02 04:42:46 PM PDT 24
Peak memory 224992 kb
Host smart-b93805b3-1067-4eef-9100-6d120f9dd7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696401196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.696401196
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.954924122
Short name T841
Test name
Test status
Simulation time 31740434 ps
CPU time 0.8 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:49 PM PDT 24
Peak memory 206892 kb
Host smart-660ef9c5-a9c2-4358-b94b-731d7ea45782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954924122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.954924122
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4059930803
Short name T360
Test name
Test status
Simulation time 32445121888 ps
CPU time 134.94 seconds
Started Aug 02 04:42:52 PM PDT 24
Finished Aug 02 04:45:07 PM PDT 24
Peak memory 251824 kb
Host smart-55f05953-9652-4527-ad89-f98a4730df08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059930803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4059930803
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.861298907
Short name T1035
Test name
Test status
Simulation time 126340477071 ps
CPU time 298.82 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 258196 kb
Host smart-51467e48-299d-4c0a-8371-8c213a03310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861298907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.861298907
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.96375321
Short name T46
Test name
Test status
Simulation time 5349008925 ps
CPU time 18.86 seconds
Started Aug 02 04:43:58 PM PDT 24
Finished Aug 02 04:44:17 PM PDT 24
Peak memory 224948 kb
Host smart-a089d390-1250-45c4-b84a-7760da9dcd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96375321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.96375321
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1694446635
Short name T294
Test name
Test status
Simulation time 2679763341 ps
CPU time 16.03 seconds
Started Aug 02 04:42:47 PM PDT 24
Finished Aug 02 04:43:03 PM PDT 24
Peak memory 233540 kb
Host smart-24ed5bbe-962b-420c-a726-33135a8dc6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694446635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1694446635
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.401018682
Short name T253
Test name
Test status
Simulation time 243893516292 ps
CPU time 143.05 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 258048 kb
Host smart-d3061784-0cf9-4532-a731-9a50832b33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401018682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
401018682
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1947792278
Short name T434
Test name
Test status
Simulation time 57503167 ps
CPU time 2.49 seconds
Started Aug 02 04:42:39 PM PDT 24
Finished Aug 02 04:42:42 PM PDT 24
Peak memory 232896 kb
Host smart-56e7aa76-3fc5-469e-9500-245d4c5caf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947792278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1947792278
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1712225568
Short name T740
Test name
Test status
Simulation time 8839726340 ps
CPU time 29.21 seconds
Started Aug 02 04:42:47 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 233320 kb
Host smart-e5ceb20e-6e64-413e-8166-a55b00d543bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712225568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1712225568
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.345801001
Short name T782
Test name
Test status
Simulation time 25115092 ps
CPU time 1.11 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:39 PM PDT 24
Peak memory 217092 kb
Host smart-c20b9bd3-eab1-4eb9-badb-43689c5eea80
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345801001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.345801001
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2899823423
Short name T55
Test name
Test status
Simulation time 816103728 ps
CPU time 4.51 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:42 PM PDT 24
Peak memory 233368 kb
Host smart-b505c694-b824-45c3-ba22-55c75b78635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899823423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2899823423
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3001851521
Short name T696
Test name
Test status
Simulation time 780183172 ps
CPU time 9.15 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 233244 kb
Host smart-a8d41ef0-900b-44b8-a270-7507adae7600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001851521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3001851521
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3276530047
Short name T328
Test name
Test status
Simulation time 1596906219 ps
CPU time 17.67 seconds
Started Aug 02 04:42:50 PM PDT 24
Finished Aug 02 04:43:08 PM PDT 24
Peak memory 219580 kb
Host smart-16f9b196-c1a3-432c-8b3d-3b172c50692f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3276530047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3276530047
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3506181177
Short name T166
Test name
Test status
Simulation time 111130957279 ps
CPU time 505.97 seconds
Started Aug 02 04:42:44 PM PDT 24
Finished Aug 02 04:51:11 PM PDT 24
Peak memory 265560 kb
Host smart-66311756-c162-4f4f-8d89-2a84ad08f781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506181177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3506181177
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3148133532
Short name T1029
Test name
Test status
Simulation time 2919316180 ps
CPU time 26.45 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:31 PM PDT 24
Peak memory 216968 kb
Host smart-548517ef-385f-44d2-a265-7e6833b49a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148133532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3148133532
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.613013808
Short name T761
Test name
Test status
Simulation time 16176497090 ps
CPU time 22.46 seconds
Started Aug 02 04:42:35 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 216928 kb
Host smart-ce7dec24-39bc-4783-ba6f-07d77df6334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613013808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.613013808
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3310171328
Short name T1027
Test name
Test status
Simulation time 64751440 ps
CPU time 1.53 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:39 PM PDT 24
Peak memory 216740 kb
Host smart-eb44fef1-5d20-457a-9a60-e33acc990fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310171328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3310171328
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3818044387
Short name T725
Test name
Test status
Simulation time 62420892 ps
CPU time 0.75 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 206396 kb
Host smart-7eb8b15f-5da1-4f18-b5a4-ceba5e9001fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818044387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3818044387
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4033867707
Short name T842
Test name
Test status
Simulation time 1163960006 ps
CPU time 7.37 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:12 PM PDT 24
Peak memory 225128 kb
Host smart-029653ca-42fb-4705-a74c-ddee8fb4154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033867707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4033867707
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1506541152
Short name T958
Test name
Test status
Simulation time 52032169 ps
CPU time 0.77 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 206000 kb
Host smart-bb8d424b-b671-457b-a269-b25225bdd12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506541152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
506541152
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.592215729
Short name T553
Test name
Test status
Simulation time 1078933182 ps
CPU time 4.76 seconds
Started Aug 02 04:42:49 PM PDT 24
Finished Aug 02 04:42:54 PM PDT 24
Peak memory 225064 kb
Host smart-dae92199-1469-4a8f-81e3-850533b30f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592215729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.592215729
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2031382502
Short name T955
Test name
Test status
Simulation time 18753575 ps
CPU time 0.77 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:49 PM PDT 24
Peak memory 206996 kb
Host smart-0fde8daa-12f5-4e02-9024-749f8add6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031382502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2031382502
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4174346904
Short name T172
Test name
Test status
Simulation time 4609895480 ps
CPU time 57.31 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:43:45 PM PDT 24
Peak memory 250808 kb
Host smart-f2a4aa7a-7198-4041-85d3-36fef6ae0fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174346904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4174346904
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.162543015
Short name T954
Test name
Test status
Simulation time 104559756691 ps
CPU time 242.92 seconds
Started Aug 02 04:43:58 PM PDT 24
Finished Aug 02 04:48:01 PM PDT 24
Peak memory 257112 kb
Host smart-9e9f2fbd-303d-4664-82cd-de79c431717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162543015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.162543015
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.262566176
Short name T226
Test name
Test status
Simulation time 3208184725 ps
CPU time 74.94 seconds
Started Aug 02 04:42:53 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 257804 kb
Host smart-834e0e1f-d7ff-4d60-b6e4-907f6fd23021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262566176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
262566176
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2135526115
Short name T277
Test name
Test status
Simulation time 80024620335 ps
CPU time 290.23 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 261688 kb
Host smart-e2988c9f-7f02-4832-8221-94f3e7071c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135526115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2135526115
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1798637209
Short name T6
Test name
Test status
Simulation time 78707452 ps
CPU time 2.68 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:51 PM PDT 24
Peak memory 233380 kb
Host smart-4f9e43d4-ec69-4dd7-bae3-55aa84518863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798637209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1798637209
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2940676670
Short name T875
Test name
Test status
Simulation time 32363020 ps
CPU time 2.29 seconds
Started Aug 02 04:42:44 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 232960 kb
Host smart-8dcf4405-9112-41a6-a9df-2259bb09ebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940676670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2940676670
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3721429326
Short name T995
Test name
Test status
Simulation time 88744411 ps
CPU time 1.03 seconds
Started Aug 02 04:42:49 PM PDT 24
Finished Aug 02 04:42:50 PM PDT 24
Peak memory 218336 kb
Host smart-a85847b8-8b17-431a-8d12-c7e5675a944c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721429326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3721429326
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1419753878
Short name T251
Test name
Test status
Simulation time 1446400766 ps
CPU time 3.64 seconds
Started Aug 02 04:42:44 PM PDT 24
Finished Aug 02 04:42:48 PM PDT 24
Peak memory 233536 kb
Host smart-13078328-71bc-4b8b-a991-5a8962e90e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419753878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1419753878
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3973412031
Short name T455
Test name
Test status
Simulation time 30213922148 ps
CPU time 22.58 seconds
Started Aug 02 04:42:53 PM PDT 24
Finished Aug 02 04:43:15 PM PDT 24
Peak memory 237292 kb
Host smart-dc144fa2-fcb1-4064-9e61-23f033580117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973412031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3973412031
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1425885538
Short name T551
Test name
Test status
Simulation time 770268328 ps
CPU time 4.71 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:52 PM PDT 24
Peak memory 222848 kb
Host smart-0e8818d7-739d-443b-ac5a-16309a18014e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425885538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1425885538
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3019716735
Short name T68
Test name
Test status
Simulation time 36182473 ps
CPU time 0.92 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:49 PM PDT 24
Peak memory 235424 kb
Host smart-cc26eb28-b446-45f2-b59c-f881b4c462d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019716735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3019716735
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2775138006
Short name T685
Test name
Test status
Simulation time 2147347773 ps
CPU time 35.44 seconds
Started Aug 02 04:42:50 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 241420 kb
Host smart-43068772-d58d-435c-b46a-969b7c32691d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775138006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2775138006
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.903720534
Short name T706
Test name
Test status
Simulation time 2938614782 ps
CPU time 20.37 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 217096 kb
Host smart-b990d082-8472-4e9d-86ec-06b9f4caa17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903720534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.903720534
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.313533075
Short name T632
Test name
Test status
Simulation time 3693601899 ps
CPU time 3.51 seconds
Started Aug 02 04:42:44 PM PDT 24
Finished Aug 02 04:42:48 PM PDT 24
Peak memory 216948 kb
Host smart-aaf9e5c8-af3f-493a-aea5-adab780ef4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313533075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.313533075
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3323140242
Short name T772
Test name
Test status
Simulation time 402543293 ps
CPU time 1.24 seconds
Started Aug 02 04:42:43 PM PDT 24
Finished Aug 02 04:42:44 PM PDT 24
Peak memory 216588 kb
Host smart-d7d878f9-5126-4d60-ab94-773e6bd7e8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323140242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3323140242
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1548497766
Short name T846
Test name
Test status
Simulation time 142007918 ps
CPU time 0.77 seconds
Started Aug 02 04:43:55 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 206112 kb
Host smart-02b3c841-c9af-4bb5-982a-7041e5c5c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548497766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1548497766
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2382260538
Short name T212
Test name
Test status
Simulation time 1988758274 ps
CPU time 14.11 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 249684 kb
Host smart-2ffb7191-d60e-466b-a361-78d2ce88abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382260538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2382260538
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1913966809
Short name T978
Test name
Test status
Simulation time 14601629 ps
CPU time 0.73 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 204812 kb
Host smart-07d56950-a953-4a5c-a5f1-5535151ffcad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913966809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1913966809
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4204233457
Short name T584
Test name
Test status
Simulation time 225266764 ps
CPU time 3.04 seconds
Started Aug 02 04:43:18 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 233340 kb
Host smart-0b6dcc04-9a0d-4ed0-a69f-6d974573ff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204233457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4204233457
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.889774738
Short name T951
Test name
Test status
Simulation time 45558134 ps
CPU time 0.76 seconds
Started Aug 02 04:43:18 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 206888 kb
Host smart-df10226f-5105-47e3-bcd2-c94b86794204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889774738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.889774738
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.122717872
Short name T633
Test name
Test status
Simulation time 37943955 ps
CPU time 0.81 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 216560 kb
Host smart-871265cc-17e2-45ea-b626-82bc149b3d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122717872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.122717872
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1572853748
Short name T877
Test name
Test status
Simulation time 12441634811 ps
CPU time 73.73 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:44:27 PM PDT 24
Peak memory 256592 kb
Host smart-2865e034-1daf-47ba-a577-7f50a485e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572853748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1572853748
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.90900743
Short name T274
Test name
Test status
Simulation time 126542124093 ps
CPU time 561.81 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:52:46 PM PDT 24
Peak memory 273916 kb
Host smart-73cc590b-a724-4c75-b6a0-8b9fadaf00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90900743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.90900743
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.878430187
Short name T687
Test name
Test status
Simulation time 2601037865 ps
CPU time 4.38 seconds
Started Aug 02 04:43:15 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 233468 kb
Host smart-58588305-3e55-4c0a-b5d1-fc6c54d5922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878430187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.878430187
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2765397474
Short name T267
Test name
Test status
Simulation time 95371316099 ps
CPU time 182.59 seconds
Started Aug 02 04:44:20 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 257564 kb
Host smart-2a7daa87-f473-4479-820d-4ed004069855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765397474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2765397474
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4132031197
Short name T577
Test name
Test status
Simulation time 695361440 ps
CPU time 6.09 seconds
Started Aug 02 04:43:15 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 233296 kb
Host smart-ccd88eeb-12f8-429c-b877-e25975862a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132031197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4132031197
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.896706679
Short name T603
Test name
Test status
Simulation time 539005792 ps
CPU time 2.28 seconds
Started Aug 02 04:43:18 PM PDT 24
Finished Aug 02 04:43:20 PM PDT 24
Peak memory 224716 kb
Host smart-ef721bd7-bb14-4219-8c3c-d35476bbc84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896706679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.896706679
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3217879993
Short name T928
Test name
Test status
Simulation time 35100523 ps
CPU time 1.07 seconds
Started Aug 02 04:43:20 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 217116 kb
Host smart-f6778c02-4190-45ea-947e-abf9a52aa644
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217879993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3217879993
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.980622993
Short name T790
Test name
Test status
Simulation time 30316162 ps
CPU time 1.93 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 224668 kb
Host smart-ec5040e0-5843-481e-9a2e-8e6d4d1e4b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980622993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.980622993
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2080369084
Short name T359
Test name
Test status
Simulation time 213807472 ps
CPU time 3.2 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225168 kb
Host smart-e9b21413-2c98-4077-99d3-f131ffb64f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080369084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2080369084
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4051984502
Short name T356
Test name
Test status
Simulation time 1325654303 ps
CPU time 11.2 seconds
Started Aug 02 04:43:16 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 219748 kb
Host smart-a7f5c7db-4c6a-4c4d-9c5b-016dcb350b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051984502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4051984502
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.152659134
Short name T302
Test name
Test status
Simulation time 8209473363 ps
CPU time 24.74 seconds
Started Aug 02 04:43:19 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 216916 kb
Host smart-500162c0-f93d-4067-b7c9-d5816f26c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152659134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.152659134
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3258645283
Short name T957
Test name
Test status
Simulation time 1675712655 ps
CPU time 8.38 seconds
Started Aug 02 04:43:17 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 216812 kb
Host smart-1f0f904c-2de0-44db-acf4-defd3b73a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258645283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3258645283
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3672693336
Short name T714
Test name
Test status
Simulation time 166497150 ps
CPU time 1.14 seconds
Started Aug 02 04:43:20 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 208456 kb
Host smart-d90ef2e9-e37a-4372-acfa-5416b3894cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672693336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3672693336
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3269614149
Short name T71
Test name
Test status
Simulation time 50755886 ps
CPU time 0.7 seconds
Started Aug 02 04:43:18 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 206392 kb
Host smart-0001eb91-867a-41eb-8dd6-be888e6f4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269614149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3269614149
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1841628656
Short name T728
Test name
Test status
Simulation time 374812593 ps
CPU time 2.6 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225124 kb
Host smart-e14c51dd-9b3a-4749-aaac-898ed877c19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841628656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1841628656
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.219232395
Short name T1007
Test name
Test status
Simulation time 23615049 ps
CPU time 0.7 seconds
Started Aug 02 04:43:21 PM PDT 24
Finished Aug 02 04:43:22 PM PDT 24
Peak memory 206092 kb
Host smart-2c26e3d9-bff0-45d4-877e-fc166813b479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219232395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.219232395
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1034390050
Short name T638
Test name
Test status
Simulation time 36536792 ps
CPU time 2.3 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:43:17 PM PDT 24
Peak memory 225212 kb
Host smart-65782611-bdec-4b1b-a2ce-ca305fe2b771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034390050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1034390050
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2797969920
Short name T333
Test name
Test status
Simulation time 21762043 ps
CPU time 0.78 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 207004 kb
Host smart-d60851db-3205-4ab8-a072-39b34c0ffd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797969920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2797969920
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3958808543
Short name T485
Test name
Test status
Simulation time 926906137 ps
CPU time 20.6 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:47 PM PDT 24
Peak memory 241576 kb
Host smart-917384b3-f6c2-4b6b-ab86-873628fab737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958808543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3958808543
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3443432535
Short name T369
Test name
Test status
Simulation time 2884284213 ps
CPU time 57.94 seconds
Started Aug 02 04:43:19 PM PDT 24
Finished Aug 02 04:44:17 PM PDT 24
Peak memory 250836 kb
Host smart-4389dd52-17b1-430b-9293-d101924b0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443432535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3443432535
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1762171617
Short name T270
Test name
Test status
Simulation time 15848795991 ps
CPU time 197.93 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 253040 kb
Host smart-c3773aac-e1d8-4356-8bdf-5ee9b9675932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762171617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1762171617
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3978578244
Short name T486
Test name
Test status
Simulation time 161876053 ps
CPU time 3.86 seconds
Started Aug 02 04:43:17 PM PDT 24
Finished Aug 02 04:43:20 PM PDT 24
Peak memory 225092 kb
Host smart-466c172b-07e5-403f-9261-2dd13073aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978578244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3978578244
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2297076587
Short name T619
Test name
Test status
Simulation time 5480347296 ps
CPU time 38.04 seconds
Started Aug 02 04:43:16 PM PDT 24
Finished Aug 02 04:43:55 PM PDT 24
Peak memory 240612 kb
Host smart-09ca5632-1e84-4acf-9827-e8dda377a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297076587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2297076587
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1408808752
Short name T1032
Test name
Test status
Simulation time 642496000 ps
CPU time 5.67 seconds
Started Aug 02 04:43:20 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 225160 kb
Host smart-2ee770af-8a81-4623-9f82-cba5eef1dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408808752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1408808752
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1949002984
Short name T743
Test name
Test status
Simulation time 423703685 ps
CPU time 1.06 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 217196 kb
Host smart-cef84fa0-3338-4380-a0af-3bf02d281212
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949002984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1949002984
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1030127684
Short name T528
Test name
Test status
Simulation time 549195007 ps
CPU time 3.1 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225084 kb
Host smart-349a3e9b-c441-4e35-80c0-be4735ed4c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030127684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1030127684
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2701460241
Short name T980
Test name
Test status
Simulation time 674447655 ps
CPU time 2.18 seconds
Started Aug 02 04:43:15 PM PDT 24
Finished Aug 02 04:43:17 PM PDT 24
Peak memory 224400 kb
Host smart-838a8e58-8327-4c08-9294-5c39ac60f2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701460241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2701460241
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3730232728
Short name T368
Test name
Test status
Simulation time 404197896 ps
CPU time 4.82 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 219376 kb
Host smart-5212e80a-8f6c-4883-ae43-10197ef31294
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3730232728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3730232728
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3403184213
Short name T817
Test name
Test status
Simulation time 229125587 ps
CPU time 1.07 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 208056 kb
Host smart-fe308795-e151-4e16-9808-d6698778e112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403184213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3403184213
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4171758477
Short name T829
Test name
Test status
Simulation time 2718999149 ps
CPU time 8.06 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 216860 kb
Host smart-10478352-188c-47d7-baea-b6cdb8b2764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171758477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4171758477
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.78922718
Short name T647
Test name
Test status
Simulation time 150814523 ps
CPU time 1.3 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 216716 kb
Host smart-ca3a62a4-260a-4cd9-b4af-405cd2faf4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78922718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.78922718
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2035883164
Short name T986
Test name
Test status
Simulation time 111634272 ps
CPU time 0.94 seconds
Started Aug 02 04:43:17 PM PDT 24
Finished Aug 02 04:43:18 PM PDT 24
Peak memory 206488 kb
Host smart-0df183f5-6bd5-494c-a026-ab273ad5740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035883164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2035883164
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2283824031
Short name T915
Test name
Test status
Simulation time 42840027799 ps
CPU time 27.5 seconds
Started Aug 02 04:43:20 PM PDT 24
Finished Aug 02 04:43:47 PM PDT 24
Peak memory 233396 kb
Host smart-16191a88-1c8f-4b27-8c9f-98cc835ecf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283824031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2283824031
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2687655435
Short name T999
Test name
Test status
Simulation time 13657433 ps
CPU time 0.76 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 205204 kb
Host smart-123e79ef-801c-4429-94fb-b0343c2e7d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687655435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2687655435
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.376262383
Short name T684
Test name
Test status
Simulation time 385147185 ps
CPU time 4.77 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:30 PM PDT 24
Peak memory 233224 kb
Host smart-e672eca9-cad3-4699-8e3c-c624be35e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376262383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.376262383
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4109867600
Short name T852
Test name
Test status
Simulation time 167049875 ps
CPU time 0.76 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:43:24 PM PDT 24
Peak memory 205828 kb
Host smart-2fa944f8-6716-4363-8e73-30f8437938ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109867600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4109867600
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3717875808
Short name T796
Test name
Test status
Simulation time 58968206175 ps
CPU time 365.96 seconds
Started Aug 02 04:44:49 PM PDT 24
Finished Aug 02 04:50:55 PM PDT 24
Peak memory 256152 kb
Host smart-0d5dd066-9244-409f-ab65-9ea9ce0554ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717875808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3717875808
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1289065768
Short name T568
Test name
Test status
Simulation time 46198357380 ps
CPU time 61.82 seconds
Started Aug 02 04:43:27 PM PDT 24
Finished Aug 02 04:44:29 PM PDT 24
Peak memory 254308 kb
Host smart-b304b011-7553-477c-972f-49fb3aeb8b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289065768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1289065768
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2892129502
Short name T337
Test name
Test status
Simulation time 2488220197 ps
CPU time 17.99 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 248816 kb
Host smart-b3a36050-06f3-48c3-ad01-a3399cd883e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892129502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2892129502
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3611424599
Short name T297
Test name
Test status
Simulation time 4143403870 ps
CPU time 8.9 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 224172 kb
Host smart-cd025eff-d4b9-4901-95e2-6da2c59fcca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611424599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3611424599
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2537009416
Short name T967
Test name
Test status
Simulation time 135795962106 ps
CPU time 212.89 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:46:59 PM PDT 24
Peak memory 253388 kb
Host smart-4fa6fc33-9738-4690-8227-e0a2403fb4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537009416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2537009416
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2226032488
Short name T887
Test name
Test status
Simulation time 237433701 ps
CPU time 4.95 seconds
Started Aug 02 04:43:21 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 233380 kb
Host smart-bd050d62-b00e-464e-b5a2-09ff224c7d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226032488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2226032488
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4015471746
Short name T738
Test name
Test status
Simulation time 1048638748 ps
CPU time 15.74 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:42 PM PDT 24
Peak memory 224772 kb
Host smart-04a4a370-0ec7-40fb-be54-4e94336c32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015471746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4015471746
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2304410987
Short name T826
Test name
Test status
Simulation time 20247056234 ps
CPU time 10.4 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:43:34 PM PDT 24
Peak memory 225208 kb
Host smart-dd605a8e-170a-4ba9-a5c1-ca1fcce30797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304410987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2304410987
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2674824913
Short name T523
Test name
Test status
Simulation time 32931995051 ps
CPU time 24.18 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 225272 kb
Host smart-1217fbdb-247f-452a-8c7e-5fd70dfb6fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674824913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2674824913
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4149260085
Short name T764
Test name
Test status
Simulation time 2738211810 ps
CPU time 20.41 seconds
Started Aug 02 04:43:21 PM PDT 24
Finished Aug 02 04:43:41 PM PDT 24
Peak memory 219960 kb
Host smart-fb1966b0-5ac8-40e1-aad8-8ed7b6e13cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149260085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4149260085
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.762914056
Short name T825
Test name
Test status
Simulation time 116593843 ps
CPU time 0.9 seconds
Started Aug 02 04:43:20 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 207320 kb
Host smart-fa3b78ef-3f38-418f-a772-b722b44f2c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762914056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.762914056
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.368059995
Short name T934
Test name
Test status
Simulation time 78457154 ps
CPU time 0.74 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 206004 kb
Host smart-0cff9a12-2857-4c34-acfb-fd9f3efa7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368059995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.368059995
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2356664241
Short name T458
Test name
Test status
Simulation time 5208597487 ps
CPU time 5.79 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 216808 kb
Host smart-5d656834-b4a9-4d6a-a521-277ed0d0d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356664241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2356664241
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2776327985
Short name T56
Test name
Test status
Simulation time 2389162407 ps
CPU time 2.83 seconds
Started Aug 02 04:43:22 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 216912 kb
Host smart-305e3322-b180-4a9a-9e3a-33ab039dab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776327985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2776327985
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.618451317
Short name T522
Test name
Test status
Simulation time 64272111 ps
CPU time 0.93 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 206496 kb
Host smart-1fc176e7-2470-431c-a536-9d1af2abde15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618451317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.618451317
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1014108069
Short name T604
Test name
Test status
Simulation time 4876438249 ps
CPU time 20.17 seconds
Started Aug 02 04:44:18 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 240604 kb
Host smart-4e45a669-8914-4abb-9d15-8f9b5a6bc2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014108069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1014108069
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2290635196
Short name T317
Test name
Test status
Simulation time 208870758 ps
CPU time 2.32 seconds
Started Aug 02 04:43:22 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 225140 kb
Host smart-fbe942ef-74d9-4995-a92e-942c5afecff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290635196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2290635196
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.564110776
Short name T578
Test name
Test status
Simulation time 16706861 ps
CPU time 0.78 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 206312 kb
Host smart-26b37ea2-077c-4d2e-b594-801ec4bf9773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564110776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.564110776
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3792225605
Short name T570
Test name
Test status
Simulation time 22713236421 ps
CPU time 160.26 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:46:07 PM PDT 24
Peak memory 254904 kb
Host smart-c9b584af-72ed-4c86-b22f-a50d6b551d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792225605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3792225605
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.938070435
Short name T1006
Test name
Test status
Simulation time 4388496206 ps
CPU time 69.43 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 248136 kb
Host smart-68fcbaf7-e3e0-4e4c-90c2-e3c68c145764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938070435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.938070435
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2744188822
Short name T511
Test name
Test status
Simulation time 27657087298 ps
CPU time 93.12 seconds
Started Aug 02 04:43:33 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 224700 kb
Host smart-0b68e435-11d0-477c-8e9c-d6dc7947841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744188822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2744188822
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.927867803
Short name T631
Test name
Test status
Simulation time 625139333 ps
CPU time 11.86 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:37 PM PDT 24
Peak memory 232952 kb
Host smart-0de5c80a-65e6-49a1-8a07-c572e3965949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927867803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.927867803
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3939437617
Short name T480
Test name
Test status
Simulation time 2038457981 ps
CPU time 10.21 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 235020 kb
Host smart-499003bc-a564-4551-b6c7-82b5ab11f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939437617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3939437617
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3100547587
Short name T873
Test name
Test status
Simulation time 19336479669 ps
CPU time 13.11 seconds
Started Aug 02 04:44:46 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 233268 kb
Host smart-325fdf17-0314-4374-8bd6-461890516f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100547587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3100547587
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3901940050
Short name T426
Test name
Test status
Simulation time 8946480118 ps
CPU time 56.51 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 233116 kb
Host smart-4b87321c-d8ad-4f1b-b5ea-5f70cc517815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901940050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3901940050
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3961817621
Short name T350
Test name
Test status
Simulation time 17992575 ps
CPU time 1.04 seconds
Started Aug 02 04:43:22 PM PDT 24
Finished Aug 02 04:43:23 PM PDT 24
Peak memory 217096 kb
Host smart-10eb6a6d-436b-4b34-a34b-e9eda8b7579c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961817621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3961817621
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3722918180
Short name T822
Test name
Test status
Simulation time 889043071 ps
CPU time 6.52 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 223328 kb
Host smart-6d4b6f05-7d23-4b2d-8441-b4d62b64cb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722918180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3722918180
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2559667562
Short name T204
Test name
Test status
Simulation time 4393322497 ps
CPU time 9.58 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:36 PM PDT 24
Peak memory 236164 kb
Host smart-98397434-6238-4c5c-b682-c9e14a63a467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559667562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2559667562
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4131878752
Short name T800
Test name
Test status
Simulation time 653805856 ps
CPU time 7.8 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 222648 kb
Host smart-85910bdc-5cc9-4a98-a059-e3f345f8e52f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131878752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4131878752
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1783513139
Short name T901
Test name
Test status
Simulation time 114041351083 ps
CPU time 267.92 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:47:59 PM PDT 24
Peak memory 251964 kb
Host smart-95529efe-4fc2-4774-a64a-363ab82fa1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783513139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1783513139
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2947794803
Short name T1011
Test name
Test status
Simulation time 6830139738 ps
CPU time 19.84 seconds
Started Aug 02 04:43:25 PM PDT 24
Finished Aug 02 04:43:45 PM PDT 24
Peak memory 216776 kb
Host smart-ccdb3af8-5fed-4bc7-8cdd-9eeb3115f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947794803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2947794803
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1063196338
Short name T415
Test name
Test status
Simulation time 1242590219 ps
CPU time 2.1 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:28 PM PDT 24
Peak memory 208324 kb
Host smart-204e37bb-04ff-4ca5-893e-1ea73eea2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063196338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1063196338
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1063092622
Short name T1017
Test name
Test status
Simulation time 95226866 ps
CPU time 1.91 seconds
Started Aug 02 04:43:23 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 216864 kb
Host smart-5823fdac-0904-4771-a204-d5b9041e89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063092622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1063092622
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3176135693
Short name T322
Test name
Test status
Simulation time 17182599 ps
CPU time 0.71 seconds
Started Aug 02 04:44:49 PM PDT 24
Finished Aug 02 04:44:50 PM PDT 24
Peak memory 206376 kb
Host smart-6c7e81fb-2fc2-4db0-a540-455c60259ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176135693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3176135693
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3577838053
Short name T618
Test name
Test status
Simulation time 1822145404 ps
CPU time 4.67 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:43:29 PM PDT 24
Peak memory 225064 kb
Host smart-239db71c-a515-4f3f-b8dd-8ebf788bd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577838053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3577838053
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3495340875
Short name T982
Test name
Test status
Simulation time 22925979 ps
CPU time 0.68 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 205408 kb
Host smart-12730231-4944-487a-b584-83399a01f6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495340875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3495340875
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1494274199
Short name T462
Test name
Test status
Simulation time 1126832673 ps
CPU time 2.26 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:41 PM PDT 24
Peak memory 223212 kb
Host smart-f09a891a-285f-468b-94eb-408eb741ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494274199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1494274199
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1419725671
Short name T432
Test name
Test status
Simulation time 17004747 ps
CPU time 0.79 seconds
Started Aug 02 04:43:32 PM PDT 24
Finished Aug 02 04:43:33 PM PDT 24
Peak memory 206892 kb
Host smart-e0c332c4-578a-4527-bee5-141dfd273dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419725671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1419725671
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3991846583
Short name T649
Test name
Test status
Simulation time 6408728362 ps
CPU time 83.72 seconds
Started Aug 02 04:43:32 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 253176 kb
Host smart-49964670-af57-47ef-a129-0f2d8873d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991846583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3991846583
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3172538308
Short name T230
Test name
Test status
Simulation time 21074699023 ps
CPU time 188.04 seconds
Started Aug 02 04:43:34 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 258032 kb
Host smart-37de835f-eae6-4cad-8c1a-ec46dfc354eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172538308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3172538308
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1991529142
Short name T275
Test name
Test status
Simulation time 17550150804 ps
CPU time 69.14 seconds
Started Aug 02 04:43:30 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 256260 kb
Host smart-ca0c5c6c-d77f-49ff-9dec-e895db0a52c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991529142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1991529142
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3398848918
Short name T863
Test name
Test status
Simulation time 2316424289 ps
CPU time 5.37 seconds
Started Aug 02 04:43:34 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 225240 kb
Host smart-e7dfb99c-95e6-4479-be15-165a50d64945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398848918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3398848918
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3137830085
Short name T564
Test name
Test status
Simulation time 1498293567 ps
CPU time 32.55 seconds
Started Aug 02 04:43:33 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 241744 kb
Host smart-9319fa65-555b-4282-b402-153a7975a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137830085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3137830085
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.700381379
Short name T334
Test name
Test status
Simulation time 128147905 ps
CPU time 2.58 seconds
Started Aug 02 04:43:36 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 232952 kb
Host smart-8ea44b41-55a3-4393-bbb2-6fec485cc328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700381379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.700381379
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3997555922
Short name T224
Test name
Test status
Simulation time 1343284756 ps
CPU time 17.2 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:43:49 PM PDT 24
Peak memory 225120 kb
Host smart-ad3f9288-fb0d-4569-9be0-27e5abcdc997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997555922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3997555922
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1414929492
Short name T858
Test name
Test status
Simulation time 24220648 ps
CPU time 1.01 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 218480 kb
Host smart-a6cfd75e-38d9-4bef-afa2-bf493d16a1f2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414929492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1414929492
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.165852715
Short name T765
Test name
Test status
Simulation time 4457877822 ps
CPU time 14.37 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:43:45 PM PDT 24
Peak memory 241524 kb
Host smart-9e357e9b-5a3b-4779-9934-9200f8487f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165852715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.165852715
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2829305485
Short name T813
Test name
Test status
Simulation time 471540273 ps
CPU time 2.39 seconds
Started Aug 02 04:43:30 PM PDT 24
Finished Aug 02 04:43:33 PM PDT 24
Peak memory 225100 kb
Host smart-220345ec-40ef-4573-a65f-04b426924e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829305485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2829305485
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2265130220
Short name T150
Test name
Test status
Simulation time 3411074434 ps
CPU time 5.67 seconds
Started Aug 02 04:43:35 PM PDT 24
Finished Aug 02 04:43:41 PM PDT 24
Peak memory 221256 kb
Host smart-23e55eb5-8369-4536-b683-0d123579ac41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265130220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2265130220
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2158360956
Short name T665
Test name
Test status
Simulation time 2518461633 ps
CPU time 6.1 seconds
Started Aug 02 04:43:34 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 217192 kb
Host smart-2c09ca9c-8073-4af9-a34c-ee8146cbbd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158360956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2158360956
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1328031786
Short name T440
Test name
Test status
Simulation time 11690308170 ps
CPU time 8.99 seconds
Started Aug 02 04:44:46 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 216768 kb
Host smart-ddece33c-c127-4cc1-97cd-6764ed30d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328031786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1328031786
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1448529667
Short name T595
Test name
Test status
Simulation time 668456048 ps
CPU time 2.22 seconds
Started Aug 02 04:43:33 PM PDT 24
Finished Aug 02 04:43:35 PM PDT 24
Peak memory 216952 kb
Host smart-4c347d6f-ccda-496c-b23c-070ffd0a9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448529667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1448529667
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.134968924
Short name T472
Test name
Test status
Simulation time 473450682 ps
CPU time 0.79 seconds
Started Aug 02 04:43:30 PM PDT 24
Finished Aug 02 04:43:31 PM PDT 24
Peak memory 206576 kb
Host smart-61bcd1a5-d18c-447f-a0ae-9fc9a7c9c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134968924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.134968924
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.278567067
Short name T882
Test name
Test status
Simulation time 5707024280 ps
CPU time 13.59 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 233344 kb
Host smart-e87a6973-f538-4749-877a-fea285f9d178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278567067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.278567067
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3984077001
Short name T952
Test name
Test status
Simulation time 12862316 ps
CPU time 0.68 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 205324 kb
Host smart-d3a52be3-cea9-4efe-8358-1bd0ff99d3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984077001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3984077001
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3963685877
Short name T457
Test name
Test status
Simulation time 92679163 ps
CPU time 2.9 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:43:41 PM PDT 24
Peak memory 233276 kb
Host smart-79335b82-e29f-4ea2-ba9a-187b40c16352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963685877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3963685877
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2206241779
Short name T759
Test name
Test status
Simulation time 42425706 ps
CPU time 0.76 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:34 PM PDT 24
Peak memory 206016 kb
Host smart-53b32101-c13a-40c5-8a2c-c7d853353e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206241779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2206241779
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3634596631
Short name T859
Test name
Test status
Simulation time 395711411 ps
CPU time 10.02 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:49 PM PDT 24
Peak memory 225108 kb
Host smart-4af5c436-f2a3-436b-b7c1-5efe82f5c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634596631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3634596631
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4209071207
Short name T662
Test name
Test status
Simulation time 3627952306 ps
CPU time 25.57 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 240456 kb
Host smart-cd49b839-5bb1-4e1b-b609-b61edfa22e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209071207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4209071207
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2607438437
Short name T367
Test name
Test status
Simulation time 141985417 ps
CPU time 2.14 seconds
Started Aug 02 04:43:36 PM PDT 24
Finished Aug 02 04:43:38 PM PDT 24
Peak memory 223676 kb
Host smart-acf759c0-f5c6-4e15-875e-9d46a0ac9994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607438437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2607438437
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1445802807
Short name T347
Test name
Test status
Simulation time 305721248 ps
CPU time 3 seconds
Started Aug 02 04:43:32 PM PDT 24
Finished Aug 02 04:43:36 PM PDT 24
Peak memory 233504 kb
Host smart-295b6c79-bee2-4aef-9567-6b8b269e8e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445802807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1445802807
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1141090581
Short name T787
Test name
Test status
Simulation time 25897975 ps
CPU time 1.04 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 217100 kb
Host smart-41c854f9-0687-4ed1-869b-b2677213ddee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141090581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1141090581
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.240873832
Short name T745
Test name
Test status
Simulation time 243603346 ps
CPU time 4.44 seconds
Started Aug 02 04:43:34 PM PDT 24
Finished Aug 02 04:43:38 PM PDT 24
Peak memory 225188 kb
Host smart-db521b37-4376-4b8a-9d4b-3b96c0abad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240873832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.240873832
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1780068089
Short name T357
Test name
Test status
Simulation time 906641743 ps
CPU time 7.5 seconds
Started Aug 02 04:43:30 PM PDT 24
Finished Aug 02 04:43:38 PM PDT 24
Peak memory 239932 kb
Host smart-ed71ebac-2ef4-493f-ac86-26d60ca2cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780068089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1780068089
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.220346794
Short name T152
Test name
Test status
Simulation time 1707757374 ps
CPU time 10.86 seconds
Started Aug 02 04:43:43 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 223800 kb
Host smart-b2d0ad9e-bff4-46d7-acce-359eb71023ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220346794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.220346794
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3860826404
Short name T299
Test name
Test status
Simulation time 1436406404 ps
CPU time 13.99 seconds
Started Aug 02 04:43:33 PM PDT 24
Finished Aug 02 04:43:47 PM PDT 24
Peak memory 216956 kb
Host smart-41ba5dfa-8e81-4f64-a988-6e3d9e9e0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860826404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3860826404
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3781836620
Short name T768
Test name
Test status
Simulation time 4711122404 ps
CPU time 7.88 seconds
Started Aug 02 04:43:31 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 216968 kb
Host smart-d9313ae5-5f65-4714-9fa6-386b362b44db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781836620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3781836620
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3161208231
Short name T387
Test name
Test status
Simulation time 102867713 ps
CPU time 1.47 seconds
Started Aug 02 04:43:33 PM PDT 24
Finished Aug 02 04:43:34 PM PDT 24
Peak memory 216872 kb
Host smart-87714b6d-efa3-449b-b3b1-5228d306992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161208231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3161208231
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2876272425
Short name T940
Test name
Test status
Simulation time 84779275 ps
CPU time 0.74 seconds
Started Aug 02 04:44:49 PM PDT 24
Finished Aug 02 04:44:50 PM PDT 24
Peak memory 206136 kb
Host smart-15c32871-0b36-43cd-9532-44eda7abc942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876272425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2876272425
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2313247253
Short name T660
Test name
Test status
Simulation time 52940268 ps
CPU time 2.69 seconds
Started Aug 02 04:43:45 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 232952 kb
Host smart-37bb25b9-77a1-47c2-812d-d6400cb13f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313247253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2313247253
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2172239762
Short name T894
Test name
Test status
Simulation time 14580640 ps
CPU time 0.75 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 205788 kb
Host smart-58154430-9b19-4e9d-991b-076f57ee95a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172239762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2172239762
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1695616769
Short name T1016
Test name
Test status
Simulation time 19134072 ps
CPU time 0.76 seconds
Started Aug 02 04:43:41 PM PDT 24
Finished Aug 02 04:43:42 PM PDT 24
Peak memory 206952 kb
Host smart-e7c18700-ffbc-4621-8110-675b279cfd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695616769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1695616769
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3466283844
Short name T217
Test name
Test status
Simulation time 15520567633 ps
CPU time 66.45 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 254904 kb
Host smart-ba06575d-d567-4222-bbd4-9421cba5bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466283844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3466283844
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3049251313
Short name T304
Test name
Test status
Simulation time 2787333167 ps
CPU time 31.75 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:44:12 PM PDT 24
Peak memory 236652 kb
Host smart-0522171b-efad-49fa-9cf3-b2e6e594c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049251313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3049251313
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4007138908
Short name T225
Test name
Test status
Simulation time 2786899598 ps
CPU time 50.12 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:44:28 PM PDT 24
Peak memory 249936 kb
Host smart-992175f5-78ab-4749-be15-9ff34e77e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007138908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4007138908
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.728663931
Short name T937
Test name
Test status
Simulation time 235166685 ps
CPU time 6.4 seconds
Started Aug 02 04:43:41 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 225084 kb
Host smart-d2fd6fe9-0f34-463b-9dca-9aac095ae109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728663931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.728663931
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2109911605
Short name T49
Test name
Test status
Simulation time 237959638248 ps
CPU time 172.61 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 249808 kb
Host smart-5fe7d708-3669-4732-a520-50ac2dd9d8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109911605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2109911605
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2865078410
Short name T686
Test name
Test status
Simulation time 1081106128 ps
CPU time 10.5 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:50 PM PDT 24
Peak memory 225052 kb
Host smart-f86104a7-4215-467e-a2fd-7a20bd0c26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865078410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2865078410
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2964572107
Short name T258
Test name
Test status
Simulation time 12059905833 ps
CPU time 68.74 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 233324 kb
Host smart-033a4a35-1c94-459c-810a-6e417533f935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964572107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2964572107
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4183975441
Short name T38
Test name
Test status
Simulation time 52622214 ps
CPU time 1.07 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 217124 kb
Host smart-e6d4891f-9f64-4b22-9c98-f76cc2e00ca7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183975441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4183975441
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.939837696
Short name T565
Test name
Test status
Simulation time 7306975955 ps
CPU time 12.14 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 225364 kb
Host smart-d2aa1985-96da-4618-b1b1-ae253bc03cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939837696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.939837696
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3976419026
Short name T775
Test name
Test status
Simulation time 1684023294 ps
CPU time 8.83 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 233268 kb
Host smart-eb890d48-f29b-4a50-9380-5522493bae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976419026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3976419026
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4259201320
Short name T425
Test name
Test status
Simulation time 441078055 ps
CPU time 3.46 seconds
Started Aug 02 04:43:42 PM PDT 24
Finished Aug 02 04:43:46 PM PDT 24
Peak memory 220760 kb
Host smart-6683d115-0354-4e3c-a480-bad1ab9df379
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4259201320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4259201320
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.374783624
Short name T751
Test name
Test status
Simulation time 7774042171 ps
CPU time 4.15 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:43 PM PDT 24
Peak memory 216904 kb
Host smart-85f6eb33-8e7e-4acf-a4cb-6df3ac675dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374783624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.374783624
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1786019636
Short name T498
Test name
Test status
Simulation time 3224811544 ps
CPU time 5.2 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:43:45 PM PDT 24
Peak memory 216896 kb
Host smart-dc563288-5c5f-43d3-ba0a-98b73dea5199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786019636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1786019636
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3908867665
Short name T989
Test name
Test status
Simulation time 111993355 ps
CPU time 2.08 seconds
Started Aug 02 04:43:41 PM PDT 24
Finished Aug 02 04:43:43 PM PDT 24
Peak memory 216992 kb
Host smart-a85c7712-a64a-4036-8292-4934cdc0dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908867665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3908867665
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2976213611
Short name T922
Test name
Test status
Simulation time 778742299 ps
CPU time 0.85 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 206480 kb
Host smart-6c12e732-a5f9-4ea7-ad1d-b0be4aca399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976213611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2976213611
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.165351366
Short name T816
Test name
Test status
Simulation time 492591232 ps
CPU time 8.18 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 233312 kb
Host smart-0a2a4aa0-e20b-4cff-9353-30377d4da8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165351366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.165351366
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1729594038
Short name T571
Test name
Test status
Simulation time 133562087 ps
CPU time 0.76 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:52 PM PDT 24
Peak memory 205356 kb
Host smart-bf972ed6-a405-438d-babd-db6ed4b0c9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729594038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1729594038
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2954933058
Short name T85
Test name
Test status
Simulation time 116208730 ps
CPU time 2.28 seconds
Started Aug 02 04:43:46 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 225160 kb
Host smart-9eb94f1c-a182-4d7b-a0a8-7a60b8eff168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954933058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2954933058
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.369737896
Short name T965
Test name
Test status
Simulation time 73742124 ps
CPU time 0.8 seconds
Started Aug 02 04:43:38 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 206932 kb
Host smart-d655c827-c57f-4980-8157-0458c231d4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369737896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.369737896
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.760723640
Short name T709
Test name
Test status
Simulation time 7969123490 ps
CPU time 82.2 seconds
Started Aug 02 04:43:49 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 249752 kb
Host smart-e1a9afb6-ef89-4f5b-a823-9bd46025f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760723640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.760723640
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2147813341
Short name T715
Test name
Test status
Simulation time 127776978451 ps
CPU time 240.88 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:47:52 PM PDT 24
Peak memory 250992 kb
Host smart-c6f14831-4f19-4516-a443-471051748657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147813341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2147813341
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2690130909
Short name T983
Test name
Test status
Simulation time 1644595202 ps
CPU time 19.92 seconds
Started Aug 02 04:43:54 PM PDT 24
Finished Aug 02 04:44:14 PM PDT 24
Peak memory 249796 kb
Host smart-9677fa67-c06b-4a80-b7b1-988e2199f491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690130909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2690130909
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1863370636
Short name T371
Test name
Test status
Simulation time 24577645817 ps
CPU time 34.18 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:44:28 PM PDT 24
Peak memory 251508 kb
Host smart-dcb62e38-2937-4edd-95f1-b4caaea69012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863370636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1863370636
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.858525274
Short name T819
Test name
Test status
Simulation time 1280379612 ps
CPU time 7.65 seconds
Started Aug 02 04:43:37 PM PDT 24
Finished Aug 02 04:43:45 PM PDT 24
Peak memory 225044 kb
Host smart-a5a17cb3-fbee-4797-8b5c-dd345f7c78d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858525274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.858525274
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1157080317
Short name T249
Test name
Test status
Simulation time 34158851413 ps
CPU time 61.17 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 233400 kb
Host smart-f6651b06-ff15-4379-ae89-80cd807a6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157080317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1157080317
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3684522348
Short name T575
Test name
Test status
Simulation time 31095179 ps
CPU time 1 seconds
Started Aug 02 04:44:21 PM PDT 24
Finished Aug 02 04:44:22 PM PDT 24
Peak memory 218332 kb
Host smart-724567b1-c1a3-4227-8f77-7b6eb5ca8999
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684522348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3684522348
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3212132486
Short name T557
Test name
Test status
Simulation time 780009671 ps
CPU time 5.82 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 241528 kb
Host smart-c0157616-a9cb-46ed-a709-8529bfe34872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212132486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3212132486
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2098931165
Short name T194
Test name
Test status
Simulation time 20771097464 ps
CPU time 11.87 seconds
Started Aug 02 04:43:41 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 235780 kb
Host smart-d19fd728-70e4-4c35-b866-86083da5a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098931165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2098931165
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.769302464
Short name T950
Test name
Test status
Simulation time 686360441 ps
CPU time 10.52 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:44:02 PM PDT 24
Peak memory 223008 kb
Host smart-c7d2c89b-b1f2-4604-a327-304e3fcf5114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=769302464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.769302464
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1108237746
Short name T1000
Test name
Test status
Simulation time 12779855 ps
CPU time 0.7 seconds
Started Aug 02 04:43:39 PM PDT 24
Finished Aug 02 04:43:39 PM PDT 24
Peak memory 206492 kb
Host smart-ca7ec4a6-b4fc-46fe-95ab-6c250cffa275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108237746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1108237746
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.160950375
Short name T82
Test name
Test status
Simulation time 1511671071 ps
CPU time 8.25 seconds
Started Aug 02 04:43:46 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 216896 kb
Host smart-0d9232cf-f936-4a10-b750-a83e4e4c5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160950375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.160950375
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2098590056
Short name T308
Test name
Test status
Simulation time 544988411 ps
CPU time 7.84 seconds
Started Aug 02 04:43:40 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 216864 kb
Host smart-bf4f0043-8b02-418c-90e9-afa9c90fa3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098590056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2098590056
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3586398869
Short name T635
Test name
Test status
Simulation time 139721418 ps
CPU time 1.12 seconds
Started Aug 02 04:43:43 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 206828 kb
Host smart-8121cb65-966a-4de3-a2fa-894a10b914aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586398869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3586398869
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1059025186
Short name T840
Test name
Test status
Simulation time 521908356 ps
CPU time 6.34 seconds
Started Aug 02 04:44:21 PM PDT 24
Finished Aug 02 04:44:27 PM PDT 24
Peak memory 233276 kb
Host smart-659389de-c6b8-4540-80fc-b4e304d54579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059025186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1059025186
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.563912860
Short name T383
Test name
Test status
Simulation time 15496874 ps
CPU time 0.76 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 205180 kb
Host smart-bcc5edbc-fc29-4810-aa82-3a4926edc14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563912860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.563912860
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3426176514
Short name T187
Test name
Test status
Simulation time 678157756 ps
CPU time 5.9 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 225120 kb
Host smart-d4dce893-5d5d-4ef5-bed7-5a43dcf95694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426176514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3426176514
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1768483358
Short name T556
Test name
Test status
Simulation time 66939767 ps
CPU time 0.81 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:52 PM PDT 24
Peak memory 205964 kb
Host smart-28e9544a-b1ff-44dc-ac44-8baf6583a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768483358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1768483358
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3432135431
Short name T205
Test name
Test status
Simulation time 66980667579 ps
CPU time 141.95 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 256752 kb
Host smart-5434fab3-0328-46fc-b2a5-56360cf8d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432135431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3432135431
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.985342480
Short name T747
Test name
Test status
Simulation time 4670235794 ps
CPU time 50.01 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 238228 kb
Host smart-f62bce78-03ff-42d7-93e0-0bb9036c31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985342480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.985342480
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.387328769
Short name T870
Test name
Test status
Simulation time 2090769824 ps
CPU time 24.31 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:44:14 PM PDT 24
Peak memory 236560 kb
Host smart-87a0e7ed-72df-429f-84d9-b9a7836c4174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387328769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.387328769
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.291222908
Short name T985
Test name
Test status
Simulation time 26250420902 ps
CPU time 69.01 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:44:59 PM PDT 24
Peak memory 250852 kb
Host smart-047bd5d7-44c9-4b4f-b345-c0e53e2d5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291222908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.291222908
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3154196891
Short name T54
Test name
Test status
Simulation time 637354888 ps
CPU time 9.34 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:44:02 PM PDT 24
Peak memory 225188 kb
Host smart-9489a58d-75c2-4127-a729-c425e298733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154196891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3154196891
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3383098426
Short name T592
Test name
Test status
Simulation time 1656480860 ps
CPU time 15.69 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 225292 kb
Host smart-b04241d9-6047-49fb-93aa-ac8b2f6f84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383098426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3383098426
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1116048056
Short name T926
Test name
Test status
Simulation time 61586862 ps
CPU time 1.06 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 217164 kb
Host smart-ead9eb42-d5c6-49b3-9905-f9dfeadbccab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116048056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1116048056
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2703550119
Short name T40
Test name
Test status
Simulation time 8870335760 ps
CPU time 15.54 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 241568 kb
Host smart-221d1d37-3e44-4799-9422-51bfa069b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703550119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2703550119
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.406669829
Short name T216
Test name
Test status
Simulation time 765810966 ps
CPU time 4.63 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 233332 kb
Host smart-1982e135-bec1-42bf-9e23-ece86c646428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406669829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.406669829
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2954180163
Short name T669
Test name
Test status
Simulation time 509274988 ps
CPU time 4.07 seconds
Started Aug 02 04:43:49 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 223020 kb
Host smart-84ae143d-f8fe-4a96-a5be-cb8f6e7b3c6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2954180163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2954180163
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.153708818
Short name T51
Test name
Test status
Simulation time 49862468936 ps
CPU time 141.39 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 256372 kb
Host smart-497ae4f2-c361-4197-b311-40aaa2601b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153708818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.153708818
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3018465819
Short name T798
Test name
Test status
Simulation time 1954819289 ps
CPU time 14.2 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 216788 kb
Host smart-cb9b1e5d-3a87-4287-987c-3ed53a57939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018465819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3018465819
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1459390369
Short name T612
Test name
Test status
Simulation time 2977196529 ps
CPU time 4.62 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 216980 kb
Host smart-395b0b87-f4e8-4b19-bc97-4b4c97af8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459390369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1459390369
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.369934976
Short name T450
Test name
Test status
Simulation time 286184053 ps
CPU time 2.5 seconds
Started Aug 02 04:43:54 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 216876 kb
Host smart-aad4a3fe-c4cf-4d97-a3cd-f2bc3c7e71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369934976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.369934976
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2478650243
Short name T653
Test name
Test status
Simulation time 44316434 ps
CPU time 0.81 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 206544 kb
Host smart-900db436-0f07-4498-8db9-3f3413124f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478650243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2478650243
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3376302873
Short name T237
Test name
Test status
Simulation time 4930530916 ps
CPU time 5.2 seconds
Started Aug 02 04:43:54 PM PDT 24
Finished Aug 02 04:43:59 PM PDT 24
Peak memory 225176 kb
Host smart-b511fe39-cb65-4f0a-86d2-268b035e27aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376302873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3376302873
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.868894444
Short name T590
Test name
Test status
Simulation time 37320884 ps
CPU time 0.68 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:52 PM PDT 24
Peak memory 206024 kb
Host smart-09a680c5-7159-4868-8f82-0533246ea181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868894444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.868894444
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3490671155
Short name T930
Test name
Test status
Simulation time 294289978 ps
CPU time 5.13 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 233276 kb
Host smart-cada766c-e358-45d7-97e1-921b965a42f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490671155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3490671155
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2101729816
Short name T563
Test name
Test status
Simulation time 47001240 ps
CPU time 0.8 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 207452 kb
Host smart-0e10b648-8fe8-4989-9fd2-2555b0ea7453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101729816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2101729816
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1430209395
Short name T419
Test name
Test status
Simulation time 4412952593 ps
CPU time 15.04 seconds
Started Aug 02 04:43:54 PM PDT 24
Finished Aug 02 04:44:09 PM PDT 24
Peak memory 233432 kb
Host smart-c0dcc2ea-b1b5-4b07-9f2a-6415ea6b444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430209395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1430209395
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1666558491
Short name T835
Test name
Test status
Simulation time 10695107790 ps
CPU time 100.49 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 249916 kb
Host smart-17c2181c-1d3e-48f7-ab55-3c7820f05256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666558491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1666558491
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3975882770
Short name T984
Test name
Test status
Simulation time 22833613788 ps
CPU time 139.03 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:46:11 PM PDT 24
Peak memory 255584 kb
Host smart-a97ce1a0-566e-44dd-ac0d-6f76c18e88e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975882770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3975882770
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1057834991
Short name T341
Test name
Test status
Simulation time 172358821 ps
CPU time 4.57 seconds
Started Aug 02 04:43:49 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 233336 kb
Host smart-e9c742ee-c74e-4ad2-b3ee-99625079c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057834991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1057834991
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2113931219
Short name T412
Test name
Test status
Simulation time 203898164 ps
CPU time 0.91 seconds
Started Aug 02 04:43:49 PM PDT 24
Finished Aug 02 04:43:50 PM PDT 24
Peak memory 216472 kb
Host smart-86304e07-277a-4eae-a3ec-5a2e7af9817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113931219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2113931219
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.85050325
Short name T808
Test name
Test status
Simulation time 2826184199 ps
CPU time 9.18 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 233424 kb
Host smart-419011d1-653b-4277-85f7-c4d36158bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85050325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.85050325
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1460865320
Short name T1020
Test name
Test status
Simulation time 3978195381 ps
CPU time 42.53 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 233376 kb
Host smart-80a1c258-8703-47e8-bfeb-c0294d37eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460865320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1460865320
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3559723256
Short name T353
Test name
Test status
Simulation time 25962767 ps
CPU time 1.07 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 217096 kb
Host smart-034c7fbe-e5c1-4d1f-8527-4458b3afdde6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559723256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3559723256
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4120957267
Short name T947
Test name
Test status
Simulation time 16372886365 ps
CPU time 21.85 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:44:12 PM PDT 24
Peak memory 249884 kb
Host smart-14f10f10-8b8b-495b-b289-766bebae0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120957267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4120957267
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3774260840
Short name T956
Test name
Test status
Simulation time 1014429124 ps
CPU time 8.22 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 233360 kb
Host smart-31414302-87c7-4f3a-9960-3e8feeece3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774260840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3774260840
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2458218064
Short name T474
Test name
Test status
Simulation time 425485779 ps
CPU time 4.07 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 223500 kb
Host smart-01944f55-f8af-4d0c-a9d4-135dadf8c088
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2458218064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2458218064
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3774975496
Short name T361
Test name
Test status
Simulation time 705338184 ps
CPU time 7.23 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 217248 kb
Host smart-f6702719-cb87-481b-a7ee-42a2e4695024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774975496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3774975496
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3462227815
Short name T3
Test name
Test status
Simulation time 9101224079 ps
CPU time 14.13 seconds
Started Aug 02 04:43:51 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 216888 kb
Host smart-24936f15-f64c-4bfd-9ded-f35b7c99bba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462227815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3462227815
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2660911234
Short name T872
Test name
Test status
Simulation time 194775217 ps
CPU time 2.39 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:43:55 PM PDT 24
Peak memory 216852 kb
Host smart-5b2a6cd4-7f1f-4b46-a176-737011240290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660911234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2660911234
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2205176304
Short name T531
Test name
Test status
Simulation time 189545326 ps
CPU time 0.79 seconds
Started Aug 02 04:43:50 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 206428 kb
Host smart-c159c73c-5e96-45be-8d2f-a05aed72ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205176304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2205176304
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1197791873
Short name T847
Test name
Test status
Simulation time 39430732249 ps
CPU time 31.66 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:44:25 PM PDT 24
Peak memory 251692 kb
Host smart-6c57de11-4dd3-4eb3-92b1-b73f36c899f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197791873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1197791873
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4039280611
Short name T1019
Test name
Test status
Simulation time 28700491 ps
CPU time 0.7 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 205192 kb
Host smart-cbebf0c9-2391-415b-b95f-b2fda3f84e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039280611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
039280611
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1574189275
Short name T911
Test name
Test status
Simulation time 86345314 ps
CPU time 3.29 seconds
Started Aug 02 04:43:01 PM PDT 24
Finished Aug 02 04:43:05 PM PDT 24
Peak memory 233272 kb
Host smart-bdc7fc5a-3357-4366-86c5-44db100773bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574189275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1574189275
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2079229838
Short name T640
Test name
Test status
Simulation time 58979438 ps
CPU time 0.82 seconds
Started Aug 02 04:42:44 PM PDT 24
Finished Aug 02 04:42:45 PM PDT 24
Peak memory 205932 kb
Host smart-a065c2ef-24cd-4a84-86ca-7b108c214d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079229838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2079229838
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1380061494
Short name T716
Test name
Test status
Simulation time 19248873 ps
CPU time 0.73 seconds
Started Aug 02 04:42:58 PM PDT 24
Finished Aug 02 04:42:58 PM PDT 24
Peak memory 216372 kb
Host smart-4c9e829c-4e6a-434d-be89-98eecb0fcce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380061494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1380061494
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.753017499
Short name T203
Test name
Test status
Simulation time 3797650993 ps
CPU time 87.94 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:44:26 PM PDT 24
Peak memory 266136 kb
Host smart-920ecc57-f737-44e9-aa30-7e3936d8379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753017499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.753017499
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1735576378
Short name T195
Test name
Test status
Simulation time 107906820345 ps
CPU time 400.73 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:49:38 PM PDT 24
Peak memory 264736 kb
Host smart-459d3fbb-60bc-4c87-b376-8df0cc599ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735576378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1735576378
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.745185845
Short name T296
Test name
Test status
Simulation time 124617223 ps
CPU time 7.63 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:04 PM PDT 24
Peak memory 233248 kb
Host smart-afd6f6f9-46c9-450b-9f73-a9b2b4d90cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745185845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.745185845
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1268930293
Short name T355
Test name
Test status
Simulation time 5323879310 ps
CPU time 67.2 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 255392 kb
Host smart-6287fd13-8c5d-4c3c-9480-b1c45b8036fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268930293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1268930293
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3216699092
Short name T546
Test name
Test status
Simulation time 8979535515 ps
CPU time 24.37 seconds
Started Aug 02 04:42:50 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 225076 kb
Host smart-2dab7c7c-67b5-446f-9dd1-759e9b04fbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216699092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3216699092
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2583192103
Short name T552
Test name
Test status
Simulation time 1032264347 ps
CPU time 8 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:54 PM PDT 24
Peak memory 234532 kb
Host smart-8ee1b057-030c-406c-a44e-bdf52bfb35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583192103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2583192103
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2167724837
Short name T36
Test name
Test status
Simulation time 21934605 ps
CPU time 1.04 seconds
Started Aug 02 04:42:48 PM PDT 24
Finished Aug 02 04:42:49 PM PDT 24
Peak memory 217108 kb
Host smart-554623a2-54c6-4a1a-8f9d-71a41d80e3cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167724837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2167724837
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.917834990
Short name T839
Test name
Test status
Simulation time 7085928395 ps
CPU time 11.41 seconds
Started Aug 02 04:43:58 PM PDT 24
Finished Aug 02 04:44:10 PM PDT 24
Peak memory 225140 kb
Host smart-bc1bd51a-25e7-4a2c-85e3-fcbd52101755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917834990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
917834990
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.72615766
Short name T73
Test name
Test status
Simulation time 34480517836 ps
CPU time 19.81 seconds
Started Aug 02 04:42:47 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 233336 kb
Host smart-908632b2-960b-475a-9cac-d619d29f3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72615766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.72615766
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2601094527
Short name T25
Test name
Test status
Simulation time 130917495 ps
CPU time 4.72 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:02 PM PDT 24
Peak memory 223488 kb
Host smart-ca0e8ce6-2d8a-4c24-bded-e3182d8d05f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2601094527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2601094527
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.693781814
Short name T16
Test name
Test status
Simulation time 116785067 ps
CPU time 1.17 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:42:58 PM PDT 24
Peak memory 237000 kb
Host smart-d78fba07-95fa-424e-a1ba-01889d915c77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693781814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.693781814
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1795678935
Short name T19
Test name
Test status
Simulation time 13716341049 ps
CPU time 187.73 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 263732 kb
Host smart-625174c2-9fa7-40ee-ac79-8a60afd8b46a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795678935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1795678935
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3857212920
Short name T795
Test name
Test status
Simulation time 926252935 ps
CPU time 10.86 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 216992 kb
Host smart-d7bcf756-e3a4-4f2a-9389-2587949a556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857212920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3857212920
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.451800180
Short name T4
Test name
Test status
Simulation time 289950999 ps
CPU time 1.68 seconds
Started Aug 02 04:42:52 PM PDT 24
Finished Aug 02 04:42:53 PM PDT 24
Peak memory 208416 kb
Host smart-1f37900b-76e5-49c4-8b50-c305a12bd8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451800180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.451800180
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4150907064
Short name T309
Test name
Test status
Simulation time 75084271 ps
CPU time 0.98 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 208476 kb
Host smart-a451a659-9281-46fe-a741-d801bdffe1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150907064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4150907064
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2588870654
Short name T396
Test name
Test status
Simulation time 45546418 ps
CPU time 0.8 seconds
Started Aug 02 04:42:47 PM PDT 24
Finished Aug 02 04:42:48 PM PDT 24
Peak memory 206400 kb
Host smart-fe28824e-427a-4b3e-8956-feb362fb296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588870654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2588870654
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2908103877
Short name T535
Test name
Test status
Simulation time 3627670779 ps
CPU time 13.23 seconds
Started Aug 02 04:42:54 PM PDT 24
Finished Aug 02 04:43:08 PM PDT 24
Peak memory 233404 kb
Host smart-49660061-8226-4c5d-af51-90edcd928751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908103877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2908103877
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2313814291
Short name T332
Test name
Test status
Simulation time 39957066 ps
CPU time 0.68 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:01 PM PDT 24
Peak memory 205160 kb
Host smart-17ed83cb-8fd3-4e12-a403-29ef6427181d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313814291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2313814291
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.235754592
Short name T736
Test name
Test status
Simulation time 1373727044 ps
CPU time 4.04 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 233340 kb
Host smart-8a138cf8-7861-48d1-b00a-f4ed2e6724c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235754592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.235754592
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.937183309
Short name T927
Test name
Test status
Simulation time 23131450 ps
CPU time 0.8 seconds
Started Aug 02 04:43:52 PM PDT 24
Finished Aug 02 04:43:53 PM PDT 24
Peak memory 207448 kb
Host smart-a998d230-0745-45e7-b42c-558e3a9053cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937183309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.937183309
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.933426775
Short name T41
Test name
Test status
Simulation time 3162255276 ps
CPU time 36.61 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 257292 kb
Host smart-747a8fe5-eadc-4296-b8f5-0582b634fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933426775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.933426775
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.33702622
Short name T2
Test name
Test status
Simulation time 4686767677 ps
CPU time 25.08 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:25 PM PDT 24
Peak memory 225284 kb
Host smart-6da4bbfe-f20d-45ec-a206-ac983b005292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33702622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.33702622
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2980768021
Short name T221
Test name
Test status
Simulation time 17164646905 ps
CPU time 89.87 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 265844 kb
Host smart-bda9c531-9a9f-4fee-a2af-6065de822460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980768021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2980768021
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1014094423
Short name T320
Test name
Test status
Simulation time 77471525 ps
CPU time 1.92 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:02 PM PDT 24
Peak memory 224388 kb
Host smart-19657f6c-fdc3-47e4-8c20-da03e806c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014094423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1014094423
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4166996339
Short name T996
Test name
Test status
Simulation time 819042569 ps
CPU time 17.01 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:44:18 PM PDT 24
Peak memory 249792 kb
Host smart-cd664ec2-24f3-434b-b7df-3e95d0038530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166996339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4166996339
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2847466356
Short name T252
Test name
Test status
Simulation time 4246870337 ps
CPU time 6.02 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 236860 kb
Host smart-aacf5aab-3419-4880-93e1-4b94b619c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847466356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2847466356
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2036178570
Short name T991
Test name
Test status
Simulation time 1907522164 ps
CPU time 4.32 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 225196 kb
Host smart-6802058e-9b0a-40c6-b3b3-8f090bdd163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036178570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2036178570
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1109824677
Short name T1005
Test name
Test status
Simulation time 10727154633 ps
CPU time 13.29 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:44:16 PM PDT 24
Peak memory 219516 kb
Host smart-3431b50e-d19e-4a65-810d-6b8ae2c18bbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109824677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1109824677
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.502396299
Short name T312
Test name
Test status
Simulation time 4382070873 ps
CPU time 80.95 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 249616 kb
Host smart-b98a4cc4-6662-4d7a-a784-113123f3fef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502396299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.502396299
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2434980653
Short name T854
Test name
Test status
Simulation time 11820794172 ps
CPU time 41.03 seconds
Started Aug 02 04:43:48 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 216912 kb
Host smart-5d8cff7f-4a25-45bc-8494-03962294c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434980653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2434980653
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2349822389
Short name T850
Test name
Test status
Simulation time 11343269532 ps
CPU time 7.78 seconds
Started Aug 02 04:43:53 PM PDT 24
Finished Aug 02 04:44:01 PM PDT 24
Peak memory 216928 kb
Host smart-14f4dcfe-2f9f-4c28-a73e-de3caefc2506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349822389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2349822389
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2918478536
Short name T393
Test name
Test status
Simulation time 1441083090 ps
CPU time 1.85 seconds
Started Aug 02 04:44:00 PM PDT 24
Finished Aug 02 04:44:02 PM PDT 24
Peak memory 216848 kb
Host smart-9fb12a9c-c9f9-48e2-b8e3-f29779a0e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918478536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2918478536
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1456346058
Short name T624
Test name
Test status
Simulation time 95231468 ps
CPU time 0.87 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:44:02 PM PDT 24
Peak memory 206316 kb
Host smart-7cc75bef-f6e1-42ae-9736-fb591c0f9ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456346058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1456346058
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1158107016
Short name T766
Test name
Test status
Simulation time 153346953 ps
CPU time 2.52 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 236944 kb
Host smart-dd5854ee-a4d9-49e6-a01b-b011648016df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158107016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1158107016
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.61496810
Short name T971
Test name
Test status
Simulation time 41832311 ps
CPU time 0.71 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:03 PM PDT 24
Peak memory 206116 kb
Host smart-eaad6082-97c3-4a79-bb0f-ba6699bd847b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61496810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.61496810
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.226795245
Short name T1009
Test name
Test status
Simulation time 744152399 ps
CPU time 2.96 seconds
Started Aug 02 04:44:08 PM PDT 24
Finished Aug 02 04:44:11 PM PDT 24
Peak memory 233320 kb
Host smart-9077e51a-be40-4575-91c4-cd3f935873e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226795245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.226795245
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2407213461
Short name T851
Test name
Test status
Simulation time 31242609 ps
CPU time 0.78 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 206900 kb
Host smart-0df72cec-4f04-449d-ac31-bd91a312cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407213461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2407213461
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1381311138
Short name T10
Test name
Test status
Simulation time 715167410004 ps
CPU time 261.1 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 273428 kb
Host smart-2db01a38-3ff4-4866-aec6-94c67b36f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381311138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1381311138
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1533598149
Short name T256
Test name
Test status
Simulation time 90074286165 ps
CPU time 126.78 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:46:07 PM PDT 24
Peak memory 268408 kb
Host smart-94e2a54e-9465-4d52-bf5f-9a9a49c42045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533598149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1533598149
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1502203688
Short name T291
Test name
Test status
Simulation time 6593662098 ps
CPU time 26.31 seconds
Started Aug 02 04:44:07 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 240868 kb
Host smart-faf2ff56-575f-4136-a01b-5da1f42c7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502203688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1502203688
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.766791860
Short name T185
Test name
Test status
Simulation time 1202382521 ps
CPU time 9.62 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:15 PM PDT 24
Peak memory 238884 kb
Host smart-eb44b925-16b2-4504-ac2b-f2fbccecd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766791860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.766791860
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4101272261
Short name T529
Test name
Test status
Simulation time 698782761 ps
CPU time 9.27 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:11 PM PDT 24
Peak memory 233428 kb
Host smart-c7f84a62-572a-4218-aab9-1601424d4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101272261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4101272261
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1808175650
Short name T711
Test name
Test status
Simulation time 105521865 ps
CPU time 2.91 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 233280 kb
Host smart-4bd267f3-d175-45c9-b467-376974c15cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808175650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1808175650
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2586961992
Short name T547
Test name
Test status
Simulation time 1967104466 ps
CPU time 9.13 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:13 PM PDT 24
Peak memory 233312 kb
Host smart-e54f192c-6d51-4167-87d7-c6e0d7ea83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586961992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2586961992
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3860950475
Short name T730
Test name
Test status
Simulation time 1951856950 ps
CPU time 10.44 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:15 PM PDT 24
Peak memory 225096 kb
Host smart-3c8cb283-e9fd-4dc2-a9eb-6fe9aca7dfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860950475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3860950475
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.133330313
Short name T500
Test name
Test status
Simulation time 4206459756 ps
CPU time 7.49 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:10 PM PDT 24
Peak memory 221320 kb
Host smart-555bd023-2f38-42e2-8a1e-634b59790872
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133330313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.133330313
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1169877308
Short name T591
Test name
Test status
Simulation time 13128771397 ps
CPU time 78.68 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 251528 kb
Host smart-2c9bc9c2-758a-4cd9-a997-0030dc996178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169877308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1169877308
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.279432109
Short name T903
Test name
Test status
Simulation time 470206709 ps
CPU time 5.38 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:09 PM PDT 24
Peak memory 216936 kb
Host smart-97bdc3f1-ab73-41ab-b2c1-319b25efd023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279432109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.279432109
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1455668523
Short name T327
Test name
Test status
Simulation time 3857102211 ps
CPU time 4.33 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 216796 kb
Host smart-d5ecb8a9-5199-4ce9-8718-3e08c7d5f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455668523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1455668523
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3859100786
Short name T1014
Test name
Test status
Simulation time 145175549 ps
CPU time 2.39 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 216888 kb
Host smart-83973244-e9fc-4134-b52a-0867115c34ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859100786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3859100786
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1713805381
Short name T443
Test name
Test status
Simulation time 310841088 ps
CPU time 0.82 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 206556 kb
Host smart-b26ab97b-92ca-422b-9b49-e75bbe2cf20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713805381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1713805381
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2969390762
Short name T941
Test name
Test status
Simulation time 585850996 ps
CPU time 2.53 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:44:03 PM PDT 24
Peak memory 225060 kb
Host smart-2b96d8db-8cbd-4dab-a096-047c5dc4d58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969390762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2969390762
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1306489817
Short name T865
Test name
Test status
Simulation time 14574335 ps
CPU time 0.74 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:05 PM PDT 24
Peak memory 206276 kb
Host smart-a20e6a8a-d05a-478e-b6d1-a393aa36b542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306489817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1306489817
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4069653344
Short name T682
Test name
Test status
Simulation time 37049221 ps
CPU time 2.4 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:07 PM PDT 24
Peak memory 233212 kb
Host smart-e81ee256-f3da-494a-8b9a-bda571966c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069653344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4069653344
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3248073188
Short name T520
Test name
Test status
Simulation time 193178387 ps
CPU time 0.82 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:44:07 PM PDT 24
Peak memory 207192 kb
Host smart-1b392411-216c-4bb1-afcb-682d702c50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248073188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3248073188
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1741404930
Short name T917
Test name
Test status
Simulation time 23310383792 ps
CPU time 98.35 seconds
Started Aug 02 04:44:01 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 249752 kb
Host smart-587a55fd-e0c0-4a03-9dde-3c1af7e78a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741404930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1741404930
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3190611050
Short name T231
Test name
Test status
Simulation time 4407585929 ps
CPU time 32.73 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 249832 kb
Host smart-3ebd7f86-0d60-4668-8564-0493b1050741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190611050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3190611050
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3481128049
Short name T844
Test name
Test status
Simulation time 4492498300 ps
CPU time 66.85 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 249832 kb
Host smart-fcfb6163-e3ce-45ac-92ae-e681d179b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481128049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3481128049
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.192880116
Short name T483
Test name
Test status
Simulation time 584281745 ps
CPU time 4.86 seconds
Started Aug 02 04:44:08 PM PDT 24
Finished Aug 02 04:44:13 PM PDT 24
Peak memory 225112 kb
Host smart-778d09b2-ca72-4d86-93e3-25e740b85488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192880116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.192880116
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2270671653
Short name T975
Test name
Test status
Simulation time 857713921 ps
CPU time 23.62 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:29 PM PDT 24
Peak memory 237912 kb
Host smart-732d0c6b-bcf6-480e-854c-f50195a68439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270671653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2270671653
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3317253000
Short name T771
Test name
Test status
Simulation time 3552737439 ps
CPU time 8.12 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:44:14 PM PDT 24
Peak memory 225248 kb
Host smart-f9a80cd6-cdff-4e37-872f-1625ec43a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317253000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3317253000
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.150442239
Short name T641
Test name
Test status
Simulation time 6139424890 ps
CPU time 21.19 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:23 PM PDT 24
Peak memory 233424 kb
Host smart-9e3eb72d-4248-471c-aae9-ae222a772751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150442239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.150442239
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3312791724
Short name T465
Test name
Test status
Simulation time 1046161082 ps
CPU time 6.42 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:11 PM PDT 24
Peak memory 233504 kb
Host smart-7900c9e5-e586-4e75-aaf1-c235c97073f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312791724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3312791724
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2382937837
Short name T896
Test name
Test status
Simulation time 10811939228 ps
CPU time 10.92 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:15 PM PDT 24
Peak memory 225296 kb
Host smart-dce7b37c-7471-4a6b-85c2-44b4eb50882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382937837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2382937837
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.419869447
Short name T515
Test name
Test status
Simulation time 82617214 ps
CPU time 3.78 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 223472 kb
Host smart-eaa42c75-119b-4779-a7e9-e2a1e98926f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419869447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.419869447
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3712134943
Short name T52
Test name
Test status
Simulation time 88276054391 ps
CPU time 764.33 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 285592 kb
Host smart-74c5118e-581e-49a1-acf7-1065712d831a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712134943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3712134943
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.868399824
Short name T380
Test name
Test status
Simulation time 546396655 ps
CPU time 4.85 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 216940 kb
Host smart-8591e11c-0da4-40e1-8d80-1e0ec2785d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868399824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.868399824
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2429663265
Short name T339
Test name
Test status
Simulation time 5221217074 ps
CPU time 4.67 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 216920 kb
Host smart-b6a42390-5e52-4701-b3f3-6a2f1cf9f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429663265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2429663265
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3735889566
Short name T7
Test name
Test status
Simulation time 79368040 ps
CPU time 1.23 seconds
Started Aug 02 04:44:02 PM PDT 24
Finished Aug 02 04:44:03 PM PDT 24
Peak memory 208452 kb
Host smart-6525e506-1d0c-4255-a3e4-b07a56755b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735889566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3735889566
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.427411761
Short name T596
Test name
Test status
Simulation time 182313130 ps
CPU time 0.79 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:44:04 PM PDT 24
Peak memory 206452 kb
Host smart-1346833e-a892-4d69-ae15-fee405998e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427411761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.427411761
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1263036155
Short name T866
Test name
Test status
Simulation time 154670943 ps
CPU time 2.17 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:06 PM PDT 24
Peak memory 223884 kb
Host smart-43ae2d5e-cf24-4c75-b948-e0df9eab4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263036155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1263036155
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2707753560
Short name T704
Test name
Test status
Simulation time 40256246 ps
CPU time 0.71 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 205184 kb
Host smart-f1636988-a7d8-45af-b6b0-542063018e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707753560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2707753560
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3869721008
Short name T566
Test name
Test status
Simulation time 205621607 ps
CPU time 3.75 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:09 PM PDT 24
Peak memory 225040 kb
Host smart-f28dc31f-e033-4203-8fd7-2c36b9ee3835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869721008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3869721008
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.257874255
Short name T671
Test name
Test status
Simulation time 33279394 ps
CPU time 0.79 seconds
Started Aug 02 04:44:07 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 206864 kb
Host smart-9684af2e-318d-44f9-808c-324b7931307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257874255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.257874255
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3097076207
Short name T664
Test name
Test status
Simulation time 56073289750 ps
CPU time 378.64 seconds
Started Aug 02 04:44:03 PM PDT 24
Finished Aug 02 04:50:22 PM PDT 24
Peak memory 265908 kb
Host smart-f781e3ee-b05f-4974-8a64-b2c218b1e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097076207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3097076207
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.220471873
Short name T650
Test name
Test status
Simulation time 11181052387 ps
CPU time 89.27 seconds
Started Aug 02 04:44:14 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 253968 kb
Host smart-03550de6-d1a2-4cff-afc7-85404aff5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220471873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.220471873
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3849136683
Short name T44
Test name
Test status
Simulation time 21122713445 ps
CPU time 212.83 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 257460 kb
Host smart-9de23a44-d5f5-46c8-8684-c2f404a7d756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849136683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3849136683
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2162306221
Short name T58
Test name
Test status
Simulation time 1979164083 ps
CPU time 19.9 seconds
Started Aug 02 04:44:08 PM PDT 24
Finished Aug 02 04:44:28 PM PDT 24
Peak memory 233384 kb
Host smart-13ebfb5e-9686-426f-aad8-a5941c700105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162306221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2162306221
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1484139965
Short name T364
Test name
Test status
Simulation time 4703069086 ps
CPU time 25.86 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 239680 kb
Host smart-986d5072-4cae-4b8e-ad05-042546fddc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484139965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1484139965
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3489940621
Short name T756
Test name
Test status
Simulation time 579820830 ps
CPU time 7.62 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:12 PM PDT 24
Peak memory 233360 kb
Host smart-838f22cd-2daa-493d-bff3-da8a33a29ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489940621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3489940621
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3859694220
Short name T494
Test name
Test status
Simulation time 269891498 ps
CPU time 5.93 seconds
Started Aug 02 04:44:09 PM PDT 24
Finished Aug 02 04:44:15 PM PDT 24
Peak memory 225188 kb
Host smart-0a98ed22-cc25-4fdb-87f3-1131c121d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859694220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3859694220
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2660448352
Short name T651
Test name
Test status
Simulation time 19834328754 ps
CPU time 14.02 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:18 PM PDT 24
Peak memory 233388 kb
Host smart-a6213436-1a92-47f4-a35f-a6e9b22982b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660448352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2660448352
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3693112056
Short name T655
Test name
Test status
Simulation time 375817193 ps
CPU time 7.46 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:44:13 PM PDT 24
Peak memory 233312 kb
Host smart-14d0fd03-02b3-49e6-80f3-8b712506ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693112056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3693112056
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3773397425
Short name T510
Test name
Test status
Simulation time 974809147 ps
CPU time 9.53 seconds
Started Aug 02 04:44:05 PM PDT 24
Finished Aug 02 04:44:14 PM PDT 24
Peak memory 219800 kb
Host smart-58ae2d62-a1c8-4273-9b26-18feba1e036f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773397425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3773397425
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4073337831
Short name T513
Test name
Test status
Simulation time 8514035730 ps
CPU time 12.6 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:17 PM PDT 24
Peak memory 216836 kb
Host smart-a48ffadc-b9de-466e-9b21-cfda4f297fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073337831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4073337831
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3411307843
Short name T446
Test name
Test status
Simulation time 4109597822 ps
CPU time 10.8 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:15 PM PDT 24
Peak memory 216884 kb
Host smart-d4977af4-c605-4df0-9d34-8a2d6e8873f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411307843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3411307843
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1339162204
Short name T391
Test name
Test status
Simulation time 23298415 ps
CPU time 0.91 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:44:07 PM PDT 24
Peak memory 207144 kb
Host smart-7737c43a-e67c-43f3-848d-2278f1d619db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339162204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1339162204
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2948458068
Short name T827
Test name
Test status
Simulation time 47998697 ps
CPU time 0.86 seconds
Started Aug 02 04:44:06 PM PDT 24
Finished Aug 02 04:44:07 PM PDT 24
Peak memory 206376 kb
Host smart-cf481d9b-31c7-4da6-bf12-105550ac47f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948458068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2948458068
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.875016322
Short name T549
Test name
Test status
Simulation time 14958576340 ps
CPU time 27.95 seconds
Started Aug 02 04:44:04 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 233384 kb
Host smart-4a58c202-ea12-4cfc-8991-db2553eb1a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875016322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.875016322
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2455880650
Short name T657
Test name
Test status
Simulation time 62049628 ps
CPU time 0.7 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 205172 kb
Host smart-903e775f-3310-4ea0-bd6d-df93a78bac11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455880650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2455880650
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2030498146
Short name T681
Test name
Test status
Simulation time 338449662 ps
CPU time 6.7 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 225048 kb
Host smart-4cadcb13-7666-408b-aea7-e00db15cc0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030498146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2030498146
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3179610999
Short name T897
Test name
Test status
Simulation time 36951755 ps
CPU time 0.75 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:31 PM PDT 24
Peak memory 206228 kb
Host smart-bba7d847-dd93-49a7-9f77-d6c98c9733a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179610999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3179610999
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3134117190
Short name T219
Test name
Test status
Simulation time 7826425449 ps
CPU time 78.33 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 257724 kb
Host smart-1ad01fc8-6838-4770-aa70-b1118da79bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134117190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3134117190
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1415756570
Short name T801
Test name
Test status
Simulation time 5762938721 ps
CPU time 54.54 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:45:26 PM PDT 24
Peak memory 257764 kb
Host smart-10e311c4-11c8-4d5c-8110-dffbb3d3f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415756570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1415756570
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2797093765
Short name T456
Test name
Test status
Simulation time 253691120 ps
CPU time 3.67 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 225068 kb
Host smart-9205161d-b23f-4b51-8035-12af5556c60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797093765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2797093765
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1324192650
Short name T679
Test name
Test status
Simulation time 8082967888 ps
CPU time 22.72 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 225252 kb
Host smart-bfce91cd-030e-45dd-8416-5d7786a4ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324192650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1324192650
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1268052185
Short name T72
Test name
Test status
Simulation time 125119311 ps
CPU time 2.22 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 227468 kb
Host smart-3149ad56-e0dd-4bd2-9ec7-40d16cef6b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268052185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1268052185
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.462303304
Short name T913
Test name
Test status
Simulation time 2904062749 ps
CPU time 6.29 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 225068 kb
Host smart-31948d92-8d65-442d-8809-3d62ce847e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462303304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.462303304
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2375783265
Short name T263
Test name
Test status
Simulation time 10038155567 ps
CPU time 10.52 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 233384 kb
Host smart-70f736fa-c54b-428d-a6de-37781e5f2071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375783265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2375783265
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1860488151
Short name T895
Test name
Test status
Simulation time 4820732985 ps
CPU time 12.88 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 220880 kb
Host smart-da6b09cb-342e-41c0-b4ae-81cf2aea1ed0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860488151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1860488151
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1692174925
Short name T861
Test name
Test status
Simulation time 67361684792 ps
CPU time 78.43 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 273552 kb
Host smart-61c9b479-723f-44a4-99b8-2fbdbe8a1600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692174925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1692174925
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.638380616
Short name T615
Test name
Test status
Simulation time 14707801147 ps
CPU time 38.51 seconds
Started Aug 02 04:44:27 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 216868 kb
Host smart-c4c9e873-50a0-4be9-a9c2-81f7d50519a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638380616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.638380616
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3049020237
Short name T388
Test name
Test status
Simulation time 1993866526 ps
CPU time 7.07 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:38 PM PDT 24
Peak memory 216792 kb
Host smart-e29f3c73-d0cc-4091-9a4b-45fe3a023579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049020237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3049020237
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3810475115
Short name T493
Test name
Test status
Simulation time 122035063 ps
CPU time 1.65 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:31 PM PDT 24
Peak memory 216812 kb
Host smart-85db477d-2625-4590-80cd-737ec1cca6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810475115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3810475115
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.519357484
Short name T381
Test name
Test status
Simulation time 399024957 ps
CPU time 0.99 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 207516 kb
Host smart-512a01f8-531c-4072-8ed2-10f8784f7f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519357484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.519357484
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1861090125
Short name T892
Test name
Test status
Simulation time 722187230 ps
CPU time 3.7 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 233328 kb
Host smart-e7cf0b70-636d-4c08-a092-3f026491a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861090125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1861090125
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2901217433
Short name T853
Test name
Test status
Simulation time 24020975 ps
CPU time 0.77 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 205840 kb
Host smart-950d66e6-b303-4e64-9790-3a69945a6d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901217433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2901217433
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3991947605
Short name T349
Test name
Test status
Simulation time 923278377 ps
CPU time 7.07 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 225084 kb
Host smart-54a04a8b-64b9-449b-a03f-8e3c162f16bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991947605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3991947605
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1178108461
Short name T366
Test name
Test status
Simulation time 17670182 ps
CPU time 0.77 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 207320 kb
Host smart-6944d0e5-3830-4019-a278-f065b66b1b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178108461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1178108461
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.666289451
Short name T781
Test name
Test status
Simulation time 47463075 ps
CPU time 0.79 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 217332 kb
Host smart-10a0369d-47cb-40eb-83cc-df8a2b743865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666289451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.666289451
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2248267501
Short name T639
Test name
Test status
Simulation time 14333747118 ps
CPU time 99.15 seconds
Started Aug 02 04:44:37 PM PDT 24
Finished Aug 02 04:46:17 PM PDT 24
Peak memory 273172 kb
Host smart-b13b6409-22cb-40d3-9588-c2ea608cfce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248267501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2248267501
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.957022383
Short name T906
Test name
Test status
Simulation time 538082263 ps
CPU time 10.38 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:46 PM PDT 24
Peak memory 225172 kb
Host smart-da5570fd-918b-461b-8594-91b20b19a586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957022383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.957022383
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.97049832
Short name T921
Test name
Test status
Simulation time 13131920456 ps
CPU time 45.35 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:19 PM PDT 24
Peak memory 249780 kb
Host smart-b16f0d14-e751-4128-82ec-b4a7f2217dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97049832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.97049832
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.959172409
Short name T654
Test name
Test status
Simulation time 180038421 ps
CPU time 3.91 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 225148 kb
Host smart-f056f2dd-6a7a-4660-839a-4affe7cca49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959172409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.959172409
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1955782726
Short name T732
Test name
Test status
Simulation time 7104522824 ps
CPU time 25.9 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 233408 kb
Host smart-d582bef1-fb64-473e-ac87-8011ea504c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955782726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1955782726
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.909988280
Short name T737
Test name
Test status
Simulation time 8417735633 ps
CPU time 7.15 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 225252 kb
Host smart-379a6bb1-989a-4623-a90d-11b856ec7b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909988280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.909988280
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.775656082
Short name T243
Test name
Test status
Simulation time 100615650 ps
CPU time 2.56 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 233396 kb
Host smart-8b903235-a901-4b9c-a749-24f7a95c54b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775656082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.775656082
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.381178272
Short name T902
Test name
Test status
Simulation time 800910184 ps
CPU time 13.09 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 220596 kb
Host smart-c69b18d4-40df-42d9-af01-12225a923cd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381178272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.381178272
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1298377707
Short name T53
Test name
Test status
Simulation time 73905588007 ps
CPU time 328.38 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:50:06 PM PDT 24
Peak memory 258000 kb
Host smart-ba2a0cfa-c20d-4942-bab4-9e5b7542e65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298377707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1298377707
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2008630223
Short name T788
Test name
Test status
Simulation time 3225348149 ps
CPU time 4.82 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 216836 kb
Host smart-94ca87dd-8ea4-4cd0-abe6-32fedce4cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008630223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2008630223
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3159950181
Short name T724
Test name
Test status
Simulation time 5976491686 ps
CPU time 16.23 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 216752 kb
Host smart-bac2451b-091d-4095-8494-e4d89305fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159950181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3159950181
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2904252380
Short name T966
Test name
Test status
Simulation time 58492112 ps
CPU time 0.71 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 205980 kb
Host smart-044a2176-5ed6-419b-9388-829e11053e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904252380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2904252380
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1301099385
Short name T390
Test name
Test status
Simulation time 373143423 ps
CPU time 0.84 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 206560 kb
Host smart-642502ee-8982-4216-8876-eca7ce5c849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301099385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1301099385
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1410321882
Short name T676
Test name
Test status
Simulation time 340240362 ps
CPU time 5.67 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 225176 kb
Host smart-719e12a6-5ae7-48b6-82c8-14c52aff2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410321882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1410321882
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2941945729
Short name T786
Test name
Test status
Simulation time 21551449 ps
CPU time 0.73 seconds
Started Aug 02 04:44:28 PM PDT 24
Finished Aug 02 04:44:29 PM PDT 24
Peak memory 205736 kb
Host smart-bc70aa87-dc6f-4bb4-8070-3ee3d0ba2aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941945729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2941945729
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2497059719
Short name T735
Test name
Test status
Simulation time 997930969 ps
CPU time 4.38 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 233292 kb
Host smart-04c91232-337d-4d9e-a2b5-0d6b58822864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497059719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2497059719
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3424136033
Short name T668
Test name
Test status
Simulation time 17329674 ps
CPU time 0.82 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 206952 kb
Host smart-52dc87d1-84bb-493f-8a41-51b81c84cc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424136033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3424136033
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3879923811
Short name T215
Test name
Test status
Simulation time 156990874050 ps
CPU time 311.67 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:49:44 PM PDT 24
Peak memory 266860 kb
Host smart-17411b20-ee17-44c4-888e-2485538d7abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879923811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3879923811
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2473207027
Short name T524
Test name
Test status
Simulation time 1476990772 ps
CPU time 17.51 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 222568 kb
Host smart-c7b827ef-8e02-4d06-a6dd-97f690f0d6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473207027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2473207027
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.791395410
Short name T539
Test name
Test status
Simulation time 8692575217 ps
CPU time 69.23 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 251636 kb
Host smart-cf0f02c3-d2d0-49a5-a57a-41374144bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791395410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.791395410
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3139491353
Short name T533
Test name
Test status
Simulation time 1561422161 ps
CPU time 19.46 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 233360 kb
Host smart-06b4f1c0-0210-4495-aa24-57838856a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139491353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3139491353
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.189212569
Short name T184
Test name
Test status
Simulation time 56377393929 ps
CPU time 51.69 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:45:22 PM PDT 24
Peak memory 249060 kb
Host smart-5f4b45ce-a3c9-4b8b-8742-7d28aae03468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189212569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.189212569
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2550654151
Short name T140
Test name
Test status
Simulation time 181268723 ps
CPU time 2.49 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 233332 kb
Host smart-da51e9da-4e19-4ed5-9a19-270e668019b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550654151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2550654151
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2334905598
Short name T323
Test name
Test status
Simulation time 80176138 ps
CPU time 2.21 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 223604 kb
Host smart-36d27fb3-74aa-49c6-95b1-8950b58cf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334905598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2334905598
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2111139774
Short name T286
Test name
Test status
Simulation time 8434003099 ps
CPU time 18.12 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 249440 kb
Host smart-a491d82c-c95c-44f1-a3da-936243ccd926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111139774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2111139774
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3703932149
Short name T420
Test name
Test status
Simulation time 17222396206 ps
CPU time 13.68 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 241136 kb
Host smart-93231166-a13c-41be-963c-b16f7496313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703932149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3703932149
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4243667159
Short name T363
Test name
Test status
Simulation time 5282198218 ps
CPU time 12.48 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 223716 kb
Host smart-dae07f4f-5c87-4a9f-a856-99f94e2c9ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243667159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4243667159
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2835958238
Short name T678
Test name
Test status
Simulation time 39206529637 ps
CPU time 64.28 seconds
Started Aug 02 04:44:27 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 264432 kb
Host smart-9e14fb48-0d8a-487c-b59a-5151c185446a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835958238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2835958238
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.194971586
Short name T451
Test name
Test status
Simulation time 11135600419 ps
CPU time 16.4 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:50 PM PDT 24
Peak memory 217000 kb
Host smart-0c99e273-14b6-4103-94a7-08388319ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194971586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.194971586
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.653212048
Short name T770
Test name
Test status
Simulation time 108966710 ps
CPU time 1.31 seconds
Started Aug 02 04:44:40 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 208344 kb
Host smart-ffa91ec9-aa2b-4bea-af9d-0091b10139d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653212048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.653212048
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2759853877
Short name T763
Test name
Test status
Simulation time 38160946 ps
CPU time 0.85 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:38 PM PDT 24
Peak memory 207328 kb
Host smart-1f3f78fc-ddcb-4f34-9f7e-ec1b4838f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759853877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2759853877
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.295918727
Short name T518
Test name
Test status
Simulation time 359629856 ps
CPU time 0.94 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 206456 kb
Host smart-952cfa32-b0e3-4d7c-b812-2ddfaff5e40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295918727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.295918727
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.63118271
Short name T414
Test name
Test status
Simulation time 2826818483 ps
CPU time 4.04 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 225224 kb
Host smart-36f4a9b3-e8e4-47f2-8227-7be570a96ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63118271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.63118271
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3561387408
Short name T424
Test name
Test status
Simulation time 13692183 ps
CPU time 0.75 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 205208 kb
Host smart-91150d89-6c38-4cfd-8bbd-dba66ee6144f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561387408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3561387408
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3023388832
Short name T785
Test name
Test status
Simulation time 165992269 ps
CPU time 2.97 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 225120 kb
Host smart-0a1b2f5d-996d-498f-acae-2aaa7a81969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023388832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3023388832
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1317994934
Short name T723
Test name
Test status
Simulation time 51201083 ps
CPU time 0.76 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:31 PM PDT 24
Peak memory 206252 kb
Host smart-b7b9a85b-6a40-411c-aa20-40bc056b5003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317994934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1317994934
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3812893635
Short name T589
Test name
Test status
Simulation time 9209344387 ps
CPU time 66.5 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 251964 kb
Host smart-3495cd21-3f72-4664-83cf-0a432907d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812893635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3812893635
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3437594676
Short name T43
Test name
Test status
Simulation time 15476650001 ps
CPU time 56.19 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 237668 kb
Host smart-d6cfcfd9-1aa8-4475-9873-d84d07acbda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437594676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3437594676
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.251561493
Short name T949
Test name
Test status
Simulation time 4104894681 ps
CPU time 77.49 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 265208 kb
Host smart-3cbad68b-10a7-4029-8f94-e28060256540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251561493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.251561493
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2736098709
Short name T929
Test name
Test status
Simulation time 330822363 ps
CPU time 8.75 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 233352 kb
Host smart-6e5dc4d8-7ad7-4c68-a745-9554697200b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736098709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2736098709
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.940084581
Short name T883
Test name
Test status
Simulation time 3544308964 ps
CPU time 77.94 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 256436 kb
Host smart-81feb1fe-01e5-49a6-bc7c-3e50cbebef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940084581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.940084581
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1192507779
Short name T734
Test name
Test status
Simulation time 135887544 ps
CPU time 2.64 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 225072 kb
Host smart-6d66aafd-5781-47e7-b274-000445ac1cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192507779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1192507779
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2432230759
Short name T836
Test name
Test status
Simulation time 220934203 ps
CPU time 6.92 seconds
Started Aug 02 04:44:32 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 233120 kb
Host smart-3a040df6-3c2d-40d6-ad26-9e5a5e376473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432230759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2432230759
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4024619463
Short name T264
Test name
Test status
Simulation time 881926734 ps
CPU time 7.11 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 224996 kb
Host smart-e7f75bd4-ed6b-4685-94de-3a12abf1dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024619463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4024619463
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2288981135
Short name T583
Test name
Test status
Simulation time 16845672325 ps
CPU time 24.84 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 249844 kb
Host smart-b6bf15bd-eb32-4a0e-8b8a-37002fe9dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288981135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2288981135
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.431599891
Short name T992
Test name
Test status
Simulation time 10054395411 ps
CPU time 22.14 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 222760 kb
Host smart-4d79c07e-d329-45f1-ab91-6ae8fc6caffd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431599891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.431599891
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1600932275
Short name T305
Test name
Test status
Simulation time 10112089350 ps
CPU time 34.48 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 221436 kb
Host smart-abce85e4-55ed-4944-b5e6-8e3bf25b8b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600932275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1600932275
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2762919348
Short name T905
Test name
Test status
Simulation time 443094849 ps
CPU time 1.59 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 208420 kb
Host smart-bb5da1f0-7260-4240-8d43-692b0d0b96b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762919348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2762919348
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.480045479
Short name T479
Test name
Test status
Simulation time 176584731 ps
CPU time 1.31 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 216832 kb
Host smart-1b7d5815-327f-4385-904e-a21f1502b494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480045479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.480045479
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1504061011
Short name T319
Test name
Test status
Simulation time 60131131 ps
CPU time 0.72 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:34 PM PDT 24
Peak memory 206440 kb
Host smart-3405eb97-78b5-4747-9b9a-037ff508490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504061011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1504061011
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.110013730
Short name T261
Test name
Test status
Simulation time 1309768142 ps
CPU time 6.05 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 233256 kb
Host smart-851c7c93-1f42-494b-b117-2b879f8e3ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110013730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.110013730
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.434911888
Short name T804
Test name
Test status
Simulation time 88543759 ps
CPU time 0.75 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 206064 kb
Host smart-8d462e29-cb73-4eb9-ad77-ea59b7c887e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434911888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.434911888
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1507886817
Short name T188
Test name
Test status
Simulation time 143621297 ps
CPU time 2.67 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 233248 kb
Host smart-9e90ef7a-5bc0-43b0-a3a9-c8149131414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507886817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1507886817
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2139347716
Short name T924
Test name
Test status
Simulation time 32357743 ps
CPU time 0.8 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 206960 kb
Host smart-39e97fbf-8d6c-4a74-9a04-4e8ead6d313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139347716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2139347716
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2597792898
Short name T762
Test name
Test status
Simulation time 1667750768 ps
CPU time 10.23 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 237312 kb
Host smart-20a279e6-bef5-48f6-9eaa-c06331753e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597792898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2597792898
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1153321292
Short name T301
Test name
Test status
Simulation time 32814606060 ps
CPU time 75.66 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 241720 kb
Host smart-5099dd58-7b4f-4863-818b-fbe28798b9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153321292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1153321292
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3132474759
Short name T417
Test name
Test status
Simulation time 16571431170 ps
CPU time 144.76 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 250928 kb
Host smart-a13a91c8-672f-4943-80dd-b0843cf0ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132474759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3132474759
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2046974562
Short name T336
Test name
Test status
Simulation time 392969472 ps
CPU time 4 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 225264 kb
Host smart-a0c3bbc4-b2f2-41f9-897a-7f84172c02b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046974562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2046974562
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1772762636
Short name T183
Test name
Test status
Simulation time 21430835575 ps
CPU time 172 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 256176 kb
Host smart-1a9a3494-68e9-4645-806a-aabdb240fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772762636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1772762636
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2302182830
Short name T755
Test name
Test status
Simulation time 74637872 ps
CPU time 2.25 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 225088 kb
Host smart-1f634b58-a5fa-484a-8ea7-128aa91fad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302182830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2302182830
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3235668921
Short name T644
Test name
Test status
Simulation time 4794446034 ps
CPU time 27.82 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:45:01 PM PDT 24
Peak memory 225172 kb
Host smart-660acbf2-6f8a-4cc1-b4fe-5db8bd1d5f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235668921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3235668921
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1359082583
Short name T276
Test name
Test status
Simulation time 591517320 ps
CPU time 6 seconds
Started Aug 02 04:44:37 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 233276 kb
Host smart-d894e2f7-2ef0-4b13-b0c5-a0336442655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359082583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1359082583
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2037077704
Short name T503
Test name
Test status
Simulation time 476923439 ps
CPU time 7.66 seconds
Started Aug 02 04:44:33 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 241024 kb
Host smart-1366a8e1-5cfd-43da-86e4-c4592165e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037077704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2037077704
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.397417293
Short name T908
Test name
Test status
Simulation time 965858067 ps
CPU time 8.18 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 222520 kb
Host smart-0312f238-a708-4859-8004-e9f8e2072f98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=397417293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.397417293
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2707811807
Short name T830
Test name
Test status
Simulation time 191594146 ps
CPU time 1.15 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 207528 kb
Host smart-2c5ed9ef-20d5-4cc2-839a-b507c4caf7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707811807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2707811807
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4103478865
Short name T444
Test name
Test status
Simulation time 4248116009 ps
CPU time 17.41 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 217096 kb
Host smart-28d116c8-edc5-4a20-b1ac-c967c89cf5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103478865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4103478865
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1877744794
Short name T794
Test name
Test status
Simulation time 8104380619 ps
CPU time 12.34 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 216980 kb
Host smart-c25184d9-c5b2-4d00-a563-52cf972b62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877744794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1877744794
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.608994507
Short name T845
Test name
Test status
Simulation time 2585966212 ps
CPU time 3.66 seconds
Started Aug 02 04:44:37 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 216896 kb
Host smart-a3a7530e-c392-4c75-8e22-cf56422de0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608994507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.608994507
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2587626609
Short name T401
Test name
Test status
Simulation time 63434389 ps
CPU time 0.92 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 206480 kb
Host smart-01d0b3e1-27a6-4867-9d7e-9aed22ef6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587626609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2587626609
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2032078895
Short name T752
Test name
Test status
Simulation time 92688304 ps
CPU time 2.8 seconds
Started Aug 02 04:44:36 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 233328 kb
Host smart-762dd067-b86c-4f77-87cd-93e7b877ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032078895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2032078895
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1458885274
Short name T345
Test name
Test status
Simulation time 15789095 ps
CPU time 0.76 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 205196 kb
Host smart-df16badb-d01c-4239-8f2a-ada24606cdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458885274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1458885274
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.425062279
Short name T900
Test name
Test status
Simulation time 294666168 ps
CPU time 2.9 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 225112 kb
Host smart-9f17fe13-9987-4483-9577-536e6f7c0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425062279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.425062279
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3343114238
Short name T935
Test name
Test status
Simulation time 42211980 ps
CPU time 0.74 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 205904 kb
Host smart-8284c96f-9ee5-4544-842b-a931f9734031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343114238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3343114238
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1892351110
Short name T288
Test name
Test status
Simulation time 5301186594 ps
CPU time 91.67 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:46:11 PM PDT 24
Peak memory 255036 kb
Host smart-c02b25fc-91b6-480e-b729-40870237a770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892351110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1892351110
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.750314476
Short name T674
Test name
Test status
Simulation time 12033510444 ps
CPU time 65.26 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:45:46 PM PDT 24
Peak memory 249808 kb
Host smart-a9441d9a-13fa-4598-a6a2-edc2951fc53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750314476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.750314476
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1371048502
Short name T542
Test name
Test status
Simulation time 414773241 ps
CPU time 2.65 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 225164 kb
Host smart-c52d9b5b-44fd-4695-82b2-911c173595c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371048502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1371048502
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2489574570
Short name T879
Test name
Test status
Simulation time 49046501979 ps
CPU time 83.54 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 241704 kb
Host smart-17141e85-fa87-4bb3-a5fc-f8ca896215ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489574570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2489574570
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2075911923
Short name T519
Test name
Test status
Simulation time 79435957 ps
CPU time 2.27 seconds
Started Aug 02 04:44:27 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 225364 kb
Host smart-5529d054-997a-43ef-b668-dfba2cfe910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075911923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2075911923
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.904574991
Short name T93
Test name
Test status
Simulation time 41828568205 ps
CPU time 92.25 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 233404 kb
Host smart-f7239669-52d1-4f45-b156-6a8c7d2dab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904574991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.904574991
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3973449335
Short name T758
Test name
Test status
Simulation time 727784601 ps
CPU time 7.48 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:38 PM PDT 24
Peak memory 233264 kb
Host smart-696003ba-1bd8-4091-93fe-1f2fb29f0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973449335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3973449335
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1256845427
Short name T616
Test name
Test status
Simulation time 2034176183 ps
CPU time 10.79 seconds
Started Aug 02 04:44:31 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 225296 kb
Host smart-0e9da345-0462-4470-84d1-62d4736d8f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256845427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1256845427
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2987857015
Short name T154
Test name
Test status
Simulation time 1014004257 ps
CPU time 6.77 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:41 PM PDT 24
Peak memory 220956 kb
Host smart-85aac6d5-0ce8-4f16-a115-e7cb8b1d16b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2987857015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2987857015
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3720178218
Short name T464
Test name
Test status
Simulation time 59609666 ps
CPU time 1.01 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 207408 kb
Host smart-63f1bc29-66b4-493b-af5b-4d13c6165386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720178218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3720178218
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1395867196
Short name T338
Test name
Test status
Simulation time 1293958051 ps
CPU time 2.86 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 216872 kb
Host smart-d9fd09b4-3a78-43e3-ac30-9497197fc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395867196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1395867196
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.975468876
Short name T828
Test name
Test status
Simulation time 1073958532 ps
CPU time 6.87 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 217000 kb
Host smart-eb063e77-6671-4d7b-bcdd-3ac1f21562c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975468876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.975468876
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3927279579
Short name T351
Test name
Test status
Simulation time 31724679 ps
CPU time 1.18 seconds
Started Aug 02 04:44:30 PM PDT 24
Finished Aug 02 04:44:31 PM PDT 24
Peak memory 207956 kb
Host smart-56e86703-2c1b-48e2-be9d-dfe628a090d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927279579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3927279579
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3957960835
Short name T471
Test name
Test status
Simulation time 1815325466 ps
CPU time 1.03 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 207656 kb
Host smart-fc8262cd-359a-4608-b5e0-563a710e9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957960835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3957960835
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1575216610
Short name T554
Test name
Test status
Simulation time 9324879895 ps
CPU time 30.53 seconds
Started Aug 02 04:44:29 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 233452 kb
Host smart-62fd6452-3010-4e33-bdaf-bf5e3da374e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575216610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1575216610
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3700042246
Short name T821
Test name
Test status
Simulation time 70210713 ps
CPU time 0.75 seconds
Started Aug 02 04:42:58 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 205188 kb
Host smart-08ddada1-a99e-488e-9a0a-95c98d111590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700042246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
700042246
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4150410372
Short name T576
Test name
Test status
Simulation time 45062571 ps
CPU time 2.8 seconds
Started Aug 02 04:42:58 PM PDT 24
Finished Aug 02 04:43:01 PM PDT 24
Peak memory 233376 kb
Host smart-91fa79f7-3b47-4ba7-8ec9-abfe50f73974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150410372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4150410372
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3418595190
Short name T377
Test name
Test status
Simulation time 15354732 ps
CPU time 0.78 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:42:58 PM PDT 24
Peak memory 206084 kb
Host smart-b7cc1d87-175b-4417-99a8-9df3615f2936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418595190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3418595190
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.492859404
Short name T769
Test name
Test status
Simulation time 21883334621 ps
CPU time 98.11 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:44:35 PM PDT 24
Peak memory 257012 kb
Host smart-19e6da98-28db-4f79-bafe-657d4b591f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492859404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.492859404
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.515267705
Short name T202
Test name
Test status
Simulation time 353287100373 ps
CPU time 563.98 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:52:20 PM PDT 24
Peak memory 271528 kb
Host smart-d7c797c6-1e87-4610-a576-e84fbf02d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515267705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.515267705
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1835180986
Short name T698
Test name
Test status
Simulation time 16065539402 ps
CPU time 59.75 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 249368 kb
Host smart-7c1307ec-2ae7-4026-aeab-f197153d9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835180986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1835180986
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3181167961
Short name T374
Test name
Test status
Simulation time 626174221 ps
CPU time 6.1 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:43:02 PM PDT 24
Peak memory 240620 kb
Host smart-631077d1-a7f5-45b5-a4b7-da4e39bcc89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181167961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3181167961
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3972555257
Short name T1018
Test name
Test status
Simulation time 14038521472 ps
CPU time 106.03 seconds
Started Aug 02 04:42:54 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 238520 kb
Host smart-03f2fa93-188d-48b8-826e-d2f1c718ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972555257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3972555257
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.885709045
Short name T534
Test name
Test status
Simulation time 1584455128 ps
CPU time 6.72 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:43:03 PM PDT 24
Peak memory 225104 kb
Host smart-bd564eb6-2d02-4b3e-b5ca-95099b63de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885709045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.885709045
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2559908678
Short name T329
Test name
Test status
Simulation time 321941818 ps
CPU time 6.15 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:03 PM PDT 24
Peak memory 225112 kb
Host smart-469c8205-f64d-415f-bf55-eaf61a1bfa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559908678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2559908678
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.796285397
Short name T945
Test name
Test status
Simulation time 168381877 ps
CPU time 1.02 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 218380 kb
Host smart-635a9003-5087-4766-9144-38d000cdba49
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796285397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.796285397
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1834281349
Short name T610
Test name
Test status
Simulation time 2823590796 ps
CPU time 12.09 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 237988 kb
Host smart-aee5cf84-857d-437f-be37-137da792f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834281349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1834281349
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2943656896
Short name T778
Test name
Test status
Simulation time 10474809950 ps
CPU time 6.38 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:43:01 PM PDT 24
Peak memory 225192 kb
Host smart-0cf33b8d-4d44-4b18-9b0d-42ee104b1dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943656896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2943656896
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3031663495
Short name T12
Test name
Test status
Simulation time 1094295512 ps
CPU time 6.75 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:04 PM PDT 24
Peak memory 222456 kb
Host smart-1a17a575-8399-4cd8-bc74-e50645802ab2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3031663495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3031663495
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.523774537
Short name T66
Test name
Test status
Simulation time 240386583 ps
CPU time 1.04 seconds
Started Aug 02 04:42:59 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 235888 kb
Host smart-e7cbafe9-7bc4-4797-b44f-c06292898618
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523774537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.523774537
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1227951230
Short name T602
Test name
Test status
Simulation time 7449871676 ps
CPU time 32.95 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:43:29 PM PDT 24
Peak memory 241528 kb
Host smart-aed62f2e-1bdd-40a4-8210-6aedacf988ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227951230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1227951230
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2803159167
Short name T1025
Test name
Test status
Simulation time 14418748 ps
CPU time 0.72 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 206080 kb
Host smart-4d324aaf-55b1-4e72-80d1-d2dd154820e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803159167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2803159167
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1932587151
Short name T467
Test name
Test status
Simulation time 14871168 ps
CPU time 0.73 seconds
Started Aug 02 04:42:54 PM PDT 24
Finished Aug 02 04:42:55 PM PDT 24
Peak memory 206032 kb
Host smart-1dc246bf-155b-4025-9bf7-206bbfc2bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932587151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1932587151
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3643308358
Short name T645
Test name
Test status
Simulation time 532666313 ps
CPU time 2.83 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 216828 kb
Host smart-19cf468d-116e-4db9-8056-0263aa54a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643308358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3643308358
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1683327527
Short name T666
Test name
Test status
Simulation time 1135006899 ps
CPU time 1.01 seconds
Started Aug 02 04:42:58 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 207476 kb
Host smart-9684290b-575e-4dd0-b1ce-fe68117037f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683327527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1683327527
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.25560389
Short name T789
Test name
Test status
Simulation time 660284633 ps
CPU time 6.26 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:04 PM PDT 24
Peak memory 233408 kb
Host smart-0bf7458a-dd7a-4157-b8b8-22b48d50a529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25560389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.25560389
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.156855072
Short name T700
Test name
Test status
Simulation time 79002250 ps
CPU time 0.74 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 205808 kb
Host smart-0a4ef2cc-80a0-4457-89c4-cc3fbc6e4097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156855072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.156855072
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3931426248
Short name T141
Test name
Test status
Simulation time 132387350 ps
CPU time 3.1 seconds
Started Aug 02 04:44:40 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 225084 kb
Host smart-d43be3c0-d037-432b-aded-672ae410be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931426248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3931426248
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.63497874
Short name T909
Test name
Test status
Simulation time 123232144 ps
CPU time 0.79 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 207324 kb
Host smart-722730c2-d740-4723-bdfa-1665030c07fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63497874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.63497874
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1403543873
Short name T269
Test name
Test status
Simulation time 55235999478 ps
CPU time 94.98 seconds
Started Aug 02 04:44:38 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 249876 kb
Host smart-c23e028c-c02f-437a-aa0f-e879f54619ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403543873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1403543873
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2851082150
Short name T643
Test name
Test status
Simulation time 23516788082 ps
CPU time 176.7 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 253368 kb
Host smart-7988efb6-46db-4219-ab2e-2580a33325c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851082150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2851082150
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.234267602
Short name T530
Test name
Test status
Simulation time 7719940772 ps
CPU time 62.87 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:45:47 PM PDT 24
Peak memory 234728 kb
Host smart-12e216ab-ce88-48b9-9d0c-fe40f3e526b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234267602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.234267602
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2508979394
Short name T1001
Test name
Test status
Simulation time 107955905 ps
CPU time 3.75 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 233452 kb
Host smart-8ce02e85-d577-4ae9-8a61-80801ea46555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508979394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2508979394
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1198170043
Short name T507
Test name
Test status
Simulation time 30662726769 ps
CPU time 125.88 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 252724 kb
Host smart-55919ba1-8e71-4743-aa10-27d5a1506588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198170043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1198170043
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2426982465
Short name T689
Test name
Test status
Simulation time 1112541222 ps
CPU time 10 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 233432 kb
Host smart-196cd460-1c45-47cc-8ea0-eb4b00c354fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426982465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2426982465
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.303306015
Short name T22
Test name
Test status
Simulation time 1544757612 ps
CPU time 9.32 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 225088 kb
Host smart-0106e7dc-5efa-4d95-a096-f2fca4b49ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303306015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.303306015
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2377644125
Short name T502
Test name
Test status
Simulation time 372865539 ps
CPU time 5.48 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 232696 kb
Host smart-7ab9d660-2b83-49de-98a6-5891b13705f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377644125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2377644125
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2489510673
Short name T981
Test name
Test status
Simulation time 24798940029 ps
CPU time 16.78 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:52 PM PDT 24
Peak memory 225176 kb
Host smart-2c39de09-82bd-4c7d-ba17-2f2cb2eec62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489510673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2489510673
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2877860034
Short name T335
Test name
Test status
Simulation time 408654843 ps
CPU time 3.71 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 220704 kb
Host smart-4c5cf75a-c480-44cc-baaf-92372503184d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2877860034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2877860034
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1011243866
Short name T726
Test name
Test status
Simulation time 1540797708 ps
CPU time 20.07 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:45:02 PM PDT 24
Peak memory 217176 kb
Host smart-a3809440-17d2-4139-9019-53f66cc33427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011243866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1011243866
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3912980622
Short name T642
Test name
Test status
Simulation time 2563542985 ps
CPU time 11.33 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:52 PM PDT 24
Peak memory 216944 kb
Host smart-76a7e4a9-7864-4f3f-a237-d66ad4401305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912980622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3912980622
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2549489337
Short name T695
Test name
Test status
Simulation time 95425698 ps
CPU time 0.99 seconds
Started Aug 02 04:44:35 PM PDT 24
Finished Aug 02 04:44:36 PM PDT 24
Peak memory 208456 kb
Host smart-6183db53-262c-4000-9617-82cf0514b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549489337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2549489337
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.610170097
Short name T389
Test name
Test status
Simulation time 82392225 ps
CPU time 0.81 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:40 PM PDT 24
Peak memory 205844 kb
Host smart-816e0ee7-c988-4e66-b19c-5d039a87dd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610170097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.610170097
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1806169269
Short name T208
Test name
Test status
Simulation time 1554467295 ps
CPU time 9.15 seconds
Started Aug 02 04:44:34 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 233460 kb
Host smart-5a7b5019-6160-46a7-8e6d-047fe36eadb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806169269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1806169269
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2766777869
Short name T325
Test name
Test status
Simulation time 32072264 ps
CPU time 0.72 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 205080 kb
Host smart-2a225236-48ce-4803-b121-93c71f798543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766777869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2766777869
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2480593433
Short name T614
Test name
Test status
Simulation time 452152123 ps
CPU time 5.31 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 233364 kb
Host smart-b7ffdffa-b0d2-41db-9c19-acbbe025123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480593433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2480593433
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2347887801
Short name T509
Test name
Test status
Simulation time 16721404 ps
CPU time 0.8 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 206976 kb
Host smart-760c5dc1-5eb2-4064-8650-401735aebb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347887801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2347887801
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2629284345
Short name T1013
Test name
Test status
Simulation time 25808784829 ps
CPU time 52.16 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 238936 kb
Host smart-3e0f0f0a-4969-433e-b2a6-ed7c150f049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629284345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2629284345
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3810596792
Short name T988
Test name
Test status
Simulation time 9251472165 ps
CPU time 50.36 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 249892 kb
Host smart-ce7fdd5e-4c47-4e26-9038-6c671d2b3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810596792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3810596792
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1537800528
Short name T421
Test name
Test status
Simulation time 18173728055 ps
CPU time 151.57 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 254376 kb
Host smart-e0001ec3-21a6-422b-bb9a-b44295fa8b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537800528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1537800528
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1318629977
Short name T832
Test name
Test status
Simulation time 1792647780 ps
CPU time 7.05 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:51 PM PDT 24
Peak memory 225168 kb
Host smart-5e690deb-1a4a-4663-bcff-062ba4b5ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318629977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1318629977
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1685048317
Short name T241
Test name
Test status
Simulation time 3434422086 ps
CPU time 19.78 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:59 PM PDT 24
Peak memory 225260 kb
Host smart-41f5414a-8717-428d-be51-7ec57dc53f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685048317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1685048317
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3017064965
Short name T489
Test name
Test status
Simulation time 4716856823 ps
CPU time 10.66 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:50 PM PDT 24
Peak memory 249380 kb
Host smart-e5e2fa07-4576-4f1d-be99-0e96ca5acc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017064965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3017064965
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3091907849
Short name T799
Test name
Test status
Simulation time 868979994 ps
CPU time 4.07 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 225008 kb
Host smart-2164ff02-1b8e-47ab-b488-6873b8381c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091907849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3091907849
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1997106963
Short name T1034
Test name
Test status
Simulation time 1360008053 ps
CPU time 6.44 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 241060 kb
Host smart-7d6d02c8-fe96-4790-be8d-6c439ab9f281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997106963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1997106963
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3965623627
Short name T773
Test name
Test status
Simulation time 248539696 ps
CPU time 4.52 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:46 PM PDT 24
Peak memory 221052 kb
Host smart-13853ea5-bdae-48b8-9e97-101cc1b21ae2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3965623627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3965623627
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.611126037
Short name T495
Test name
Test status
Simulation time 78814948 ps
CPU time 1.04 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 207640 kb
Host smart-ef587c7c-66de-428d-b904-7611c3d88b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611126037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.611126037
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2131937108
Short name T712
Test name
Test status
Simulation time 26468039292 ps
CPU time 37.61 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:45:22 PM PDT 24
Peak memory 217048 kb
Host smart-0bde32a7-b373-486a-8843-ced75acf6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131937108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2131937108
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.527219244
Short name T314
Test name
Test status
Simulation time 7166878839 ps
CPU time 2.99 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 216928 kb
Host smart-80baa869-825e-46a0-93a8-9f062885d0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527219244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.527219244
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3324532276
Short name T376
Test name
Test status
Simulation time 100178293 ps
CPU time 1.65 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 216872 kb
Host smart-35743786-0db7-41a6-9f5d-69ad7836fb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324532276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3324532276
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2614348062
Short name T630
Test name
Test status
Simulation time 59667605 ps
CPU time 0.84 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 206356 kb
Host smart-351860a9-7821-4aa4-b00f-9cf9075476ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614348062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2614348062
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3591227052
Short name T239
Test name
Test status
Simulation time 12308272393 ps
CPU time 20.88 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:45:02 PM PDT 24
Peak memory 225200 kb
Host smart-855b6058-aae7-4be4-baaa-78bda144faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591227052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3591227052
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1572434301
Short name T833
Test name
Test status
Simulation time 13381846 ps
CPU time 0.68 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:43 PM PDT 24
Peak memory 205712 kb
Host smart-7adca29f-82de-427c-9cce-9eae47fddbc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572434301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1572434301
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2142184304
Short name T871
Test name
Test status
Simulation time 1981574143 ps
CPU time 17.3 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 233372 kb
Host smart-02191536-24e8-4c37-b09c-3b4deb0f37e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142184304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2142184304
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2369353027
Short name T516
Test name
Test status
Simulation time 18168766 ps
CPU time 0.76 seconds
Started Aug 02 04:44:39 PM PDT 24
Finished Aug 02 04:44:39 PM PDT 24
Peak memory 207308 kb
Host smart-09117d2a-4fa1-487b-a92e-721530dc49d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369353027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2369353027
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3445254300
Short name T990
Test name
Test status
Simulation time 8495940267 ps
CPU time 120.91 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 265900 kb
Host smart-af60d321-7ddc-48b6-ae9e-ed495bd7b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445254300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3445254300
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1631986187
Short name T1024
Test name
Test status
Simulation time 7061216624 ps
CPU time 47.91 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 250036 kb
Host smart-39bb4da2-1319-4a4e-b2ce-311c7732b7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631986187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1631986187
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.598755414
Short name T938
Test name
Test status
Simulation time 1854505143 ps
CPU time 7.11 seconds
Started Aug 02 04:44:41 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 225200 kb
Host smart-4581b928-d6c6-4479-b5c1-006b1c84f8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598755414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.598755414
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.454502053
Short name T197
Test name
Test status
Simulation time 202200342145 ps
CPU time 385.05 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:51:10 PM PDT 24
Peak memory 274380 kb
Host smart-29d20a3c-3383-4501-b0f7-550e6610dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454502053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.454502053
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2448376462
Short name T392
Test name
Test status
Simulation time 3430706973 ps
CPU time 8.88 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:44:51 PM PDT 24
Peak memory 225188 kb
Host smart-b270178a-c805-45ca-921a-5523bd4d62f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448376462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2448376462
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2107534119
Short name T899
Test name
Test status
Simulation time 299988656 ps
CPU time 2.19 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 224724 kb
Host smart-ba5c516f-001c-4fc0-a41a-ad246b1c324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107534119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2107534119
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1424066442
Short name T488
Test name
Test status
Simulation time 2352226466 ps
CPU time 11.67 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 237808 kb
Host smart-5bc9f16b-878f-4174-8c35-52c35eaac32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424066442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1424066442
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.842066221
Short name T92
Test name
Test status
Simulation time 297665633 ps
CPU time 7.3 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:51 PM PDT 24
Peak memory 241564 kb
Host smart-1cfb56e5-ecba-45fb-a7c6-35bd1d7fafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842066221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.842066221
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3904618501
Short name T352
Test name
Test status
Simulation time 2632717850 ps
CPU time 16.84 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 220880 kb
Host smart-2fb578b9-5081-4adb-9115-98b5ec5bdb00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3904618501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3904618501
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.595604518
Short name T757
Test name
Test status
Simulation time 41290109 ps
CPU time 0.97 seconds
Started Aug 02 04:44:55 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 207176 kb
Host smart-90db8d88-b465-4744-bae0-67e0df19d32a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595604518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.595604518
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3492788308
Short name T559
Test name
Test status
Simulation time 35922922 ps
CPU time 0.74 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 206140 kb
Host smart-b5a979f8-1d33-4116-8ed9-a555b7e7ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492788308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3492788308
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2587808885
Short name T803
Test name
Test status
Simulation time 10191987142 ps
CPU time 7.7 seconds
Started Aug 02 04:44:37 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 218040 kb
Host smart-62cde5fd-2c0f-4a46-8271-68355b774c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587808885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2587808885
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1555082720
Short name T307
Test name
Test status
Simulation time 94186625 ps
CPU time 1.84 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:46 PM PDT 24
Peak memory 216864 kb
Host smart-5aeecb58-7190-44de-a7b8-a90dfc6d27dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555082720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1555082720
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2243273642
Short name T824
Test name
Test status
Simulation time 25378851 ps
CPU time 0.83 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 206528 kb
Host smart-8610589f-1cd0-4427-bc14-49f0eada7eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243273642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2243273642
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1602020988
Short name T238
Test name
Test status
Simulation time 1730141882 ps
CPU time 11.93 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 225252 kb
Host smart-d96251a9-258c-4c61-a9ee-e9b384c38252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602020988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1602020988
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.101533837
Short name T884
Test name
Test status
Simulation time 15301408 ps
CPU time 0.73 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 206124 kb
Host smart-050f9ba1-766a-46d3-b041-80c418e83022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101533837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.101533837
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.239572416
Short name T242
Test name
Test status
Simulation time 14969275717 ps
CPU time 12.01 seconds
Started Aug 02 04:44:45 PM PDT 24
Finished Aug 02 04:44:57 PM PDT 24
Peak memory 225224 kb
Host smart-db3c5848-2311-4c08-a925-d879af7eab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239572416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.239572416
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1509165797
Short name T560
Test name
Test status
Simulation time 16595756 ps
CPU time 0.79 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:44 PM PDT 24
Peak memory 206932 kb
Host smart-411ae2d9-965e-4f69-a9a0-12a67d046fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509165797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1509165797
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1559511910
Short name T284
Test name
Test status
Simulation time 50567458681 ps
CPU time 213.65 seconds
Started Aug 02 04:44:48 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 255336 kb
Host smart-774c8837-ed9d-4935-af09-47a7eed42c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559511910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1559511910
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.245345679
Short name T573
Test name
Test status
Simulation time 13819913547 ps
CPU time 57.3 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:45:42 PM PDT 24
Peak memory 250440 kb
Host smart-09990ef3-c734-4568-a58a-fda146f8cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245345679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.245345679
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2297494324
Short name T864
Test name
Test status
Simulation time 238471300 ps
CPU time 6.17 seconds
Started Aug 02 04:44:42 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 233340 kb
Host smart-853535a6-cb19-44a8-a436-b785eb9de733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297494324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2297494324
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1553888929
Short name T932
Test name
Test status
Simulation time 1769717981 ps
CPU time 14.97 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:58 PM PDT 24
Peak memory 233288 kb
Host smart-6a1d2794-1aff-4339-9501-9f645a23814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553888929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1553888929
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2238880508
Short name T24
Test name
Test status
Simulation time 2896635659 ps
CPU time 38.66 seconds
Started Aug 02 04:44:46 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 233596 kb
Host smart-25d7e5f5-8df9-461e-8869-592ec4281c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238880508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2238880508
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2926244055
Short name T59
Test name
Test status
Simulation time 1057599402 ps
CPU time 11.84 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 225092 kb
Host smart-eaa2e361-a3b4-42a5-bf18-67287c74ffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926244055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2926244055
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.77724121
Short name T409
Test name
Test status
Simulation time 213578317 ps
CPU time 3.59 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 233284 kb
Host smart-3fb6a1d7-8421-44a6-8d34-6527211f5bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77724121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.77724121
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1271146137
Short name T153
Test name
Test status
Simulation time 280355268 ps
CPU time 3.9 seconds
Started Aug 02 04:44:43 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 221320 kb
Host smart-f423ef22-fcf3-4be6-a50f-bd0a897ee357
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1271146137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1271146137
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4161182243
Short name T997
Test name
Test status
Simulation time 138376231 ps
CPU time 0.88 seconds
Started Aug 02 04:44:45 PM PDT 24
Finished Aug 02 04:44:46 PM PDT 24
Peak memory 207296 kb
Host smart-bba21d3a-0ec5-4551-866e-9c58e95fa5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161182243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4161182243
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3554358116
Short name T977
Test name
Test status
Simulation time 1641680018 ps
CPU time 10.37 seconds
Started Aug 02 04:44:40 PM PDT 24
Finished Aug 02 04:44:50 PM PDT 24
Peak memory 220292 kb
Host smart-2211572f-7185-47ac-8292-f43f2930fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554358116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3554358116
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1347117652
Short name T435
Test name
Test status
Simulation time 478023850 ps
CPU time 3.15 seconds
Started Aug 02 04:44:44 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 216872 kb
Host smart-ef2008f9-0770-421f-a212-4c59fbc6f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347117652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1347117652
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.467906192
Short name T694
Test name
Test status
Simulation time 236972202 ps
CPU time 1.79 seconds
Started Aug 02 04:44:45 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 216956 kb
Host smart-b05a5d8b-a869-4c52-8065-c7f2e13df254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467906192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.467906192
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1784999436
Short name T970
Test name
Test status
Simulation time 24785133 ps
CPU time 0.73 seconds
Started Aug 02 04:44:46 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 206408 kb
Host smart-2cced69f-3e7a-4360-9557-611844a81c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784999436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1784999436
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3883391643
Short name T492
Test name
Test status
Simulation time 2240410452 ps
CPU time 7.6 seconds
Started Aug 02 04:44:46 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 225388 kb
Host smart-d3b4ebec-9180-44c2-9a35-71c5af00552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883391643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3883391643
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2588211882
Short name T1004
Test name
Test status
Simulation time 23184533 ps
CPU time 0.71 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 205680 kb
Host smart-bd9dcbaa-06b9-40c7-abcd-622a0fbd4a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588211882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2588211882
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.897263198
Short name T476
Test name
Test status
Simulation time 11967802208 ps
CPU time 31.12 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:45:24 PM PDT 24
Peak memory 225180 kb
Host smart-7d44d52c-84b6-426c-b306-d6a0b3365bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897263198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.897263198
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1639069642
Short name T910
Test name
Test status
Simulation time 15888569 ps
CPU time 0.78 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:44:51 PM PDT 24
Peak memory 206880 kb
Host smart-88fc653c-d529-4152-aba2-0f27bc42be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639069642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1639069642
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3248127521
Short name T855
Test name
Test status
Simulation time 11098337 ps
CPU time 0.77 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 216356 kb
Host smart-8db78c49-1798-4384-8a2d-7c6275a6aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248127521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3248127521
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3947356546
Short name T76
Test name
Test status
Simulation time 213107917632 ps
CPU time 231.4 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 262916 kb
Host smart-94dd1dbb-e3ec-43c9-bc27-82dfe6f2a29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947356546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3947356546
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.571929357
Short name T652
Test name
Test status
Simulation time 32301467371 ps
CPU time 78.93 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:46:10 PM PDT 24
Peak memory 233728 kb
Host smart-c9174336-5e96-47a6-9a6e-727fcc2e5bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571929357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.571929357
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3995062129
Short name T1028
Test name
Test status
Simulation time 306665248 ps
CPU time 3.68 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 225188 kb
Host smart-87279a01-d735-4151-a6bb-6d1370016579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995062129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3995062129
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2325273048
Short name T834
Test name
Test status
Simulation time 128467939141 ps
CPU time 195.04 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:48:06 PM PDT 24
Peak memory 257988 kb
Host smart-37d5b85e-521f-4bf3-bc2f-e4f233597dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325273048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2325273048
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2069801786
Short name T620
Test name
Test status
Simulation time 2418692655 ps
CPU time 12.78 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:45:04 PM PDT 24
Peak memory 233472 kb
Host smart-d0704f22-646c-49a2-b875-3eb96aa24d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069801786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2069801786
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3224682567
Short name T567
Test name
Test status
Simulation time 9773033935 ps
CPU time 31.27 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 235332 kb
Host smart-8d593bf4-7568-4bb2-b5c9-acb1aec53cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224682567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3224682567
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2970446142
Short name T69
Test name
Test status
Simulation time 2501710507 ps
CPU time 7.28 seconds
Started Aug 02 04:44:55 PM PDT 24
Finished Aug 02 04:45:02 PM PDT 24
Peak memory 233444 kb
Host smart-80ade044-7a26-4be0-89be-255a38b1ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970446142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2970446142
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1835526816
Short name T857
Test name
Test status
Simulation time 328426510 ps
CPU time 4.18 seconds
Started Aug 02 04:44:55 PM PDT 24
Finished Aug 02 04:44:59 PM PDT 24
Peak memory 236280 kb
Host smart-157fd822-cfc2-4bdc-b805-93e1f8b27e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835526816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1835526816
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3172142944
Short name T598
Test name
Test status
Simulation time 487471075 ps
CPU time 5.27 seconds
Started Aug 02 04:44:55 PM PDT 24
Finished Aug 02 04:45:01 PM PDT 24
Peak memory 223060 kb
Host smart-b425edfe-bd70-4930-8f40-f8b8487c52f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3172142944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3172142944
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1078407913
Short name T812
Test name
Test status
Simulation time 421127104 ps
CPU time 3.48 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:44:57 PM PDT 24
Peak memory 225076 kb
Host smart-3934c6af-b953-4663-87f8-03ad31618265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078407913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1078407913
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2249905456
Short name T998
Test name
Test status
Simulation time 19173141478 ps
CPU time 47.53 seconds
Started Aug 02 04:44:51 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 216952 kb
Host smart-04c84ca6-d187-4ad3-abd5-250440db0d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249905456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2249905456
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.210692674
Short name T310
Test name
Test status
Simulation time 31524658824 ps
CPU time 14.82 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 216920 kb
Host smart-83df3b1e-db27-42db-bffe-5865782c705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210692674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.210692674
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.703334248
Short name T874
Test name
Test status
Simulation time 1372301717 ps
CPU time 11.14 seconds
Started Aug 02 04:45:06 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 216788 kb
Host smart-e1f06e55-a8d6-49d3-b3d6-c39befdc1c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703334248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.703334248
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3090446769
Short name T544
Test name
Test status
Simulation time 13259848 ps
CPU time 0.69 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 206060 kb
Host smart-769d66db-e9d4-4b82-a5ef-c184fa84ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090446769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3090446769
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3604852965
Short name T885
Test name
Test status
Simulation time 1431032316 ps
CPU time 4.8 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:57 PM PDT 24
Peak memory 233484 kb
Host smart-b9f32959-2d1b-423f-80a6-e98176323fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604852965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3604852965
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3837563573
Short name T330
Test name
Test status
Simulation time 39574123 ps
CPU time 0.7 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 205740 kb
Host smart-8ecc4bba-9d43-410d-a38a-8fefecc57c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837563573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3837563573
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3073993878
Short name T28
Test name
Test status
Simulation time 1277185754 ps
CPU time 14.7 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 233292 kb
Host smart-3a25898c-a57a-4ebe-87be-7e59677b6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073993878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3073993878
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2788819554
Short name T760
Test name
Test status
Simulation time 26213654 ps
CPU time 0.76 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 206096 kb
Host smart-ef5082c3-c9e8-41e6-a6f3-018b7b39a1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788819554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2788819554
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2932156274
Short name T408
Test name
Test status
Simulation time 2714528420 ps
CPU time 54.19 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 251984 kb
Host smart-f3630ffd-5da0-44a5-822a-2c1d013281c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932156274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2932156274
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3745192731
Short name T35
Test name
Test status
Simulation time 57918286932 ps
CPU time 150.99 seconds
Started Aug 02 04:44:59 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 257160 kb
Host smart-3d2391b6-ca91-49b3-a75e-02b3c4fb14be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745192731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3745192731
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.309701003
Short name T968
Test name
Test status
Simulation time 146148868864 ps
CPU time 267.63 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:49:25 PM PDT 24
Peak memory 256512 kb
Host smart-b0d4adda-3f8f-466a-b4c9-4d08910bf761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309701003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.309701003
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.571564660
Short name T973
Test name
Test status
Simulation time 2559364011 ps
CPU time 9.75 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:45:07 PM PDT 24
Peak memory 241704 kb
Host smart-f0e8147f-30e4-4882-a55d-f950264e8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571564660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.571564660
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.944932196
Short name T741
Test name
Test status
Simulation time 3444619062 ps
CPU time 24.93 seconds
Started Aug 02 04:45:07 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 235536 kb
Host smart-e7530468-5acf-4f22-9b5e-b1471fa3cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944932196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.944932196
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4097666585
Short name T622
Test name
Test status
Simulation time 27597335 ps
CPU time 2.21 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 224424 kb
Host smart-03548c15-f86a-4c04-975b-3e6dd48dfcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097666585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4097666585
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2259922216
Short name T933
Test name
Test status
Simulation time 4983940370 ps
CPU time 20.06 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:45:13 PM PDT 24
Peak memory 233284 kb
Host smart-d723e318-01af-4216-b427-9a429b5ca545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259922216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2259922216
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.119914689
Short name T886
Test name
Test status
Simulation time 246315275 ps
CPU time 3.84 seconds
Started Aug 02 04:45:05 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 225048 kb
Host smart-dbb158e7-39f0-4be8-bbaf-1e9d0b0919fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119914689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.119914689
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1302458207
Short name T673
Test name
Test status
Simulation time 56048120 ps
CPU time 2.41 seconds
Started Aug 02 04:45:05 PM PDT 24
Finished Aug 02 04:45:07 PM PDT 24
Peak memory 232880 kb
Host smart-ead1567a-244a-40b0-9578-0839acefe2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302458207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1302458207
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2308084306
Short name T441
Test name
Test status
Simulation time 138010123 ps
CPU time 3.42 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 219960 kb
Host smart-35c08fe1-7c17-4238-8687-dbb8dac79de5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2308084306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2308084306
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3749774578
Short name T342
Test name
Test status
Simulation time 14847919 ps
CPU time 0.7 seconds
Started Aug 02 04:45:05 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 206008 kb
Host smart-464d5263-f60b-43bc-9e36-a40bd0ad4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749774578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3749774578
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1138750326
Short name T470
Test name
Test status
Simulation time 5898234881 ps
CPU time 17.26 seconds
Started Aug 02 04:44:53 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 216920 kb
Host smart-2a7902e2-af4c-4bf7-804d-ef68a735a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138750326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1138750326
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3087806654
Short name T582
Test name
Test status
Simulation time 79511891 ps
CPU time 1.81 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:44:59 PM PDT 24
Peak memory 216904 kb
Host smart-a1e2ec44-e7f6-46e4-b3e0-b3887b8f6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087806654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3087806654
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3093095452
Short name T815
Test name
Test status
Simulation time 63924080 ps
CPU time 0.91 seconds
Started Aug 02 04:44:55 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 206496 kb
Host smart-7aebc9e3-13b4-4b92-a8bc-b950bf574d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093095452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3093095452
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3394765874
Short name T229
Test name
Test status
Simulation time 1982078394 ps
CPU time 3.52 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 225236 kb
Host smart-a182d800-fbdb-4777-936d-6bb7e080a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394765874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3394765874
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3843955692
Short name T137
Test name
Test status
Simulation time 38022081 ps
CPU time 0.75 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:45:04 PM PDT 24
Peak memory 205132 kb
Host smart-d0504783-f502-47e1-a6a3-c3a6b8fd54de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843955692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3843955692
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1628134654
Short name T889
Test name
Test status
Simulation time 5355276003 ps
CPU time 10.89 seconds
Started Aug 02 04:45:04 PM PDT 24
Finished Aug 02 04:45:15 PM PDT 24
Peak memory 233444 kb
Host smart-8d364d23-c804-41c7-87da-e8452a9ed90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628134654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1628134654
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3084105323
Short name T597
Test name
Test status
Simulation time 28201402 ps
CPU time 0.75 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 207220 kb
Host smart-9855259b-71d5-4068-9569-805c2d9b3ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084105323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3084105323
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1489314723
Short name T962
Test name
Test status
Simulation time 41829077836 ps
CPU time 41.93 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 249824 kb
Host smart-0f0a6d64-560a-4a1e-9986-e8bf41c4cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489314723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1489314723
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.941026754
Short name T196
Test name
Test status
Simulation time 3790329542 ps
CPU time 53.42 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:55 PM PDT 24
Peak memory 253672 kb
Host smart-29d92f14-f528-4e07-8f6c-f2bdabe74156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941026754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.941026754
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.270520932
Short name T460
Test name
Test status
Simulation time 10325428392 ps
CPU time 71.86 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 267432 kb
Host smart-41b2020e-e14d-475f-a933-8b05a20edc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270520932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.270520932
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2540982039
Short name T233
Test name
Test status
Simulation time 583981223 ps
CPU time 6.58 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 225076 kb
Host smart-36eb28fa-0a12-4c1e-8e28-50e648e2bde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540982039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2540982039
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2093900807
Short name T702
Test name
Test status
Simulation time 97753560257 ps
CPU time 167.28 seconds
Started Aug 02 04:45:00 PM PDT 24
Finished Aug 02 04:47:48 PM PDT 24
Peak memory 251432 kb
Host smart-8f8b928c-81dd-4ddb-99d7-2bc9f67096d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093900807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2093900807
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1632488319
Short name T143
Test name
Test status
Simulation time 1861994712 ps
CPU time 12.19 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:45:15 PM PDT 24
Peak memory 225076 kb
Host smart-570c040d-8c83-49fb-9d58-f1fb33a6e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632488319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1632488319
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3846353503
Short name T555
Test name
Test status
Simulation time 28441606 ps
CPU time 2.11 seconds
Started Aug 02 04:45:00 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 223648 kb
Host smart-b670b5ea-8d83-4ef3-baba-ef4ebf396c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846353503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3846353503
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1207422045
Short name T708
Test name
Test status
Simulation time 5187620384 ps
CPU time 18.14 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 239412 kb
Host smart-bbc94842-6001-42b5-93de-34d5c51cd5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207422045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1207422045
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3955157165
Short name T228
Test name
Test status
Simulation time 10578140449 ps
CPU time 15.34 seconds
Started Aug 02 04:45:05 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 241180 kb
Host smart-b95bc7a5-ea79-4733-9677-759820d7af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955157165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3955157165
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1968722762
Short name T558
Test name
Test status
Simulation time 3206561687 ps
CPU time 9.06 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 222060 kb
Host smart-9d26274c-dc8a-4e57-976b-59f9753ec1ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968722762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1968722762
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1609236482
Short name T285
Test name
Test status
Simulation time 151512488997 ps
CPU time 745.91 seconds
Started Aug 02 04:45:06 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 270076 kb
Host smart-a285c263-3ed0-4955-ad5b-851b71cbe75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609236482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1609236482
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2493076742
Short name T890
Test name
Test status
Simulation time 1370996535 ps
CPU time 10.38 seconds
Started Aug 02 04:45:05 PM PDT 24
Finished Aug 02 04:45:15 PM PDT 24
Peak memory 216520 kb
Host smart-757291c8-8989-4c0a-8c8d-c6fed840ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493076742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2493076742
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3740432345
Short name T914
Test name
Test status
Simulation time 455362029 ps
CPU time 3.37 seconds
Started Aug 02 04:44:54 PM PDT 24
Finished Aug 02 04:44:57 PM PDT 24
Peak memory 216736 kb
Host smart-9a9cecf8-9f43-45c0-a5bc-fa682345205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740432345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3740432345
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4211032233
Short name T466
Test name
Test status
Simulation time 226425301 ps
CPU time 3 seconds
Started Aug 02 04:44:57 PM PDT 24
Finished Aug 02 04:45:00 PM PDT 24
Peak memory 216888 kb
Host smart-f93dc720-f991-443c-95d5-ccfe71a7e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211032233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4211032233
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.709655133
Short name T783
Test name
Test status
Simulation time 21435930 ps
CPU time 0.78 seconds
Started Aug 02 04:44:52 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 206364 kb
Host smart-01be0ef9-d6cc-4c7b-8440-c4884ea601cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709655133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.709655133
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1089945658
Short name T527
Test name
Test status
Simulation time 513186220 ps
CPU time 5.79 seconds
Started Aug 02 04:45:00 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 241452 kb
Host smart-9e76ce57-4843-46cb-a9b5-a7c700d5e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089945658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1089945658
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3416043475
Short name T599
Test name
Test status
Simulation time 38315028 ps
CPU time 0.69 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 205168 kb
Host smart-a090580f-2b68-4613-bfbd-d0649a48ae3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416043475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3416043475
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2677019453
Short name T410
Test name
Test status
Simulation time 317482987 ps
CPU time 5.35 seconds
Started Aug 02 04:45:00 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 225312 kb
Host smart-53252bb4-4582-4978-abbd-fd544b3957db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677019453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2677019453
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3194741845
Short name T411
Test name
Test status
Simulation time 19733210 ps
CPU time 0.8 seconds
Started Aug 02 04:45:07 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 206948 kb
Host smart-dfc18e5e-f024-45f8-b524-59c194b98533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194741845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3194741845
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3942839586
Short name T190
Test name
Test status
Simulation time 21469458350 ps
CPU time 182.49 seconds
Started Aug 02 04:45:01 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 253864 kb
Host smart-64728250-2473-4579-a78a-79d9adf27bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942839586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3942839586
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2721948408
Short name T581
Test name
Test status
Simulation time 165569944983 ps
CPU time 296.74 seconds
Started Aug 02 04:45:04 PM PDT 24
Finished Aug 02 04:50:01 PM PDT 24
Peak memory 258124 kb
Host smart-1515f807-8eab-40cf-be14-c14933b5e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721948408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2721948408
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2187641435
Short name T326
Test name
Test status
Simulation time 97167510 ps
CPU time 3.24 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:45:06 PM PDT 24
Peak memory 233328 kb
Host smart-e6e6ec4a-75fc-4ee4-8449-eebf6e7a5c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187641435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2187641435
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1152147815
Short name T907
Test name
Test status
Simulation time 4965807681 ps
CPU time 81.83 seconds
Started Aug 02 04:45:07 PM PDT 24
Finished Aug 02 04:46:28 PM PDT 24
Peak memory 250796 kb
Host smart-1317cc75-1fde-47af-9d98-8fcacf3b20b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152147815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1152147815
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4274067375
Short name T206
Test name
Test status
Simulation time 437285837 ps
CPU time 5.47 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 225128 kb
Host smart-af5814d0-1969-421d-a58f-65f82fc3aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274067375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4274067375
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3500062495
Short name T721
Test name
Test status
Simulation time 168641046 ps
CPU time 5.89 seconds
Started Aug 02 04:45:02 PM PDT 24
Finished Aug 02 04:45:08 PM PDT 24
Peak memory 239488 kb
Host smart-c928aae2-06e6-4d53-81e7-0a5e944272e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500062495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3500062495
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2433889635
Short name T273
Test name
Test status
Simulation time 65837668578 ps
CPU time 23.74 seconds
Started Aug 02 04:45:00 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 233376 kb
Host smart-42284b5b-47e3-45ba-ac17-fa1ed319879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433889635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2433889635
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1634349129
Short name T218
Test name
Test status
Simulation time 5642538620 ps
CPU time 6.02 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:45:09 PM PDT 24
Peak memory 233516 kb
Host smart-d2c77112-4e4e-4af2-8986-d71e2069be13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634349129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1634349129
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2626794540
Short name T155
Test name
Test status
Simulation time 4651811915 ps
CPU time 26.1 seconds
Started Aug 02 04:45:01 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 221488 kb
Host smart-9761ed7c-7da8-423f-b355-aaf2cf66b0f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2626794540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2626794540
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3215450260
Short name T625
Test name
Test status
Simulation time 160367233 ps
CPU time 1.04 seconds
Started Aug 02 04:45:08 PM PDT 24
Finished Aug 02 04:45:09 PM PDT 24
Peak memory 207352 kb
Host smart-abaf785f-ccec-49ff-acb0-c0f17c0463dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215450260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3215450260
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2109116190
Short name T974
Test name
Test status
Simulation time 8131855584 ps
CPU time 41.47 seconds
Started Aug 02 04:45:01 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 217056 kb
Host smart-7050dcb1-9f98-4352-9391-0c49ebd85647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109116190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2109116190
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2688249800
Short name T413
Test name
Test status
Simulation time 7087080221 ps
CPU time 4.55 seconds
Started Aug 02 04:45:07 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 216884 kb
Host smart-71477bd9-6b0a-48c6-9d47-defe16cf14dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688249800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2688249800
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2418646362
Short name T948
Test name
Test status
Simulation time 96173233 ps
CPU time 1.36 seconds
Started Aug 02 04:45:01 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 216860 kb
Host smart-4d6e51e5-aa0a-4bcf-8e79-f744e4a50064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418646362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2418646362
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1599617368
Short name T667
Test name
Test status
Simulation time 19143673 ps
CPU time 0.86 seconds
Started Aug 02 04:45:03 PM PDT 24
Finished Aug 02 04:45:04 PM PDT 24
Peak memory 206332 kb
Host smart-1765ab60-6e57-43a7-a808-c85167e35c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599617368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1599617368
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3435990640
Short name T430
Test name
Test status
Simulation time 1945148173 ps
CPU time 9.81 seconds
Started Aug 02 04:45:06 PM PDT 24
Finished Aug 02 04:45:16 PM PDT 24
Peak memory 233260 kb
Host smart-6f08d7f5-af9e-4411-a934-359160c885c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435990640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3435990640
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3837877186
Short name T395
Test name
Test status
Simulation time 39334046 ps
CPU time 0.73 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 205200 kb
Host smart-00f440f7-aeb7-43e9-b6fc-bea20750be9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837877186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3837877186
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.753166254
Short name T245
Test name
Test status
Simulation time 1268278611 ps
CPU time 3.68 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:14 PM PDT 24
Peak memory 233032 kb
Host smart-4cbd65f2-0809-4ad7-a00d-b00875256a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753166254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.753166254
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1960499608
Short name T418
Test name
Test status
Simulation time 133285581 ps
CPU time 0.77 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:10 PM PDT 24
Peak memory 206928 kb
Host smart-ee670ed8-76dd-4316-b864-5ae914d5cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960499608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1960499608
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1834002044
Short name T214
Test name
Test status
Simulation time 5743858567 ps
CPU time 30.72 seconds
Started Aug 02 04:45:12 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 253988 kb
Host smart-98c931f7-a4b1-41c1-91d0-4f2141d9999a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834002044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1834002044
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2811494430
Short name T580
Test name
Test status
Simulation time 13895089727 ps
CPU time 65.76 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:46:16 PM PDT 24
Peak memory 249824 kb
Host smart-c2d055ca-5365-4e9a-9074-9956eeb63c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811494430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2811494430
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2160705250
Short name T278
Test name
Test status
Simulation time 2666930570 ps
CPU time 62.74 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 255068 kb
Host smart-69533243-93aa-4f1e-88cb-a8df2ab3875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160705250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2160705250
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4170399563
Short name T386
Test name
Test status
Simulation time 317453092 ps
CPU time 4.08 seconds
Started Aug 02 04:45:09 PM PDT 24
Finished Aug 02 04:45:14 PM PDT 24
Peak memory 241532 kb
Host smart-5a363086-3e80-4989-94cc-e920450e1883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170399563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4170399563
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.416210782
Short name T287
Test name
Test status
Simulation time 1757987530 ps
CPU time 42.38 seconds
Started Aug 02 04:45:09 PM PDT 24
Finished Aug 02 04:45:52 PM PDT 24
Peak memory 236960 kb
Host smart-cdaa5c09-1ab0-4d31-91d6-305bfa5751b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416210782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.416210782
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.350895729
Short name T637
Test name
Test status
Simulation time 9583867830 ps
CPU time 31.07 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:42 PM PDT 24
Peak memory 225268 kb
Host smart-1f7908bb-3992-4cea-964c-a49d816fddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350895729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.350895729
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1363976184
Short name T439
Test name
Test status
Simulation time 16946975425 ps
CPU time 59.09 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:46:10 PM PDT 24
Peak memory 249348 kb
Host smart-ae2477cb-9b13-4161-b7ac-9b2244d6518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363976184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1363976184
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.625723492
Short name T744
Test name
Test status
Simulation time 1037372136 ps
CPU time 5.64 seconds
Started Aug 02 04:45:09 PM PDT 24
Finished Aug 02 04:45:15 PM PDT 24
Peak memory 234244 kb
Host smart-0b77db7c-b276-4a3f-b9b0-0510198d377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625723492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.625723492
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2002909946
Short name T27
Test name
Test status
Simulation time 473151748 ps
CPU time 3.59 seconds
Started Aug 02 04:45:08 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 225076 kb
Host smart-6429536a-c8ea-4595-a230-49c4e4107876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002909946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2002909946
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2527140329
Short name T142
Test name
Test status
Simulation time 3830478765 ps
CPU time 12.23 seconds
Started Aug 02 04:45:13 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 223092 kb
Host smart-5be5ba2f-4a0d-49fd-ad13-bbc550c1fd6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527140329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2527140329
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2354437969
Short name T617
Test name
Test status
Simulation time 54712201 ps
CPU time 1.11 seconds
Started Aug 02 04:45:09 PM PDT 24
Finished Aug 02 04:45:10 PM PDT 24
Peak memory 207520 kb
Host smart-3a8c46ba-62f8-45e7-8f22-31da0f20a486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354437969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2354437969
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3703326377
Short name T484
Test name
Test status
Simulation time 7949203123 ps
CPU time 20.5 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 217328 kb
Host smart-dd393004-2585-4e7f-9cfb-5bb05b545567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703326377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3703326377
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2762263885
Short name T379
Test name
Test status
Simulation time 709174410 ps
CPU time 2.88 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:13 PM PDT 24
Peak memory 216896 kb
Host smart-8f43129a-351e-43b2-b638-2af2c663fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762263885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2762263885
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.422524648
Short name T468
Test name
Test status
Simulation time 112411509 ps
CPU time 1.38 seconds
Started Aug 02 04:45:12 PM PDT 24
Finished Aug 02 04:45:13 PM PDT 24
Peak memory 216912 kb
Host smart-3fc54ca9-2499-4b6e-8bdf-639ca9b8aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422524648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.422524648
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.220260082
Short name T416
Test name
Test status
Simulation time 372685538 ps
CPU time 0.99 seconds
Started Aug 02 04:45:12 PM PDT 24
Finished Aug 02 04:45:13 PM PDT 24
Peak memory 206416 kb
Host smart-c7e9db6e-4501-4df4-a4c4-a6993d0400ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220260082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.220260082
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2813862450
Short name T442
Test name
Test status
Simulation time 6019790452 ps
CPU time 14.46 seconds
Started Aug 02 04:45:12 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 241276 kb
Host smart-3f4189fd-b047-412f-ba99-3e285ec4d380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813862450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2813862450
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.710104633
Short name T878
Test name
Test status
Simulation time 14455998 ps
CPU time 0.69 seconds
Started Aug 02 04:45:17 PM PDT 24
Finished Aug 02 04:45:18 PM PDT 24
Peak memory 205668 kb
Host smart-954b367f-a50e-4f21-87ed-83f702a52a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710104633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.710104633
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.128863385
Short name T1
Test name
Test status
Simulation time 1162156603 ps
CPU time 6.67 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 233244 kb
Host smart-14e0ef38-871b-4182-bdc5-280010042c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128863385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.128863385
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.152294940
Short name T848
Test name
Test status
Simulation time 72128827 ps
CPU time 0.74 seconds
Started Aug 02 04:45:08 PM PDT 24
Finished Aug 02 04:45:09 PM PDT 24
Peak memory 206956 kb
Host smart-e57e0409-dfd8-4a77-898a-119f5b11472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152294940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.152294940
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.903865090
Short name T987
Test name
Test status
Simulation time 6716568849 ps
CPU time 21.6 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:41 PM PDT 24
Peak memory 241584 kb
Host smart-1edc410c-0395-459b-ab03-ccfa35e82829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903865090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.903865090
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2181776951
Short name T550
Test name
Test status
Simulation time 83926257959 ps
CPU time 199.05 seconds
Started Aug 02 04:45:17 PM PDT 24
Finished Aug 02 04:48:37 PM PDT 24
Peak memory 255252 kb
Host smart-f5ede7ef-4730-483e-9fe3-b061dad2921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181776951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2181776951
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4215263001
Short name T303
Test name
Test status
Simulation time 41927594396 ps
CPU time 27.53 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:46 PM PDT 24
Peak memory 218316 kb
Host smart-54f6d6e2-8c1a-405b-ba30-5bd04813b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215263001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4215263001
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1543732784
Short name T1012
Test name
Test status
Simulation time 483257416 ps
CPU time 6.18 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 233368 kb
Host smart-f92a00c4-68ff-4e99-84ba-934968b26d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543732784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1543732784
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.114458635
Short name T220
Test name
Test status
Simulation time 19979262970 ps
CPU time 155.74 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:47:56 PM PDT 24
Peak memory 255524 kb
Host smart-a633d112-a9a6-44ad-867b-ac33576586c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114458635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.114458635
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.554248710
Short name T11
Test name
Test status
Simulation time 5166543174 ps
CPU time 11.38 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 233408 kb
Host smart-af379edd-fe47-4b2f-a028-471a07ba2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554248710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.554248710
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.950776788
Short name T733
Test name
Test status
Simulation time 624895179 ps
CPU time 8.98 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 233300 kb
Host smart-91623145-615e-48bb-9ed7-da89759a6e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950776788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.950776788
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3388805326
Short name T1030
Test name
Test status
Simulation time 2540433694 ps
CPU time 10.15 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 225028 kb
Host smart-3818e0a6-d9c7-4b03-b27b-3fb6edc80689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388805326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3388805326
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.871926032
Short name T838
Test name
Test status
Simulation time 4709816787 ps
CPU time 7.16 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 234496 kb
Host smart-ca9a84ea-6a83-43a5-9dde-8bfd59bab818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871926032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.871926032
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4118068570
Short name T370
Test name
Test status
Simulation time 2275352222 ps
CPU time 9.65 seconds
Started Aug 02 04:45:23 PM PDT 24
Finished Aug 02 04:45:33 PM PDT 24
Peak memory 222404 kb
Host smart-13cf1a7f-a8a0-4869-ad9c-ca20ee665e25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4118068570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4118068570
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3269829284
Short name T211
Test name
Test status
Simulation time 25266045554 ps
CPU time 170.07 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 273540 kb
Host smart-4b987959-2e3d-41ea-940b-fd8db29fc2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269829284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3269829284
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.348736122
Short name T365
Test name
Test status
Simulation time 588260706 ps
CPU time 5.93 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:16 PM PDT 24
Peak memory 217252 kb
Host smart-a8ba1c1b-d71f-4f39-9e71-10a72fb28e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348736122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.348736122
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4204551388
Short name T746
Test name
Test status
Simulation time 810299811 ps
CPU time 3.73 seconds
Started Aug 02 04:45:10 PM PDT 24
Finished Aug 02 04:45:14 PM PDT 24
Peak memory 216904 kb
Host smart-85ad765f-a55a-4534-b684-b2b0b40d3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204551388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4204551388
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3128029564
Short name T703
Test name
Test status
Simulation time 55468349 ps
CPU time 1.42 seconds
Started Aug 02 04:45:11 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 217112 kb
Host smart-1c085d28-f07e-47b9-be06-65b549fbf8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128029564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3128029564
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4241190636
Short name T447
Test name
Test status
Simulation time 543513328 ps
CPU time 0.96 seconds
Started Aug 02 04:45:08 PM PDT 24
Finished Aug 02 04:45:09 PM PDT 24
Peak memory 207476 kb
Host smart-4f1b482a-7439-406c-8abc-526ef43ab9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241190636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4241190636
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3216146633
Short name T118
Test name
Test status
Simulation time 38727915 ps
CPU time 2.68 seconds
Started Aug 02 04:45:24 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 224736 kb
Host smart-a37601c6-a582-498c-868b-e7c9401dd2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216146633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3216146633
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1067699339
Short name T705
Test name
Test status
Simulation time 13023930 ps
CPU time 0.7 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:42:58 PM PDT 24
Peak memory 205708 kb
Host smart-4b1a814e-9943-4e27-9297-1674ddcee054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067699339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
067699339
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1415076463
Short name T946
Test name
Test status
Simulation time 30696798 ps
CPU time 2.19 seconds
Started Aug 02 04:43:00 PM PDT 24
Finished Aug 02 04:43:03 PM PDT 24
Peak memory 224696 kb
Host smart-62f989ba-c1d4-4ce3-8317-2f9606d07447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415076463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1415076463
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2268380198
Short name T683
Test name
Test status
Simulation time 48221613 ps
CPU time 0.79 seconds
Started Aug 02 04:42:58 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 207296 kb
Host smart-96046b72-228d-4e24-a3f5-42993b9f63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268380198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2268380198
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3343514913
Short name T48
Test name
Test status
Simulation time 213310326587 ps
CPU time 398.34 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:49:35 PM PDT 24
Peak memory 254732 kb
Host smart-acdf58a5-7665-44b6-a489-535abfff4253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343514913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3343514913
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2715215709
Short name T658
Test name
Test status
Simulation time 243025908948 ps
CPU time 150.92 seconds
Started Aug 02 04:42:59 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 241364 kb
Host smart-bacde9b4-1786-4610-809e-8dafe66a1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715215709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2715215709
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1909478209
Short name T574
Test name
Test status
Simulation time 1494590244 ps
CPU time 11.42 seconds
Started Aug 02 04:42:59 PM PDT 24
Finished Aug 02 04:43:10 PM PDT 24
Peak memory 241520 kb
Host smart-f0067842-5a4d-41d2-9ea5-506fd72593ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909478209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1909478209
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2728068029
Short name T514
Test name
Test status
Simulation time 28298994644 ps
CPU time 138.83 seconds
Started Aug 02 04:43:01 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 256000 kb
Host smart-3614bbc6-6153-48e6-8740-acf7b9619cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728068029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2728068029
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3858250175
Short name T888
Test name
Test status
Simulation time 1949154496 ps
CPU time 19.31 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 225168 kb
Host smart-059a0e0f-5959-410a-82f4-36cb89133e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858250175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3858250175
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4111826974
Short name T767
Test name
Test status
Simulation time 3226324785 ps
CPU time 23.68 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 234720 kb
Host smart-48495674-7fdf-44e7-a6d0-65dc0b4fcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111826974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4111826974
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4071426101
Short name T496
Test name
Test status
Simulation time 118124814 ps
CPU time 1.09 seconds
Started Aug 02 04:42:59 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 217116 kb
Host smart-9cf3a0a7-73f1-42cc-80f1-c989a1129666
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071426101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4071426101
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.616803821
Short name T636
Test name
Test status
Simulation time 4348025046 ps
CPU time 10.62 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:08 PM PDT 24
Peak memory 249540 kb
Host smart-421908b3-4a1d-4f89-80f4-65bb6dae7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616803821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
616803821
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.109168021
Short name T585
Test name
Test status
Simulation time 400831158 ps
CPU time 5.46 seconds
Started Aug 02 04:43:00 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 233288 kb
Host smart-db087d79-90e7-495e-bdb3-a741f870fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109168021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.109168021
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2154951939
Short name T423
Test name
Test status
Simulation time 582904768 ps
CPU time 4.47 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:43:02 PM PDT 24
Peak memory 223660 kb
Host smart-3070e539-72c8-476c-b53a-47f4916e1ddc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2154951939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2154951939
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1378261945
Short name T67
Test name
Test status
Simulation time 38304810 ps
CPU time 0.95 seconds
Started Aug 02 04:42:59 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 235548 kb
Host smart-9b193c9a-df5c-4556-baba-b0876856283e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378261945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1378261945
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1884457272
Short name T867
Test name
Test status
Simulation time 41825884086 ps
CPU time 73.09 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:44:10 PM PDT 24
Peak memory 249888 kb
Host smart-9916fedd-45fc-4258-8888-1d496bb040ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884457272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1884457272
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1594150369
Short name T600
Test name
Test status
Simulation time 927168906 ps
CPU time 12.95 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:43:08 PM PDT 24
Peak memory 219768 kb
Host smart-051a1293-c178-448b-a64f-1322c4006c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594150369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1594150369
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1962651236
Short name T793
Test name
Test status
Simulation time 17178992529 ps
CPU time 22.71 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 216888 kb
Host smart-6ddad194-e467-412e-8647-c491a6a32c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962651236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1962651236
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3467932553
Short name T626
Test name
Test status
Simulation time 161500272 ps
CPU time 1.79 seconds
Started Aug 02 04:43:00 PM PDT 24
Finished Aug 02 04:43:02 PM PDT 24
Peak memory 216904 kb
Host smart-dd7433c3-9e64-42f7-bf17-8f384576b0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467932553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3467932553
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2019934512
Short name T860
Test name
Test status
Simulation time 40823476 ps
CPU time 0.75 seconds
Started Aug 02 04:42:57 PM PDT 24
Finished Aug 02 04:42:57 PM PDT 24
Peak memory 206380 kb
Host smart-3f5111f1-ea98-4b77-8458-cc2b7c1ee221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019934512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2019934512
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4220829399
Short name T119
Test name
Test status
Simulation time 76639001038 ps
CPU time 21.75 seconds
Started Aug 02 04:42:56 PM PDT 24
Finished Aug 02 04:43:18 PM PDT 24
Peak memory 233356 kb
Host smart-4c350602-642b-4572-9eea-3becb93158f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220829399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4220829399
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2658647824
Short name T1003
Test name
Test status
Simulation time 23407173 ps
CPU time 0.77 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:19 PM PDT 24
Peak memory 205188 kb
Host smart-fa2a20d6-4b1b-4b3c-b437-0bc0af7476cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658647824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2658647824
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.424334459
Short name T722
Test name
Test status
Simulation time 7249993520 ps
CPU time 5.12 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 233348 kb
Host smart-80283543-5031-4834-a088-57b0adea55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424334459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.424334459
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2624292324
Short name T739
Test name
Test status
Simulation time 27044573 ps
CPU time 0.77 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 206916 kb
Host smart-036d2565-cbb8-4a93-9a85-088ca7504957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624292324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2624292324
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3519092698
Short name T198
Test name
Test status
Simulation time 63007702672 ps
CPU time 267.68 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:49:49 PM PDT 24
Peak memory 272584 kb
Host smart-b65f15f7-eec2-4e58-a1d1-2883cbaa7b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519092698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3519092698
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1970004457
Short name T30
Test name
Test status
Simulation time 128561212659 ps
CPU time 178.76 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 258076 kb
Host smart-3bc6a6d1-9af4-4458-92e4-787238007817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970004457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1970004457
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3054626348
Short name T811
Test name
Test status
Simulation time 20919564734 ps
CPU time 70.64 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 233488 kb
Host smart-6f7b2976-6b98-49a0-951b-62911ad8b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054626348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3054626348
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.767352244
Short name T478
Test name
Test status
Simulation time 41918451139 ps
CPU time 142.75 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 249760 kb
Host smart-bead59c3-5483-4427-b1d5-664c190676cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767352244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.767352244
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2441626354
Short name T445
Test name
Test status
Simulation time 1764757252 ps
CPU time 20.19 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:41 PM PDT 24
Peak memory 233480 kb
Host smart-66713470-0572-41e4-9fb5-f51557ab9f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441626354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2441626354
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.227740139
Short name T710
Test name
Test status
Simulation time 74277253 ps
CPU time 2.29 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 232908 kb
Host smart-26fd15d0-8b25-4a41-a1b9-b6d5ee59224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227740139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.227740139
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3423369649
Short name T265
Test name
Test status
Simulation time 17833722645 ps
CPU time 24.42 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 233304 kb
Host smart-1a0ab478-5c1b-439c-9540-9837ce433fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423369649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3423369649
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2586680758
Short name T346
Test name
Test status
Simulation time 2422050005 ps
CPU time 11.56 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 237344 kb
Host smart-7a817b22-ee66-468a-996e-a7038e966fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586680758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2586680758
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3299781006
Short name T324
Test name
Test status
Simulation time 170346709 ps
CPU time 3.51 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:24 PM PDT 24
Peak memory 219396 kb
Host smart-0dd89eb1-1086-499a-8ef4-998d158ce59f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299781006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3299781006
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2548135312
Short name T168
Test name
Test status
Simulation time 110299857538 ps
CPU time 224.62 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 265924 kb
Host smart-a94ee8e6-2d77-4ed1-96ed-22bc8226c15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548135312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2548135312
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.788049936
Short name T561
Test name
Test status
Simulation time 11645445327 ps
CPU time 16.48 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 216928 kb
Host smart-5bd89c5c-1268-4c30-8eea-e8876edfc5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788049936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.788049936
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3873588454
Short name T562
Test name
Test status
Simulation time 849686820 ps
CPU time 4.14 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 216856 kb
Host smart-ec3397d7-7ba0-4561-bd80-1c065e9c3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873588454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3873588454
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1944227715
Short name T849
Test name
Test status
Simulation time 271687246 ps
CPU time 2 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 216920 kb
Host smart-852344ca-b896-4310-9569-fadca2117810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944227715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1944227715
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2181586245
Short name T656
Test name
Test status
Simulation time 157761065 ps
CPU time 1.02 seconds
Started Aug 02 04:45:16 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 207568 kb
Host smart-39b72ee1-0cf4-4cd7-96f8-ab5ddeba8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181586245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2181586245
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2637008100
Short name T607
Test name
Test status
Simulation time 33576818505 ps
CPU time 23.19 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:42 PM PDT 24
Peak memory 233408 kb
Host smart-55761fe4-507a-4225-b742-bde1acb86a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637008100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2637008100
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1448032554
Short name T138
Test name
Test status
Simulation time 35300352 ps
CPU time 0.68 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 206040 kb
Host smart-d83ff040-f24f-4051-8f04-a1021bdb306b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448032554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1448032554
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4050460270
Short name T797
Test name
Test status
Simulation time 1585206121 ps
CPU time 14.24 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 233356 kb
Host smart-00c0512d-9dd2-4c42-8768-cc7dfcfc7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050460270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4050460270
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.980520244
Short name T362
Test name
Test status
Simulation time 66187114 ps
CPU time 0.74 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 206004 kb
Host smart-500b740e-ff42-4b27-baac-6a04b2e3aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980520244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.980520244
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2492230177
Short name T234
Test name
Test status
Simulation time 1033893934 ps
CPU time 21.25 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:42 PM PDT 24
Peak memory 253140 kb
Host smart-693ba649-31f9-4417-a994-0183eb73691b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492230177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2492230177
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4009941020
Short name T232
Test name
Test status
Simulation time 32421335908 ps
CPU time 312.52 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:50:31 PM PDT 24
Peak memory 257152 kb
Host smart-8122009f-eb7e-45de-9f8d-51aac6e6f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009941020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4009941020
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1798343410
Short name T805
Test name
Test status
Simulation time 7822171470 ps
CPU time 69.92 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:46:30 PM PDT 24
Peak memory 241708 kb
Host smart-909f7d40-7cf8-4434-9ac1-910cb4838583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798343410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1798343410
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.664549966
Short name T508
Test name
Test status
Simulation time 16650745183 ps
CPU time 18.41 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 241552 kb
Host smart-1b0a1f62-91e1-4a67-be27-8606c8aaa03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664549966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.664549966
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3856979497
Short name T90
Test name
Test status
Simulation time 82236846609 ps
CPU time 163.98 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 253360 kb
Host smart-5f5844e7-63eb-497f-b87f-a8c66c689b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856979497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3856979497
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2616380729
Short name T469
Test name
Test status
Simulation time 997382188 ps
CPU time 7.05 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 225128 kb
Host smart-d8f7d666-e934-49cd-b237-69e2a8687ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616380729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2616380729
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4248205179
Short name T869
Test name
Test status
Simulation time 16620238453 ps
CPU time 37.6 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:57 PM PDT 24
Peak memory 238632 kb
Host smart-748a72dd-da8b-4cfe-84d5-aab5c03cb9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248205179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4248205179
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.286285502
Short name T255
Test name
Test status
Simulation time 4906032182 ps
CPU time 17.56 seconds
Started Aug 02 04:45:23 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 240908 kb
Host smart-ee5d70b1-1c8f-47e9-beb9-6ebbaf397564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286285502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.286285502
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3506988059
Short name T490
Test name
Test status
Simulation time 22205030137 ps
CPU time 16.95 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 241312 kb
Host smart-374f6938-501f-4517-998a-bab95e0e964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506988059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3506988059
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.656068507
Short name T627
Test name
Test status
Simulation time 533861361 ps
CPU time 4.3 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 221232 kb
Host smart-c5c319d8-bd64-48e0-a61d-8201ed8d2831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=656068507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.656068507
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1521975511
Short name T21
Test name
Test status
Simulation time 50551991 ps
CPU time 0.97 seconds
Started Aug 02 04:45:22 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 207224 kb
Host smart-16618edb-ac54-489c-af3a-7131962d2114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521975511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1521975511
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.792986017
Short name T31
Test name
Test status
Simulation time 1377717932 ps
CPU time 4.13 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:24 PM PDT 24
Peak memory 216936 kb
Host smart-55ce7c6b-ec80-4fc5-9b44-36728836b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792986017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.792986017
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3241082973
Short name T1033
Test name
Test status
Simulation time 1156588259 ps
CPU time 4 seconds
Started Aug 02 04:45:23 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 216764 kb
Host smart-c6ca0f96-4b1c-41e4-adc6-cc2e6868d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241082973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3241082973
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.984044492
Short name T532
Test name
Test status
Simulation time 18289114 ps
CPU time 0.93 seconds
Started Aug 02 04:45:25 PM PDT 24
Finished Aug 02 04:45:26 PM PDT 24
Peak memory 207356 kb
Host smart-57dc66b9-c55f-4075-8df9-c0c12606b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984044492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.984044492
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2837990952
Short name T672
Test name
Test status
Simulation time 51952135 ps
CPU time 0.94 seconds
Started Aug 02 04:45:19 PM PDT 24
Finished Aug 02 04:45:20 PM PDT 24
Peak memory 207480 kb
Host smart-50487d99-5e95-47ab-b7c0-71cdd83a96d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837990952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2837990952
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4085023714
Short name T452
Test name
Test status
Simulation time 1074351155 ps
CPU time 6.32 seconds
Started Aug 02 04:45:21 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 229056 kb
Host smart-3b208719-6ac5-4478-bdb5-3bef76bc82a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085023714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4085023714
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2459010163
Short name T63
Test name
Test status
Simulation time 14441475 ps
CPU time 0.74 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 205736 kb
Host smart-de776b5b-8964-4a6b-996d-0156366a5c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459010163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2459010163
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3774337785
Short name T246
Test name
Test status
Simulation time 1381541129 ps
CPU time 10.59 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 233272 kb
Host smart-f3e30c27-6d7d-46fa-a13c-5c0b219f37f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774337785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3774337785
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1296532763
Short name T862
Test name
Test status
Simulation time 38825730 ps
CPU time 0.75 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 206964 kb
Host smart-89c3631b-2110-4f29-a0d6-a19019215510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296532763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1296532763
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3154041495
Short name T613
Test name
Test status
Simulation time 5979240439 ps
CPU time 56.37 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:46:28 PM PDT 24
Peak memory 266212 kb
Host smart-1284a1c3-669d-4d4a-803c-c6bf8b2d7aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154041495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3154041495
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3234669557
Short name T881
Test name
Test status
Simulation time 4058489294 ps
CPU time 84.14 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 262692 kb
Host smart-4cde971a-9d50-4162-b828-a028e35651b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234669557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3234669557
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.81946939
Short name T9
Test name
Test status
Simulation time 58704960644 ps
CPU time 95.69 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 251496 kb
Host smart-34036b01-7243-4e1b-9afa-b4a4101c0508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81946939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.81946939
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1839717781
Short name T331
Test name
Test status
Simulation time 808540788 ps
CPU time 6.1 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 236556 kb
Host smart-fb061e16-00ab-4535-83ce-02c9c76c0d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839717781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1839717781
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1812779908
Short name T139
Test name
Test status
Simulation time 3255260844 ps
CPU time 62.03 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:46:34 PM PDT 24
Peak memory 252476 kb
Host smart-81ecd137-9e00-4aea-941a-aab723b29262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812779908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1812779908
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2866169015
Short name T754
Test name
Test status
Simulation time 139264038 ps
CPU time 4.32 seconds
Started Aug 02 04:45:22 PM PDT 24
Finished Aug 02 04:45:26 PM PDT 24
Peak memory 233288 kb
Host smart-d5d3dcae-e0ef-4a2c-be59-f293db143988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866169015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2866169015
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3180537338
Short name T313
Test name
Test status
Simulation time 102977377 ps
CPU time 2.28 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 224064 kb
Host smart-81a02de2-073f-4346-b502-d670b5a9457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180537338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3180537338
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4191075389
Short name T260
Test name
Test status
Simulation time 701510642 ps
CPU time 3.89 seconds
Started Aug 02 04:45:20 PM PDT 24
Finished Aug 02 04:45:24 PM PDT 24
Peak memory 225084 kb
Host smart-3f34213b-1131-4646-a277-f9753cbfe980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191075389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4191075389
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2752197403
Short name T506
Test name
Test status
Simulation time 4272969637 ps
CPU time 6.12 seconds
Started Aug 02 04:45:24 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 233416 kb
Host smart-9c26d993-f79c-4a85-84a4-97ab25b936c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752197403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2752197403
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3754698275
Short name T1026
Test name
Test status
Simulation time 227398732 ps
CPU time 3.97 seconds
Started Aug 02 04:45:27 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 222972 kb
Host smart-c3d1f3ac-9dfa-4384-97de-bd2378670b1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754698275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3754698275
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3465320880
Short name T784
Test name
Test status
Simulation time 52667742 ps
CPU time 0.99 seconds
Started Aug 02 04:45:26 PM PDT 24
Finished Aug 02 04:45:27 PM PDT 24
Peak memory 207896 kb
Host smart-7bb6d4b8-c662-4ddf-9893-fb5e8decb737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465320880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3465320880
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.406553821
Short name T727
Test name
Test status
Simulation time 32798844628 ps
CPU time 11.33 seconds
Started Aug 02 04:45:22 PM PDT 24
Finished Aug 02 04:45:33 PM PDT 24
Peak memory 216896 kb
Host smart-e8880104-6392-4ce5-a176-c092c0211a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406553821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.406553821
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2384698583
Short name T856
Test name
Test status
Simulation time 1569668753 ps
CPU time 5.82 seconds
Started Aug 02 04:45:18 PM PDT 24
Finished Aug 02 04:45:24 PM PDT 24
Peak memory 216832 kb
Host smart-789cf760-59a4-46b0-9cfa-1b80a5d9f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384698583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2384698583
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2084565061
Short name T898
Test name
Test status
Simulation time 28779022 ps
CPU time 1.35 seconds
Started Aug 02 04:45:24 PM PDT 24
Finished Aug 02 04:45:26 PM PDT 24
Peak memory 216800 kb
Host smart-faed9544-a2db-482e-9d15-305a61f7877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084565061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2084565061
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4217975979
Short name T959
Test name
Test status
Simulation time 32019306 ps
CPU time 0.71 seconds
Started Aug 02 04:45:22 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 205928 kb
Host smart-6ece266c-0ea8-4265-99ca-04bdd3ee7d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217975979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4217975979
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3958641160
Short name T375
Test name
Test status
Simulation time 112784978 ps
CPU time 2.48 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 232912 kb
Host smart-d037d7ef-f9c1-4c0a-923f-17c60b56ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958641160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3958641160
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3738133417
Short name T448
Test name
Test status
Simulation time 13172258 ps
CPU time 0.75 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 205156 kb
Host smart-66509c96-c265-4a38-be67-edfdf2d26554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738133417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3738133417
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2648017504
Short name T477
Test name
Test status
Simulation time 128548306 ps
CPU time 2.72 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 225136 kb
Host smart-ec52c5a5-30c9-45e1-97e2-5951828a8013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648017504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2648017504
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3333988483
Short name T701
Test name
Test status
Simulation time 38062388 ps
CPU time 0.84 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 206956 kb
Host smart-055e8a4d-5711-4ec5-9138-18116342820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333988483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3333988483
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4274333566
Short name T963
Test name
Test status
Simulation time 5587435769 ps
CPU time 34.38 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 252076 kb
Host smart-5a4ae33d-c26e-4535-94e0-d006c0076013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274333566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4274333566
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2123679098
Short name T282
Test name
Test status
Simulation time 35269095172 ps
CPU time 79.83 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 253208 kb
Host smart-88aff978-1591-4886-9d68-c7617a8d5c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123679098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2123679098
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1298547424
Short name T295
Test name
Test status
Simulation time 179184269 ps
CPU time 7.38 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 233396 kb
Host smart-b8809052-2a46-47e6-ad5b-b1ead4432328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298547424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1298547424
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3192815088
Short name T525
Test name
Test status
Simulation time 6101546225 ps
CPU time 82.86 seconds
Started Aug 02 04:45:27 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 257236 kb
Host smart-e669efa3-5bbc-4249-aa9b-ebf449bf83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192815088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3192815088
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3264347847
Short name T201
Test name
Test status
Simulation time 182127369 ps
CPU time 4.7 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 233348 kb
Host smart-e6f7a1ef-d18d-4504-852e-34abfac68d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264347847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3264347847
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3924678163
Short name T1002
Test name
Test status
Simulation time 155635865 ps
CPU time 5.43 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 233416 kb
Host smart-a68826da-f13a-4e72-a599-15f3942cabb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924678163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3924678163
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3058252259
Short name T699
Test name
Test status
Simulation time 7978525591 ps
CPU time 23.53 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:54 PM PDT 24
Peak memory 225264 kb
Host smart-7c3f0291-e9d5-4d72-a68b-55182f306873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058252259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3058252259
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3290345836
Short name T481
Test name
Test status
Simulation time 277785344 ps
CPU time 3.43 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 233312 kb
Host smart-8c942e0f-5df6-4ebf-b2a2-e43d49b6bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290345836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3290345836
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4293794377
Short name T976
Test name
Test status
Simulation time 828918775 ps
CPU time 4.23 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 219024 kb
Host smart-eb0a9ae0-ddfa-4735-9e6b-0dd758cee70e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293794377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4293794377
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1860949407
Short name T670
Test name
Test status
Simulation time 39205010490 ps
CPU time 40.19 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 217244 kb
Host smart-c43fe744-4776-49de-a0b8-15f07c893fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860949407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1860949407
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1318748140
Short name T321
Test name
Test status
Simulation time 5886169037 ps
CPU time 5.62 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 217000 kb
Host smart-dfd41663-36e5-4774-97f1-026c7588ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318748140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1318748140
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1492259788
Short name T405
Test name
Test status
Simulation time 206099454 ps
CPU time 3.56 seconds
Started Aug 02 04:45:26 PM PDT 24
Finished Aug 02 04:45:29 PM PDT 24
Peak memory 216824 kb
Host smart-850733a6-1ae1-4c09-a019-f0dcf99bb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492259788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1492259788
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2696833882
Short name T663
Test name
Test status
Simulation time 78700546 ps
CPU time 0.91 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 206360 kb
Host smart-35964959-15da-4af0-98ff-65210698140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696833882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2696833882
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3423953643
Short name T236
Test name
Test status
Simulation time 9891319717 ps
CPU time 11.7 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 241632 kb
Host smart-263f5ad1-5494-4244-aea9-6cc70ab6a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423953643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3423953643
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1190474657
Short name T621
Test name
Test status
Simulation time 13427226 ps
CPU time 0.72 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 205704 kb
Host smart-97ecf2a6-b7f5-4ff9-bef2-687e336d3a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190474657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1190474657
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3070207406
Short name T378
Test name
Test status
Simulation time 108036498 ps
CPU time 3.4 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 233304 kb
Host smart-406f7fd6-ea52-430a-ab6a-960345437c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070207406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3070207406
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3148982774
Short name T776
Test name
Test status
Simulation time 20669742 ps
CPU time 0.77 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:45:29 PM PDT 24
Peak memory 205900 kb
Host smart-18d88827-1148-4645-b8af-220c8c65ddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148982774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3148982774
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1010761851
Short name T731
Test name
Test status
Simulation time 4815282118 ps
CPU time 30.51 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 253172 kb
Host smart-14718f20-ad0d-403f-a42e-9caf25dac547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010761851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1010761851
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3329436205
Short name T501
Test name
Test status
Simulation time 9526876580 ps
CPU time 81.62 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:46:54 PM PDT 24
Peak memory 253924 kb
Host smart-4bd431a5-7999-4642-b0df-868de0623035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329436205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3329436205
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.216345064
Short name T608
Test name
Test status
Simulation time 3680601372 ps
CPU time 19.37 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 249920 kb
Host smart-0b444293-fd32-4229-80bb-4344bbdec040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216345064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.216345064
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4282182098
Short name T254
Test name
Test status
Simulation time 27077587790 ps
CPU time 49.41 seconds
Started Aug 02 04:45:27 PM PDT 24
Finished Aug 02 04:46:17 PM PDT 24
Peak memory 251884 kb
Host smart-1c80fbba-2b39-4a87-9ca7-50b966f8357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282182098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4282182098
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.705962886
Short name T247
Test name
Test status
Simulation time 75171317 ps
CPU time 3.63 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 233324 kb
Host smart-2287fb35-ced7-41bd-a842-d131a18b5809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705962886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.705962886
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1450038152
Short name T521
Test name
Test status
Simulation time 8384515833 ps
CPU time 30.82 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 219620 kb
Host smart-50a05459-838e-4df7-8712-c7c14abe72ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450038152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1450038152
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3986515445
Short name T925
Test name
Test status
Simulation time 241789965 ps
CPU time 2.26 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 232976 kb
Host smart-85472972-12aa-46dc-8bc4-489a68eac398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986515445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3986515445
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.623876965
Short name T61
Test name
Test status
Simulation time 108227652 ps
CPU time 2.57 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:33 PM PDT 24
Peak memory 225076 kb
Host smart-380ab40c-f126-4740-a998-c879cd3f362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623876965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.623876965
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.652491878
Short name T404
Test name
Test status
Simulation time 117619128 ps
CPU time 4.31 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 223616 kb
Host smart-1a9204ec-7f4e-4d53-ae50-78b84a4d09e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=652491878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.652491878
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3649416458
Short name T281
Test name
Test status
Simulation time 23153186980 ps
CPU time 264.65 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:49:56 PM PDT 24
Peak memory 258100 kb
Host smart-cdb6a261-ba2c-411e-8965-30abfd5e5f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649416458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3649416458
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2742477458
Short name T427
Test name
Test status
Simulation time 2183029922 ps
CPU time 33.17 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 217068 kb
Host smart-87c94acf-81ed-4aec-87f5-2a5c57c2bcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742477458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2742477458
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3130813434
Short name T677
Test name
Test status
Simulation time 3980072214 ps
CPU time 8.69 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 216932 kb
Host smart-4235f895-3870-4d36-bba2-978e404943dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130813434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3130813434
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4078441358
Short name T306
Test name
Test status
Simulation time 523448279 ps
CPU time 1.41 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 208580 kb
Host smart-abe72036-ce36-4b6d-be2a-37cad024cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078441358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4078441358
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2268421228
Short name T717
Test name
Test status
Simulation time 92566120 ps
CPU time 0.96 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:33 PM PDT 24
Peak memory 206556 kb
Host smart-9c4906d7-bc54-43f2-8cbc-9387f31fc228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268421228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2268421228
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3984102821
Short name T809
Test name
Test status
Simulation time 1524931354 ps
CPU time 5.94 seconds
Started Aug 02 04:45:26 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 224964 kb
Host smart-7efe1122-ff44-4e22-a9d4-d7c17b5c75bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984102821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3984102821
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2888474192
Short name T26
Test name
Test status
Simulation time 26336469 ps
CPU time 0.77 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:45:33 PM PDT 24
Peak memory 205760 kb
Host smart-7dea00e1-6177-4073-830f-1b6906f9c001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888474192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2888474192
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3901032093
Short name T86
Test name
Test status
Simulation time 1114358792 ps
CPU time 3.65 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 225036 kb
Host smart-0603d4dd-31ec-43b6-bdd9-84f74af99e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901032093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3901032093
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2143847588
Short name T382
Test name
Test status
Simulation time 15882745 ps
CPU time 0.77 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 206316 kb
Host smart-d05556bf-9ec2-43c5-8e08-7d88f9332a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143847588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2143847588
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.372825381
Short name T209
Test name
Test status
Simulation time 671926472725 ps
CPU time 257.96 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:49:50 PM PDT 24
Peak memory 257416 kb
Host smart-fae5d960-822c-401c-8b16-2d0df3e0873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372825381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.372825381
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3411093897
Short name T170
Test name
Test status
Simulation time 16453171908 ps
CPU time 76.01 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 241556 kb
Host smart-5a9bf4b4-009f-4e2d-86ac-a72e2a325e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411093897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3411093897
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4003232214
Short name T348
Test name
Test status
Simulation time 228241163 ps
CPU time 4.72 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 233244 kb
Host smart-46a31089-c52f-4184-8c0b-df0e6c958c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003232214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4003232214
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1913014323
Short name T315
Test name
Test status
Simulation time 113823655 ps
CPU time 2.15 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 232896 kb
Host smart-7c31ad9d-06ea-4e55-8e46-dc4c7c709635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913014323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1913014323
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.383812648
Short name T1010
Test name
Test status
Simulation time 1408625350 ps
CPU time 20.68 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 225124 kb
Host smart-e603a205-0bd3-423d-ad4b-c425b4c5d4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383812648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.383812648
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1117427960
Short name T659
Test name
Test status
Simulation time 10056005814 ps
CPU time 11.09 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 225156 kb
Host smart-4ca64340-9141-4bda-bff4-3560cab162bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117427960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1117427960
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3467562102
Short name T545
Test name
Test status
Simulation time 20821207830 ps
CPU time 25.86 seconds
Started Aug 02 04:45:29 PM PDT 24
Finished Aug 02 04:45:55 PM PDT 24
Peak memory 233384 kb
Host smart-b3c3e1c5-759e-442f-99fd-803fc40fabd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467562102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3467562102
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.628328815
Short name T5
Test name
Test status
Simulation time 1231334240 ps
CPU time 4.61 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 224820 kb
Host smart-7cb09680-32d5-4f20-8da2-bd6e217e13de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=628328815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.628328815
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2863143637
Short name T17
Test name
Test status
Simulation time 62290194725 ps
CPU time 528.32 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 251268 kb
Host smart-8adbfdeb-3125-43db-bd5c-d96c58c64ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863143637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2863143637
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.462060173
Short name T594
Test name
Test status
Simulation time 12804047667 ps
CPU time 14.31 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 216872 kb
Host smart-c19e1807-eea2-40b9-802c-47d91a9cc721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462060173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.462060173
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.99423933
Short name T713
Test name
Test status
Simulation time 710604698 ps
CPU time 3.68 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 216920 kb
Host smart-ca62a3b8-f8d3-4872-bac7-3993e93e0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99423933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.99423933
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.368430760
Short name T449
Test name
Test status
Simulation time 126211268 ps
CPU time 2.21 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 216996 kb
Host smart-7ad30ccc-40cd-4ca6-8901-d5de36edfa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368430760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.368430760
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2455588578
Short name T431
Test name
Test status
Simulation time 151240405 ps
CPU time 0.93 seconds
Started Aug 02 04:45:28 PM PDT 24
Finished Aug 02 04:45:29 PM PDT 24
Peak memory 206496 kb
Host smart-2af3d22d-65c2-4930-818b-0c7a49627e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455588578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2455588578
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1089056037
Short name T207
Test name
Test status
Simulation time 9057782445 ps
CPU time 14.84 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 230024 kb
Host smart-71df4fd7-5df1-46b7-b1f2-65a7b4851a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089056037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1089056037
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.563166111
Short name T343
Test name
Test status
Simulation time 14320781 ps
CPU time 0.72 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:45:47 PM PDT 24
Peak memory 206300 kb
Host smart-ede1cf3d-ba0f-4c92-887b-7a2c0751a963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563166111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.563166111
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3511792127
Short name T634
Test name
Test status
Simulation time 44376731 ps
CPU time 2.51 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 225204 kb
Host smart-c1b3da72-7b23-4c6f-8d77-ff556e0ca77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511792127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3511792127
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3379779362
Short name T939
Test name
Test status
Simulation time 13401809 ps
CPU time 0.79 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 207036 kb
Host smart-9b662449-07d1-42bd-af65-0e52fce674a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379779362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3379779362
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.67208695
Short name T693
Test name
Test status
Simulation time 29335813079 ps
CPU time 193.78 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 254636 kb
Host smart-f5b9ffb5-e664-4d36-a094-99848a6fa0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67208695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.67208695
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3385948762
Short name T268
Test name
Test status
Simulation time 178546606627 ps
CPU time 199.25 seconds
Started Aug 02 04:45:41 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 257996 kb
Host smart-b6eb8ece-1f3d-4905-88e4-2a5b16db9964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385948762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3385948762
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4284109209
Short name T453
Test name
Test status
Simulation time 14171516053 ps
CPU time 84.69 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:46:58 PM PDT 24
Peak memory 253748 kb
Host smart-f8088d1c-1964-4e0b-ac5a-77b0ec9a40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284109209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4284109209
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4169221750
Short name T473
Test name
Test status
Simulation time 2034860225 ps
CPU time 10.8 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 250552 kb
Host smart-f7952c48-d55c-4e79-98d4-cbc6ec2b5bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169221750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4169221750
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3736214128
Short name T748
Test name
Test status
Simulation time 34745063235 ps
CPU time 90.44 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 268240 kb
Host smart-1761cb4b-683d-48b7-b0e3-f0ed28f46d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736214128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3736214128
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1712130254
Short name T777
Test name
Test status
Simulation time 1339844552 ps
CPU time 3.91 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 225272 kb
Host smart-b8e4f206-36b2-46ff-9714-4b6472439f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712130254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1712130254
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.627375809
Short name T750
Test name
Test status
Simulation time 15616282239 ps
CPU time 41.73 seconds
Started Aug 02 04:45:33 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 233472 kb
Host smart-fb3b74f8-30ed-421b-845f-acb593f9990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627375809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.627375809
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1053656062
Short name T548
Test name
Test status
Simulation time 1266844048 ps
CPU time 4.62 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 233460 kb
Host smart-df57be1e-147e-45c9-9518-d5d1f973e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053656062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1053656062
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.692804727
Short name T244
Test name
Test status
Simulation time 11982678746 ps
CPU time 5.11 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 225204 kb
Host smart-aba2edce-765a-403d-b3e7-ef08dbd11935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692804727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.692804727
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3986648530
Short name T814
Test name
Test status
Simulation time 759404994 ps
CPU time 3.91 seconds
Started Aug 02 04:45:30 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 221000 kb
Host smart-5f06306f-a360-4353-9bea-3134f539597d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986648530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3986648530
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2317465320
Short name T32
Test name
Test status
Simulation time 57693909786 ps
CPU time 493.91 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:53:52 PM PDT 24
Peak memory 271132 kb
Host smart-f280121b-8adf-455f-950d-3ff70b2e64b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317465320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2317465320
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3601282141
Short name T1021
Test name
Test status
Simulation time 4536720198 ps
CPU time 23.66 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:45:58 PM PDT 24
Peak memory 220480 kb
Host smart-89e2326d-1c13-4e4b-83a0-a803421c418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601282141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3601282141
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2537686951
Short name T880
Test name
Test status
Simulation time 2713007524 ps
CPU time 4.12 seconds
Started Aug 02 04:45:32 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 216888 kb
Host smart-7c6fabdf-686b-440c-acd3-b5db53555bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537686951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2537686951
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3123639642
Short name T29
Test name
Test status
Simulation time 29156416 ps
CPU time 0.72 seconds
Started Aug 02 04:45:31 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 206008 kb
Host smart-244f496f-50e9-45cb-ad83-8caf45417e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123639642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3123639642
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.532896890
Short name T526
Test name
Test status
Simulation time 58009659 ps
CPU time 0.9 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 207568 kb
Host smart-e89f62c2-4580-4df5-8f19-e7c74d171284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532896890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.532896890
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4131972195
Short name T399
Test name
Test status
Simulation time 518974317 ps
CPU time 7.23 seconds
Started Aug 02 04:45:34 PM PDT 24
Finished Aug 02 04:45:41 PM PDT 24
Peak memory 233240 kb
Host smart-1a07682a-88be-4ca0-83c8-e52acc464697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131972195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4131972195
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2808065811
Short name T944
Test name
Test status
Simulation time 33121632 ps
CPU time 0.69 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 205688 kb
Host smart-e768e604-98cf-4fda-9c1e-a9080ea27975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808065811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2808065811
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2130821926
Short name T89
Test name
Test status
Simulation time 431137816 ps
CPU time 3.82 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:41 PM PDT 24
Peak memory 225120 kb
Host smart-f54a9758-cd0e-41a7-84c1-dcb4e6c38a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130821926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2130821926
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2751003955
Short name T837
Test name
Test status
Simulation time 67441708 ps
CPU time 0.8 seconds
Started Aug 02 04:45:36 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 206952 kb
Host smart-fd054b08-2249-44a8-9aab-563d8999c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751003955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2751003955
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.640507745
Short name T893
Test name
Test status
Simulation time 59810622 ps
CPU time 0.78 seconds
Started Aug 02 04:45:39 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 216252 kb
Host smart-f023a1e2-6124-43ca-9280-17ee109f0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640507745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.640507745
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3447425308
Short name T147
Test name
Test status
Simulation time 91046948802 ps
CPU time 233.02 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:49:39 PM PDT 24
Peak memory 266252 kb
Host smart-23f98c86-fde6-416d-b70a-d899a889431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447425308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3447425308
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1982028318
Short name T373
Test name
Test status
Simulation time 26206148635 ps
CPU time 182.67 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:48:41 PM PDT 24
Peak memory 256528 kb
Host smart-170268e5-a427-459d-b326-259461c4beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982028318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1982028318
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.638018528
Short name T290
Test name
Test status
Simulation time 2050914591 ps
CPU time 9.86 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 225104 kb
Host smart-273b2c63-703b-438c-b8dd-baffd7cdf4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638018528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.638018528
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1550646382
Short name T779
Test name
Test status
Simulation time 67750033063 ps
CPU time 97.41 seconds
Started Aug 02 04:45:45 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 253996 kb
Host smart-cb78117b-8182-440f-8a0a-3d3e38b0b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550646382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1550646382
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1289464833
Short name T400
Test name
Test status
Simulation time 162460528 ps
CPU time 3.75 seconds
Started Aug 02 04:45:36 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 225040 kb
Host smart-b0195b5e-3877-4dd4-9f4c-1c4d090a391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289464833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1289464833
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2138301250
Short name T499
Test name
Test status
Simulation time 1647587644 ps
CPU time 15.13 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 233304 kb
Host smart-5edf1dbe-f08e-4a35-8e5b-f12f2e4ab8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138301250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2138301250
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3731671746
Short name T611
Test name
Test status
Simulation time 340660681 ps
CPU time 2.23 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 232892 kb
Host smart-3b733ab0-de1c-4c82-92e8-eb97b1cf5661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731671746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3731671746
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3102308859
Short name T749
Test name
Test status
Simulation time 2876125773 ps
CPU time 7.81 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 239104 kb
Host smart-5bdd79fb-cea8-4c0e-a73d-89b51ec034ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102308859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3102308859
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3318554684
Short name T891
Test name
Test status
Simulation time 1960787771 ps
CPU time 8.15 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:45:46 PM PDT 24
Peak memory 220824 kb
Host smart-1f580419-e76c-4b4f-838b-644010b8ab61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3318554684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3318554684
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1922260265
Short name T191
Test name
Test status
Simulation time 154030806119 ps
CPU time 602.35 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 282808 kb
Host smart-09b49960-15ad-46b6-853b-5111f16f4e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922260265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1922260265
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2085831652
Short name T298
Test name
Test status
Simulation time 4268958366 ps
CPU time 9.57 seconds
Started Aug 02 04:45:41 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 216844 kb
Host smart-c3755004-969d-43ad-a28a-06f90f89f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085831652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2085831652
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3347060711
Short name T646
Test name
Test status
Simulation time 22045620 ps
CPU time 0.7 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 206020 kb
Host smart-4fa8b653-cd59-4ab6-b286-23e5ac0f6951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347060711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3347060711
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.60151861
Short name T718
Test name
Test status
Simulation time 25263685 ps
CPU time 0.85 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 206968 kb
Host smart-0a749642-cc22-44c5-b745-8e738822cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60151861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.60151861
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.76525431
Short name T774
Test name
Test status
Simulation time 160110631 ps
CPU time 1.1 seconds
Started Aug 02 04:45:42 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 206444 kb
Host smart-bf48d754-b457-4198-ae10-27b9427d6b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76525431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.76525431
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1506688029
Short name T74
Test name
Test status
Simulation time 202339788 ps
CPU time 2.44 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 225032 kb
Host smart-8e07d2ea-a714-4669-8e47-db9362832833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506688029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1506688029
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3870817102
Short name T1022
Test name
Test status
Simulation time 13887118 ps
CPU time 0.7 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 205896 kb
Host smart-dd0a0e3c-a20c-4518-b93e-d8e08ab8cae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870817102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3870817102
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2229797852
Short name T1031
Test name
Test status
Simulation time 1981296845 ps
CPU time 5.69 seconds
Started Aug 02 04:45:42 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 233368 kb
Host smart-db361beb-7ba1-4b86-9299-901767657e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229797852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2229797852
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1492308462
Short name T340
Test name
Test status
Simulation time 61255976 ps
CPU time 0.77 seconds
Started Aug 02 04:45:42 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 206904 kb
Host smart-3420e5a2-b7a5-4a57-a6a0-3d12fd311592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492308462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1492308462
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3461944543
Short name T609
Test name
Test status
Simulation time 6452102526 ps
CPU time 46.05 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 249848 kb
Host smart-c82c55c2-eb61-4d88-a151-f38ad543b824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461944543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3461944543
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2469637580
Short name T753
Test name
Test status
Simulation time 3303304243 ps
CPU time 24.65 seconds
Started Aug 02 04:45:40 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 249756 kb
Host smart-8fe3c6a0-05ad-4e2c-a4c7-6a54c898af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469637580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2469637580
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1399382924
Short name T916
Test name
Test status
Simulation time 16382795629 ps
CPU time 173.91 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 252320 kb
Host smart-4efcec15-8d7b-449b-9732-09e9ddfeca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399382924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1399382924
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.99416140
Short name T964
Test name
Test status
Simulation time 135707228 ps
CPU time 5.81 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 237556 kb
Host smart-93489ea4-1c02-425f-9dba-53a5e40a9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99416140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.99416140
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3279721701
Short name T250
Test name
Test status
Simulation time 15827769413 ps
CPU time 90.44 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 256420 kb
Host smart-910b90f9-aa1a-4a0e-833f-6d5b99d7dea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279721701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3279721701
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.663816064
Short name T1008
Test name
Test status
Simulation time 34681249 ps
CPU time 2.56 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:40 PM PDT 24
Peak memory 233016 kb
Host smart-29acee7f-4815-41fe-a06e-68ae217101f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663816064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.663816064
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3047220297
Short name T266
Test name
Test status
Simulation time 10576547809 ps
CPU time 98.6 seconds
Started Aug 02 04:45:38 PM PDT 24
Finished Aug 02 04:47:17 PM PDT 24
Peak memory 234468 kb
Host smart-4aeaa39f-4a81-431c-9f5a-e1ee99b2c568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047220297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3047220297
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1580402175
Short name T289
Test name
Test status
Simulation time 2111280628 ps
CPU time 10.01 seconds
Started Aug 02 04:45:39 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 234436 kb
Host smart-581266de-df40-41d6-ae19-5db3ea39a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580402175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1580402175
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2335272014
Short name T192
Test name
Test status
Simulation time 372595703 ps
CPU time 2.37 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:39 PM PDT 24
Peak memory 225220 kb
Host smart-7afdca28-ac30-4c38-95a6-914c0a5add15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335272014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2335272014
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.605910227
Short name T438
Test name
Test status
Simulation time 650987608 ps
CPU time 9.31 seconds
Started Aug 02 04:45:36 PM PDT 24
Finished Aug 02 04:45:46 PM PDT 24
Peak memory 222520 kb
Host smart-a21188d4-218b-419b-bef8-e51dbd9dc182
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605910227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.605910227
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3756726886
Short name T802
Test name
Test status
Simulation time 48307657 ps
CPU time 1.03 seconds
Started Aug 02 04:45:42 PM PDT 24
Finished Aug 02 04:45:43 PM PDT 24
Peak memory 208004 kb
Host smart-d9399f99-b662-402c-9813-287148f1c36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756726886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3756726886
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3780934271
Short name T475
Test name
Test status
Simulation time 4790226910 ps
CPU time 23.83 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 216936 kb
Host smart-6ccf38da-7b63-4ff1-8443-8890b5adb91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780934271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3780934271
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2604392354
Short name T372
Test name
Test status
Simulation time 2734936093 ps
CPU time 6.66 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:45:56 PM PDT 24
Peak memory 216964 kb
Host smart-16b0e969-be8c-4a62-ae89-01d4e269b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604392354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2604392354
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3364065994
Short name T459
Test name
Test status
Simulation time 55182546 ps
CPU time 0.85 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 206408 kb
Host smart-ccc6bfad-791e-4597-b3fe-b36aa4015bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364065994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3364065994
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3528511743
Short name T83
Test name
Test status
Simulation time 48288819 ps
CPU time 0.86 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 206456 kb
Host smart-caf9ddd8-d6c7-480d-8c5b-2e7cb3858490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528511743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3528511743
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3435862385
Short name T690
Test name
Test status
Simulation time 1716207009 ps
CPU time 4.05 seconds
Started Aug 02 04:45:43 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 233296 kb
Host smart-8d3c2aa2-b5ca-45c6-a8e5-36e4cf638639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435862385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3435862385
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2265493543
Short name T436
Test name
Test status
Simulation time 12754319 ps
CPU time 0.75 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 205692 kb
Host smart-25537679-9df4-4a5b-8fb3-98ce0d9a9621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265493543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2265493543
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1633766315
Short name T623
Test name
Test status
Simulation time 6442149471 ps
CPU time 13.74 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:45:58 PM PDT 24
Peak memory 233372 kb
Host smart-a6e2a47e-44bc-49c6-9381-d645e731c1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633766315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1633766315
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1819636522
Short name T62
Test name
Test status
Simulation time 19951129 ps
CPU time 0.78 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 207032 kb
Host smart-b9bfbfa8-5477-4bd3-b464-16c25f2f6adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819636522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1819636522
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3278095427
Short name T463
Test name
Test status
Simulation time 2404406917 ps
CPU time 10.67 seconds
Started Aug 02 04:45:45 PM PDT 24
Finished Aug 02 04:45:56 PM PDT 24
Peak memory 225404 kb
Host smart-53f038f8-6509-4d7d-b6b2-6d41aa6b6938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278095427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3278095427
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4217755847
Short name T136
Test name
Test status
Simulation time 22840218450 ps
CPU time 113.24 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 258000 kb
Host smart-696aa9ca-c660-46ba-b3a8-2c59ae3f284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217755847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4217755847
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.301047255
Short name T931
Test name
Test status
Simulation time 3824698619 ps
CPU time 27.72 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:46:17 PM PDT 24
Peak memory 233320 kb
Host smart-57ae3001-520b-4181-ac41-56e40aa6863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301047255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.301047255
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2535289286
Short name T729
Test name
Test status
Simulation time 126888561547 ps
CPU time 181.67 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:48:50 PM PDT 24
Peak memory 241556 kb
Host smart-ac8232c4-5968-4a75-b4ab-c867b2ff0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535289286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2535289286
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1562642568
Short name T593
Test name
Test status
Simulation time 169549068 ps
CPU time 2.93 seconds
Started Aug 02 04:45:35 PM PDT 24
Finished Aug 02 04:45:38 PM PDT 24
Peak memory 225108 kb
Host smart-b118668d-27b3-4099-afed-eb83de2969a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562642568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1562642568
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3320927744
Short name T429
Test name
Test status
Simulation time 12619959194 ps
CPU time 64.09 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 240700 kb
Host smart-80329849-b6df-422e-b167-53e9c551bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320927744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3320927744
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2446235185
Short name T428
Test name
Test status
Simulation time 61984691 ps
CPU time 2.2 seconds
Started Aug 02 04:45:42 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 232908 kb
Host smart-2494c12c-c1fb-46d8-81fe-46d747a56b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446235185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2446235185
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.988071500
Short name T843
Test name
Test status
Simulation time 72097798 ps
CPU time 2.05 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 224264 kb
Host smart-76117b63-eae1-4259-b03c-82b28b268ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988071500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.988071500
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2429190625
Short name T697
Test name
Test status
Simulation time 719357529 ps
CPU time 4.36 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 223024 kb
Host smart-d056c117-b3c5-4365-a485-60689a408235
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429190625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2429190625
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4175995637
Short name T34
Test name
Test status
Simulation time 44615984229 ps
CPU time 119.22 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 249792 kb
Host smart-bb55cb97-5e5a-4173-86fc-123d26ec3925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175995637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4175995637
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.868280205
Short name T344
Test name
Test status
Simulation time 14044779 ps
CPU time 0.75 seconds
Started Aug 02 04:45:43 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 206176 kb
Host smart-81b37827-2158-4c7b-aa0b-70439df33c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868280205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.868280205
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.592777052
Short name T961
Test name
Test status
Simulation time 2167121677 ps
CPU time 5.1 seconds
Started Aug 02 04:45:39 PM PDT 24
Finished Aug 02 04:45:44 PM PDT 24
Peak memory 216780 kb
Host smart-4845f470-8a0f-430e-b07f-0460989f3410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592777052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.592777052
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1234488428
Short name T680
Test name
Test status
Simulation time 452474491 ps
CPU time 5.01 seconds
Started Aug 02 04:45:37 PM PDT 24
Finished Aug 02 04:45:42 PM PDT 24
Peak memory 216924 kb
Host smart-d16bf9c5-8315-41e2-a021-7c4f41249ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234488428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1234488428
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2548867306
Short name T1015
Test name
Test status
Simulation time 17471502 ps
CPU time 0.79 seconds
Started Aug 02 04:45:53 PM PDT 24
Finished Aug 02 04:45:54 PM PDT 24
Peak memory 206488 kb
Host smart-9639f6aa-ba5f-4100-81d2-57b8105d70b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548867306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2548867306
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3484325603
Short name T235
Test name
Test status
Simulation time 12535938008 ps
CPU time 21.37 seconds
Started Aug 02 04:45:44 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 249744 kb
Host smart-d378d5d6-1490-4640-9f76-b1413f93663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484325603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3484325603
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4094742421
Short name T64
Test name
Test status
Simulation time 13975036 ps
CPU time 0.72 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 205816 kb
Host smart-985c6ae8-ecae-42bc-afac-716f7f93a6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094742421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
094742421
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3682448743
Short name T88
Test name
Test status
Simulation time 5603649379 ps
CPU time 8.59 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 233340 kb
Host smart-d6a23022-862a-4f0b-b7b0-66bc4868bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682448743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3682448743
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1198651559
Short name T403
Test name
Test status
Simulation time 14669987 ps
CPU time 0.73 seconds
Started Aug 02 04:42:55 PM PDT 24
Finished Aug 02 04:42:56 PM PDT 24
Peak memory 206200 kb
Host smart-495dec06-de8a-405c-9615-1cdd77a42a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198651559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1198651559
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.277452597
Short name T661
Test name
Test status
Simulation time 137136239553 ps
CPU time 78.65 seconds
Started Aug 02 04:43:03 PM PDT 24
Finished Aug 02 04:44:22 PM PDT 24
Peak memory 249988 kb
Host smart-d2c12515-77a4-4c55-a63b-75c324b0ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277452597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.277452597
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1323821899
Short name T720
Test name
Test status
Simulation time 3572860286 ps
CPU time 22.27 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 241720 kb
Host smart-42f4a28a-e2b4-4eb8-9dc6-818abe10b6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323821899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1323821899
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2832655283
Short name T707
Test name
Test status
Simulation time 4945128302 ps
CPU time 37.35 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:43 PM PDT 24
Peak memory 249800 kb
Host smart-dda01302-2f93-4732-879d-04020757cf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832655283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2832655283
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3673781677
Short name T354
Test name
Test status
Simulation time 2093788733 ps
CPU time 6.53 seconds
Started Aug 02 04:43:11 PM PDT 24
Finished Aug 02 04:43:17 PM PDT 24
Peak memory 225176 kb
Host smart-1876a5f4-e070-47e7-9667-1fca4fb7374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673781677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3673781677
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3375429593
Short name T541
Test name
Test status
Simulation time 5196687721 ps
CPU time 34.33 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 249748 kb
Host smart-196218a1-27a2-4056-952b-d966e0fcdc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375429593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3375429593
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4226864229
Short name T831
Test name
Test status
Simulation time 1677820032 ps
CPU time 9.67 seconds
Started Aug 02 04:43:06 PM PDT 24
Finished Aug 02 04:43:15 PM PDT 24
Peak memory 233276 kb
Host smart-69554b65-e0ad-45d0-ad55-d124a5658166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226864229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4226864229
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.157697132
Short name T780
Test name
Test status
Simulation time 1495402030 ps
CPU time 15.94 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 225156 kb
Host smart-6a095bc3-4ad9-483f-839a-3effb983ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157697132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.157697132
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.206392285
Short name T37
Test name
Test status
Simulation time 26949192 ps
CPU time 1.07 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 217136 kb
Host smart-f195e07d-0269-4310-bac5-1d5009a3b828
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206392285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.206392285
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1235639633
Short name T536
Test name
Test status
Simulation time 14256683456 ps
CPU time 8.05 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225224 kb
Host smart-5c2a6579-611b-4957-8374-1d2b7506451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235639633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1235639633
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.147992009
Short name T384
Test name
Test status
Simulation time 3850387364 ps
CPU time 3.9 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 233488 kb
Host smart-24320a31-0bd1-40fa-bdbc-5fdc2d22e31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147992009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.147992009
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3437643629
Short name T385
Test name
Test status
Simulation time 455512706 ps
CPU time 4.19 seconds
Started Aug 02 04:43:03 PM PDT 24
Finished Aug 02 04:43:07 PM PDT 24
Peak memory 223808 kb
Host smart-59734677-5ef1-45de-85ec-5b40e4f65dfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3437643629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3437643629
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2881150470
Short name T283
Test name
Test status
Simulation time 9839904149 ps
CPU time 191.45 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:46:18 PM PDT 24
Peak memory 268280 kb
Host smart-3d8342f2-dab6-4559-b13c-56ecaa803c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881150470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2881150470
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.920534169
Short name T912
Test name
Test status
Simulation time 13337992317 ps
CPU time 20.01 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:43:28 PM PDT 24
Peak memory 216812 kb
Host smart-9e598a67-9b64-45c2-a96d-a2dfe853d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920534169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.920534169
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2846832191
Short name T572
Test name
Test status
Simulation time 32288474808 ps
CPU time 20.03 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:30 PM PDT 24
Peak memory 216896 kb
Host smart-745a7295-49bb-4a53-aabf-121ebf7c7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846832191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2846832191
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2531636344
Short name T972
Test name
Test status
Simulation time 101337995 ps
CPU time 0.86 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 207416 kb
Host smart-128a09ca-fafb-4fc0-a73c-5df44af2ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531636344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2531636344
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1313097937
Short name T936
Test name
Test status
Simulation time 121116720 ps
CPU time 0.9 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 206460 kb
Host smart-55d2b4c9-6c91-40ae-b79f-78278bc62356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313097937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1313097937
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1920501480
Short name T491
Test name
Test status
Simulation time 3521207526 ps
CPU time 6.19 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:43:10 PM PDT 24
Peak memory 233344 kb
Host smart-818f5adc-f6c5-4190-86d5-334659b53335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920501480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1920501480
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.225295749
Short name T648
Test name
Test status
Simulation time 40511267 ps
CPU time 0.72 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 205760 kb
Host smart-6158884f-c2a8-4a46-a09a-dda35992ff55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225295749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.225295749
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3585014591
Short name T876
Test name
Test status
Simulation time 253806720 ps
CPU time 3.57 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 225324 kb
Host smart-89404d72-9e6b-4923-b932-d1c1e30b96b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585014591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3585014591
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3342064250
Short name T397
Test name
Test status
Simulation time 18745829 ps
CPU time 0.8 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 207164 kb
Host smart-9a8dd2d0-333d-46e3-ab96-bcf88a077dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342064250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3342064250
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3460775049
Short name T42
Test name
Test status
Simulation time 19501929458 ps
CPU time 128.52 seconds
Started Aug 02 04:43:13 PM PDT 24
Finished Aug 02 04:45:22 PM PDT 24
Peak memory 256556 kb
Host smart-1b3996db-3c5a-440e-8ba8-cb3f023fd010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460775049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3460775049
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3837885686
Short name T210
Test name
Test status
Simulation time 8481648126 ps
CPU time 58.09 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 251332 kb
Host smart-aea9fca4-2989-40e0-bff8-6698a0e3f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837885686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3837885686
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.559033442
Short name T454
Test name
Test status
Simulation time 7249144105 ps
CPU time 121.62 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:45:11 PM PDT 24
Peak memory 254972 kb
Host smart-0798ec6f-8531-4f51-9282-c5b9588b20ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559033442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
559033442
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3421726758
Short name T293
Test name
Test status
Simulation time 2729698722 ps
CPU time 47.31 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:52 PM PDT 24
Peak memory 249716 kb
Host smart-a6f604d4-830e-440d-a3e7-c17ab10b1b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421726758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3421726758
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2233708031
Short name T227
Test name
Test status
Simulation time 57882665686 ps
CPU time 46.68 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 249852 kb
Host smart-791d55b6-4caa-4d2a-b0c5-41934495c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233708031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2233708031
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3328608121
Short name T569
Test name
Test status
Simulation time 5983326528 ps
CPU time 22.09 seconds
Started Aug 02 04:43:02 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 233392 kb
Host smart-ee9c7187-4c74-4c75-9fca-85aabaa2c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328608121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3328608121
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2815906917
Short name T248
Test name
Test status
Simulation time 737640711 ps
CPU time 3.17 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 225068 kb
Host smart-770716b0-2ac4-460e-855a-adf868dfd195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815906917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2815906917
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.114942104
Short name T742
Test name
Test status
Simulation time 57164074 ps
CPU time 1.1 seconds
Started Aug 02 04:43:03 PM PDT 24
Finished Aug 02 04:43:04 PM PDT 24
Peak memory 217244 kb
Host smart-36c4b0b2-b780-49a1-a032-b19a6a3813d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114942104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.114942104
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1305468843
Short name T199
Test name
Test status
Simulation time 81989335 ps
CPU time 3.74 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 233360 kb
Host smart-20fbdc71-6512-4ee7-bdc8-0093b8a8f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305468843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1305468843
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3981178159
Short name T407
Test name
Test status
Simulation time 5015306450 ps
CPU time 5.93 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225076 kb
Host smart-68a61147-fd70-4ad1-9e06-990c5b67b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981178159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3981178159
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4152364606
Short name T151
Test name
Test status
Simulation time 954277581 ps
CPU time 8.25 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:18 PM PDT 24
Peak memory 222472 kb
Host smart-2e2eb866-29ed-441b-abe1-8bd5db5fd90e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152364606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4152364606
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4068170079
Short name T517
Test name
Test status
Simulation time 131758260602 ps
CPU time 327.74 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 264576 kb
Host smart-a5f7d596-4a95-4ae1-be1a-91663a512173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068170079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4068170079
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3396894138
Short name T953
Test name
Test status
Simulation time 9012205503 ps
CPU time 18.92 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 217012 kb
Host smart-88757ef2-c507-44b7-8e1c-0f7ea53584f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396894138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3396894138
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3572932741
Short name T538
Test name
Test status
Simulation time 18941725 ps
CPU time 0.69 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 206036 kb
Host smart-179ee125-662a-4f9b-89bd-3b030e5660f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572932741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3572932741
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3777176006
Short name T422
Test name
Test status
Simulation time 58991714 ps
CPU time 0.75 seconds
Started Aug 02 04:43:03 PM PDT 24
Finished Aug 02 04:43:04 PM PDT 24
Peak memory 206416 kb
Host smart-3c72729e-12ed-4de9-aa02-700828acbc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777176006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3777176006
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2468253824
Short name T318
Test name
Test status
Simulation time 50502680 ps
CPU time 0.74 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 206448 kb
Host smart-e7c3ca21-e2a2-40a3-973f-509ac57107b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468253824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2468253824
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.741979223
Short name T543
Test name
Test status
Simulation time 36556771937 ps
CPU time 34.1 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 249768 kb
Host smart-fe5a77dd-f710-4816-a689-52919ea849f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741979223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.741979223
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3513802036
Short name T402
Test name
Test status
Simulation time 29436371 ps
CPU time 0.73 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:43:05 PM PDT 24
Peak memory 205172 kb
Host smart-6bb99df2-0a02-4e41-a7f2-c217ab1efee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513802036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
513802036
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4099837422
Short name T904
Test name
Test status
Simulation time 9290105112 ps
CPU time 21.32 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:31 PM PDT 24
Peak memory 225196 kb
Host smart-bd7b57ce-5681-4df4-bb46-4d06895e5352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099837422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4099837422
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1756387039
Short name T993
Test name
Test status
Simulation time 12137609 ps
CPU time 0.75 seconds
Started Aug 02 04:43:06 PM PDT 24
Finished Aug 02 04:43:07 PM PDT 24
Peak memory 205944 kb
Host smart-329f9565-bce4-44f2-aa29-388f89e58a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756387039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1756387039
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.368860369
Short name T271
Test name
Test status
Simulation time 55092034362 ps
CPU time 189.66 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:46:20 PM PDT 24
Peak memory 257892 kb
Host smart-7a117d4d-f564-4fdd-a537-aaccfadbe5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368860369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.368860369
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1735718960
Short name T60
Test name
Test status
Simulation time 48599797097 ps
CPU time 46.97 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 254820 kb
Host smart-bea863c5-154f-43d3-80ae-d72714d5b2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735718960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1735718960
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3759778842
Short name T979
Test name
Test status
Simulation time 63691694043 ps
CPU time 597.24 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:53:07 PM PDT 24
Peak memory 265636 kb
Host smart-47772f93-bb41-47f3-9c1c-8b9f025f286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759778842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3759778842
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4042542481
Short name T586
Test name
Test status
Simulation time 4975378766 ps
CPU time 20.02 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:43:28 PM PDT 24
Peak memory 241020 kb
Host smart-8aeac763-79bf-4fb9-8176-f88b380bc700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042542481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4042542481
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1790471973
Short name T587
Test name
Test status
Simulation time 120340850434 ps
CPU time 149.74 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:45:34 PM PDT 24
Peak memory 241584 kb
Host smart-5124d368-223f-4082-b4c1-87085cc7c5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790471973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1790471973
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4004713718
Short name T807
Test name
Test status
Simulation time 353065557 ps
CPU time 3.86 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 233252 kb
Host smart-d8f98a81-4080-4228-9bbd-449545ee5ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004713718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4004713718
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3753082496
Short name T240
Test name
Test status
Simulation time 3679326497 ps
CPU time 16.6 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 241440 kb
Host smart-5ec16836-941b-445b-96cf-0a0e501e9326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753082496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3753082496
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.646794434
Short name T398
Test name
Test status
Simulation time 86420198 ps
CPU time 1.02 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 217112 kb
Host smart-546729af-1291-4f23-a74a-9237b11b3a87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646794434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.646794434
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.744189796
Short name T688
Test name
Test status
Simulation time 34858903 ps
CPU time 2.31 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 233320 kb
Host smart-79d01c47-0e16-4ebf-99a2-93eec828691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744189796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
744189796
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2929375232
Short name T691
Test name
Test status
Simulation time 232657963 ps
CPU time 3.31 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 225192 kb
Host smart-f369ee79-bca3-47cc-baa2-9808a5abfdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929375232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2929375232
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2415347662
Short name T487
Test name
Test status
Simulation time 295786784 ps
CPU time 6.31 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 222676 kb
Host smart-8e347a2a-7cb9-45d6-a566-670ad0b16ea8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2415347662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2415347662
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1587469380
Short name T497
Test name
Test status
Simulation time 262932880 ps
CPU time 1.14 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 208164 kb
Host smart-06d6a4c9-8744-41de-b37f-4761de47eb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587469380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1587469380
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.132261077
Short name T437
Test name
Test status
Simulation time 76652858238 ps
CPU time 26.92 seconds
Started Aug 02 04:43:03 PM PDT 24
Finished Aug 02 04:43:30 PM PDT 24
Peak memory 216948 kb
Host smart-30e9156b-3446-4b8b-b23b-5d3c37256aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132261077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.132261077
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4216799856
Short name T512
Test name
Test status
Simulation time 17515933063 ps
CPU time 4.69 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:15 PM PDT 24
Peak memory 216920 kb
Host smart-5669cf31-f118-4856-be40-efa7a4014b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216799856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4216799856
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1899207903
Short name T394
Test name
Test status
Simulation time 204557163 ps
CPU time 2.94 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:08 PM PDT 24
Peak memory 216840 kb
Host smart-4bbb9e20-738b-465c-8d7a-0cc8c650a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899207903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1899207903
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4203844164
Short name T588
Test name
Test status
Simulation time 324705918 ps
CPU time 0.94 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:43:05 PM PDT 24
Peak memory 206608 kb
Host smart-98d83125-e6ef-488f-aad9-34610d08efbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203844164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4203844164
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.804578543
Short name T969
Test name
Test status
Simulation time 40832626 ps
CPU time 2.63 seconds
Started Aug 02 04:43:04 PM PDT 24
Finished Aug 02 04:43:07 PM PDT 24
Peak memory 224736 kb
Host smart-13111809-70ee-4afe-8c47-26a553a20f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804578543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.804578543
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3691189631
Short name T606
Test name
Test status
Simulation time 38778937 ps
CPU time 0.79 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 205204 kb
Host smart-8880c1e7-e0b8-44a8-8378-41d2e70454db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691189631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
691189631
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4083848086
Short name T579
Test name
Test status
Simulation time 1031751187 ps
CPU time 7.58 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:17 PM PDT 24
Peak memory 233252 kb
Host smart-8a520bf8-52ba-4a9c-b8bd-37dd6c568a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083848086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4083848086
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.606853799
Short name T605
Test name
Test status
Simulation time 16566271 ps
CPU time 0.77 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 207024 kb
Host smart-5726bd07-e947-46aa-bee1-52606d193d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606853799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.606853799
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.170254149
Short name T943
Test name
Test status
Simulation time 1815755735 ps
CPU time 30.37 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 257836 kb
Host smart-a0a65375-a7ec-4848-bcb0-f335e4ca19a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170254149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.170254149
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2759434629
Short name T601
Test name
Test status
Simulation time 14814534443 ps
CPU time 141.55 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:45:30 PM PDT 24
Peak memory 255160 kb
Host smart-363fa65d-0346-4b96-a974-a71758b965bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759434629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2759434629
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2755150254
Short name T144
Test name
Test status
Simulation time 3421662226 ps
CPU time 34.3 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:44 PM PDT 24
Peak memory 240576 kb
Host smart-81bf62be-2709-4dfd-9290-82f2a550462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755150254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2755150254
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3292971378
Short name T169
Test name
Test status
Simulation time 1825135136 ps
CPU time 9.43 seconds
Started Aug 02 04:43:06 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 233400 kb
Host smart-77e120e6-f7dd-46b5-805f-101e0115d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292971378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3292971378
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3447190035
Short name T919
Test name
Test status
Simulation time 749323395 ps
CPU time 4.01 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 225176 kb
Host smart-49deba05-ce08-4a6f-ad2a-291f41f9df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447190035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3447190035
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.109530318
Short name T257
Test name
Test status
Simulation time 7698925848 ps
CPU time 99.63 seconds
Started Aug 02 04:43:07 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 225292 kb
Host smart-af0617cd-266a-4f94-8a57-5f0a3fd8f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109530318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.109530318
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.35850773
Short name T960
Test name
Test status
Simulation time 32442382 ps
CPU time 1.06 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 218396 kb
Host smart-ea422b0d-d55b-4d19-9619-2cc77b884f8d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.35850773
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2069746914
Short name T791
Test name
Test status
Simulation time 2157169844 ps
CPU time 8.03 seconds
Started Aug 02 04:43:06 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 241416 kb
Host smart-157c0e42-d0ea-4685-9722-9c932d7cc0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069746914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2069746914
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3768117730
Short name T433
Test name
Test status
Simulation time 29784262 ps
CPU time 2.1 seconds
Started Aug 02 04:43:05 PM PDT 24
Finished Aug 02 04:43:07 PM PDT 24
Peak memory 224648 kb
Host smart-fd05477b-7ed9-4d28-9e69-2cd3bc574c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768117730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3768117730
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2555989680
Short name T792
Test name
Test status
Simulation time 1756035771 ps
CPU time 12.09 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:22 PM PDT 24
Peak memory 219824 kb
Host smart-08a3352c-c786-4891-8987-57f1e817a513
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2555989680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2555989680
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4021371884
Short name T167
Test name
Test status
Simulation time 184233297072 ps
CPU time 283.17 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:47:52 PM PDT 24
Peak memory 252252 kb
Host smart-06bde2a3-8029-4b92-adb1-a9e29cd2af4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021371884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4021371884
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4060285486
Short name T300
Test name
Test status
Simulation time 1046883850 ps
CPU time 4.27 seconds
Started Aug 02 04:43:06 PM PDT 24
Finished Aug 02 04:43:10 PM PDT 24
Peak memory 216948 kb
Host smart-dae1f77e-3eec-4737-a066-da42ae7a17b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060285486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4060285486
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2529808549
Short name T504
Test name
Test status
Simulation time 1167289853 ps
CPU time 3.94 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 216932 kb
Host smart-14e5800b-2e74-4c47-a3b3-1f0492fb2174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529808549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2529808549
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.753248574
Short name T675
Test name
Test status
Simulation time 155154470 ps
CPU time 1.06 seconds
Started Aug 02 04:43:12 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 207428 kb
Host smart-8c5f8f77-f19b-4db3-9923-d4ac622240e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753248574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.753248574
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1817049297
Short name T994
Test name
Test status
Simulation time 54366092 ps
CPU time 0.93 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 207488 kb
Host smart-341a0309-05f8-4138-b84b-f24bc1e3e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817049297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1817049297
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1113346104
Short name T810
Test name
Test status
Simulation time 10910000334 ps
CPU time 18.63 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:26 PM PDT 24
Peak memory 241432 kb
Host smart-3ea12418-09c8-4fc7-a52a-e6f09127fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113346104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1113346104
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2735370514
Short name T920
Test name
Test status
Simulation time 39217477 ps
CPU time 0.77 seconds
Started Aug 02 04:43:15 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 206124 kb
Host smart-2304874d-3844-4f12-b272-c7d35b076944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735370514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
735370514
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2051966063
Short name T84
Test name
Test status
Simulation time 5603222007 ps
CPU time 23.15 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:43:37 PM PDT 24
Peak memory 233396 kb
Host smart-20a65249-b3eb-41b1-b311-fb1bda3ff10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051966063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2051966063
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.926918081
Short name T537
Test name
Test status
Simulation time 16712508 ps
CPU time 0.78 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 206960 kb
Host smart-b6e473e1-6359-441c-9f9c-03da58326cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926918081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.926918081
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1973897684
Short name T806
Test name
Test status
Simulation time 68796734403 ps
CPU time 125.68 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:45:32 PM PDT 24
Peak memory 251272 kb
Host smart-104ff25f-a3e7-41d7-8a3e-0e704232ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973897684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1973897684
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1483622814
Short name T262
Test name
Test status
Simulation time 63551523791 ps
CPU time 116.7 seconds
Started Aug 02 04:43:24 PM PDT 24
Finished Aug 02 04:45:21 PM PDT 24
Peak memory 240816 kb
Host smart-e3386f7e-ad17-4f78-87e1-05ea3a6b055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483622814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1483622814
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3585754425
Short name T868
Test name
Test status
Simulation time 48431880997 ps
CPU time 228.85 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:47:03 PM PDT 24
Peak memory 255732 kb
Host smart-19e4af0a-166c-4475-aaf8-0e757829cc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585754425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3585754425
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3734238164
Short name T461
Test name
Test status
Simulation time 6563125603 ps
CPU time 80.15 seconds
Started Aug 02 04:43:22 PM PDT 24
Finished Aug 02 04:44:42 PM PDT 24
Peak memory 241236 kb
Host smart-a159cddd-466b-4f7d-ae1c-c6cd793dd09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734238164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3734238164
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.81930664
Short name T316
Test name
Test status
Simulation time 18015593 ps
CPU time 0.77 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 216432 kb
Host smart-48685947-c6c0-4c5b-8638-bf5627097dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81930664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.81930664
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1399939649
Short name T692
Test name
Test status
Simulation time 135570158 ps
CPU time 3.96 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:14 PM PDT 24
Peak memory 233360 kb
Host smart-451de153-f428-494d-ac69-08c44dd96b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399939649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1399939649
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.293175518
Short name T70
Test name
Test status
Simulation time 14391423095 ps
CPU time 30 seconds
Started Aug 02 04:43:11 PM PDT 24
Finished Aug 02 04:43:41 PM PDT 24
Peak memory 251868 kb
Host smart-68862756-bb5a-4196-9c4a-9490ddf75e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293175518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.293175518
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2384464891
Short name T406
Test name
Test status
Simulation time 15555565 ps
CPU time 1 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 217072 kb
Host smart-fe723d5e-1cb2-4c17-aba8-7a42cea18f96
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384464891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2384464891
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3529460259
Short name T942
Test name
Test status
Simulation time 8463205451 ps
CPU time 8.37 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:18 PM PDT 24
Peak memory 233428 kb
Host smart-27ebc302-e38f-4664-92a3-b2b3a98f5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529460259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3529460259
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1288630943
Short name T918
Test name
Test status
Simulation time 7321556798 ps
CPU time 7.94 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 225044 kb
Host smart-6667c5d1-6eac-4b31-8c4d-90e557de8782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288630943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1288630943
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4096151866
Short name T540
Test name
Test status
Simulation time 483722133 ps
CPU time 3.9 seconds
Started Aug 02 04:43:26 PM PDT 24
Finished Aug 02 04:43:30 PM PDT 24
Peak memory 222716 kb
Host smart-15584763-e268-4f12-868b-9930f26b855d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096151866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4096151866
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3318671093
Short name T505
Test name
Test status
Simulation time 16584284684 ps
CPU time 188.4 seconds
Started Aug 02 04:43:14 PM PDT 24
Finished Aug 02 04:46:23 PM PDT 24
Peak memory 268348 kb
Host smart-49aa2b51-2b80-4a8e-9034-d30d97026f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318671093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3318671093
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2178783828
Short name T629
Test name
Test status
Simulation time 2795808154 ps
CPU time 14.79 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 216892 kb
Host smart-87ec30a6-85b3-4870-b06b-5a53160747c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178783828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2178783828
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3410683605
Short name T923
Test name
Test status
Simulation time 6287359744 ps
CPU time 18 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:27 PM PDT 24
Peak memory 216964 kb
Host smart-e5de0fc3-2aae-4528-ad63-f869765021a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410683605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3410683605
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3067373108
Short name T719
Test name
Test status
Simulation time 16195650 ps
CPU time 0.73 seconds
Started Aug 02 04:43:08 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 206448 kb
Host smart-43d889fd-1556-49b7-b4ee-021d7429a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067373108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3067373108
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3512606413
Short name T818
Test name
Test status
Simulation time 90897283 ps
CPU time 0.72 seconds
Started Aug 02 04:43:10 PM PDT 24
Finished Aug 02 04:43:11 PM PDT 24
Peak memory 206428 kb
Host smart-a51a58be-1b35-4608-bbc8-2ec8574bc0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512606413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3512606413
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3697788350
Short name T820
Test name
Test status
Simulation time 101487637 ps
CPU time 2.15 seconds
Started Aug 02 04:43:09 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 224768 kb
Host smart-6f8a15c1-9bc3-43e8-8417-b47186626b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697788350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3697788350
Directory /workspace/9.spi_device_upload/latest
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