Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2789478	1			T1	1		T2	1		T3	7
all_values[1]	2789478	1			T1	1		T2	1		T3	7
all_values[2]	2789478	1			T1	1		T2	1		T3	7
all_values[3]	2789478	1			T1	1		T2	1		T3	7
all_values[4]	2789478	1			T1	1		T2	1		T3	7
all_values[5]	2789478	1			T1	1		T2	1		T3	7
all_values[6]	2789478	1			T1	1		T2	1		T3	7
all_values[7]	2789478	1			T1	1		T2	1		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21544721

1

T1

8

T2

8

T3

56

auto[1]

771103

1

T16

9744

T17

44

T19

86636

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22290631

1

T1

8

T2

8

T3

56

auto[1]

25193

1

T14

266

T27

48

T32

35

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2737956	1			T1	1		T2	1		T3	7
all_values[0]	auto[0]	auto[1]	11616	1			T14	119		T27	24		T32	33
all_values[0]	auto[1]	auto[0]	39604	1			T16	6		T17	4		T19	7
all_values[0]	auto[1]	auto[1]	302	1			T17	3		T19	6		T20	5
all_values[1]	auto[0]	auto[0]	2705431	1			T1	1		T2	1		T3	7
all_values[1]	auto[0]	auto[1]	7585	1			T14	94		T27	24		T32	2
all_values[1]	auto[1]	auto[0]	75910	1			T16	3237		T17	4		T19	9
all_values[1]	auto[1]	auto[1]	552	1			T16	2		T17	2		T19	9
all_values[2]	auto[0]	auto[0]	2715260	1			T1	1		T2	1		T3	7
all_values[2]	auto[0]	auto[1]	2733	1			T14	53		T33	40		T42	1
all_values[2]	auto[1]	auto[0]	71141	1			T16	3237		T17	1		T19	4
all_values[2]	auto[1]	auto[1]	344	1			T16	1		T17	4		T19	7
all_values[3]	auto[0]	auto[0]	2732583	1			T1	1		T2	1		T3	7
all_values[3]	auto[0]	auto[1]	219	1			T16	5		T17	2		T184	1
all_values[3]	auto[1]	auto[0]	56462	1			T16	1		T17	2		T19	5
all_values[3]	auto[1]	auto[1]	214	1			T16	1		T17	3		T19	7
all_values[4]	auto[0]	auto[0]	2656340	1			T1	1		T2	1		T3	7
all_values[4]	auto[0]	auto[1]	191	1			T16	1		T17	3		T19	7
all_values[4]	auto[1]	auto[0]	132722	1			T16	4		T17	1		T19	7
all_values[4]	auto[1]	auto[1]	225	1			T16	3		T17	2		T19	10
all_values[5]	auto[0]	auto[0]	2604345	1			T1	1		T2	1		T3	7
all_values[5]	auto[0]	auto[1]	212	1			T16	6		T17	1		T19	11
all_values[5]	auto[1]	auto[0]	184736	1			T16	1		T17	2		T19	43269
all_values[5]	auto[1]	auto[1]	185	1			T16	2		T17	5		T19	5
all_values[6]	auto[0]	auto[0]	2666102	1			T1	1		T2	1		T3	7
all_values[6]	auto[0]	auto[1]	223	1			T16	2		T17	1		T19	8
all_values[6]	auto[1]	auto[0]	122940	1			T16	6		T17	4		T19	10
all_values[6]	auto[1]	auto[1]	213	1			T16	1		T17	1		T19	6
all_values[7]	auto[0]	auto[0]	2703749	1			T1	1		T2	1		T3	7
all_values[7]	auto[0]	auto[1]	176	1			T16	1		T17	3		T19	3
all_values[7]	auto[1]	auto[0]	85350	1			T16	3241		T17	4		T19	43270
all_values[7]	auto[1]	auto[1]	203	1			T16	1		T17	2		T19	5