Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34822	1			T2	6		T9	2		T10	215
auto[SpiFlashAddrCfg]	7727	1			T2	2		T8	4		T9	2
auto[SpiFlashAddr3b]	9486	1			T6	1		T8	4		T10	41
auto[SpiFlashAddr4b]	7789	1			T3	2		T6	2		T8	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34738

1

T3

2

T6

3

T8

12

auto[1]

25086

1

T2

8

T9

4

T10

124

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31767

1

T2

6

T3

2

T6

1

auto[1]

28057

1

T2

2

T6

2

T8

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39474	1			T2	6		T6	2		T9	4
values[1]	1136	1			T10	12		T13	2		T14	4
values[2]	1521	1			T10	2		T14	9		T15	5
values[3]	1486	1			T10	4		T14	3		T15	7
values[4]	1478	1			T2	2		T10	2		T12	4
values[5]	1553	1			T8	4		T10	9		T14	1
values[6]	1505	1			T6	1		T10	6		T14	10
values[7]	1472	1			T10	6		T14	7		T15	7
values[8]	10199	1			T3	2		T8	8		T10	48

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32510

1

T2

8

T8

12

T9

4

auto[1]

27314

1

T3

2

T6

3

T10

325

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56643

1

T2

8

T3

2

T6

3

write

3181

1

T9

2

T10

19

T14

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19851

1

T3

2

T6

1

T8

12

valids[0x1]

39973

1

T2

8

T6

2

T9

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1630	1			T2	2		T10	11		T14	10
internal_process_ops[0x5a]	1583	1			T10	8		T14	8		T15	11
internal_process_ops[0x05]	20478	1			T9	2		T10	137		T12	2
internal_process_ops[0x35]	1618	1			T2	2		T10	10		T14	13
internal_process_ops[0x15]	1584	1			T2	2		T10	6		T13	2
internal_process_ops[0x03]	1091	1			T6	2		T10	2		T13	2
internal_process_ops[0x0b]	1121	1			T10	1		T12	4		T14	3
internal_process_ops[0x3b]	1095	1			T3	2		T10	1		T13	2
internal_process_ops[0x6b]	1068	1			T6	1		T8	4		T10	1
internal_process_ops[0xbb]	1108	1			T8	4		T10	2		T14	5
internal_process_ops[0xeb]	1064	1			T8	4		T10	2		T14	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58269

1

T2

8

T3

2

T6

3

auto[1]

1555

1

T9

2

T10

7

T14

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57554

1

T2

8

T3

2

T6

3

auto[1]

2270

1

T10

15

T14

9

T15

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11343

1

T12

8

T13

6

T15

142

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6554

1

T2

6

T9

2

T15

120

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2185

1

T8

4

T13

6

T15

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1785

1

T2

2

T15

14

T26

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2625

1

T8

4

T12

8

T13

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2363

1

T15

18

T26

18

T33

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2189

1

T8

4

T12

2

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1858

1

T15

14

T26

4

T36

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T15

3

T33

2

T51

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T15

4

T46

1

T49

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T33

1

T42

4

T51

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T49

1

T18

1

T19

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

118

1

T15

1

T33

3

T49

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T15

3

T26

1

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T15

1

T26

2

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T9

2

T15

2

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T33

1

T181

2

T51

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T33

1

T49

2

T182

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T33

1

T182

1

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

117

1

T48

2

T49

2

T182

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T15

1

T36

1

T33

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T15

1

T33

1

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

96

1

T15

2

T26

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T15

4

T33

2

T48

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9787

1

T10

131

T14

85

T27

135

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6386

1

T10

83

T14

30

T27

79

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1565

1

T10

8

T14

17

T27

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1415

1

T10

8

T14

14

T27

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1952

1

T6

1

T10

21

T14

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1731

1

T10

16

T14

17

T27

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1457

1

T3

2

T6

2

T10

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1448

1

T10

10

T14

19

T27

27

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T14

1

T183

1

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T14

2

T32

3

T37

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T10

1

T37

1

T94

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T27

1

T183

4

T16

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T10

2

T27

1

T37

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T10

3

T14

1

T27

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T10

1

T27

2

T37

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

111

1

T14

1

T32

1

T183

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T10

1

T27

5

T37

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T14

1

T37

2

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T10

2

T27

1

T37

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

88

1

T10

1

T27

3

T37

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T10

4

T14

1

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T10

2

T14

3

T183

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T10

1

T27

3

T94

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T10

1

T37

3

T16

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4184	1			T12	6		T13	2		T15	36
auto[0]	values[0]	valids[0x1]	16595	1			T2	6		T9	4		T12	4
auto[0]	values[1]	valids[0x1]	597	1			T13	2		T15	7		T26	1
auto[0]	values[2]	valids[0x0]	586	1			T15	2		T36	1		T33	4
auto[0]	values[2]	valids[0x1]	312	1			T15	3		T26	1		T36	1
auto[0]	values[3]	valids[0x0]	579	1			T15	5		T26	2		T33	4
auto[0]	values[3]	valids[0x1]	296	1			T15	2		T24	10		T33	1
auto[0]	values[4]	valids[0x0]	561	1			T13	2		T15	4		T26	3
auto[0]	values[4]	valids[0x1]	297	1			T2	2		T12	4		T15	5
auto[0]	values[5]	valids[0x0]	550	1			T8	4		T15	3		T26	7
auto[0]	values[5]	valids[0x1]	332	1			T15	3		T26	4		T33	4
auto[0]	values[6]	valids[0x0]	576	1			T15	7		T26	2		T33	6
auto[0]	values[6]	valids[0x1]	286	1			T15	3		T26	1		T33	4
auto[0]	values[7]	valids[0x0]	519	1			T15	3		T26	4		T33	9
auto[0]	values[7]	valids[0x1]	369	1			T15	4		T26	3		T33	5
auto[0]	values[8]	valids[0x0]	3695	1			T8	8		T13	8		T15	26
auto[0]	values[8]	valids[0x1]	2176	1			T12	4		T13	2		T15	20
auto[1]	values[0]	valids[0x0]	3894	1			T10	46		T14	45		T27	52
auto[1]	values[0]	valids[0x1]	14801	1			T6	2		T10	190		T14	90
auto[1]	values[1]	valids[0x1]	539	1			T10	12		T14	4		T27	7
auto[1]	values[2]	valids[0x0]	374	1			T10	2		T14	8		T27	2
auto[1]	values[2]	valids[0x1]	249	1			T14	1		T27	3		T43	1
auto[1]	values[3]	valids[0x0]	360	1			T10	3		T14	2		T27	6
auto[1]	values[3]	valids[0x1]	251	1			T10	1		T14	1		T27	4
auto[1]	values[4]	valids[0x0]	356	1			T10	1		T14	7		T27	2
auto[1]	values[4]	valids[0x1]	264	1			T10	1		T27	9		T37	2
auto[1]	values[5]	valids[0x0]	390	1			T10	7		T14	1		T27	7
auto[1]	values[5]	valids[0x1]	281	1			T10	2		T27	3		T37	7
auto[1]	values[6]	valids[0x0]	379	1			T6	1		T10	4		T14	7
auto[1]	values[6]	valids[0x1]	264	1			T10	2		T14	3		T27	4
auto[1]	values[7]	valids[0x0]	343	1			T10	5		T14	5		T27	4
auto[1]	values[7]	valids[0x1]	241	1			T10	1		T14	2		T27	1
auto[1]	values[8]	valids[0x0]	2505	1			T3	2		T10	24		T14	38
auto[1]	values[8]	valids[0x1]	1823	1			T10	24		T14	23		T27	16