Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3505979

1

T1

1

T2

1

T3

2367

auto[1]

29261

1

T10

125

T14

17

T15

192

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958725

1

T1

1

T2

1

T3

2367

auto[1]

2576515

1

T10

14132

T12

512

T13

3998

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	645174	1			T1	1		T2	1		T6	272
auto[524288:1048575]	412462	1			T3	2143		T8	13		T10	2825
auto[1048576:1572863]	428555	1			T3	221		T8	69		T10	261
auto[1572864:2097151]	407446	1			T8	311		T10	28		T14	4073
auto[2097152:2621439]	434668	1			T3	3		T6	2		T8	459
auto[2621440:3145727]	381147	1			T6	1511		T8	169		T10	4206
auto[3145728:3670015]	413433	1			T8	11		T10	3206		T14	820
auto[3670016:4194303]	412355	1			T8	753		T10	542		T14	2293

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2612147

1

T1

1

T2

1

T3

6

auto[1]

923093

1

T3

2361

T6

1777

T8

2019

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3032823

1

T1

1

T2

1

T3

2367

auto[1]

502417

1

T10

4982

T14

263

T15

4636

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	183678	1			T1	1		T2	1		T6	272
auto[0]	auto[0]	auto[0:524287]	auto[1]	390020	1			T10	1651		T12	512		T13	3998
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	116571	1			T3	2143		T8	13		T10	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	242323	1			T10	2817		T14	345		T15	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	109105	1			T3	221		T8	69		T10	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	228903	1			T10	256		T14	5861		T27	3366
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	104078	1			T8	311		T10	6		T14	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	228754	1			T10	3		T14	4061		T15	5178
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	111265	1			T3	3		T6	2		T8	459
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	260404	1			T10	515		T14	1285		T15	4779
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103085	1			T6	1511		T8	169		T10	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	220840	1			T10	900		T14	391		T27	1951
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92811	1			T8	11		T10	12		T14	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	254704	1			T10	2398		T14	816		T15	1469
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	125071	1			T8	753		T10	5		T14	12
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	236420	1			T10	514		T14	2016		T15	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	1845	1			T14	1		T15	1		T26	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	63512	1			T33	5		T46	2		T48	749
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	527	1			T26	1		T27	5		T33	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49427	1			T26	1		T27	1		T42	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1610	1			T42	2		T183	11		T16	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	85674	1			T42	128		T183	1701		T16	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1335	1			T27	1		T33	1		T42	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	69660	1			T33	5		T42	1		T183	2596
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	847	1			T10	1		T15	10		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59300	1			T10	910		T15	2298		T27	257
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	723	1			T10	3		T14	1		T26	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52805	1			T10	3288		T26	1		T27	1705
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1041	1			T10	3		T15	1		T33	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	62271	1			T10	770		T15	2247		T27	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1478	1			T14	3		T27	1		T42	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45892	1			T14	257		T26	1		T27	137
auto[1]	auto[0]	auto[0:524287]	auto[0]	513	1			T10	1		T27	1		T32	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4793	1			T10	9		T27	7		T32	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	373	1			T10	1		T27	2		T33	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2740	1			T10	4		T27	17		T33	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	313	1			T14	1		T27	3		T33	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2367	1			T14	3		T27	28		T212	15
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	432	1			T10	1		T14	2		T15	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2490	1			T10	18		T14	3		T15	7
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	294	1			T10	3		T14	2		T15	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1912	1			T10	32		T15	37		T27	24
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	381	1			T10	1		T37	4		T46	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2934	1			T10	2		T37	4		T46	21
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	365	1			T10	5		T14	1		T15	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1835	1			T10	18		T15	64		T27	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	382	1			T10	2		T14	2		T27	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2667	1			T10	21		T14	2		T27	21
auto[1]	auto[1]	auto[0:524287]	auto[0]	86	1			T33	1		T48	4		T17	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	727	1			T33	2		T48	27		T17	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	73	1			T26	1		T27	1		T42	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	428	1			T26	18		T27	1		T42	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	81	1			T183	5		T17	1		T50	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	502	1			T183	60		T17	4		T243	100
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	77	1			T42	1		T99	6		T237	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	620	1			T99	13		T237	3		T18	40
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	69	1			T15	5		T27	1		T37	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	577	1			T15	74		T27	3		T37	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	47	1			T10	1		T26	1		T16	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	332	1			T10	6		T26	45		T16	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T37	3		T46	1		T49	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	316	1			T37	1		T49	1		T17	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	79	1			T14	1		T48	2		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	366	1			T16	7		T17	1		T237	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2089505	1			T1	1		T2	1		T3	6
auto[0]	auto[0]	auto[1]	918527	1			T3	2361		T6	1777		T8	2019
auto[0]	auto[1]	auto[0]	494040	1			T10	4975		T14	262		T15	4554
auto[0]	auto[1]	auto[1]	3907	1			T15	3		T26	1		T255	105
auto[1]	auto[0]	auto[0]	24238	1			T10	112		T14	15		T15	111
auto[1]	auto[0]	auto[1]	553	1			T10	6		T14	1		T15	2
auto[1]	auto[1]	auto[0]	4364	1			T10	7		T14	1		T15	78
auto[1]	auto[1]	auto[1]	106	1			T15	1		T27	1		T48	1