Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2789478	1			T1	1		T2	1		T3	7
all_pins[1]	2789478	1			T1	1		T2	1		T3	7
all_pins[2]	2789478	1			T1	1		T2	1		T3	7
all_pins[3]	2789478	1			T1	1		T2	1		T3	7
all_pins[4]	2789478	1			T1	1		T2	1		T3	7
all_pins[5]	2789478	1			T1	1		T2	1		T3	7
all_pins[6]	2789478	1			T1	1		T2	1		T3	7
all_pins[7]	2789478	1			T1	1		T2	1		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22189332	1			T1	8		T2	8		T3	56
values[0x1]	126492	1			T16	14		T17	22		T19	433
transitions[0x0=>0x1]	124665	1			T16	12		T17	15		T19	413
transitions[0x1=>0x0]	124678	1			T16	12		T17	15		T19	413

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2789140	1			T1	1		T2	1		T3	7
all_pins[0]	values[0x1]	338	1			T17	3		T19	6		T20	5
all_pins[0]	transitions[0x0=>0x1]	229	1			T17	3		T19	3		T20	3
all_pins[0]	transitions[0x1=>0x0]	498	1			T16	4		T17	2		T19	6
all_pins[1]	values[0x0]	2788871	1			T1	1		T2	1		T3	7
all_pins[1]	values[0x1]	607	1			T16	4		T17	2		T19	9
all_pins[1]	transitions[0x0=>0x1]	447	1			T16	2		T17	1		T19	5
all_pins[1]	transitions[0x1=>0x0]	213	1			T17	3		T19	3		T20	3
all_pins[2]	values[0x0]	2789105	1			T1	1		T2	1		T3	7
all_pins[2]	values[0x1]	373	1			T16	2		T17	4		T19	7
all_pins[2]	transitions[0x0=>0x1]	306	1			T16	2		T17	2		T19	2
all_pins[2]	transitions[0x1=>0x0]	147	1			T16	1		T17	1		T19	2
all_pins[3]	values[0x0]	2789264	1			T1	1		T2	1		T3	7
all_pins[3]	values[0x1]	214	1			T16	1		T17	3		T19	7
all_pins[3]	transitions[0x0=>0x1]	150	1			T16	1		T17	2		T19	3
all_pins[3]	transitions[0x1=>0x0]	161	1			T16	3		T17	1		T19	6
all_pins[4]	values[0x0]	2789253	1			T1	1		T2	1		T3	7
all_pins[4]	values[0x1]	225	1			T16	3		T17	2		T19	10
all_pins[4]	transitions[0x0=>0x1]	179	1			T16	3		T19	8		T20	7
all_pins[4]	transitions[0x1=>0x0]	2395	1			T16	2		T17	3		T19	381
all_pins[5]	values[0x0]	2787037	1			T1	1		T2	1		T3	7
all_pins[5]	values[0x1]	2441	1			T16	2		T17	5		T19	383
all_pins[5]	transitions[0x0=>0x1]	1172	1			T16	2		T17	4		T19	382
all_pins[5]	transitions[0x1=>0x0]	120822	1			T16	1		T19	5		T20	3
all_pins[6]	values[0x0]	2667387	1			T1	1		T2	1		T3	7
all_pins[6]	values[0x1]	122091	1			T16	1		T17	1		T19	6
all_pins[6]	transitions[0x0=>0x1]	122033	1			T16	1		T17	1		T19	6
all_pins[6]	transitions[0x1=>0x0]	145	1			T16	1		T17	2		T19	5
all_pins[7]	values[0x0]	2789275	1			T1	1		T2	1		T3	7
all_pins[7]	values[0x1]	203	1			T16	1		T17	2		T19	5
all_pins[7]	transitions[0x0=>0x1]	149	1			T16	1		T17	2		T19	4
all_pins[7]	transitions[0x1=>0x0]	297	1			T17	3		T19	5		T20	5