Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19197

1

T8

12

T12

18

T13

20

auto[1]

13313

1

T2

8

T9

4

T15

175

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3669	1			T9	4		T15	20		T24	14
values[1]	4265	1			T15	20		T26	106		T28	6
values[2]	3743	1			T15	48		T47	14		T33	22
values[3]	4569	1			T8	12		T12	18		T15	155
values[4]	4323	1			T15	42		T33	60		T251	18
values[5]	3253	1			T2	8		T15	20		T33	23
values[6]	4364	1			T13	20		T25	2		T33	92
values[7]	4324	1			T15	87		T26	20		T33	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4593	1			T15	87		T26	84		T33	65
values[1]	4276	1			T2	8		T13	20		T15	40
values[2]	4062	1			T15	50		T29	4		T33	29
values[3]	4143	1			T12	18		T15	20		T24	14
values[4]	4102	1			T8	12		T15	155		T33	20
values[5]	4419	1			T9	4		T15	40		T36	20
values[6]	3502	1			T26	86		T42	20		T46	31
values[7]	3413	1			T109	10		T33	50		T46	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	273	1			T26	37		T18	12		T229	7
auto[0]	values[0]	values[1]	308	1			T15	12		T42	18		T256	18
auto[0]	values[0]	values[2]	338	1			T257	2		T258	23		T87	9
auto[0]	values[0]	values[3]	441	1			T24	14		T192	9		T204	11
auto[0]	values[0]	values[4]	312	1			T33	14		T19	13		T210	11
auto[0]	values[0]	values[5]	295	1			T21	14		T202	10		T218	10
auto[0]	values[0]	values[6]	205	1			T46	27		T34	16		T225	10
auto[0]	values[0]	values[7]	219	1			T48	8		T18	12		T259	18
auto[0]	values[1]	values[0]	384	1			T26	14		T49	12		T210	17
auto[0]	values[1]	values[1]	300	1			T46	8		T101	4		T18	14
auto[0]	values[1]	values[2]	298	1			T18	16		T206	11		T192	14
auto[0]	values[1]	values[3]	319	1			T15	10		T28	6		T46	9
auto[0]	values[1]	values[4]	299	1			T46	11		T260	2		T261	24
auto[0]	values[1]	values[5]	185	1			T36	10		T22	12		T100	9
auto[0]	values[1]	values[6]	225	1			T26	68		T18	8		T192	14
auto[0]	values[1]	values[7]	355	1			T18	18		T144	45		T192	14
auto[0]	values[2]	values[0]	482	1			T33	16		T219	6		T51	17
auto[0]	values[2]	values[1]	272	1			T15	8		T255	12		T262	4
auto[0]	values[2]	values[2]	316	1			T15	19		T18	21		T206	68
auto[0]	values[2]	values[3]	233	1			T47	14		T177	12		T87	19
auto[0]	values[2]	values[4]	155	1			T50	11		T210	6		T207	19
auto[0]	values[2]	values[5]	268	1			T46	18		T100	9		T193	17
auto[0]	values[2]	values[6]	371	1			T49	20		T34	3		T202	16
auto[0]	values[2]	values[7]	143	1			T263	2		T50	13		T210	10
auto[0]	values[3]	values[0]	362	1			T176	10		T18	36		T207	15
auto[0]	values[3]	values[1]	388	1			T48	8		T49	29		T50	12
auto[0]	values[3]	values[2]	309	1			T29	4		T42	13		T264	16
auto[0]	values[3]	values[3]	316	1			T12	18		T18	11		T34	11
auto[0]	values[3]	values[4]	285	1			T8	12		T15	50		T226	6
auto[0]	values[3]	values[5]	403	1			T46	55		T265	2		T266	43
auto[0]	values[3]	values[6]	393	1			T21	12		T225	71		T192	29
auto[0]	values[3]	values[7]	226	1			T109	10		T46	25		T18	21
auto[0]	values[4]	values[0]	387	1			T33	9		T49	31		T100	13
auto[0]	values[4]	values[1]	188	1			T19	14		T34	17		T193	8
auto[0]	values[4]	values[2]	244	1			T15	13		T50	14		T87	12
auto[0]	values[4]	values[3]	382	1			T33	7		T178	14		T267	14
auto[0]	values[4]	values[4]	550	1			T51	14		T19	14		T210	28
auto[0]	values[4]	values[5]	464	1			T15	10		T33	14		T268	2
auto[0]	values[4]	values[6]	293	1			T269	8		T270	26		T213	7
auto[0]	values[4]	values[7]	162	1			T100	14		T204	14		T229	13
auto[0]	values[5]	values[0]	320	1			T33	13		T271	4		T210	10
auto[0]	values[5]	values[1]	234	1			T192	7		T202	36		T232	8
auto[0]	values[5]	values[2]	177	1			T42	11		T19	25		T206	9
auto[0]	values[5]	values[3]	184	1			T214	16		T206	9		T270	9
auto[0]	values[5]	values[4]	235	1			T18	19		T216	20		T272	4
auto[0]	values[5]	values[5]	190	1			T15	14		T173	8		T22	6
auto[0]	values[5]	values[6]	273	1			T193	14		T231	8		T207	24
auto[0]	values[5]	values[7]	291	1			T34	11		T100	8		T192	11
auto[0]	values[6]	values[0]	191	1			T205	8		T182	28		T87	11
auto[0]	values[6]	values[1]	501	1			T13	20		T33	28		T50	8
auto[0]	values[6]	values[2]	555	1			T33	20		T46	11		T273	8
auto[0]	values[6]	values[3]	366	1			T25	2		T181	21		T51	15
auto[0]	values[6]	values[4]	384	1			T18	35		T34	9		T87	13
auto[0]	values[6]	values[5]	226	1			T19	12		T274	6		T245	14
auto[0]	values[6]	values[6]	157	1			T202	11		T229	12		T240	11
auto[0]	values[6]	values[7]	220	1			T33	13		T51	12		T193	14
auto[0]	values[7]	values[0]	311	1			T15	81		T26	12		T18	28
auto[0]	values[7]	values[1]	260	1			T275	14		T210	13		T204	16
auto[0]	values[7]	values[2]	341	1			T21	12		T22	12		T34	11
auto[0]	values[7]	values[3]	296	1			T227	16		T100	24		T193	17
auto[0]	values[7]	values[4]	280	1			T182	8		T240	12		T201	14
auto[0]	values[7]	values[5]	305	1			T21	10		T34	8		T192	13
auto[0]	values[7]	values[6]	193	1			T42	13		T18	23		T204	12
auto[0]	values[7]	values[7]	359	1			T33	15		T49	16		T182	21
auto[1]	values[0]	values[0]	154	1			T26	7		T18	8		T229	16
auto[1]	values[0]	values[1]	106	1			T15	8		T42	8		T276	10
auto[1]	values[0]	values[2]	149	1			T87	15		T220	5		T213	9
auto[1]	values[0]	values[3]	298	1			T192	11		T204	9		T218	8
auto[1]	values[0]	values[4]	109	1			T33	6		T19	14		T210	9
auto[1]	values[0]	values[5]	198	1			T9	4		T21	6		T202	32
auto[1]	values[0]	values[6]	129	1			T46	4		T228	12		T34	4
auto[1]	values[0]	values[7]	135	1			T48	12		T18	8		T259	5
auto[1]	values[1]	values[0]	306	1			T26	6		T49	8		T210	58
auto[1]	values[1]	values[1]	255	1			T46	12		T18	6		T192	7
auto[1]	values[1]	values[2]	201	1			T18	8		T206	48		T192	6
auto[1]	values[1]	values[3]	223	1			T15	10		T46	11		T51	35
auto[1]	values[1]	values[4]	198	1			T46	18		T277	2		T18	12
auto[1]	values[1]	values[5]	292	1			T36	10		T22	60		T100	11
auto[1]	values[1]	values[6]	226	1			T26	18		T18	28		T192	6
auto[1]	values[1]	values[7]	199	1			T18	8		T192	6		T193	9
auto[1]	values[2]	values[0]	308	1			T33	6		T51	9		T225	3
auto[1]	values[2]	values[1]	167	1			T15	12		T278	4		T279	10
auto[1]	values[2]	values[2]	121	1			T15	9		T18	24		T206	10
auto[1]	values[2]	values[3]	196	1			T87	7		T218	7		T39	7
auto[1]	values[2]	values[4]	116	1			T50	9		T210	14		T207	6
auto[1]	values[2]	values[5]	253	1			T46	3		T100	11		T193	3
auto[1]	values[2]	values[6]	294	1			T49	20		T34	20		T202	58
auto[1]	values[2]	values[7]	48	1			T50	7		T210	10		T209	10
auto[1]	values[3]	values[0]	205	1			T18	37		T207	12		T280	34
auto[1]	values[3]	values[1]	376	1			T48	12		T49	6		T50	8
auto[1]	values[3]	values[2]	162	1			T42	11		T18	9		T34	9
auto[1]	values[3]	values[3]	229	1			T18	9		T34	9		T193	18
auto[1]	values[3]	values[4]	221	1			T15	105		T49	8		T34	5
auto[1]	values[3]	values[5]	225	1			T46	5		T204	14		T202	10
auto[1]	values[3]	values[6]	192	1			T21	14		T225	13		T192	11
auto[1]	values[3]	values[7]	277	1			T46	15		T18	20		T232	46
auto[1]	values[4]	values[0]	256	1			T33	11		T49	9		T100	7
auto[1]	values[4]	values[1]	109	1			T174	2		T19	10		T34	3
auto[1]	values[4]	values[2]	159	1			T15	9		T50	6		T87	13
auto[1]	values[4]	values[3]	112	1			T33	13		T251	18		T182	2
auto[1]	values[4]	values[4]	176	1			T51	10		T19	9		T210	6
auto[1]	values[4]	values[5]	538	1			T15	10		T33	6		T49	4
auto[1]	values[4]	values[6]	134	1			T270	7		T213	13		T281	9
auto[1]	values[4]	values[7]	169	1			T100	6		T204	8		T229	30
auto[1]	values[5]	values[0]	230	1			T33	10		T210	21		T279	31
auto[1]	values[5]	values[1]	221	1			T2	8		T192	13		T202	11
auto[1]	values[5]	values[2]	168	1			T42	13		T19	3		T206	82
auto[1]	values[5]	values[3]	182	1			T248	14		T206	11		T270	18
auto[1]	values[5]	values[4]	125	1			T18	13		T208	6		T238	10
auto[1]	values[5]	values[5]	130	1			T15	6		T22	14		T169	21
auto[1]	values[5]	values[6]	126	1			T193	6		T207	11		T240	12
auto[1]	values[5]	values[7]	167	1			T34	9		T100	12		T192	9
auto[1]	values[6]	values[0]	173	1			T182	16		T87	9		T282	24
auto[1]	values[6]	values[1]	229	1			T33	6		T50	12		T18	10
auto[1]	values[6]	values[2]	302	1			T33	9		T46	9		T182	9
auto[1]	values[6]	values[3]	205	1			T51	7		T18	9		T87	11
auto[1]	values[6]	values[4]	392	1			T18	13		T34	11		T87	8
auto[1]	values[6]	values[5]	103	1			T19	15		T245	6		T39	19
auto[1]	values[6]	values[6]	141	1			T202	9		T229	8		T240	19
auto[1]	values[6]	values[7]	219	1			T33	16		T51	8		T193	6
auto[1]	values[7]	values[0]	251	1			T15	6		T26	8		T18	16
auto[1]	values[7]	values[1]	362	1			T210	7		T204	4		T220	215
auto[1]	values[7]	values[2]	222	1			T21	8		T22	31		T34	13
auto[1]	values[7]	values[3]	161	1			T100	16		T193	3		T194	8
auto[1]	values[7]	values[4]	265	1			T283	6		T284	8		T182	36
auto[1]	values[7]	values[5]	344	1			T21	20		T34	14		T192	7
auto[1]	values[7]	values[6]	150	1			T42	7		T18	4		T204	8
auto[1]	values[7]	values[7]	224	1			T33	6		T49	10		T182	5