Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	439	1			T15	2		T33	2		T219	4
auto[ReadAddrCrossIntoMailbox]	307	1			T15	3		T33	2		T48	1
auto[ReadAddrCrossOutOfMailbox]	315	1			T15	3		T33	7		T48	1
auto[ReadAddrCrossAllMailbox]	222	1			T15	3		T47	2		T176	2
auto[ReadAddrOutsideMailbox]	3702	1			T8	12		T12	4		T13	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2460

1

T8

6

T12

2

T13

4

auto[1]

2525

1

T8

6

T12

2

T13

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	808	1			T13	2		T15	6		T26	8
read_ops[0x0b]	868	1			T12	4		T15	8		T24	8
read_ops[0x3b]	811	1			T13	2		T15	2		T26	3
read_ops[0x6b]	836	1			T8	4		T13	4		T15	6
read_ops[0xbb]	844	1			T8	4		T15	3		T26	3
read_ops[0xeb]	818	1			T8	4		T15	4		T26	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T49	1		T18	2		T19	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T51	2		T18	2		T204	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T15	1		T33	1		T18	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T51	1		T34	1		T204	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T15	1		T33	1		T225	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T182	1		T18	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T34	1		T204	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T49	1		T18	1		T210	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T13	1		T15	2		T26	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T13	1		T15	2		T26	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T15	1		T33	1		T219	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T219	1		T49	1		T50	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T48	1		T34	1		T204	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T33	1		T18	2		T232	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T49	2		T50	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T49	1		T210	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T206	2		T204	2		T213	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T15	1		T50	1		T240	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	345	1			T12	2		T15	5		T24	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T12	2		T15	1		T24	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T49	1		T34	1		T206	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T22	1		T34	1		T204	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T15	1		T49	3		T18	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T49	1		T210	1		T100	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T100	1		T192	1		T234	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T18	3		T21	1		T234	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T22	1		T225	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T210	1		T100	1		T193	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T13	1		T15	1		T26	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T13	1		T26	1		T33	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T18	1		T34	1		T234	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T19	1		T210	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T49	1		T18	2		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T15	1		T193	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T15	1		T176	2		T49	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T176	2		T18	1		T22	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T176	1		T34	1		T100	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T15	1		T176	1		T234	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T8	2		T13	2		T15	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T8	2		T13	2		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T219	1		T49	1		T182	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T15	1		T219	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T49	1		T21	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T50	1		T51	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T49	1		T182	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T15	1		T33	2		T48	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T182	1		T19	1		T234	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T18	1		T19	1		T21	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T8	2		T26	1		T47	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T8	2		T15	1		T26	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T33	1		T18	1		T34	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T49	1		T18	2		T206	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T49	1		T202	1		T270	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T210	1		T34	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T33	3		T210	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T33	1		T19	2		T234	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T15	1		T47	1		T177	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T47	1		T177	1		T192	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T8	2		T15	2		T26	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T8	2		T15	1		T109	1