Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4290	1			T15	62		T26	66		T47	14
values[1]	3862	1			T9	4		T15	20		T26	20
values[2]	4674	1			T13	20		T15	28		T26	20
values[3]	3891	1			T15	20		T25	2		T26	20
values[4]	3886	1			T15	127		T33	29		T263	2
values[5]	4152	1			T24	14		T28	6		T33	73
values[6]	3748	1			T2	8		T15	135		T26	44
values[7]	4007	1			T8	12		T12	18		T29	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3824	1			T15	20		T26	66		T36	20
values[1]	3869	1			T8	12		T12	18		T15	115
values[2]	4176	1			T26	20		T28	6		T47	14
values[3]	3760	1			T33	51		T46	131		T48	20
values[4]	3420	1			T15	62		T33	20		T101	4
values[5]	4468	1			T15	127		T26	20		T42	50
values[6]	4988	1			T15	40		T29	4		T33	49
values[7]	4005	1			T2	8		T9	4		T13	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31725

1

T2

8

T8

12

T9

2

auto[1]

785

1

T9

2

T15

14

T26

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	702	1			T26	66		T48	15		T182	24
auto[0]	values[0]	values[1]	443	1			T42	20		T205	8		T50	20
auto[0]	values[0]	values[2]	671	1			T47	14		T33	18		T34	20
auto[0]	values[0]	values[3]	612	1			T33	22		T48	18		T19	25
auto[0]	values[0]	values[4]	378	1			T15	40		T21	28		T56	21
auto[0]	values[0]	values[5]	584	1			T15	20		T144	45		T21	20
auto[0]	values[0]	values[6]	387	1			T19	23		T204	17		T80	20
auto[0]	values[0]	values[7]	403	1			T273	8		T252	22		T18	29
auto[0]	values[1]	values[0]	492	1			T15	16		T100	17		T225	20
auto[0]	values[1]	values[1]	407	1			T251	18		T174	2		T18	19
auto[0]	values[1]	values[2]	515	1			T26	20		T46	20		T51	25
auto[0]	values[1]	values[3]	701	1			T46	20		T18	26		T34	23
auto[0]	values[1]	values[4]	527	1			T18	21		T206	57		T194	18
auto[0]	values[1]	values[5]	358	1			T42	25		T178	14		T286	8
auto[0]	values[1]	values[6]	471	1			T46	20		T210	20		T34	22
auto[0]	values[1]	values[7]	300	1			T9	2		T220	20		T245	20
auto[0]	values[2]	values[0]	698	1			T36	19		T275	14		T18	63
auto[0]	values[2]	values[1]	539	1			T42	22		T100	20		T240	18
auto[0]	values[2]	values[2]	371	1			T49	19		T50	17		T100	19
auto[0]	values[2]	values[3]	436	1			T256	18		T18	20		T19	26
auto[0]	values[2]	values[4]	478	1			T268	2		T267	14		T18	49
auto[0]	values[2]	values[5]	661	1			T42	24		T19	24		T202	42
auto[0]	values[2]	values[6]	703	1			T33	20		T173	8		T277	2
auto[0]	values[2]	values[7]	677	1			T13	20		T15	26		T26	20
auto[0]	values[3]	values[0]	289	1			T18	20		T204	22		T287	6
auto[0]	values[3]	values[1]	412	1			T49	19		T285	139		T34	20
auto[0]	values[3]	values[2]	629	1			T214	16		T182	23		T210	35
auto[0]	values[3]	values[3]	485	1			T46	20		T266	43		T18	20
auto[0]	values[3]	values[4]	281	1			T210	29		T192	20		T207	35
auto[0]	values[3]	values[5]	630	1			T15	20		T26	20		T177	12
auto[0]	values[3]	values[6]	687	1			T288	8		T207	24		T229	19
auto[0]	values[3]	values[7]	401	1			T25	2		T265	2		T289	6
auto[0]	values[4]	values[0]	624	1			T49	30		T51	20		T241	108
auto[0]	values[4]	values[1]	463	1			T21	19		T213	37		T218	37
auto[0]	values[4]	values[2]	288	1			T176	10		T270	29		T290	24
auto[0]	values[4]	values[3]	396	1			T263	2		T50	20		T34	18
auto[0]	values[4]	values[4]	529	1			T182	42		T87	23		T204	33
auto[0]	values[4]	values[5]	610	1			T15	87		T284	8		T22	71
auto[0]	values[4]	values[6]	501	1			T15	39		T33	28		T260	2
auto[0]	values[4]	values[7]	371	1			T49	26		T100	20		T192	20
auto[0]	values[5]	values[0]	314	1			T226	6		T18	23		T270	23
auto[0]	values[5]	values[1]	485	1			T100	20		T192	19		T269	8
auto[0]	values[5]	values[2]	566	1			T28	6		T19	24		T262	4
auto[0]	values[5]	values[3]	335	1			T33	29		T46	31		T49	39
auto[0]	values[5]	values[4]	352	1			T34	43		T100	20		T240	30
auto[0]	values[5]	values[5]	664	1			T18	23		T270	27		T291	14
auto[0]	values[5]	values[6]	742	1			T18	20		T292	12		T216	20
auto[0]	values[5]	values[7]	572	1			T24	14		T33	43		T182	25
auto[0]	values[6]	values[0]	264	1			T46	21		T225	40		T234	26
auto[0]	values[6]	values[1]	545	1			T15	112		T26	43		T181	21
auto[0]	values[6]	values[2]	533	1			T33	20		T228	8		T100	20
auto[0]	values[6]	values[3]	321	1			T264	16		T87	20		T204	20
auto[0]	values[6]	values[4]	295	1			T15	18		T33	20		T101	4
auto[0]	values[6]	values[5]	539	1			T283	6		T51	24		T182	21
auto[0]	values[6]	values[6]	727	1			T49	33		T261	24		T18	20
auto[0]	values[6]	values[7]	446	1			T2	8		T33	34		T255	12
auto[0]	values[7]	values[0]	331	1			T182	21		T19	24		T278	4
auto[0]	values[7]	values[1]	470	1			T8	12		T12	18		T227	16
auto[0]	values[7]	values[2]	491	1			T210	19		T193	19		T202	45
auto[0]	values[7]	values[3]	392	1			T46	58		T271	4		T210	20
auto[0]	values[7]	values[4]	482	1			T18	20		T22	20		T213	26
auto[0]	values[7]	values[5]	338	1			T219	6		T248	14		T204	19
auto[0]	values[7]	values[6]	658	1			T29	4		T46	20		T18	20
auto[0]	values[7]	values[7]	753	1			T109	10		T46	29		T50	20
auto[1]	values[0]	values[0]	22	1			T48	5		T182	2		T206	1
auto[1]	values[0]	values[1]	9	1			T21	1		T87	3		T293	2
auto[1]	values[0]	values[2]	14	1			T33	2		T225	2		T209	2
auto[1]	values[0]	values[3]	18	1			T48	2		T19	3		T208	2
auto[1]	values[0]	values[4]	11	1			T15	2		T21	2		T294	3
auto[1]	values[0]	values[5]	11	1			T202	1		T232	3		T295	1
auto[1]	values[0]	values[6]	19	1			T19	1		T204	3		T39	1
auto[1]	values[0]	values[7]	6	1			T87	2		T196	1		T296	1
auto[1]	values[1]	values[0]	14	1			T15	4		T100	3		T39	2
auto[1]	values[1]	values[1]	8	1			T18	1		T245	1		T207	1
auto[1]	values[1]	values[2]	13	1			T51	1		T19	2		T192	1
auto[1]	values[1]	values[3]	15	1			T220	1		T218	1		T238	7
auto[1]	values[1]	values[4]	15	1			T206	2		T194	2		T80	1
auto[1]	values[1]	values[5]	6	1			T42	1		T192	1		T297	2
auto[1]	values[1]	values[6]	10	1			T169	1		T39	1		T298	2
auto[1]	values[1]	values[7]	10	1			T9	2		T169	1		T80	4
auto[1]	values[2]	values[0]	18	1			T36	1		T18	2		T206	2
auto[1]	values[2]	values[1]	15	1			T42	2		T240	2		T281	2
auto[1]	values[2]	values[2]	11	1			T49	3		T50	3		T100	1
auto[1]	values[2]	values[3]	6	1			T19	1		T299	4		T300	1
auto[1]	values[2]	values[4]	10	1			T18	3		T192	1		T280	2
auto[1]	values[2]	values[5]	12	1			T19	3		T240	1		T301	1
auto[1]	values[2]	values[6]	14	1			T18	1		T100	3		T192	1
auto[1]	values[2]	values[7]	25	1			T15	2		T193	1		T209	4
auto[1]	values[3]	values[0]	4	1			T39	1		T302	1		T295	1
auto[1]	values[3]	values[1]	10	1			T49	1		T87	1		T208	1
auto[1]	values[3]	values[2]	16	1			T210	2		T39	3		T303	2
auto[1]	values[3]	values[3]	7	1			T240	2		T304	1		T305	1
auto[1]	values[3]	values[4]	10	1			T210	5		T169	1		T281	2
auto[1]	values[3]	values[5]	8	1			T202	1		T194	3		T198	1
auto[1]	values[3]	values[6]	16	1			T207	1		T229	1		T306	2
auto[1]	values[3]	values[7]	6	1			T192	1		T240	1		T196	1
auto[1]	values[4]	values[0]	21	1			T49	5		T225	3		T276	2
auto[1]	values[4]	values[1]	21	1			T21	1		T213	1		T218	1
auto[1]	values[4]	values[2]	8	1			T270	4		T279	1		T307	2
auto[1]	values[4]	values[3]	13	1			T34	2		T202	3		T220	2
auto[1]	values[4]	values[4]	12	1			T182	2		T87	1		T301	1
auto[1]	values[4]	values[5]	10	1			T22	1		T100	1		T206	2
auto[1]	values[4]	values[6]	15	1			T15	1		T33	1		T294	1
auto[1]	values[4]	values[7]	4	1			T296	3		T308	1		-	-
auto[1]	values[5]	values[0]	11	1			T18	1		T270	2		T218	1
auto[1]	values[5]	values[1]	17	1			T192	1		T280	4		T295	1
auto[1]	values[5]	values[2]	17	1			T220	1		T229	2		T39	1
auto[1]	values[5]	values[3]	9	1			T49	1		T201	4		T247	2
auto[1]	values[5]	values[4]	16	1			T34	3		T301	1		T196	2
auto[1]	values[5]	values[5]	21	1			T18	1		T309	2		T310	3
auto[1]	values[5]	values[6]	16	1			T193	1		T194	1		T280	4
auto[1]	values[5]	values[7]	15	1			T33	1		T182	1		T280	1
auto[1]	values[6]	values[0]	8	1			T225	1		T304	4		T54	1
auto[1]	values[6]	values[1]	16	1			T15	3		T26	1		T301	5
auto[1]	values[6]	values[2]	18	1			T228	4		T213	1		T279	2
auto[1]	values[6]	values[3]	5	1			T229	1		T240	1		T311	1
auto[1]	values[6]	values[4]	4	1			T15	2		T232	1		T312	1
auto[1]	values[6]	values[5]	10	1			T238	1		T295	3		T313	1
auto[1]	values[6]	values[6]	11	1			T204	1		T213	2		T314	1
auto[1]	values[6]	values[7]	6	1			T192	2		T204	2		T207	1
auto[1]	values[7]	values[0]	12	1			T192	1		T315	2		T80	3
auto[1]	values[7]	values[1]	9	1			T194	3		T293	1		T169	2
auto[1]	values[7]	values[2]	15	1			T210	1		T193	1		T202	2
auto[1]	values[7]	values[3]	9	1			T46	2		T247	1		T316	4
auto[1]	values[7]	values[4]	20	1			T213	1		T317	1		T172	4
auto[1]	values[7]	values[5]	6	1			T204	1		T209	3		T318	1
auto[1]	values[7]	values[6]	11	1			T296	1		T309	2		T319	1
auto[1]	values[7]	values[7]	10	1			T209	1		T172	4		T259	2