Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	875	1			T16	11		T17	10		T19	27
all_values[1]	875	1			T16	11		T17	10		T19	27
all_values[2]	875	1			T16	11		T17	10		T19	27
all_values[3]	875	1			T16	11		T17	10		T19	27
all_values[4]	875	1			T16	11		T17	10		T19	27
all_values[5]	875	1			T16	11		T17	10		T19	27
all_values[6]	875	1			T16	11		T17	10		T19	27
all_values[7]	875	1			T16	11		T17	10		T19	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3750

1

T16

52

T17

38

T19

118

auto[1]

3250

1

T16

36

T17

42

T19

98

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2782

1

T16

42

T17

30

T19

74

auto[1]

4218

1

T16

46

T17

50

T19

142

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3995

1

T16

50

T17

42

T19

123

auto[1]

3005

1

T16

38

T17

38

T19

93

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	195	1			T16	5		T17	3		T19	6
all_values[0]	auto[0]	auto[0]	auto[1]	91	1			T17	1		T19	3		T20	2
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T16	5		T17	1		T19	5
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T17	1		T19	4		T20	3
all_values[0]	auto[1]	auto[0]	auto[1]	202	1			T17	1		T19	4		T20	4
all_values[0]	auto[1]	auto[1]	auto[1]	162	1			T16	1		T17	3		T19	5
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T16	4		T17	1		T19	5
all_values[1]	auto[0]	auto[0]	auto[1]	100	1			T16	1		T17	2		T19	3
all_values[1]	auto[0]	auto[1]	auto[0]	141	1			T16	2		T17	2		T19	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T19	7		T35	1		T166	2
all_values[1]	auto[1]	auto[0]	auto[1]	206	1			T16	2		T17	3		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	181	1			T16	2		T17	2		T19	5
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T16	2		T17	2		T19	5
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T16	2		T19	2		T20	3
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T16	2		T19	1		T20	2
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T17	1		T19	4		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T16	4		T17	3		T19	8
all_values[2]	auto[1]	auto[1]	auto[1]	183	1			T16	1		T17	4		T19	7
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T16	4		T17	2		T19	6
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T16	2		T19	3		T20	1
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T16	1		T19	1		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	90	1			T17	2		T19	3		T20	1
all_values[3]	auto[1]	auto[0]	auto[1]	221	1			T16	4		T17	2		T19	8
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T17	4		T19	6		T20	1
all_values[4]	auto[0]	auto[0]	auto[0]	187	1			T16	2		T17	4		T19	2
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T17	2		T19	3		T20	5
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T16	2		T19	3		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T16	1		T19	5		T20	3
all_values[4]	auto[1]	auto[0]	auto[1]	195	1			T16	1		T17	1		T19	9
all_values[4]	auto[1]	auto[1]	auto[1]	172	1			T16	5		T17	3		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	254	1			T16	2		T17	2		T19	5
all_values[5]	auto[0]	auto[1]	auto[0]	224	1			T16	1		T17	2		T19	6
all_values[5]	auto[1]	auto[0]	auto[1]	221	1			T16	7		T17	1		T19	12
all_values[5]	auto[1]	auto[1]	auto[1]	176	1			T16	1		T17	5		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T16	1		T17	3		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T16	1		T19	6		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T16	3		T17	4		T19	7
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T16	1		T17	1		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	218	1			T16	3		T17	1		T19	4
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T16	2		T17	1		T19	6
all_values[7]	auto[0]	auto[0]	auto[0]	188	1			T16	3		T17	2		T19	10
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T17	1		T19	3		T20	3
all_values[7]	auto[0]	auto[1]	auto[0]	180	1			T16	3		T17	2		T19	6
all_values[7]	auto[0]	auto[1]	auto[1]	92	1			T17	1		T19	2		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T16	2		T17	1		T19	4
all_values[7]	auto[1]	auto[1]	auto[1]	160	1			T16	3		T17	3		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal