Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1851

1

T4

6

T5

5

T7

3

auto[1]

1807

1

T4

11

T5

4

T7

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T4

17

T14

19

T32

5

auto[1]

1742

1

T5

9

T7

14

T30

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2924

1

T4

12

T5

9

T7

14

auto[1]

734

1

T4

5

T14

4

T32

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	690	1			T4	4		T5	2		T7	5
valid[1]	774	1			T4	5		T5	1		T7	3
valid[2]	719	1			T4	2		T5	3		T7	3
valid[3]	728	1			T4	3		T5	1		T7	1
valid[4]	747	1			T4	3		T5	2		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T4	2		T14	2		T32	1
auto[0]	auto[0]	valid[0]	auto[1]	172	1			T5	2		T30	2		T31	1
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T4	2		T33	1		T42	2
auto[0]	auto[0]	valid[1]	auto[1]	174	1			T30	1		T31	1		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	122	1			T14	3		T332	3		T325	1
auto[0]	auto[0]	valid[2]	auto[1]	169	1			T5	2		T7	1		T30	3
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T14	2		T37	1		T53	1
auto[0]	auto[0]	valid[3]	auto[1]	181	1			T30	1		T31	2		T33	1
auto[0]	auto[0]	valid[4]	auto[0]	110	1			T32	1		T324	1		T49	1
auto[0]	auto[0]	valid[4]	auto[1]	196	1			T5	1		T7	2		T30	3
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T4	2		T14	4		T37	3
auto[0]	auto[1]	valid[0]	auto[1]	163	1			T7	5		T31	4		T32	1
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T4	3		T14	1		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	195	1			T5	1		T7	3		T31	8
auto[0]	auto[1]	valid[2]	auto[0]	135	1			T14	2		T42	2		T37	1
auto[0]	auto[1]	valid[2]	auto[1]	135	1			T5	1		T7	2		T31	4
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T4	1		T49	1		T325	1
auto[0]	auto[1]	valid[3]	auto[1]	186	1			T5	1		T7	1		T31	10
auto[0]	auto[1]	valid[4]	auto[0]	105	1			T4	2		T14	1		T33	1
auto[0]	auto[1]	valid[4]	auto[1]	171	1			T5	1		T30	1		T31	4
auto[1]	auto[0]	valid[0]	auto[0]	64	1			T32	1		T37	1		T324	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T33	1		T37	1		T324	1
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T4	1		T14	1		T37	1
auto[1]	auto[0]	valid[3]	auto[0]	58	1			T325	1		T242	1		T51	2
auto[1]	auto[0]	valid[4]	auto[0]	94	1			T4	1		T14	1		T42	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T14	1		T37	2		T332	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T33	1		T37	1		T332	1
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T4	1		T32	1		T49	2
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T4	2		T33	1		T42	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T14	1		T32	1		T37	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal