Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49697

1

T4

468

T11

13

T14

510

auto[1]

18760

1

T5

9

T7

147

T30

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50285

1

T4

297

T5

9

T7

147

auto[1]

18172

1

T4

171

T11

7

T14

197

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35132	1			T4	240		T5	9		T7	79
others[1]	5742	1			T4	39		T7	13		T11	1
others[2]	5907	1			T4	39		T7	7		T31	56
others[3]	6531	1			T4	52		T7	15		T31	49
interest[1]	3864	1			T4	34		T7	9		T31	29
interest[4]	23070	1			T4	154		T5	9		T7	51
interest[64]	11281	1			T4	64		T7	24		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16116	1			T4	145		T11	6		T14	148
auto[0]	auto[0]	others[1]	2610	1			T4	23		T14	28		T27	3
auto[0]	auto[0]	others[2]	2738	1			T4	23		T14	31		T27	2
auto[0]	auto[0]	others[3]	2989	1			T4	34		T14	30		T27	3
auto[0]	auto[0]	interest[1]	1843	1			T4	24		T14	21		T32	9
auto[0]	auto[0]	interest[4]	10522	1			T4	91		T11	6		T14	91
auto[0]	auto[0]	interest[64]	5229	1			T4	48		T14	55		T27	9
auto[0]	auto[1]	others[0]	9783	1			T5	9		T7	79		T30	11
auto[0]	auto[1]	others[1]	1545	1			T7	13		T31	29		T14	6
auto[0]	auto[1]	others[2]	1558	1			T7	7		T31	56		T14	5
auto[0]	auto[1]	others[3]	1808	1			T7	15		T31	49		T14	4
auto[0]	auto[1]	interest[1]	1015	1			T7	9		T31	29		T14	2
auto[0]	auto[1]	interest[4]	6511	1			T5	9		T7	51		T30	11
auto[0]	auto[1]	interest[64]	3051	1			T7	24		T31	90		T14	9
auto[1]	auto[0]	others[0]	9233	1			T4	95		T11	5		T14	96
auto[1]	auto[0]	others[1]	1587	1			T4	16		T11	1		T14	21
auto[1]	auto[0]	others[2]	1611	1			T4	16		T14	17		T32	9
auto[1]	auto[0]	others[3]	1734	1			T4	18		T14	20		T27	5
auto[1]	auto[0]	interest[1]	1006	1			T4	10		T14	7		T27	1
auto[1]	auto[0]	interest[4]	6037	1			T4	63		T11	4		T14	67
auto[1]	auto[0]	interest[64]	3001	1			T4	16		T11	1		T14	36

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal