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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T1040 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1173903456 Aug 03 04:27:28 PM PDT 24 Aug 03 04:27:29 PM PDT 24 11471958 ps
T124 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2319944025 Aug 03 04:27:06 PM PDT 24 Aug 03 04:27:27 PM PDT 24 801641366 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1504868066 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:09 PM PDT 24 312102797 ps
T159 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3371373946 Aug 03 04:26:58 PM PDT 24 Aug 03 04:27:11 PM PDT 24 1737393711 ps
T1042 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4184591779 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:13 PM PDT 24 33668508 ps
T1043 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2992666751 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:15 PM PDT 24 31045231 ps
T132 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1478759061 Aug 03 04:27:08 PM PDT 24 Aug 03 04:27:10 PM PDT 24 403837873 ps
T89 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3263762504 Aug 03 04:26:55 PM PDT 24 Aug 03 04:26:56 PM PDT 24 42363531 ps
T1044 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4063617404 Aug 03 04:27:39 PM PDT 24 Aug 03 04:27:40 PM PDT 24 30443241 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2502025293 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:24 PM PDT 24 1048638483 ps
T1046 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1954408185 Aug 03 04:27:26 PM PDT 24 Aug 03 04:27:27 PM PDT 24 13298634 ps
T125 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3774869624 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:23 PM PDT 24 435162321 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1069401783 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:23 PM PDT 24 131355193 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.239120022 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:54 PM PDT 24 60341333 ps
T1048 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.113531847 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:19 PM PDT 24 15941651 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3851842117 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:09 PM PDT 24 515205051 ps
T1050 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2832078335 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:09 PM PDT 24 229057313 ps
T121 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1437826771 Aug 03 04:27:07 PM PDT 24 Aug 03 04:27:10 PM PDT 24 43480454 ps
T126 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3585959949 Aug 03 04:27:16 PM PDT 24 Aug 03 04:27:20 PM PDT 24 157126442 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1515513693 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:05 PM PDT 24 10846577 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1778542534 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:13 PM PDT 24 20584016 ps
T115 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3969401596 Aug 03 04:27:14 PM PDT 24 Aug 03 04:27:16 PM PDT 24 25412325 ps
T186 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3720498709 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:17 PM PDT 24 785946998 ps
T1053 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2263700190 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:03 PM PDT 24 54079911 ps
T160 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2484919303 Aug 03 04:26:50 PM PDT 24 Aug 03 04:27:06 PM PDT 24 699185857 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.176447858 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:15 PM PDT 24 161049325 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.348486079 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:57 PM PDT 24 2433614883 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1261556991 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 11347690 ps
T187 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1658791431 Aug 03 04:27:15 PM PDT 24 Aug 03 04:27:36 PM PDT 24 3504764831 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036191470 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:22 PM PDT 24 524500577 ps
T161 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1019839030 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:27 PM PDT 24 5175796058 ps
T1056 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.228295798 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:22 PM PDT 24 208845872 ps
T133 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1303091814 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:22 PM PDT 24 325965461 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3826847038 Aug 03 04:26:52 PM PDT 24 Aug 03 04:26:53 PM PDT 24 43173818 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1782354517 Aug 03 04:26:56 PM PDT 24 Aug 03 04:26:57 PM PDT 24 40607641 ps
T188 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.102501460 Aug 03 04:26:53 PM PDT 24 Aug 03 04:27:04 PM PDT 24 758644296 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.646008065 Aug 03 04:27:06 PM PDT 24 Aug 03 04:27:10 PM PDT 24 308341346 ps
T1060 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2566236015 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 43699023 ps
T1061 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1488199917 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 15088922 ps
T1062 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1139344118 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 12190237 ps
T111 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3213951993 Aug 03 04:27:04 PM PDT 24 Aug 03 04:27:07 PM PDT 24 154994562 ps
T162 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2714214905 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:43 PM PDT 24 7662731404 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2206723953 Aug 03 04:26:52 PM PDT 24 Aug 03 04:27:15 PM PDT 24 1259687989 ps
T1064 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.148843011 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:21 PM PDT 24 19173939 ps
T112 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.553538600 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:15 PM PDT 24 108980404 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2686311542 Aug 03 04:27:15 PM PDT 24 Aug 03 04:27:16 PM PDT 24 32496098 ps
T1066 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2085103740 Aug 03 04:27:08 PM PDT 24 Aug 03 04:27:09 PM PDT 24 11144377 ps
T163 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.937933803 Aug 03 04:27:00 PM PDT 24 Aug 03 04:27:01 PM PDT 24 26196507 ps
T1067 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1117626986 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:23 PM PDT 24 17092412 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1505571825 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:26 PM PDT 24 5029251439 ps
T164 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3034466279 Aug 03 04:27:09 PM PDT 24 Aug 03 04:27:11 PM PDT 24 406356224 ps
T1069 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3744568700 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:18 PM PDT 24 97905622 ps
T1070 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.860132704 Aug 03 04:27:23 PM PDT 24 Aug 03 04:27:24 PM PDT 24 26077779 ps
T134 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.798522636 Aug 03 04:27:15 PM PDT 24 Aug 03 04:27:17 PM PDT 24 26896399 ps
T114 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2685366103 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:22 PM PDT 24 135945691 ps
T1071 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.969027230 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 15719414 ps
T135 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3996025649 Aug 03 04:26:52 PM PDT 24 Aug 03 04:27:18 PM PDT 24 12881654430 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1293154284 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:25 PM PDT 24 102569697 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2067969191 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:24 PM PDT 24 57177341 ps
T1074 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2552567968 Aug 03 04:27:24 PM PDT 24 Aug 03 04:27:25 PM PDT 24 24167411 ps
T1075 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3561133793 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:34 PM PDT 24 2877254995 ps
T136 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.77294761 Aug 03 04:27:10 PM PDT 24 Aug 03 04:27:12 PM PDT 24 322265509 ps
T165 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1431440420 Aug 03 04:26:55 PM PDT 24 Aug 03 04:26:59 PM PDT 24 378989582 ps
T1076 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3377284384 Aug 03 04:27:28 PM PDT 24 Aug 03 04:27:29 PM PDT 24 49147831 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3880840732 Aug 03 04:26:57 PM PDT 24 Aug 03 04:26:59 PM PDT 24 73704107 ps
T138 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3806615669 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:53 PM PDT 24 26294044 ps
T119 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2424410108 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:24 PM PDT 24 157967636 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1375165987 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:52 PM PDT 24 30719189 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1310705133 Aug 03 04:26:59 PM PDT 24 Aug 03 04:27:03 PM PDT 24 878169283 ps
T139 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1893803126 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 75936215 ps
T1079 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1089642817 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:23 PM PDT 24 14520024 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1166134641 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:16 PM PDT 24 162542276 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2358669626 Aug 03 04:26:52 PM PDT 24 Aug 03 04:26:55 PM PDT 24 238474242 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.577952816 Aug 03 04:26:53 PM PDT 24 Aug 03 04:27:02 PM PDT 24 974974760 ps
T190 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4140780122 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:18 PM PDT 24 2609248157 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1580112568 Aug 03 04:27:00 PM PDT 24 Aug 03 04:27:02 PM PDT 24 29046902 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3598194015 Aug 03 04:26:52 PM PDT 24 Aug 03 04:27:15 PM PDT 24 1630116354 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1337763615 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:23 PM PDT 24 36013436 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1380879890 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:08 PM PDT 24 37974417 ps
T116 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1557402902 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:26 PM PDT 24 191770600 ps
T1086 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3049180771 Aug 03 04:27:39 PM PDT 24 Aug 03 04:27:40 PM PDT 24 14355798 ps
T118 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1991738374 Aug 03 04:27:11 PM PDT 24 Aug 03 04:27:16 PM PDT 24 260868710 ps
T1087 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1429751396 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:22 PM PDT 24 155809646 ps
T90 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.222533332 Aug 03 04:26:59 PM PDT 24 Aug 03 04:27:00 PM PDT 24 125693141 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.733140766 Aug 03 04:26:53 PM PDT 24 Aug 03 04:26:54 PM PDT 24 19206863 ps
T117 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.100738577 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:09 PM PDT 24 255123737 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.892215006 Aug 03 04:27:08 PM PDT 24 Aug 03 04:27:16 PM PDT 24 1252793933 ps
T1090 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.216847220 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:22 PM PDT 24 44286837 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1434982496 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:02 PM PDT 24 27368969 ps
T1092 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3599348416 Aug 03 04:26:57 PM PDT 24 Aug 03 04:26:59 PM PDT 24 121707408 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.358276013 Aug 03 04:27:11 PM PDT 24 Aug 03 04:27:13 PM PDT 24 104209625 ps
T1094 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3367954368 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:21 PM PDT 24 239716609 ps
T1095 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2109261587 Aug 03 04:27:14 PM PDT 24 Aug 03 04:27:17 PM PDT 24 42635350 ps
T1096 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1042214384 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 34989329 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3361653588 Aug 03 04:27:08 PM PDT 24 Aug 03 04:27:11 PM PDT 24 38264413 ps
T1098 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4291093017 Aug 03 04:26:50 PM PDT 24 Aug 03 04:26:52 PM PDT 24 353941828 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.556097683 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:23 PM PDT 24 15395427 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1100010489 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:02 PM PDT 24 10856621 ps
T1101 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1409294963 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:22 PM PDT 24 12820371 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2477075154 Aug 03 04:27:24 PM PDT 24 Aug 03 04:27:26 PM PDT 24 111906170 ps
T1103 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3230780454 Aug 03 04:27:25 PM PDT 24 Aug 03 04:27:26 PM PDT 24 25352035 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1281286527 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:04 PM PDT 24 85525725 ps
T1105 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2212869984 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:15 PM PDT 24 49455739 ps
T189 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.377836534 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:19 PM PDT 24 211673114 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.377375045 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:18 PM PDT 24 37094580 ps
T1107 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.785172594 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:19 PM PDT 24 23672674 ps
T1108 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2434639027 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:42 PM PDT 24 13457652145 ps
T1109 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3352615274 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:21 PM PDT 24 12954009 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4160854451 Aug 03 04:26:58 PM PDT 24 Aug 03 04:26:59 PM PDT 24 22039413 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.719226990 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:54 PM PDT 24 351011247 ps
T1112 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1723777958 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:19 PM PDT 24 38272581 ps
T185 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3107871024 Aug 03 04:27:05 PM PDT 24 Aug 03 04:27:09 PM PDT 24 56964107 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2813590416 Aug 03 04:26:49 PM PDT 24 Aug 03 04:26:53 PM PDT 24 157324638 ps
T1114 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2462771765 Aug 03 04:26:56 PM PDT 24 Aug 03 04:27:05 PM PDT 24 443268552 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.213833270 Aug 03 04:26:58 PM PDT 24 Aug 03 04:26:59 PM PDT 24 14828931 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1642588160 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:17 PM PDT 24 18262147 ps
T1117 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4184324643 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:18 PM PDT 24 44651211 ps
T1118 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1206318540 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:15 PM PDT 24 25882487 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2277044682 Aug 03 04:27:00 PM PDT 24 Aug 03 04:27:04 PM PDT 24 466804719 ps
T1120 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2606421885 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:22 PM PDT 24 43450918 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3462173915 Aug 03 04:27:22 PM PDT 24 Aug 03 04:27:25 PM PDT 24 39293295 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2957763529 Aug 03 04:26:55 PM PDT 24 Aug 03 04:26:57 PM PDT 24 705419242 ps
T1123 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3219126519 Aug 03 04:27:18 PM PDT 24 Aug 03 04:27:20 PM PDT 24 85318885 ps
T1124 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4101416410 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 40126279 ps
T1125 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1336758903 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:24 PM PDT 24 233403194 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.372493501 Aug 03 04:26:57 PM PDT 24 Aug 03 04:26:57 PM PDT 24 31908352 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1271499279 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:55 PM PDT 24 479158467 ps
T1128 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3574708199 Aug 03 04:27:06 PM PDT 24 Aug 03 04:27:07 PM PDT 24 23838547 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2403159317 Aug 03 04:27:14 PM PDT 24 Aug 03 04:27:16 PM PDT 24 66375961 ps
T1130 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2238981616 Aug 03 04:27:32 PM PDT 24 Aug 03 04:27:33 PM PDT 24 12539979 ps
T1131 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2276509464 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:14 PM PDT 24 37745841 ps
T1132 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3886077774 Aug 03 04:27:21 PM PDT 24 Aug 03 04:27:22 PM PDT 24 47614064 ps
T1133 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3488433474 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:57 PM PDT 24 800301013 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1335292339 Aug 03 04:26:59 PM PDT 24 Aug 03 04:27:08 PM PDT 24 424912524 ps
T1135 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2809392135 Aug 03 04:27:01 PM PDT 24 Aug 03 04:27:05 PM PDT 24 151103540 ps
T1136 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3183334626 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:23 PM PDT 24 181937490 ps
T1137 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3618642702 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:16 PM PDT 24 871548292 ps
T1138 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1086698280 Aug 03 04:27:11 PM PDT 24 Aug 03 04:27:12 PM PDT 24 30488803 ps
T1139 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1920916559 Aug 03 04:27:12 PM PDT 24 Aug 03 04:27:15 PM PDT 24 983307187 ps
T1140 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1406294905 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:20 PM PDT 24 77611160 ps
T1141 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2362455914 Aug 03 04:27:28 PM PDT 24 Aug 03 04:27:29 PM PDT 24 35438363 ps
T1142 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3883127100 Aug 03 04:27:13 PM PDT 24 Aug 03 04:27:14 PM PDT 24 19084729 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.940224205 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:52 PM PDT 24 82362346 ps
T1144 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1481077539 Aug 03 04:27:17 PM PDT 24 Aug 03 04:27:19 PM PDT 24 92725519 ps
T1145 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3382736406 Aug 03 04:27:00 PM PDT 24 Aug 03 04:27:02 PM PDT 24 139586182 ps
T1146 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.199743864 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:52 PM PDT 24 76047925 ps
T1147 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1609086743 Aug 03 04:27:15 PM PDT 24 Aug 03 04:27:23 PM PDT 24 267396677 ps
T1148 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4006081318 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:21 PM PDT 24 16534017 ps
T1149 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3381982209 Aug 03 04:27:19 PM PDT 24 Aug 03 04:27:20 PM PDT 24 43615493 ps
T1150 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2157559286 Aug 03 04:27:20 PM PDT 24 Aug 03 04:27:21 PM PDT 24 54649872 ps
T1151 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3887607899 Aug 03 04:26:52 PM PDT 24 Aug 03 04:27:22 PM PDT 24 5233285326 ps

Test location /workspace/coverage/default/41.spi_device_flash_all.866978953
Short name T10
Test name
Test status
Simulation time 31406623367 ps
CPU time 200.94 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:31:14 PM PDT 24
Peak memory 250944 kb
Host smart-bc7be943-d286-4e03-b9a5-52687365574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866978953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.866978953
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3090104205
Short name T33
Test name
Test status
Simulation time 8584384723 ps
CPU time 138.1 seconds
Started Aug 03 05:27:21 PM PDT 24
Finished Aug 03 05:29:39 PM PDT 24
Peak memory 249896 kb
Host smart-41885891-500f-4e6d-a4b3-16814d56484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090104205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3090104205
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2678660953
Short name T18
Test name
Test status
Simulation time 67547705806 ps
CPU time 704.46 seconds
Started Aug 03 05:27:55 PM PDT 24
Finished Aug 03 05:39:39 PM PDT 24
Peak memory 286360 kb
Host smart-4f4e1f2b-17da-4297-ba2e-4ec586b4eedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678660953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2678660953
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1040631655
Short name T19
Test name
Test status
Simulation time 148120768834 ps
CPU time 373.11 seconds
Started Aug 03 05:28:20 PM PDT 24
Finished Aug 03 05:34:34 PM PDT 24
Peak memory 262892 kb
Host smart-6dd3b93d-a99b-4b91-9990-b0d2abd7e65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040631655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1040631655
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3774869624
Short name T125
Test name
Test status
Simulation time 435162321 ps
CPU time 2.81 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 217880 kb
Host smart-787d6049-7f63-4c98-8b6c-fe74ed5c195c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774869624 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3774869624
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2620606542
Short name T15
Test name
Test status
Simulation time 8677983751 ps
CPU time 116.46 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 265668 kb
Host smart-37b4fcb3-fbed-45e3-adba-646ef101fb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620606542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2620606542
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2304606937
Short name T70
Test name
Test status
Simulation time 38731289 ps
CPU time 0.73 seconds
Started Aug 03 05:25:43 PM PDT 24
Finished Aug 03 05:25:44 PM PDT 24
Peak memory 216672 kb
Host smart-6588a03b-4c0a-4b4c-a327-e92bd8704053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304606937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2304606937
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4138613209
Short name T14
Test name
Test status
Simulation time 201984263538 ps
CPU time 336.93 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:32:29 PM PDT 24
Peak memory 256888 kb
Host smart-b879339a-db93-48c0-979b-b720bdde7a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138613209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4138613209
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4199041239
Short name T49
Test name
Test status
Simulation time 4035539300 ps
CPU time 96.86 seconds
Started Aug 03 05:27:31 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 268500 kb
Host smart-453b5583-685a-4bd4-bdde-3f48831ee38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199041239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4199041239
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2433010295
Short name T204
Test name
Test status
Simulation time 49797794857 ps
CPU time 497.11 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:34:32 PM PDT 24
Peak memory 274208 kb
Host smart-12ffe11e-f284-4dca-ad63-649ac954aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433010295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2433010295
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3036415453
Short name T102
Test name
Test status
Simulation time 296371166 ps
CPU time 16.13 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:37 PM PDT 24
Peak memory 215452 kb
Host smart-f8bd394f-9c77-4f9d-8ead-dd8934cf5b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036415453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3036415453
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3233248116
Short name T3
Test name
Test status
Simulation time 729648032 ps
CPU time 13.5 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 233492 kb
Host smart-e85ea58a-ad87-438e-8955-91bb53d7f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233248116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3233248116
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2838513998
Short name T39
Test name
Test status
Simulation time 452726871741 ps
CPU time 547.13 seconds
Started Aug 03 05:27:42 PM PDT 24
Finished Aug 03 05:36:49 PM PDT 24
Peak memory 257148 kb
Host smart-2238a1ff-03d5-47ba-a68e-fc9f213078d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838513998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2838513998
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3905667469
Short name T68
Test name
Test status
Simulation time 19909803 ps
CPU time 0.73 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:25:45 PM PDT 24
Peak memory 205872 kb
Host smart-f4b096b0-b065-4624-8325-fe2ffdfe62ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905667469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
905667469
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1845571949
Short name T87
Test name
Test status
Simulation time 77838432688 ps
CPU time 665.97 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:38:22 PM PDT 24
Peak memory 265888 kb
Host smart-fe316834-d301-4799-9a6e-210e2e654092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845571949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1845571949
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3099871359
Short name T192
Test name
Test status
Simulation time 185564580329 ps
CPU time 223.62 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:29:56 PM PDT 24
Peak memory 273632 kb
Host smart-af81fb86-bfcd-4d47-b49e-9f835d6fdf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099871359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3099871359
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3996025649
Short name T135
Test name
Test status
Simulation time 12881654430 ps
CPU time 26.28 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 215448 kb
Host smart-462de580-273f-4e5b-a3bd-48060a60c3a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996025649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3996025649
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2901246918
Short name T172
Test name
Test status
Simulation time 858540534876 ps
CPU time 2061.38 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 06:01:52 PM PDT 24
Peak memory 304940 kb
Host smart-72494207-5d89-47f4-b2bf-79e7b4804968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901246918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2901246918
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1419348896
Short name T104
Test name
Test status
Simulation time 55284567 ps
CPU time 3.18 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215772 kb
Host smart-1bd25e00-2f4e-42d6-b5d1-dc968a7d69ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419348896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1419348896
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2948510344
Short name T363
Test name
Test status
Simulation time 108372207 ps
CPU time 1.06 seconds
Started Aug 03 05:25:48 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 218476 kb
Host smart-faf6f912-d54d-47dd-88b0-88043d390923
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948510344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2948510344
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3107592128
Short name T281
Test name
Test status
Simulation time 22410226127 ps
CPU time 44.79 seconds
Started Aug 03 05:28:19 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 255980 kb
Host smart-32a1fda7-9b84-48f3-b025-73e29c0f278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107592128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3107592128
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3487332497
Short name T182
Test name
Test status
Simulation time 3888920543 ps
CPU time 93.87 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:28:34 PM PDT 24
Peak memory 266284 kb
Host smart-73ce8442-8784-4215-a242-b8d7c9621539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487332497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3487332497
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3901008291
Short name T54
Test name
Test status
Simulation time 267696324111 ps
CPU time 679.89 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:37:12 PM PDT 24
Peak memory 262460 kb
Host smart-d54c5fc9-239c-408c-bc45-ac7a6a6fe719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901008291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3901008291
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.757227201
Short name T75
Test name
Test status
Simulation time 329043984 ps
CPU time 1.18 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:47 PM PDT 24
Peak memory 235592 kb
Host smart-e914aa30-32f6-43a9-b6b3-4e438e40d6b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757227201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.757227201
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3045951306
Short name T16
Test name
Test status
Simulation time 26306274589 ps
CPU time 249.98 seconds
Started Aug 03 05:26:13 PM PDT 24
Finished Aug 03 05:30:23 PM PDT 24
Peak memory 258036 kb
Host smart-eedf4f50-8426-4109-8afe-fc3e78572db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045951306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3045951306
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2432013938
Short name T280
Test name
Test status
Simulation time 130782860106 ps
CPU time 458.91 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:35:23 PM PDT 24
Peak memory 282388 kb
Host smart-a41b7dfa-ef78-4455-9906-15dbe5291e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432013938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2432013938
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1462458628
Short name T200
Test name
Test status
Simulation time 143123883754 ps
CPU time 693.38 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:37:23 PM PDT 24
Peak memory 258104 kb
Host smart-77f87ab0-f51d-4033-9921-9356cdf34951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462458628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1462458628
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3107871024
Short name T185
Test name
Test status
Simulation time 56964107 ps
CPU time 3.29 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 215592 kb
Host smart-1308af64-bbca-4174-9f6a-dbb96a20df78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107871024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
107871024
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.77464752
Short name T240
Test name
Test status
Simulation time 245927653901 ps
CPU time 563.3 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:35:25 PM PDT 24
Peak memory 269560 kb
Host smart-24d885c1-5fdb-4f52-b334-a158c21ff222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77464752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_
all.77464752
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3142378848
Short name T56
Test name
Test status
Simulation time 117690395026 ps
CPU time 96.53 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:28:28 PM PDT 24
Peak memory 237928 kb
Host smart-de8509cc-dee3-46a1-a077-bac9ed88d5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142378848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3142378848
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.314879719
Short name T300
Test name
Test status
Simulation time 4274031445 ps
CPU time 101.9 seconds
Started Aug 03 05:26:31 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 258032 kb
Host smart-583dc326-d211-4b3e-8276-7b190ded8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314879719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.314879719
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3821314634
Short name T194
Test name
Test status
Simulation time 42090481182 ps
CPU time 49.95 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 254524 kb
Host smart-7c637ede-72a1-44f3-8a5b-33fa378b1d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821314634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3821314634
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2319944025
Short name T124
Test name
Test status
Simulation time 801641366 ps
CPU time 20.12 seconds
Started Aug 03 04:27:06 PM PDT 24
Finished Aug 03 04:27:27 PM PDT 24
Peak memory 215444 kb
Host smart-2833402a-305e-4af4-bb63-8e42d861a898
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319944025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2319944025
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3550549516
Short name T296
Test name
Test status
Simulation time 15736897962 ps
CPU time 247.09 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:30:53 PM PDT 24
Peak memory 289916 kb
Host smart-e40667c2-24c6-440d-ae37-411133ef7a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550549516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3550549516
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1629868518
Short name T324
Test name
Test status
Simulation time 8922958447 ps
CPU time 52.18 seconds
Started Aug 03 05:27:50 PM PDT 24
Finished Aug 03 05:28:42 PM PDT 24
Peak memory 258196 kb
Host smart-7f5dc52d-67f0-4726-836e-f9e2c5754c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629868518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1629868518
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4231670324
Short name T320
Test name
Test status
Simulation time 760442192 ps
CPU time 9.31 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:33 PM PDT 24
Peak memory 249788 kb
Host smart-72730e75-8ef1-4ac6-92c0-be7fe453f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231670324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4231670324
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4215242781
Short name T46
Test name
Test status
Simulation time 147816640741 ps
CPU time 280.19 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:30:47 PM PDT 24
Peak memory 241248 kb
Host smart-75ce4307-c98b-49fc-ab0f-c7e708c3e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215242781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4215242781
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2810745376
Short name T196
Test name
Test status
Simulation time 108263636063 ps
CPU time 933.98 seconds
Started Aug 03 05:26:49 PM PDT 24
Finished Aug 03 05:42:23 PM PDT 24
Peak memory 282748 kb
Host smart-6e8ce4b3-b384-4f30-9539-612be0432035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810745376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2810745376
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3523111910
Short name T22
Test name
Test status
Simulation time 6448644307 ps
CPU time 116.56 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:29:43 PM PDT 24
Peak memory 267824 kb
Host smart-dfca7723-3a7b-4eaf-b368-f4bcf8e9f9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523111910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3523111910
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2279896562
Short name T322
Test name
Test status
Simulation time 841367531 ps
CPU time 5.25 seconds
Started Aug 03 05:25:58 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 225320 kb
Host smart-8206178a-eefa-4293-9348-f893632027df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279896562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2279896562
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2999673698
Short name T96
Test name
Test status
Simulation time 96601906 ps
CPU time 3.44 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 233488 kb
Host smart-0e5bf107-8790-4f1b-8b6d-8a2a527437a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999673698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2999673698
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1609086743
Short name T1147
Test name
Test status
Simulation time 267396677 ps
CPU time 7.2 seconds
Started Aug 03 04:27:15 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 215460 kb
Host smart-8d7fe252-feed-41be-89c6-49462d406532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609086743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1609086743
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1400948502
Short name T246
Test name
Test status
Simulation time 4261633977 ps
CPU time 12.66 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 225256 kb
Host smart-847d8764-4328-4677-a76e-da6605ed3718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400948502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1400948502
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1177942141
Short name T202
Test name
Test status
Simulation time 65897826481 ps
CPU time 153.67 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:28:18 PM PDT 24
Peak memory 249972 kb
Host smart-8652d54d-9881-47c3-945b-a4814d4d10ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177942141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1177942141
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1186252321
Short name T17
Test name
Test status
Simulation time 7057012230 ps
CPU time 104.01 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:27:41 PM PDT 24
Peak memory 256588 kb
Host smart-a2328ee9-200c-4530-b74c-d8dfefeda99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186252321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1186252321
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.100738577
Short name T117
Test name
Test status
Simulation time 255123737 ps
CPU time 3.91 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 215636 kb
Host smart-f5a59e28-7c04-43f2-9237-077909b20dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100738577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.100738577
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3696687234
Short name T282
Test name
Test status
Simulation time 8977255328 ps
CPU time 26.09 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 225280 kb
Host smart-c5c66fbf-3752-4b35-a6b8-c49c2a150cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696687234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3696687234
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.31907223
Short name T91
Test name
Test status
Simulation time 69121716337 ps
CPU time 251.24 seconds
Started Aug 03 05:27:17 PM PDT 24
Finished Aug 03 05:31:29 PM PDT 24
Peak memory 249936 kb
Host smart-8d972222-8769-4adc-a41c-13c967bdf08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31907223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.31907223
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2392063072
Short name T88
Test name
Test status
Simulation time 23368257 ps
CPU time 1.3 seconds
Started Aug 03 04:27:06 PM PDT 24
Finished Aug 03 04:27:08 PM PDT 24
Peak memory 207196 kb
Host smart-3f1bb839-62a3-45b2-ade3-aa7f22fcc020
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392063072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2392063072
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2462988371
Short name T131
Test name
Test status
Simulation time 644665021 ps
CPU time 8.42 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 207188 kb
Host smart-052408e1-c22e-47cf-8732-f8e782db5ffa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462988371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2462988371
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3887607899
Short name T1151
Test name
Test status
Simulation time 5233285326 ps
CPU time 30.18 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 207336 kb
Host smart-da2663b8-f4f5-48dd-a4af-b66cd0ea8d3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887607899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3887607899
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.222533332
Short name T90
Test name
Test status
Simulation time 125693141 ps
CPU time 1.02 seconds
Started Aug 03 04:26:59 PM PDT 24
Finished Aug 03 04:27:00 PM PDT 24
Peak memory 207244 kb
Host smart-57f5ae27-e10d-44e1-8261-af5a5f735576
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222533332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.222533332
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2277044682
Short name T1119
Test name
Test status
Simulation time 466804719 ps
CPU time 3.55 seconds
Started Aug 03 04:27:00 PM PDT 24
Finished Aug 03 04:27:04 PM PDT 24
Peak memory 218312 kb
Host smart-69e61912-65e3-4630-b936-7756b6268e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277044682 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2277044682
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.733140766
Short name T1088
Test name
Test status
Simulation time 19206863 ps
CPU time 1.21 seconds
Started Aug 03 04:26:53 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 215400 kb
Host smart-5ecf3993-b962-40e1-953e-ec8f07dda4a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733140766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.733140766
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1208385262
Short name T1039
Test name
Test status
Simulation time 15196825 ps
CPU time 0.71 seconds
Started Aug 03 04:26:49 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 204248 kb
Host smart-9049a596-4bb1-4a93-be19-f5b9c9338ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208385262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
208385262
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1893803126
Short name T139
Test name
Test status
Simulation time 75936215 ps
CPU time 1.21 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 215416 kb
Host smart-7b6c7797-171e-467f-817b-f6f1def98bff
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893803126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1893803126
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1261556991
Short name T1055
Test name
Test status
Simulation time 11347690 ps
CPU time 0.64 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 203756 kb
Host smart-12913ea4-324e-46bb-910e-1a3af09ce1f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261556991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1261556991
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1431440420
Short name T165
Test name
Test status
Simulation time 378989582 ps
CPU time 4.01 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 215420 kb
Host smart-02cebcfa-d285-42af-ac81-5de239165173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431440420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1431440420
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.239120022
Short name T108
Test name
Test status
Simulation time 60341333 ps
CPU time 3.25 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 215604 kb
Host smart-540ea8a7-9663-4b7e-8b9b-8aa3cab8a86e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239120022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.239120022
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.348486079
Short name T113
Test name
Test status
Simulation time 2433614883 ps
CPU time 12.35 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 215512 kb
Host smart-c195423d-1431-4da4-af7a-426262376b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348486079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.348486079
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2462771765
Short name T1114
Test name
Test status
Simulation time 443268552 ps
CPU time 8.82 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:27:05 PM PDT 24
Peak memory 207084 kb
Host smart-261175a2-6009-4c0f-87fa-bb6aa7609934
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462771765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2462771765
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3263762504
Short name T89
Test name
Test status
Simulation time 42363531 ps
CPU time 0.94 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 206948 kb
Host smart-8a3c03f1-d640-46cd-a68e-33f1fc6861a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263762504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3263762504
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.719226990
Short name T1111
Test name
Test status
Simulation time 351011247 ps
CPU time 2.8 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 216412 kb
Host smart-54421586-e368-420c-bf85-18af93d41159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719226990 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.719226990
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.199743864
Short name T1146
Test name
Test status
Simulation time 76047925 ps
CPU time 1.2 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 215456 kb
Host smart-f7dfdfb0-558b-48ec-824f-e9263ce990e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199743864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.199743864
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.372493501
Short name T1126
Test name
Test status
Simulation time 31908352 ps
CPU time 0.69 seconds
Started Aug 03 04:26:57 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 203776 kb
Host smart-84134068-5994-4217-98db-c52ebac79eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372493501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.372493501
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3382736406
Short name T1145
Test name
Test status
Simulation time 139586182 ps
CPU time 2.3 seconds
Started Aug 03 04:27:00 PM PDT 24
Finished Aug 03 04:27:02 PM PDT 24
Peak memory 215396 kb
Host smart-c09e67a8-60fa-42d9-82e9-87cecf66751a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382736406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3382736406
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1782354517
Short name T1058
Test name
Test status
Simulation time 40607641 ps
CPU time 0.69 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 203684 kb
Host smart-5c9ae215-c976-4b6f-87bb-949bdb7f0d81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782354517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1782354517
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2813590416
Short name T1113
Test name
Test status
Simulation time 157324638 ps
CPU time 4.03 seconds
Started Aug 03 04:26:49 PM PDT 24
Finished Aug 03 04:26:53 PM PDT 24
Peak memory 215436 kb
Host smart-20984bc3-82c3-4cfe-8d72-d77e7d5c8960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813590416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2813590416
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4291093017
Short name T1098
Test name
Test status
Simulation time 353941828 ps
CPU time 2.47 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 215764 kb
Host smart-2ad6c0c6-7ce1-4abd-8b5d-15f9f2885eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291093017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
291093017
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.102501460
Short name T188
Test name
Test status
Simulation time 758644296 ps
CPU time 11.61 seconds
Started Aug 03 04:26:53 PM PDT 24
Finished Aug 03 04:27:04 PM PDT 24
Peak memory 215656 kb
Host smart-08825da9-1694-45e0-96ba-8da320e58f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102501460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.102501460
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3969401596
Short name T115
Test name
Test status
Simulation time 25412325 ps
CPU time 1.44 seconds
Started Aug 03 04:27:14 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215456 kb
Host smart-a3b4584f-a563-4dbc-810f-4882f54e4845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969401596 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3969401596
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1162736270
Short name T127
Test name
Test status
Simulation time 26258422 ps
CPU time 1.35 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:14 PM PDT 24
Peak memory 215440 kb
Host smart-91761d12-bd36-4889-940c-3b3e5ecbe482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162736270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1162736270
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1086698280
Short name T1138
Test name
Test status
Simulation time 30488803 ps
CPU time 0.75 seconds
Started Aug 03 04:27:11 PM PDT 24
Finished Aug 03 04:27:12 PM PDT 24
Peak memory 204156 kb
Host smart-cc2eae4d-5fce-4d73-aa57-0c3a2ae8f032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086698280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1086698280
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.176447858
Short name T1054
Test name
Test status
Simulation time 161049325 ps
CPU time 2.55 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 215552 kb
Host smart-0878cb8a-46ea-43cb-a05a-9cc1b64ff1cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176447858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.176447858
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1991738374
Short name T118
Test name
Test status
Simulation time 260868710 ps
CPU time 4.47 seconds
Started Aug 03 04:27:11 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215716 kb
Host smart-784f13ac-d9e8-4d83-9b41-49d228dab3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991738374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1991738374
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2028404818
Short name T107
Test name
Test status
Simulation time 828625645 ps
CPU time 21.27 seconds
Started Aug 03 04:27:10 PM PDT 24
Finished Aug 03 04:27:32 PM PDT 24
Peak memory 215576 kb
Host smart-3b92b796-fb91-4d4a-831e-a5160d23bb12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028404818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2028404818
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2212869984
Short name T1105
Test name
Test status
Simulation time 49455739 ps
CPU time 1.99 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 215468 kb
Host smart-f94b516c-195f-4045-8265-e51933eb7091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212869984 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2212869984
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2992666751
Short name T1043
Test name
Test status
Simulation time 31045231 ps
CPU time 1.92 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 207248 kb
Host smart-7cd152d2-7d60-4213-8243-736822a8085b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992666751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2992666751
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2276509464
Short name T1131
Test name
Test status
Simulation time 37745841 ps
CPU time 0.76 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:14 PM PDT 24
Peak memory 203872 kb
Host smart-985fdce6-832e-4191-8c77-abd69547c7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276509464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2276509464
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1920916559
Short name T1139
Test name
Test status
Simulation time 983307187 ps
CPU time 2.87 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 215472 kb
Host smart-dd30719e-f06d-4c07-babf-00206db9d234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920916559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1920916559
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.358276013
Short name T1093
Test name
Test status
Simulation time 104209625 ps
CPU time 1.77 seconds
Started Aug 03 04:27:11 PM PDT 24
Finished Aug 03 04:27:13 PM PDT 24
Peak memory 215616 kb
Host smart-6ce36144-72bc-468b-9fc2-9ee10b947003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358276013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.358276013
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1658791431
Short name T187
Test name
Test status
Simulation time 3504764831 ps
CPU time 21.22 seconds
Started Aug 03 04:27:15 PM PDT 24
Finished Aug 03 04:27:36 PM PDT 24
Peak memory 215496 kb
Host smart-dbf7300a-27d2-4d2e-9796-eccd78808405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658791431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1658791431
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1166134641
Short name T1080
Test name
Test status
Simulation time 162542276 ps
CPU time 3.99 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 217996 kb
Host smart-ec1c3668-542b-4a22-a335-d8a85eb1d613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166134641 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1166134641
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2406726156
Short name T128
Test name
Test status
Simulation time 38953033 ps
CPU time 1.27 seconds
Started Aug 03 04:27:11 PM PDT 24
Finished Aug 03 04:27:12 PM PDT 24
Peak memory 215420 kb
Host smart-cd709355-0ce4-42d0-89fa-e34ea552593e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406726156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2406726156
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4184591779
Short name T1042
Test name
Test status
Simulation time 33668508 ps
CPU time 0.74 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:13 PM PDT 24
Peak memory 203856 kb
Host smart-c8d26c01-55e6-4f30-8b5b-97d3a44885c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184591779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4184591779
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2403159317
Short name T1129
Test name
Test status
Simulation time 66375961 ps
CPU time 1.84 seconds
Started Aug 03 04:27:14 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215380 kb
Host smart-0ecd3578-fdda-4624-b83c-31bcfa09aedb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403159317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2403159317
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1406294905
Short name T1140
Test name
Test status
Simulation time 77611160 ps
CPU time 2.77 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 217216 kb
Host smart-f450290b-38b9-418f-a8f9-0e966d7e68d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406294905 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1406294905
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3123407872
Short name T150
Test name
Test status
Simulation time 88391734 ps
CPU time 2.14 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 215444 kb
Host smart-7c2d3dfd-32aa-41c3-82ff-a4d51b1f4e82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123407872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3123407872
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3381982209
Short name T1149
Test name
Test status
Simulation time 43615493 ps
CPU time 0.69 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 204140 kb
Host smart-e101b3e7-58dc-4df9-8a1a-e8d5ffd6bd5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381982209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3381982209
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2502025293
Short name T1045
Test name
Test status
Simulation time 1048638483 ps
CPU time 2.29 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215456 kb
Host smart-251998d1-08a2-4a3a-87c9-a57e47d4268a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502025293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2502025293
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036191470
Short name T110
Test name
Test status
Simulation time 524500577 ps
CPU time 3.44 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 215576 kb
Host smart-edc886f7-952e-436e-9cad-7f03d1bdecd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036191470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3036191470
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2115407311
Short name T106
Test name
Test status
Simulation time 3062474938 ps
CPU time 11.19 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:33 PM PDT 24
Peak memory 215588 kb
Host smart-e48eaf57-4f8d-4157-a96d-7477f4b4edd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115407311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2115407311
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3367954368
Short name T1094
Test name
Test status
Simulation time 239716609 ps
CPU time 3.11 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 218272 kb
Host smart-f507cd75-b369-4023-b8a0-3f1b5623ce20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367954368 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3367954368
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1337763615
Short name T1084
Test name
Test status
Simulation time 36013436 ps
CPU time 2.25 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 215420 kb
Host smart-dd926711-3e41-4c4c-a3d6-73f69d737cf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337763615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1337763615
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2157559286
Short name T1150
Test name
Test status
Simulation time 54649872 ps
CPU time 0.8 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 203872 kb
Host smart-49903d9d-728d-4d03-8914-4192089c70ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157559286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2157559286
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1293154284
Short name T1072
Test name
Test status
Simulation time 102569697 ps
CPU time 2.77 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 215352 kb
Host smart-918ef979-735a-4085-b484-74965c742570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293154284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1293154284
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2993333052
Short name T105
Test name
Test status
Simulation time 47141025 ps
CPU time 1.55 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 216696 kb
Host smart-d7504ba4-3cc0-42db-96ce-db96bb374941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993333052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2993333052
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3004501141
Short name T123
Test name
Test status
Simulation time 199880629 ps
CPU time 11.46 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:30 PM PDT 24
Peak memory 215316 kb
Host smart-9951945a-2060-49f6-a4b9-a6748f9ade33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004501141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3004501141
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3219126519
Short name T1123
Test name
Test status
Simulation time 85318885 ps
CPU time 1.62 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 215416 kb
Host smart-049ac885-131d-4dbd-8b88-89d4c8843ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219126519 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3219126519
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1069401783
Short name T1047
Test name
Test status
Simulation time 131355193 ps
CPU time 1.91 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 206908 kb
Host smart-e6ef1405-0da9-433e-ba64-645e3be93744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069401783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1069401783
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1429751396
Short name T1087
Test name
Test status
Simulation time 155809646 ps
CPU time 0.75 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 204212 kb
Host smart-ef881a88-523f-43e6-97a7-c6402b736081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429751396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1429751396
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1336758903
Short name T1125
Test name
Test status
Simulation time 233403194 ps
CPU time 3.63 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215336 kb
Host smart-6d492e8e-beb4-4433-be51-03c43fbe6eec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336758903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1336758903
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3585959949
Short name T126
Test name
Test status
Simulation time 157126442 ps
CPU time 3.19 seconds
Started Aug 03 04:27:16 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 215780 kb
Host smart-5fcce933-020e-40ed-81ed-2d77f1dbb4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585959949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3585959949
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3744568700
Short name T1069
Test name
Test status
Simulation time 97905622 ps
CPU time 1.62 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 215472 kb
Host smart-a42c82ab-1090-4165-9b9f-7ac0e46546b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744568700 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3744568700
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.216847220
Short name T1090
Test name
Test status
Simulation time 44286837 ps
CPU time 1.3 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 207204 kb
Host smart-d7223ced-1db0-4773-86c5-3f8cfd415015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216847220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.216847220
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4184324643
Short name T1117
Test name
Test status
Simulation time 44651211 ps
CPU time 0.75 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 203868 kb
Host smart-19d5ecf0-1161-4af6-b01b-bfeb2cf69754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184324643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4184324643
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1481077539
Short name T1144
Test name
Test status
Simulation time 92725519 ps
CPU time 1.74 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:19 PM PDT 24
Peak memory 215336 kb
Host smart-b53b543d-6db6-45f7-881b-a0041d79d668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481077539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1481077539
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2477075154
Short name T1102
Test name
Test status
Simulation time 111906170 ps
CPU time 2.04 seconds
Started Aug 03 04:27:24 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 215688 kb
Host smart-16695f9c-bb97-4346-ad53-7ed226142cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477075154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2477075154
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2714214905
Short name T162
Test name
Test status
Simulation time 7662731404 ps
CPU time 22.94 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:43 PM PDT 24
Peak memory 216348 kb
Host smart-3c36cbd3-f2e4-4e45-94d3-73a88cefcff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714214905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2714214905
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.785172594
Short name T1107
Test name
Test status
Simulation time 23672674 ps
CPU time 1.68 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:19 PM PDT 24
Peak memory 215460 kb
Host smart-d1a9246d-1cae-4395-ac7b-136283d805ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785172594 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.785172594
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2261442779
Short name T130
Test name
Test status
Simulation time 82382596 ps
CPU time 2.15 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215360 kb
Host smart-1f527426-0488-4dec-a051-fc9b93e49b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261442779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2261442779
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1642588160
Short name T1116
Test name
Test status
Simulation time 18262147 ps
CPU time 0.72 seconds
Started Aug 03 04:27:17 PM PDT 24
Finished Aug 03 04:27:17 PM PDT 24
Peak memory 203872 kb
Host smart-f33674dd-7bbb-424e-9821-9ee346a068c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642588160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1642588160
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2067969191
Short name T1073
Test name
Test status
Simulation time 57177341 ps
CPU time 3.56 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215412 kb
Host smart-f28e7f4e-278c-4d2c-a373-5c2e3cd28a5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067969191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2067969191
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1557402902
Short name T116
Test name
Test status
Simulation time 191770600 ps
CPU time 4.22 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 215640 kb
Host smart-8b0c371c-331b-4e7f-997b-aea1c0f53db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557402902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1557402902
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3561133793
Short name T1075
Test name
Test status
Simulation time 2877254995 ps
CPU time 14.12 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:34 PM PDT 24
Peak memory 215848 kb
Host smart-f40259a4-f1a3-4c4c-ab65-a387a97905f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561133793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3561133793
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3462173915
Short name T1121
Test name
Test status
Simulation time 39293295 ps
CPU time 2.51 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 216848 kb
Host smart-be3ac03b-430b-49c8-8f8a-d9b89c56afd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462173915 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3462173915
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1303091814
Short name T133
Test name
Test status
Simulation time 325965461 ps
CPU time 2.08 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 215428 kb
Host smart-5b6d5343-de24-4540-8ac7-19a1fb537645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303091814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1303091814
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4006081318
Short name T1148
Test name
Test status
Simulation time 16534017 ps
CPU time 0.73 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 204164 kb
Host smart-5e13f908-563f-4fa8-b2f5-c511ba44f025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006081318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4006081318
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2048472165
Short name T152
Test name
Test status
Simulation time 115311320 ps
CPU time 2.55 seconds
Started Aug 03 04:27:23 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 215312 kb
Host smart-55b596b9-1054-4675-af64-d67a8a086b38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048472165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2048472165
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2424410108
Short name T119
Test name
Test status
Simulation time 157967636 ps
CPU time 3.56 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215756 kb
Host smart-64cf00b3-0399-4a1a-82ab-f711d6e3cc4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424410108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2424410108
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1019839030
Short name T161
Test name
Test status
Simulation time 5175796058 ps
CPU time 6.82 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:27 PM PDT 24
Peak memory 215432 kb
Host smart-07b024ca-7883-4fb3-ab38-85817210cfde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019839030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1019839030
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3183334626
Short name T1136
Test name
Test status
Simulation time 181937490 ps
CPU time 2.86 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 207180 kb
Host smart-ab34ea0a-31b6-48dd-8b39-77f728eda699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183334626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3183334626
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.377375045
Short name T1106
Test name
Test status
Simulation time 37094580 ps
CPU time 0.75 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 203824 kb
Host smart-a117bc23-ad34-4fb3-9f3d-16ef26d355cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377375045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.377375045
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.133501875
Short name T153
Test name
Test status
Simulation time 378850580 ps
CPU time 2.95 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 215052 kb
Host smart-ae93622f-d3e5-41b5-86b3-3e9505e008a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133501875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.133501875
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2685366103
Short name T114
Test name
Test status
Simulation time 135945691 ps
CPU time 2.34 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 215624 kb
Host smart-31ab7b9e-7396-43f3-8d5d-00660bd4ea54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685366103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2685366103
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2434639027
Short name T1108
Test name
Test status
Simulation time 13457652145 ps
CPU time 21.57 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:42 PM PDT 24
Peak memory 215532 kb
Host smart-16aa6b8a-f67f-4462-a42c-c4337c30a5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434639027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2434639027
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.577952816
Short name T1081
Test name
Test status
Simulation time 974974760 ps
CPU time 8.28 seconds
Started Aug 03 04:26:53 PM PDT 24
Finished Aug 03 04:27:02 PM PDT 24
Peak memory 215296 kb
Host smart-c99aa5f4-3bd9-4c74-a43a-7d2620ad308f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577952816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.577952816
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2206723953
Short name T1063
Test name
Test status
Simulation time 1259687989 ps
CPU time 22.81 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 207132 kb
Host smart-79d5a593-ae9a-488e-9b97-79a9659427ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206723953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2206723953
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2405732242
Short name T1037
Test name
Test status
Simulation time 17409948 ps
CPU time 0.94 seconds
Started Aug 03 04:26:53 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 206768 kb
Host smart-251d2644-e285-475a-8e3e-b3a56755d1b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405732242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2405732242
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2358669626
Short name T120
Test name
Test status
Simulation time 238474242 ps
CPU time 3.48 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:26:55 PM PDT 24
Peak memory 218176 kb
Host smart-ffadfcf7-dd82-4b0a-816a-ebf164e1f92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358669626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2358669626
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.940224205
Short name T1143
Test name
Test status
Simulation time 82362346 ps
CPU time 1.25 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 207140 kb
Host smart-e4f05fa5-c1dd-4c0e-992f-fbb36ae65381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940224205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.940224205
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3826847038
Short name T1057
Test name
Test status
Simulation time 43173818 ps
CPU time 0.75 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:26:53 PM PDT 24
Peak memory 203876 kb
Host smart-60db1ede-60a2-497e-a1e4-8e66961b8037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826847038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
826847038
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1153747888
Short name T129
Test name
Test status
Simulation time 275685506 ps
CPU time 2.13 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 215392 kb
Host smart-389b4657-b28b-442e-b578-4722ba2932df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153747888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1153747888
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1100010489
Short name T1100
Test name
Test status
Simulation time 10856621 ps
CPU time 0.67 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:02 PM PDT 24
Peak memory 203752 kb
Host smart-5230a254-5229-4324-8fa3-e40b13d0f467
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100010489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1100010489
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2809392135
Short name T1135
Test name
Test status
Simulation time 151103540 ps
CPU time 3.9 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:05 PM PDT 24
Peak memory 215392 kb
Host smart-59980b9e-92a7-4a72-a960-0cb8280800af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809392135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2809392135
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2957763529
Short name T1122
Test name
Test status
Simulation time 705419242 ps
CPU time 1.76 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 215628 kb
Host smart-46565b32-c8f6-4ff6-b43e-4077fba4dd7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957763529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
957763529
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3488433474
Short name T1133
Test name
Test status
Simulation time 800301013 ps
CPU time 5.78 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 215968 kb
Host smart-81b5199f-43ac-4d43-b97f-a3f1158becff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488433474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3488433474
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.228295798
Short name T1056
Test name
Test status
Simulation time 208845872 ps
CPU time 0.73 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 203816 kb
Host smart-03c38c3c-6f41-4107-a051-fa9eb2d74c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228295798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.228295798
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2606421885
Short name T1120
Test name
Test status
Simulation time 43450918 ps
CPU time 0.72 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 203864 kb
Host smart-e5ffa815-a312-4c3a-a150-69d95b323ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606421885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2606421885
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3886077774
Short name T1132
Test name
Test status
Simulation time 47614064 ps
CPU time 0.72 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 203644 kb
Host smart-82dc39b2-86e5-4d5b-a548-6b8b7aaa2335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886077774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3886077774
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1042214384
Short name T1096
Test name
Test status
Simulation time 34989329 ps
CPU time 0.72 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 203892 kb
Host smart-b90af290-ae8d-4277-9a14-5a2755b6a340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042214384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1042214384
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2552567968
Short name T1074
Test name
Test status
Simulation time 24167411 ps
CPU time 0.74 seconds
Started Aug 03 04:27:24 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 203864 kb
Host smart-b6fe629e-9277-4556-88e6-0fd9e518ab64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552567968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2552567968
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1723777958
Short name T1112
Test name
Test status
Simulation time 38272581 ps
CPU time 0.67 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:19 PM PDT 24
Peak memory 203832 kb
Host smart-5b542e0e-2b2e-4468-9030-565dec2018a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723777958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1723777958
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.113531847
Short name T1048
Test name
Test status
Simulation time 15941651 ps
CPU time 0.73 seconds
Started Aug 03 04:27:18 PM PDT 24
Finished Aug 03 04:27:19 PM PDT 24
Peak memory 203828 kb
Host smart-61d7b3e1-1359-4c02-a9f9-99aad422d25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113531847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.113531847
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3352615274
Short name T1109
Test name
Test status
Simulation time 12954009 ps
CPU time 0.74 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 203856 kb
Host smart-f02d6c94-b209-4348-8343-3945752efafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352615274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3352615274
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4101416410
Short name T1124
Test name
Test status
Simulation time 40126279 ps
CPU time 0.73 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 203884 kb
Host smart-cbbba9b9-b2a9-45b2-8927-0d0a0fc76c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101416410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4101416410
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2566236015
Short name T1060
Test name
Test status
Simulation time 43699023 ps
CPU time 0.72 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 204204 kb
Host smart-6720b79d-d2b3-456a-9955-5d16c77d2e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566236015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2566236015
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1335292339
Short name T1134
Test name
Test status
Simulation time 424912524 ps
CPU time 9.09 seconds
Started Aug 03 04:26:59 PM PDT 24
Finished Aug 03 04:27:08 PM PDT 24
Peak memory 215364 kb
Host smart-224b1dd8-24f9-497c-a636-959c0883061b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335292339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1335292339
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3598194015
Short name T1083
Test name
Test status
Simulation time 1630116354 ps
CPU time 22.91 seconds
Started Aug 03 04:26:52 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 215320 kb
Host smart-1e1f8667-59ea-43ff-973c-0ef3ccf27ddf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598194015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3598194015
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.937933803
Short name T163
Test name
Test status
Simulation time 26196507 ps
CPU time 0.99 seconds
Started Aug 03 04:27:00 PM PDT 24
Finished Aug 03 04:27:01 PM PDT 24
Peak memory 206936 kb
Host smart-5b5b52d4-db76-480e-8da8-16739c10554d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937933803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.937933803
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2263700190
Short name T1053
Test name
Test status
Simulation time 54079911 ps
CPU time 1.84 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:03 PM PDT 24
Peak memory 215628 kb
Host smart-cd54c700-0f0f-4672-9d0c-101ec155d8ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263700190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2263700190
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1281286527
Short name T1104
Test name
Test status
Simulation time 85525725 ps
CPU time 2.21 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:04 PM PDT 24
Peak memory 207200 kb
Host smart-06520fc3-6443-4ac9-92c4-343713ff0c1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281286527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
281286527
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1434982496
Short name T1091
Test name
Test status
Simulation time 27368969 ps
CPU time 0.69 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:02 PM PDT 24
Peak memory 204184 kb
Host smart-c012620c-4622-4b20-b6ff-8455a9460016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434982496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
434982496
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3806615669
Short name T138
Test name
Test status
Simulation time 26294044 ps
CPU time 2.04 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:53 PM PDT 24
Peak memory 215544 kb
Host smart-5fc53d0d-8479-4f12-9e5d-2ee30d74fb5f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806615669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3806615669
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1375165987
Short name T1077
Test name
Test status
Simulation time 30719189 ps
CPU time 0.63 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 203740 kb
Host smart-17e3d42e-bda5-419a-a6f7-d045bfea3e1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375165987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1375165987
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1310705133
Short name T1078
Test name
Test status
Simulation time 878169283 ps
CPU time 4.19 seconds
Started Aug 03 04:26:59 PM PDT 24
Finished Aug 03 04:27:03 PM PDT 24
Peak memory 207152 kb
Host smart-01f8bb34-be97-46af-a9ab-0556f15a384c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310705133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1310705133
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1271499279
Short name T1127
Test name
Test status
Simulation time 479158467 ps
CPU time 3.99 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:55 PM PDT 24
Peak memory 215628 kb
Host smart-31457394-a1a1-46b5-a827-3c0702db1e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271499279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
271499279
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2484919303
Short name T160
Test name
Test status
Simulation time 699185857 ps
CPU time 15.4 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:27:06 PM PDT 24
Peak memory 215524 kb
Host smart-62ad880b-41eb-4ce7-84b0-fca78505b5dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484919303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2484919303
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1488199917
Short name T1061
Test name
Test status
Simulation time 15088922 ps
CPU time 0.72 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 203852 kb
Host smart-cac3217b-426d-48d5-8a44-931b9aaf30c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488199917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1488199917
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.148843011
Short name T1064
Test name
Test status
Simulation time 19173939 ps
CPU time 0.76 seconds
Started Aug 03 04:27:20 PM PDT 24
Finished Aug 03 04:27:21 PM PDT 24
Peak memory 204112 kb
Host smart-59970971-f791-4dd8-8b6a-1ac5eb591c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148843011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.148843011
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.556097683
Short name T1099
Test name
Test status
Simulation time 15395427 ps
CPU time 0.73 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 203864 kb
Host smart-e0320992-6365-40b2-8e41-da728e6d67fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556097683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.556097683
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.969027230
Short name T1071
Test name
Test status
Simulation time 15719414 ps
CPU time 0.72 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 203840 kb
Host smart-8392d2f3-d306-48ab-937f-b928342191c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969027230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.969027230
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1409294963
Short name T1101
Test name
Test status
Simulation time 12820371 ps
CPU time 0.72 seconds
Started Aug 03 04:27:21 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 203844 kb
Host smart-4a827dc3-4831-4965-a13d-d0c655aacbb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409294963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1409294963
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1139344118
Short name T1062
Test name
Test status
Simulation time 12190237 ps
CPU time 0.68 seconds
Started Aug 03 04:27:19 PM PDT 24
Finished Aug 03 04:27:20 PM PDT 24
Peak memory 204224 kb
Host smart-8ab3db9d-75cb-4c07-931f-86ad48ac7162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139344118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1139344118
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1117626986
Short name T1067
Test name
Test status
Simulation time 17092412 ps
CPU time 0.75 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 203888 kb
Host smart-7db66057-9f41-4096-bd37-6c47166e913a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117626986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1117626986
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1089642817
Short name T1079
Test name
Test status
Simulation time 14520024 ps
CPU time 0.85 seconds
Started Aug 03 04:27:22 PM PDT 24
Finished Aug 03 04:27:23 PM PDT 24
Peak memory 203968 kb
Host smart-98806c30-7ab5-4c68-8a48-76e97a259956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089642817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1089642817
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3377284384
Short name T1076
Test name
Test status
Simulation time 49147831 ps
CPU time 0.71 seconds
Started Aug 03 04:27:28 PM PDT 24
Finished Aug 03 04:27:29 PM PDT 24
Peak memory 204152 kb
Host smart-f1030667-f7f3-445b-b35a-9dd76d61a7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377284384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3377284384
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1954408185
Short name T1046
Test name
Test status
Simulation time 13298634 ps
CPU time 0.74 seconds
Started Aug 03 04:27:26 PM PDT 24
Finished Aug 03 04:27:27 PM PDT 24
Peak memory 204200 kb
Host smart-4bf3192f-d837-4573-a858-6efd3018a150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954408185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1954408185
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1504868066
Short name T1041
Test name
Test status
Simulation time 312102797 ps
CPU time 8.16 seconds
Started Aug 03 04:27:01 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 215452 kb
Host smart-80fa7c6e-4dd3-4bf6-aa81-1d1ddc89f1f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504868066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1504868066
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3371373946
Short name T159
Test name
Test status
Simulation time 1737393711 ps
CPU time 13.01 seconds
Started Aug 03 04:26:58 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 215324 kb
Host smart-e4a6777b-3152-4f8c-8ba8-c6caa10b2758
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371373946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3371373946
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1580112568
Short name T1082
Test name
Test status
Simulation time 29046902 ps
CPU time 2 seconds
Started Aug 03 04:27:00 PM PDT 24
Finished Aug 03 04:27:02 PM PDT 24
Peak memory 216376 kb
Host smart-dddc3add-2cbe-4821-978e-d1699fab693f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580112568 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1580112568
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.789271160
Short name T149
Test name
Test status
Simulation time 52485563 ps
CPU time 1.89 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:26:58 PM PDT 24
Peak memory 215456 kb
Host smart-df5fae68-ffa1-45f3-90c6-df2c840eb1e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789271160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.789271160
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.213833270
Short name T1115
Test name
Test status
Simulation time 14828931 ps
CPU time 0.72 seconds
Started Aug 03 04:26:58 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 203852 kb
Host smart-816fcf88-d7a1-4fa9-a5de-39e42bbd8630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213833270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.213833270
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3880840732
Short name T137
Test name
Test status
Simulation time 73704107 ps
CPU time 1.54 seconds
Started Aug 03 04:26:57 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 215384 kb
Host smart-0939645e-5ddb-43d2-bf55-801dc62ada97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880840732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3880840732
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4160854451
Short name T1110
Test name
Test status
Simulation time 22039413 ps
CPU time 0.73 seconds
Started Aug 03 04:26:58 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 204116 kb
Host smart-f99f3ccd-aa1d-4c0d-b101-9e8e654d3645
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160854451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4160854451
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.646008065
Short name T1059
Test name
Test status
Simulation time 308341346 ps
CPU time 4.15 seconds
Started Aug 03 04:27:06 PM PDT 24
Finished Aug 03 04:27:10 PM PDT 24
Peak memory 215836 kb
Host smart-e444339b-9cf0-483b-997b-927a106afd18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646008065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.646008065
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3599348416
Short name T1092
Test name
Test status
Simulation time 121707408 ps
CPU time 2.08 seconds
Started Aug 03 04:26:57 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 215584 kb
Host smart-a2236e63-c076-4a7e-b29b-6d266a98c656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599348416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
599348416
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4140780122
Short name T190
Test name
Test status
Simulation time 2609248157 ps
CPU time 13.19 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 215916 kb
Host smart-ee531bb0-c1a2-4e57-a2cb-44b82f02f5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140780122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4140780122
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.860132704
Short name T1070
Test name
Test status
Simulation time 26077779 ps
CPU time 0.69 seconds
Started Aug 03 04:27:23 PM PDT 24
Finished Aug 03 04:27:24 PM PDT 24
Peak memory 203872 kb
Host smart-0ae52ee1-ed34-4d28-b73e-1444a44ac419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860132704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.860132704
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3688983137
Short name T1038
Test name
Test status
Simulation time 42593575 ps
CPU time 0.73 seconds
Started Aug 03 04:27:37 PM PDT 24
Finished Aug 03 04:27:37 PM PDT 24
Peak memory 203852 kb
Host smart-ebce2287-3264-461b-a868-6d1aeb8b0a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688983137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3688983137
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4063617404
Short name T1044
Test name
Test status
Simulation time 30443241 ps
CPU time 0.73 seconds
Started Aug 03 04:27:39 PM PDT 24
Finished Aug 03 04:27:40 PM PDT 24
Peak memory 203908 kb
Host smart-ce3c8f4d-9141-4478-88a9-ca8085343729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063617404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4063617404
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2692488404
Short name T1035
Test name
Test status
Simulation time 29669426 ps
CPU time 0.69 seconds
Started Aug 03 04:27:30 PM PDT 24
Finished Aug 03 04:27:31 PM PDT 24
Peak memory 203812 kb
Host smart-3c0cbc91-6113-47a6-ac17-9ab6b5ad36c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692488404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2692488404
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3230780454
Short name T1103
Test name
Test status
Simulation time 25352035 ps
CPU time 0.7 seconds
Started Aug 03 04:27:25 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 203972 kb
Host smart-fcdf3c71-1467-4a49-ad43-562570f7d465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230780454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3230780454
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2362455914
Short name T1141
Test name
Test status
Simulation time 35438363 ps
CPU time 0.74 seconds
Started Aug 03 04:27:28 PM PDT 24
Finished Aug 03 04:27:29 PM PDT 24
Peak memory 203896 kb
Host smart-11bd52ee-f150-4216-9ec3-0eff49705676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362455914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2362455914
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2238981616
Short name T1130
Test name
Test status
Simulation time 12539979 ps
CPU time 0.75 seconds
Started Aug 03 04:27:32 PM PDT 24
Finished Aug 03 04:27:33 PM PDT 24
Peak memory 204228 kb
Host smart-61fb91a8-11fe-4a27-81c3-77b00f640ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238981616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2238981616
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3049180771
Short name T1086
Test name
Test status
Simulation time 14355798 ps
CPU time 0.73 seconds
Started Aug 03 04:27:39 PM PDT 24
Finished Aug 03 04:27:40 PM PDT 24
Peak memory 204220 kb
Host smart-c0c781a8-5d21-45cd-9592-f14dcefea21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049180771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3049180771
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1173903456
Short name T1040
Test name
Test status
Simulation time 11471958 ps
CPU time 0.75 seconds
Started Aug 03 04:27:28 PM PDT 24
Finished Aug 03 04:27:29 PM PDT 24
Peak memory 203884 kb
Host smart-1a6e1956-9bdc-4cac-ae1f-1e1bdb7e9c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173903456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1173903456
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2536625218
Short name T1036
Test name
Test status
Simulation time 13920208 ps
CPU time 0.69 seconds
Started Aug 03 04:27:28 PM PDT 24
Finished Aug 03 04:27:29 PM PDT 24
Peak memory 204152 kb
Host smart-45394113-8d04-487e-9d14-a20be05b104e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536625218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2536625218
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1380879890
Short name T1085
Test name
Test status
Simulation time 37974417 ps
CPU time 2.53 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:08 PM PDT 24
Peak memory 215724 kb
Host smart-384e7be7-cbdd-4610-a16b-843f0b2a5f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380879890 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1380879890
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.77294761
Short name T136
Test name
Test status
Simulation time 322265509 ps
CPU time 2.5 seconds
Started Aug 03 04:27:10 PM PDT 24
Finished Aug 03 04:27:12 PM PDT 24
Peak memory 207084 kb
Host smart-64eed5b9-76ac-4b40-80e6-384a995d5a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77294761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.77294761
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1515513693
Short name T1051
Test name
Test status
Simulation time 10846577 ps
CPU time 0.65 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:05 PM PDT 24
Peak memory 203800 kb
Host smart-5664d7fb-c651-4cde-8bc7-5761c8b5d37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515513693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
515513693
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3851842117
Short name T1049
Test name
Test status
Simulation time 515205051 ps
CPU time 3.49 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 215496 kb
Host smart-c5c352ee-8814-4335-a700-c18e673b783b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851842117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3851842117
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3213951993
Short name T111
Test name
Test status
Simulation time 154994562 ps
CPU time 2.77 seconds
Started Aug 03 04:27:04 PM PDT 24
Finished Aug 03 04:27:07 PM PDT 24
Peak memory 215632 kb
Host smart-fc02d374-8d90-4711-bbf8-4db3ee07fc43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213951993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
213951993
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3720498709
Short name T186
Test name
Test status
Simulation time 785946998 ps
CPU time 12.22 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:17 PM PDT 24
Peak memory 222520 kb
Host smart-5a533d90-6b46-4ec0-bea9-77e40aba1352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720498709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3720498709
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1437826771
Short name T121
Test name
Test status
Simulation time 43480454 ps
CPU time 2.72 seconds
Started Aug 03 04:27:07 PM PDT 24
Finished Aug 03 04:27:10 PM PDT 24
Peak memory 217404 kb
Host smart-0e9f71ff-d257-46cc-a7fa-38e9e6841193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437826771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1437826771
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3308564716
Short name T151
Test name
Test status
Simulation time 184085690 ps
CPU time 1.43 seconds
Started Aug 03 04:27:08 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 215452 kb
Host smart-763a8673-0275-4add-9eea-8f94e140c6cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308564716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
308564716
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2085103740
Short name T1066
Test name
Test status
Simulation time 11144377 ps
CPU time 0.7 seconds
Started Aug 03 04:27:08 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 203896 kb
Host smart-f511babf-c47b-4291-bd85-7f7e2c3b7027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085103740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
085103740
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3034466279
Short name T164
Test name
Test status
Simulation time 406356224 ps
CPU time 1.95 seconds
Started Aug 03 04:27:09 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 215408 kb
Host smart-a8ef9076-56ea-4724-bd84-459aedef61e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034466279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3034466279
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.892215006
Short name T1089
Test name
Test status
Simulation time 1252793933 ps
CPU time 8.03 seconds
Started Aug 03 04:27:08 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215396 kb
Host smart-dde5ba31-780d-4500-9e39-5b4e049f25ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892215006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.892215006
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3361653588
Short name T1097
Test name
Test status
Simulation time 38264413 ps
CPU time 2.36 seconds
Started Aug 03 04:27:08 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 215528 kb
Host smart-a3cc5584-6364-4a9f-a9e0-c05d5b286773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361653588 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3361653588
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1478759061
Short name T132
Test name
Test status
Simulation time 403837873 ps
CPU time 2.5 seconds
Started Aug 03 04:27:08 PM PDT 24
Finished Aug 03 04:27:10 PM PDT 24
Peak memory 215492 kb
Host smart-8ea7e5b8-f4e2-4d03-a30f-50b973472701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478759061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
478759061
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3574708199
Short name T1128
Test name
Test status
Simulation time 23838547 ps
CPU time 0.71 seconds
Started Aug 03 04:27:06 PM PDT 24
Finished Aug 03 04:27:07 PM PDT 24
Peak memory 203884 kb
Host smart-68e49464-af27-44ae-a492-81e0ecc4d347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574708199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
574708199
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2832078335
Short name T1050
Test name
Test status
Simulation time 229057313 ps
CPU time 3.53 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:09 PM PDT 24
Peak memory 207224 kb
Host smart-cce40639-b545-49b0-8dd8-34cc7ae8dd6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832078335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2832078335
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.553538600
Short name T112
Test name
Test status
Simulation time 108980404 ps
CPU time 2.63 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 215672 kb
Host smart-73a81ccc-f82e-45a8-ac3d-9a05c7060179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553538600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.553538600
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1505571825
Short name T1068
Test name
Test status
Simulation time 5029251439 ps
CPU time 20.02 seconds
Started Aug 03 04:27:05 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 220732 kb
Host smart-d529d5c5-eb65-4ffe-bfe0-7db452dffe72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505571825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1505571825
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2109261587
Short name T1095
Test name
Test status
Simulation time 42635350 ps
CPU time 2.68 seconds
Started Aug 03 04:27:14 PM PDT 24
Finished Aug 03 04:27:17 PM PDT 24
Peak memory 216868 kb
Host smart-ac4f6978-38b0-417d-ab08-9855af7fcc10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109261587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2109261587
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.798522636
Short name T134
Test name
Test status
Simulation time 26896399 ps
CPU time 1.79 seconds
Started Aug 03 04:27:15 PM PDT 24
Finished Aug 03 04:27:17 PM PDT 24
Peak memory 215376 kb
Host smart-97097f89-d88c-49c3-8b1f-e730f78ec73d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798522636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.798522636
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2686311542
Short name T1065
Test name
Test status
Simulation time 32496098 ps
CPU time 0.74 seconds
Started Aug 03 04:27:15 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 203828 kb
Host smart-4bdd3670-c7de-4db1-865a-7f9f8309f81e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686311542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
686311542
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1206318540
Short name T1118
Test name
Test status
Simulation time 25882487 ps
CPU time 1.75 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 207372 kb
Host smart-29f47ecc-8674-4a4b-8256-f0d98eaff42d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206318540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1206318540
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.22610871
Short name T122
Test name
Test status
Simulation time 79091117 ps
CPU time 2.24 seconds
Started Aug 03 04:27:14 PM PDT 24
Finished Aug 03 04:27:17 PM PDT 24
Peak memory 216388 kb
Host smart-03fbe79a-871f-46a3-b18d-b3201dcbc3c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22610871 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.22610871
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1778542534
Short name T1052
Test name
Test status
Simulation time 20584016 ps
CPU time 1.3 seconds
Started Aug 03 04:27:12 PM PDT 24
Finished Aug 03 04:27:13 PM PDT 24
Peak memory 215352 kb
Host smart-340b0dd1-93c9-44aa-9e99-ef1a349af5ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778542534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
778542534
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3883127100
Short name T1142
Test name
Test status
Simulation time 19084729 ps
CPU time 0.73 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:14 PM PDT 24
Peak memory 204228 kb
Host smart-1dac0ab4-fbd4-4238-8cb8-7e4aa537251b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883127100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
883127100
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3618642702
Short name T1137
Test name
Test status
Simulation time 871548292 ps
CPU time 3.17 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 215412 kb
Host smart-1f47e1f0-0cd1-4165-9974-9afe1147533a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618642702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3618642702
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1338399605
Short name T103
Test name
Test status
Simulation time 425015611 ps
CPU time 1.6 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:14 PM PDT 24
Peak memory 215640 kb
Host smart-874ac77a-8640-4337-94ce-9846437c87f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338399605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
338399605
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.377836534
Short name T189
Test name
Test status
Simulation time 211673114 ps
CPU time 6.19 seconds
Started Aug 03 04:27:13 PM PDT 24
Finished Aug 03 04:27:19 PM PDT 24
Peak memory 215428 kb
Host smart-2c090394-aef7-43eb-bd9e-6c546bfbcdb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377836534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.377836534
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3160790268
Short name T887
Test name
Test status
Simulation time 85003368 ps
CPU time 2.21 seconds
Started Aug 03 05:25:51 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 225236 kb
Host smart-9d428d7c-b62f-4bfe-b112-b76c04814f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160790268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3160790268
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1595181188
Short name T728
Test name
Test status
Simulation time 18331710 ps
CPU time 0.82 seconds
Started Aug 03 05:25:37 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 206060 kb
Host smart-dbcbe338-62ba-4e9b-8737-015f13959790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595181188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1595181188
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4289297674
Short name T36
Test name
Test status
Simulation time 1176533425 ps
CPU time 6.25 seconds
Started Aug 03 05:25:45 PM PDT 24
Finished Aug 03 05:25:51 PM PDT 24
Peak memory 225216 kb
Host smart-0e25add8-0457-4eb4-9806-7328e7bc8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289297674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4289297674
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3597885543
Short name T297
Test name
Test status
Simulation time 7211332939 ps
CPU time 118.03 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 257244 kb
Host smart-1712377f-51a7-4928-93b3-6e37a802f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597885543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3597885543
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1513723463
Short name T394
Test name
Test status
Simulation time 449323372 ps
CPU time 4.54 seconds
Started Aug 03 05:25:38 PM PDT 24
Finished Aug 03 05:25:43 PM PDT 24
Peak memory 241644 kb
Host smart-af08ac1f-a658-403a-9689-8627d8079226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513723463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1513723463
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3750464629
Short name T48
Test name
Test status
Simulation time 14773116837 ps
CPU time 55 seconds
Started Aug 03 05:25:41 PM PDT 24
Finished Aug 03 05:26:36 PM PDT 24
Peak memory 255528 kb
Host smart-eee0e03c-0985-4edb-b981-c31a9a4d6b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750464629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3750464629
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2801569314
Short name T902
Test name
Test status
Simulation time 326877038 ps
CPU time 6.56 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:46 PM PDT 24
Peak memory 233540 kb
Host smart-c1bae54e-7c54-4e36-9071-a127e3f85bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801569314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2801569314
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3517706810
Short name T895
Test name
Test status
Simulation time 2981859071 ps
CPU time 23.76 seconds
Started Aug 03 05:25:32 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 225372 kb
Host smart-1dc1f374-4171-4e68-a435-8432cdf0e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517706810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3517706810
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4193904878
Short name T682
Test name
Test status
Simulation time 51466993 ps
CPU time 1.1 seconds
Started Aug 03 05:25:35 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 217232 kb
Host smart-74acdc4c-edce-4cf7-bc23-4cef28216459
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193904878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4193904878
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1257660828
Short name T174
Test name
Test status
Simulation time 193105601 ps
CPU time 2.78 seconds
Started Aug 03 05:25:37 PM PDT 24
Finished Aug 03 05:25:40 PM PDT 24
Peak memory 225220 kb
Host smart-82bc9ca7-7d13-4b30-9cf9-7770d659dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257660828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1257660828
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1473868953
Short name T576
Test name
Test status
Simulation time 112649949 ps
CPU time 2.33 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:25:36 PM PDT 24
Peak memory 233116 kb
Host smart-74c49917-bc23-4006-af7d-1e1ef0e4e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473868953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1473868953
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3436070133
Short name T157
Test name
Test status
Simulation time 259606484 ps
CPU time 3.74 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:25:48 PM PDT 24
Peak memory 219456 kb
Host smart-75ac4274-0b08-4bdb-ba75-12fa974cbf72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3436070133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3436070133
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.413997386
Short name T35
Test name
Test status
Simulation time 29475552349 ps
CPU time 206.49 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:29:22 PM PDT 24
Peak memory 253888 kb
Host smart-d97a8613-1ad0-4806-8558-259e21d6c617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413997386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.413997386
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2942998794
Short name T982
Test name
Test status
Simulation time 8930918782 ps
CPU time 29.07 seconds
Started Aug 03 05:25:33 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 217008 kb
Host smart-4e88015d-2521-4a9f-93a5-d8e50a63e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942998794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2942998794
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3476133640
Short name T403
Test name
Test status
Simulation time 1996114186 ps
CPU time 8.12 seconds
Started Aug 03 05:25:45 PM PDT 24
Finished Aug 03 05:25:59 PM PDT 24
Peak memory 216992 kb
Host smart-ff53ca21-4dfa-46bf-ab1c-060b789fc34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476133640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3476133640
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1587063397
Short name T1028
Test name
Test status
Simulation time 232262472 ps
CPU time 0.85 seconds
Started Aug 03 05:25:40 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 206628 kb
Host smart-ef63a092-4291-4001-88bf-dc8bc4196735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587063397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1587063397
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1529605900
Short name T380
Test name
Test status
Simulation time 30984970 ps
CPU time 0.81 seconds
Started Aug 03 05:25:37 PM PDT 24
Finished Aug 03 05:25:38 PM PDT 24
Peak memory 206560 kb
Host smart-a781d867-d803-4307-aa27-9ea3248281fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529605900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1529605900
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3466074280
Short name T904
Test name
Test status
Simulation time 8339866785 ps
CPU time 8.41 seconds
Started Aug 03 05:25:43 PM PDT 24
Finished Aug 03 05:25:51 PM PDT 24
Peak memory 225304 kb
Host smart-3f294014-b693-49d8-8574-e451e0bb8dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466074280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3466074280
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2889531534
Short name T705
Test name
Test status
Simulation time 14059637 ps
CPU time 0.69 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 205284 kb
Host smart-cc7ea9ba-8ce5-4334-8e98-451d63be80fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889531534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
889531534
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1930377118
Short name T817
Test name
Test status
Simulation time 357805068 ps
CPU time 6.87 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 225268 kb
Host smart-a2fabb5e-0733-4079-9701-dcf9adbfb793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930377118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1930377118
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1229804743
Short name T561
Test name
Test status
Simulation time 15325403 ps
CPU time 0.77 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:25:51 PM PDT 24
Peak memory 207404 kb
Host smart-5aab838b-4ad1-4503-8228-36a232f3c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229804743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1229804743
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1407219758
Short name T534
Test name
Test status
Simulation time 22667846 ps
CPU time 0.74 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 216488 kb
Host smart-4ff41e02-8eb6-4e13-80f1-93b42d9312d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407219758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1407219758
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2706538818
Short name T326
Test name
Test status
Simulation time 5526319173 ps
CPU time 20.24 seconds
Started Aug 03 05:25:40 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 233648 kb
Host smart-b87c01df-7506-4e70-9cae-549d44d1f454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706538818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2706538818
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.928735685
Short name T866
Test name
Test status
Simulation time 196325374940 ps
CPU time 343.01 seconds
Started Aug 03 05:25:38 PM PDT 24
Finished Aug 03 05:31:21 PM PDT 24
Peak memory 257308 kb
Host smart-a30df335-492d-44ca-bac3-dda7a2679850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928735685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
928735685
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2603658023
Short name T747
Test name
Test status
Simulation time 4802783937 ps
CPU time 39.62 seconds
Started Aug 03 05:25:41 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 241608 kb
Host smart-79e3fca9-913f-4552-b4c1-e2fc5f331721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603658023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2603658023
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4144275125
Short name T670
Test name
Test status
Simulation time 43444854 ps
CPU time 0.76 seconds
Started Aug 03 05:25:40 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 216456 kb
Host smart-1947846f-339b-4f42-b15d-b20037fd9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144275125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4144275125
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2155321616
Short name T786
Test name
Test status
Simulation time 1319481157 ps
CPU time 6.52 seconds
Started Aug 03 05:25:38 PM PDT 24
Finished Aug 03 05:25:45 PM PDT 24
Peak memory 233540 kb
Host smart-8ae758ba-d633-4f84-a8af-63f5b367604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155321616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2155321616
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.607743342
Short name T598
Test name
Test status
Simulation time 64990669406 ps
CPU time 53.63 seconds
Started Aug 03 05:25:41 PM PDT 24
Finished Aug 03 05:26:34 PM PDT 24
Peak memory 233584 kb
Host smart-fb41fcaf-88be-4f62-964b-229bb952c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607743342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.607743342
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.691622307
Short name T777
Test name
Test status
Simulation time 5063527265 ps
CPU time 16.47 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:26:12 PM PDT 24
Peak memory 249300 kb
Host smart-470cbb27-621d-46e5-9aa0-8c3ced5fa7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691622307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
691622307
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4108863350
Short name T803
Test name
Test status
Simulation time 149968278 ps
CPU time 4.2 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:25:48 PM PDT 24
Peak memory 225272 kb
Host smart-bd5eb5bc-8ec9-431c-9455-629a716ae72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108863350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4108863350
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3261009520
Short name T993
Test name
Test status
Simulation time 996894492 ps
CPU time 4.86 seconds
Started Aug 03 05:25:47 PM PDT 24
Finished Aug 03 05:25:52 PM PDT 24
Peak memory 221160 kb
Host smart-fe4c5709-fbac-426b-87b7-be356ba2673a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261009520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3261009520
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2078869768
Short name T72
Test name
Test status
Simulation time 82740338 ps
CPU time 1.15 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:47 PM PDT 24
Peak memory 235664 kb
Host smart-92995e10-6686-4260-8262-b13a1b04a2e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078869768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2078869768
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1644592434
Short name T816
Test name
Test status
Simulation time 3922233110 ps
CPU time 22.95 seconds
Started Aug 03 05:25:38 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 216988 kb
Host smart-d709ea28-d1fc-470b-bea2-1bb31f36c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644592434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1644592434
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1505982448
Short name T573
Test name
Test status
Simulation time 1663349413 ps
CPU time 4.68 seconds
Started Aug 03 05:25:39 PM PDT 24
Finished Aug 03 05:25:44 PM PDT 24
Peak memory 217048 kb
Host smart-5d2e317b-e1d6-44f1-a58e-0c4f45494dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505982448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1505982448
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1378617948
Short name T738
Test name
Test status
Simulation time 247332812 ps
CPU time 11.09 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 216936 kb
Host smart-07c00191-9b0e-4d61-b253-aa06f83214a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378617948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1378617948
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1984863369
Short name T415
Test name
Test status
Simulation time 39328365 ps
CPU time 0.84 seconds
Started Aug 03 05:25:42 PM PDT 24
Finished Aug 03 05:25:43 PM PDT 24
Peak memory 206532 kb
Host smart-c3216998-d73d-4ed0-9df5-7e66c8182c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984863369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1984863369
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.308262757
Short name T285
Test name
Test status
Simulation time 465449057 ps
CPU time 7.63 seconds
Started Aug 03 05:25:42 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 233456 kb
Host smart-25132e75-8469-49d3-ba7e-dbfa42df2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308262757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.308262757
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2277419247
Short name T543
Test name
Test status
Simulation time 15278522 ps
CPU time 0.74 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 206200 kb
Host smart-99125545-7f02-4fc4-ae9d-8f37cb5e4874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277419247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2277419247
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.865590206
Short name T564
Test name
Test status
Simulation time 524114341 ps
CPU time 4.9 seconds
Started Aug 03 05:26:26 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 233500 kb
Host smart-318d7a77-b5b0-4f7a-915b-8183e6a04e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865590206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.865590206
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1195424853
Short name T669
Test name
Test status
Simulation time 19329139 ps
CPU time 0.78 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:08 PM PDT 24
Peak memory 207008 kb
Host smart-1cc0d8d3-c352-46e3-89bf-06aecb03421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195424853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1195424853
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1810534682
Short name T213
Test name
Test status
Simulation time 41330812621 ps
CPU time 102.47 seconds
Started Aug 03 05:26:09 PM PDT 24
Finished Aug 03 05:27:52 PM PDT 24
Peak memory 241704 kb
Host smart-1f6d1718-d6c2-40c1-af7a-8f613d212b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810534682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1810534682
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1754432784
Short name T886
Test name
Test status
Simulation time 19975456283 ps
CPU time 66.4 seconds
Started Aug 03 05:26:16 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 248620 kb
Host smart-22ddbf5f-3c03-464c-919b-8ee5ee2b180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754432784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1754432784
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.73005608
Short name T636
Test name
Test status
Simulation time 23790705249 ps
CPU time 55.47 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 241800 kb
Host smart-d051e96b-59ae-4423-8dad-957a42c8e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73005608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.73005608
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.190530692
Short name T377
Test name
Test status
Simulation time 341277038 ps
CPU time 9.33 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:17 PM PDT 24
Peak memory 249140 kb
Host smart-8bf392a4-8d51-428c-ba05-ccb95b5c74e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190530692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.190530692
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1673717917
Short name T802
Test name
Test status
Simulation time 3058218538 ps
CPU time 56.12 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 254456 kb
Host smart-a52efbfe-8e49-4b2b-89b0-3899ccff7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673717917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1673717917
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2638303879
Short name T979
Test name
Test status
Simulation time 151681697 ps
CPU time 4.92 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 228904 kb
Host smart-a3be958b-59b7-41a8-95e7-1d4f54a2e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638303879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2638303879
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.34718192
Short name T783
Test name
Test status
Simulation time 1108701874 ps
CPU time 16.59 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 233472 kb
Host smart-ceadc019-f973-45b8-a464-7c08e7ac1a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34718192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.34718192
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2006041726
Short name T41
Test name
Test status
Simulation time 47911622 ps
CPU time 1 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 218452 kb
Host smart-c8f3f829-e1bf-4988-ae4a-19759ed1b50d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006041726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2006041726
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3747091685
Short name T596
Test name
Test status
Simulation time 56851921 ps
CPU time 2.09 seconds
Started Aug 03 05:26:26 PM PDT 24
Finished Aug 03 05:26:28 PM PDT 24
Peak memory 224460 kb
Host smart-30196945-290b-40f7-897c-75effa77a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747091685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3747091685
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.527670033
Short name T24
Test name
Test status
Simulation time 29079637907 ps
CPU time 19.73 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:38 PM PDT 24
Peak memory 225316 kb
Host smart-12b183df-ac06-49ab-92ad-11dac91c3091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527670033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.527670033
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1862544442
Short name T616
Test name
Test status
Simulation time 393086831 ps
CPU time 4.51 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 220784 kb
Host smart-453e07ce-ea06-42aa-a28f-dfaac092be6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862544442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1862544442
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3081105177
Short name T179
Test name
Test status
Simulation time 533864798 ps
CPU time 7.04 seconds
Started Aug 03 05:26:10 PM PDT 24
Finished Aug 03 05:26:17 PM PDT 24
Peak memory 217360 kb
Host smart-a92906a2-ec52-4703-ae24-e40d762baee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081105177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3081105177
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3477712476
Short name T1013
Test name
Test status
Simulation time 24096096 ps
CPU time 0.71 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 206212 kb
Host smart-fa4c9fe6-074c-4e4e-9ffc-2e54adb348eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477712476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3477712476
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.771160433
Short name T897
Test name
Test status
Simulation time 34428555 ps
CPU time 1.15 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:10 PM PDT 24
Peak memory 208804 kb
Host smart-ac7730d3-53a9-40c9-bf36-54852dcef1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771160433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.771160433
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2008812660
Short name T1026
Test name
Test status
Simulation time 260101633 ps
CPU time 1.13 seconds
Started Aug 03 05:26:13 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 207528 kb
Host smart-16b12ea9-a1c9-4952-a90f-1057194dce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008812660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2008812660
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.615705749
Short name T718
Test name
Test status
Simulation time 33038006 ps
CPU time 2.45 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 233380 kb
Host smart-216c507b-57d3-469c-8be6-6683d01c2d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615705749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.615705749
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.84105799
Short name T365
Test name
Test status
Simulation time 58168259 ps
CPU time 0.7 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 205308 kb
Host smart-27225fd3-9fd6-4c73-b14d-3cf8fc1b9136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84105799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.84105799
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1032204438
Short name T261
Test name
Test status
Simulation time 57250328 ps
CPU time 3.1 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 233480 kb
Host smart-af7254f5-cec2-4b4b-bc9b-0b815416165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032204438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1032204438
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2984654373
Short name T389
Test name
Test status
Simulation time 80560429 ps
CPU time 0.84 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:19 PM PDT 24
Peak memory 207328 kb
Host smart-a8becd1f-a34a-44cf-92a5-3fd490adf954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984654373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2984654373
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3612927215
Short name T229
Test name
Test status
Simulation time 25217987128 ps
CPU time 208.47 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:29:40 PM PDT 24
Peak memory 255492 kb
Host smart-cea0e8d4-befd-4638-aae2-14436d4cb88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612927215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3612927215
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3362222380
Short name T673
Test name
Test status
Simulation time 1767617365 ps
CPU time 23.23 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:26:38 PM PDT 24
Peak memory 238528 kb
Host smart-205b3d88-1597-4df3-8840-fe3db92b8b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362222380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3362222380
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.147142497
Short name T498
Test name
Test status
Simulation time 6708745689 ps
CPU time 51.9 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 241720 kb
Host smart-4333b07e-346d-4a4e-a7bf-1f1037b3192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147142497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.147142497
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1900633517
Short name T484
Test name
Test status
Simulation time 34866594177 ps
CPU time 65.4 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 254964 kb
Host smart-0b12546a-35ac-4f3e-862a-a46120936198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900633517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1900633517
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3408622467
Short name T820
Test name
Test status
Simulation time 589322684 ps
CPU time 8.14 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 225224 kb
Host smart-1c69dad4-f037-4406-b80e-07840776f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408622467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3408622467
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1163019759
Short name T898
Test name
Test status
Simulation time 115068703 ps
CPU time 3.81 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 233484 kb
Host smart-3663e069-2614-43c8-8e9b-94743cc17cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163019759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1163019759
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2139856797
Short name T23
Test name
Test status
Simulation time 14949045 ps
CPU time 0.99 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:13 PM PDT 24
Peak memory 217224 kb
Host smart-ce9122e2-cf81-4b5b-b1e1-2a1ccb6f88b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139856797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2139856797
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2871587042
Short name T662
Test name
Test status
Simulation time 1128258365 ps
CPU time 11.79 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:35 PM PDT 24
Peak memory 228964 kb
Host smart-43c31d8b-b1b8-4eac-8380-1a22efc1078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871587042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2871587042
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1628110253
Short name T640
Test name
Test status
Simulation time 1480967446 ps
CPU time 12.24 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 223088 kb
Host smart-7d8838d0-3463-4254-9d72-9c5711b90661
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1628110253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1628110253
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2112006364
Short name T435
Test name
Test status
Simulation time 126645045 ps
CPU time 0.92 seconds
Started Aug 03 05:26:13 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 207284 kb
Host smart-a1978c18-2886-4e59-b7e7-3aa51c78dbdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112006364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2112006364
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2311987409
Short name T698
Test name
Test status
Simulation time 53640615642 ps
CPU time 24.95 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 217084 kb
Host smart-59aa0a1b-aea2-4495-8d2e-b242b1eaa551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311987409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2311987409
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.102617634
Short name T451
Test name
Test status
Simulation time 6390386613 ps
CPU time 18.39 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 217024 kb
Host smart-eaaa890e-adc6-45c6-91f6-071dc53b47bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102617634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.102617634
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.658423747
Short name T470
Test name
Test status
Simulation time 497783267 ps
CPU time 1.64 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:13 PM PDT 24
Peak memory 217004 kb
Host smart-86583bbb-1df8-47d8-9397-ede72fea8978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658423747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.658423747
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1070230623
Short name T5
Test name
Test status
Simulation time 71798803 ps
CPU time 0.97 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 206540 kb
Host smart-29831979-2177-4879-8ce0-88e5d5010063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070230623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1070230623
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3323101633
Short name T286
Test name
Test status
Simulation time 295052627 ps
CPU time 3.56 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:15 PM PDT 24
Peak memory 225180 kb
Host smart-d734e104-2d7f-40bb-8a02-8c29dfc3a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323101633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3323101633
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3661646038
Short name T703
Test name
Test status
Simulation time 42066420 ps
CPU time 0.71 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:15 PM PDT 24
Peak memory 205320 kb
Host smart-06090894-c905-4560-a762-4d2ce4f3586b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661646038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3661646038
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2228186212
Short name T845
Test name
Test status
Simulation time 471519164 ps
CPU time 3.9 seconds
Started Aug 03 05:26:13 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 233460 kb
Host smart-dc0087a2-f5cd-4b79-af64-07c4556d4e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228186212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2228186212
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3256661623
Short name T936
Test name
Test status
Simulation time 13874629 ps
CPU time 0.81 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 207068 kb
Host smart-976b3f8a-1a6e-4b3b-9f51-cf6a9cc409d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256661623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3256661623
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3105708013
Short name T243
Test name
Test status
Simulation time 1042302416 ps
CPU time 21.62 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:26:36 PM PDT 24
Peak memory 241876 kb
Host smart-48e1c261-ee28-4ee7-bed9-d354159aad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105708013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3105708013
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3492742227
Short name T549
Test name
Test status
Simulation time 2634046119 ps
CPU time 29.57 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 241476 kb
Host smart-4c119968-51ab-43e4-88f4-6a6366f93892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492742227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3492742227
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.942420613
Short name T746
Test name
Test status
Simulation time 7496846649 ps
CPU time 33.44 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 233560 kb
Host smart-19f9c1d7-2d00-4dfe-9b69-3301854a351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942420613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.942420613
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3112699546
Short name T760
Test name
Test status
Simulation time 64441852359 ps
CPU time 455.44 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:33:58 PM PDT 24
Peak memory 256460 kb
Host smart-ef18fcc3-87e3-4f27-8e26-8695e876a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112699546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3112699546
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.312565273
Short name T846
Test name
Test status
Simulation time 4189684842 ps
CPU time 16.88 seconds
Started Aug 03 05:26:16 PM PDT 24
Finished Aug 03 05:26:33 PM PDT 24
Peak memory 225276 kb
Host smart-964657bb-0c66-451f-ba17-30691409916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312565273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.312565273
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2594659632
Short name T929
Test name
Test status
Simulation time 5936283879 ps
CPU time 6.77 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 225344 kb
Host smart-0b5eb064-f1a8-4c5d-8941-5b41bbf44a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594659632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2594659632
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2213007062
Short name T685
Test name
Test status
Simulation time 16376521 ps
CPU time 1.06 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:13 PM PDT 24
Peak memory 217212 kb
Host smart-ffb24dd1-93a4-426d-bc34-1e294d1f8727
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213007062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2213007062
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1361343216
Short name T957
Test name
Test status
Simulation time 112388263 ps
CPU time 2.36 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 233108 kb
Host smart-03702944-0801-4cd0-ba32-7d57aabe7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361343216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1361343216
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3286631179
Short name T440
Test name
Test status
Simulation time 3142103453 ps
CPU time 7.34 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:19 PM PDT 24
Peak memory 225376 kb
Host smart-e170976f-703a-4723-8867-880f536559de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286631179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3286631179
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2099016279
Short name T428
Test name
Test status
Simulation time 5093341817 ps
CPU time 11.87 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 223456 kb
Host smart-6140b785-71b7-4a5e-a600-ece66e69cf82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2099016279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2099016279
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3360955041
Short name T203
Test name
Test status
Simulation time 57955655275 ps
CPU time 201.91 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:29:39 PM PDT 24
Peak memory 273424 kb
Host smart-9fa6ea93-5382-45d2-9c87-9711b87353ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360955041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3360955041
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.715472085
Short name T864
Test name
Test status
Simulation time 13237047134 ps
CPU time 27.2 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 220876 kb
Host smart-e0760d4f-ae5a-49af-9651-77fbe0066a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715472085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.715472085
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3683505726
Short name T824
Test name
Test status
Simulation time 2368720872 ps
CPU time 6.21 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:26:18 PM PDT 24
Peak memory 217080 kb
Host smart-abccd2f2-5942-481f-bf9b-2df787c0ee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683505726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3683505726
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2283622592
Short name T757
Test name
Test status
Simulation time 65939900 ps
CPU time 1.57 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 217036 kb
Host smart-1c095791-f60e-4a3e-9e28-645fa2465fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283622592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2283622592
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1887729197
Short name T960
Test name
Test status
Simulation time 184788969 ps
CPU time 0.86 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 206568 kb
Host smart-120d3de4-eaf1-4203-a667-ce2ae77fef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887729197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1887729197
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4234756710
Short name T262
Test name
Test status
Simulation time 713548800 ps
CPU time 3.9 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:28 PM PDT 24
Peak memory 225168 kb
Host smart-4487f03f-700a-4241-b8b9-f5b5dda6ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234756710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4234756710
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2563104580
Short name T79
Test name
Test status
Simulation time 123555678 ps
CPU time 0.73 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:22 PM PDT 24
Peak memory 205908 kb
Host smart-5f7bccf7-a373-45af-b0b6-836c947cf748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563104580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2563104580
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1686131377
Short name T633
Test name
Test status
Simulation time 32354650 ps
CPU time 2.25 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:26:19 PM PDT 24
Peak memory 225260 kb
Host smart-d956947f-49c2-45ed-b53e-1561bd07c2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686131377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1686131377
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.461009351
Short name T619
Test name
Test status
Simulation time 15926086 ps
CPU time 0.78 seconds
Started Aug 03 05:26:13 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 207412 kb
Host smart-808a1c50-a758-47cb-99c5-48261052da26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461009351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.461009351
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4024459294
Short name T860
Test name
Test status
Simulation time 70178121235 ps
CPU time 61.86 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 250012 kb
Host smart-5fc59f9c-4c44-4918-bdee-78cd5bb70014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024459294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4024459294
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.461350463
Short name T716
Test name
Test status
Simulation time 6191565547 ps
CPU time 30.44 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 235688 kb
Host smart-a9eb48f1-4ddb-41e7-9306-53a82cac9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461350463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.461350463
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1712454636
Short name T530
Test name
Test status
Simulation time 321542919 ps
CPU time 6.54 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:29 PM PDT 24
Peak memory 241232 kb
Host smart-54970772-ccce-4a9c-b2ed-0597369df361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712454636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1712454636
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2728523778
Short name T893
Test name
Test status
Simulation time 28037735929 ps
CPU time 69.46 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:27:29 PM PDT 24
Peak memory 250956 kb
Host smart-003b44a8-8815-41d5-a398-c8839d837f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728523778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2728523778
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.418262310
Short name T62
Test name
Test status
Simulation time 709707609 ps
CPU time 9.9 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 225260 kb
Host smart-01e296c1-d08a-486f-ba88-9e2613817063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418262310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.418262310
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3673226141
Short name T1029
Test name
Test status
Simulation time 1250809383 ps
CPU time 10.65 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:33 PM PDT 24
Peak memory 225232 kb
Host smart-bf90b4e5-e1d3-4a80-af9a-f52ca384bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673226141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3673226141
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1613921692
Short name T621
Test name
Test status
Simulation time 89767659 ps
CPU time 1.06 seconds
Started Aug 03 05:26:16 PM PDT 24
Finished Aug 03 05:26:18 PM PDT 24
Peak memory 218448 kb
Host smart-4cfc0b7d-e3af-4d55-922a-7f04975ee335
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613921692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1613921692
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1097814422
Short name T988
Test name
Test status
Simulation time 1077131630 ps
CPU time 2.38 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 225204 kb
Host smart-8d9f96b5-75c2-45a1-8f55-25fba190820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097814422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1097814422
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3986455867
Short name T263
Test name
Test status
Simulation time 21037243311 ps
CPU time 12.01 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:26:27 PM PDT 24
Peak memory 240748 kb
Host smart-5a76a622-d0b9-4806-a1ca-fb187a9c1272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986455867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3986455867
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.856766655
Short name T506
Test name
Test status
Simulation time 1904815167 ps
CPU time 5.65 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:28 PM PDT 24
Peak memory 222968 kb
Host smart-3b3d93b5-9cd5-42ea-ad61-85f0c4968a46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=856766655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.856766655
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2714010631
Short name T725
Test name
Test status
Simulation time 172480407163 ps
CPU time 848.97 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:40:30 PM PDT 24
Peak memory 274540 kb
Host smart-f126a1c8-8ae2-4d37-85cd-41e89d968781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714010631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2714010631
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2248040399
Short name T84
Test name
Test status
Simulation time 32350347469 ps
CPU time 44.45 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 217060 kb
Host smart-636de882-1974-48af-a19a-2150fd933578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248040399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2248040399
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.134594301
Short name T31
Test name
Test status
Simulation time 14102227814 ps
CPU time 6.53 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 217100 kb
Host smart-879ece99-3f1d-4129-aa9e-35837d056f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134594301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.134594301
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4179877156
Short name T970
Test name
Test status
Simulation time 11400511 ps
CPU time 0.7 seconds
Started Aug 03 05:26:25 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 206116 kb
Host smart-d179020b-2d44-4eeb-8258-a907420f1cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179877156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4179877156
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3271328277
Short name T351
Test name
Test status
Simulation time 19206559 ps
CPU time 0.72 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 206596 kb
Host smart-55e35a60-9cf7-4c19-8c86-aa36ff89005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271328277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3271328277
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.560786094
Short name T256
Test name
Test status
Simulation time 9128559918 ps
CPU time 8.17 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 249936 kb
Host smart-024bfc04-8b42-4b61-837a-0fa2ea23ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560786094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.560786094
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4220016475
Short name T1002
Test name
Test status
Simulation time 26206781 ps
CPU time 0.71 seconds
Started Aug 03 05:26:16 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 205880 kb
Host smart-de3a3e3b-e63c-4ae1-a480-2951bf80f07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220016475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4220016475
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2135595575
Short name T839
Test name
Test status
Simulation time 277766646 ps
CPU time 2.45 seconds
Started Aug 03 05:26:30 PM PDT 24
Finished Aug 03 05:26:33 PM PDT 24
Peak memory 225240 kb
Host smart-172aceaf-84aa-4006-b717-70ef317f37ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135595575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2135595575
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1587737912
Short name T810
Test name
Test status
Simulation time 36568602 ps
CPU time 0.78 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 207052 kb
Host smart-c92b6071-8f44-4eaf-a672-08f53a718776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587737912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1587737912
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4098672873
Short name T828
Test name
Test status
Simulation time 9295262249 ps
CPU time 65.6 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 249948 kb
Host smart-6e3a2242-9a30-4d59-bac8-2c02f3d02072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098672873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4098672873
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3312599553
Short name T27
Test name
Test status
Simulation time 60953328474 ps
CPU time 175.33 seconds
Started Aug 03 05:26:27 PM PDT 24
Finished Aug 03 05:29:22 PM PDT 24
Peak memory 271736 kb
Host smart-db2db2e7-c186-493c-832c-5324ebb1abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312599553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3312599553
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2364398215
Short name T949
Test name
Test status
Simulation time 2252260337 ps
CPU time 17.8 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:35 PM PDT 24
Peak memory 251416 kb
Host smart-00c44eda-1ffe-440b-8fe7-8fa485c90300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364398215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2364398215
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3875057643
Short name T154
Test name
Test status
Simulation time 3060462999 ps
CPU time 13.03 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:32 PM PDT 24
Peak memory 241708 kb
Host smart-cb74cecc-c5df-4bc2-af72-638c7195efc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875057643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3875057643
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1193580854
Short name T752
Test name
Test status
Simulation time 14523072548 ps
CPU time 50.91 seconds
Started Aug 03 05:26:31 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 250164 kb
Host smart-2329a895-2b75-4aab-9d1b-57dc2503042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193580854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1193580854
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.690956680
Short name T529
Test name
Test status
Simulation time 1080346755 ps
CPU time 4.59 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 225184 kb
Host smart-e840b70e-f510-488e-ae51-281ba4c5f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690956680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.690956680
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3488739293
Short name T176
Test name
Test status
Simulation time 911197331 ps
CPU time 16.24 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 233396 kb
Host smart-775a8d7f-ed74-4a39-a2f2-51bcd8fe3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488739293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3488739293
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2756509044
Short name T343
Test name
Test status
Simulation time 109695790 ps
CPU time 1.11 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:26:38 PM PDT 24
Peak memory 217184 kb
Host smart-4fbd5b0e-b6be-46fb-a023-100f90f1e506
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756509044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2756509044
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1976746716
Short name T278
Test name
Test status
Simulation time 1609153627 ps
CPU time 6.98 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 241628 kb
Host smart-6218f971-e9af-4373-8e6c-49ae399c2ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976746716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1976746716
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4009441260
Short name T748
Test name
Test status
Simulation time 4785956407 ps
CPU time 16.37 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:34 PM PDT 24
Peak memory 236340 kb
Host smart-8f97a940-438d-4ff5-b9c3-50095fef1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009441260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4009441260
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2222685450
Short name T143
Test name
Test status
Simulation time 362654541 ps
CPU time 5.7 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:30 PM PDT 24
Peak memory 219896 kb
Host smart-62ab1bfe-c5c2-4a8e-896e-946e2e2caeb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2222685450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2222685450
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4195364690
Short name T775
Test name
Test status
Simulation time 183369714 ps
CPU time 0.96 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 207268 kb
Host smart-17629eb5-4c7c-4d9d-941c-d1494ce5d61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195364690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4195364690
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3102221131
Short name T547
Test name
Test status
Simulation time 7348161224 ps
CPU time 31.01 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:54 PM PDT 24
Peak memory 217032 kb
Host smart-49164a60-1219-42fc-a867-0681dddcf219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102221131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3102221131
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3565549908
Short name T933
Test name
Test status
Simulation time 30030344 ps
CPU time 0.72 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 206116 kb
Host smart-19184148-4ba8-4fc7-bbb6-ad14164434b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565549908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3565549908
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4232935490
Short name T965
Test name
Test status
Simulation time 844225423 ps
CPU time 7.77 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:27 PM PDT 24
Peak memory 216940 kb
Host smart-6d459af9-7aca-4217-8a7a-1297b716cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232935490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4232935490
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2712346012
Short name T859
Test name
Test status
Simulation time 29174281 ps
CPU time 0.82 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 206604 kb
Host smart-783d77dd-d584-4508-ad2a-da2a17393929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712346012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2712346012
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1000843425
Short name T287
Test name
Test status
Simulation time 3003886822 ps
CPU time 5.35 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:27 PM PDT 24
Peak memory 225348 kb
Host smart-d19805da-4fc1-4b52-9d5a-d0bea06fc04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000843425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1000843425
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.98392802
Short name T597
Test name
Test status
Simulation time 62773315 ps
CPU time 0.73 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 205296 kb
Host smart-bb0d679f-d9fe-42de-b5f0-c6d310dae5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98392802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.98392802
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2048027806
Short name T962
Test name
Test status
Simulation time 4846005691 ps
CPU time 14.8 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:27:00 PM PDT 24
Peak memory 225312 kb
Host smart-9030665f-8c97-47ac-897a-f77121942025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048027806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2048027806
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2456863561
Short name T352
Test name
Test status
Simulation time 148002795 ps
CPU time 0.72 seconds
Started Aug 03 05:26:30 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 207100 kb
Host smart-b6844098-5f3e-4661-9201-5d3850da7046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456863561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2456863561
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2784148252
Short name T225
Test name
Test status
Simulation time 18837487461 ps
CPU time 153.18 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:28:56 PM PDT 24
Peak memory 255580 kb
Host smart-edaf8e89-e97f-42c7-8e49-d757a6e739af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784148252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2784148252
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2765354766
Short name T676
Test name
Test status
Simulation time 3490417536 ps
CPU time 68.12 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:27:31 PM PDT 24
Peak memory 252960 kb
Host smart-a213db23-a861-4450-a7e5-595074b2d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765354766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2765354766
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2502123662
Short name T520
Test name
Test status
Simulation time 6989074921 ps
CPU time 26.24 seconds
Started Aug 03 05:26:25 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 218312 kb
Host smart-bc1e3425-58a4-412d-9e56-067ac5fae080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502123662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2502123662
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1231990507
Short name T6
Test name
Test status
Simulation time 442955455 ps
CPU time 8.25 seconds
Started Aug 03 05:26:37 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 225196 kb
Host smart-703c5b69-11d2-49ee-9900-c9a8c5abeb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231990507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1231990507
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1934015746
Short name T767
Test name
Test status
Simulation time 27810709212 ps
CPU time 71.22 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 254148 kb
Host smart-da1d4b95-cdf3-4bbe-a666-d7f87ccb3a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934015746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1934015746
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3103508050
Short name T968
Test name
Test status
Simulation time 5978170493 ps
CPU time 27.9 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 225332 kb
Host smart-2a577292-c545-47fd-8a59-75a0558c0592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103508050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3103508050
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2948596973
Short name T223
Test name
Test status
Simulation time 25898066846 ps
CPU time 36.95 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 249500 kb
Host smart-9dce63d3-32c7-4493-baf4-bd2f1b66dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948596973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2948596973
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3331917623
Short name T372
Test name
Test status
Simulation time 60245025 ps
CPU time 1.04 seconds
Started Aug 03 05:26:29 PM PDT 24
Finished Aug 03 05:26:32 PM PDT 24
Peak memory 218428 kb
Host smart-7382fda1-a67c-4b92-bea1-07b81dbe4f76
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331917623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3331917623
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4030558105
Short name T631
Test name
Test status
Simulation time 971047976 ps
CPU time 8.21 seconds
Started Aug 03 05:26:25 PM PDT 24
Finished Aug 03 05:26:33 PM PDT 24
Peak memory 225256 kb
Host smart-a336cc47-528e-4763-a965-0cce71a3b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030558105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4030558105
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1650070449
Short name T61
Test name
Test status
Simulation time 3498359359 ps
CPU time 5.66 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 241560 kb
Host smart-3bfc67ee-c1f0-4599-9ba7-bf4c363006d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650070449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1650070449
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1687852745
Short name T156
Test name
Test status
Simulation time 952347717 ps
CPU time 6.24 seconds
Started Aug 03 05:26:22 PM PDT 24
Finished Aug 03 05:26:28 PM PDT 24
Peak memory 219408 kb
Host smart-0f0c0a5c-1bf6-420d-b3d9-cc66e3442133
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1687852745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1687852745
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4140749337
Short name T20
Test name
Test status
Simulation time 20407234104 ps
CPU time 224.34 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:30:23 PM PDT 24
Peak memory 251024 kb
Host smart-ea96ef77-e79c-4b0a-8555-30251136791e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140749337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4140749337
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3740378082
Short name T86
Test name
Test status
Simulation time 17598955 ps
CPU time 0.71 seconds
Started Aug 03 05:26:35 PM PDT 24
Finished Aug 03 05:26:36 PM PDT 24
Peak memory 206224 kb
Host smart-88285695-5fe8-4ba2-8cbe-c0c3bb85e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740378082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3740378082
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.634994580
Short name T85
Test name
Test status
Simulation time 13711495 ps
CPU time 0.68 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 206220 kb
Host smart-476246e9-6149-4cb2-8262-0b9ba9cec5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634994580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.634994580
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4259246279
Short name T1020
Test name
Test status
Simulation time 22551264 ps
CPU time 1.39 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 216988 kb
Host smart-e74a5bf5-8f1a-4384-8703-2a4157b3e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259246279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4259246279
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2469051986
Short name T805
Test name
Test status
Simulation time 37862656 ps
CPU time 0.76 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 206588 kb
Host smart-92301ff2-b23a-4d85-8f9c-e250a102d599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469051986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2469051986
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3823540349
Short name T269
Test name
Test status
Simulation time 7179888950 ps
CPU time 16.07 seconds
Started Aug 03 05:26:25 PM PDT 24
Finished Aug 03 05:26:41 PM PDT 24
Peak memory 233580 kb
Host smart-7565fec2-489d-4019-8672-e03c6c7a9aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823540349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3823540349
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1095710812
Short name T990
Test name
Test status
Simulation time 46123332 ps
CPU time 0.78 seconds
Started Aug 03 05:26:33 PM PDT 24
Finished Aug 03 05:26:34 PM PDT 24
Peak memory 205244 kb
Host smart-0062f25d-59e4-4593-bd96-298b0b42df50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095710812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1095710812
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4165130282
Short name T463
Test name
Test status
Simulation time 369617690 ps
CPU time 4.81 seconds
Started Aug 03 05:26:31 PM PDT 24
Finished Aug 03 05:26:36 PM PDT 24
Peak memory 225280 kb
Host smart-503da853-b90c-4e41-8ee4-b5f57683e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165130282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4165130282
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1411768272
Short name T755
Test name
Test status
Simulation time 55575887 ps
CPU time 0.82 seconds
Started Aug 03 05:26:25 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 207024 kb
Host smart-29dc350a-90a8-424b-a82b-de0079da974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411768272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1411768272
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3279496182
Short name T311
Test name
Test status
Simulation time 96247230913 ps
CPU time 217.09 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:30:12 PM PDT 24
Peak memory 271388 kb
Host smart-695e01b2-7725-4cbb-9864-de407175a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279496182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3279496182
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1710447864
Short name T909
Test name
Test status
Simulation time 13466780352 ps
CPU time 106.46 seconds
Started Aug 03 05:26:31 PM PDT 24
Finished Aug 03 05:28:18 PM PDT 24
Peak memory 265728 kb
Host smart-d6daa5b5-31f0-424b-9e44-36404aa3b5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710447864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1710447864
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2804435488
Short name T615
Test name
Test status
Simulation time 5433523855 ps
CPU time 56.16 seconds
Started Aug 03 05:26:33 PM PDT 24
Finished Aug 03 05:27:29 PM PDT 24
Peak memory 241804 kb
Host smart-59b17607-a610-4cc0-9c08-01db40d3fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804435488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2804435488
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3121436551
Short name T870
Test name
Test status
Simulation time 1688640848 ps
CPU time 20 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 225248 kb
Host smart-7926b04d-9f6a-4a1a-a85e-c6d3da9032e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121436551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3121436551
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3696634820
Short name T316
Test name
Test status
Simulation time 3412178597 ps
CPU time 34.34 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:27:15 PM PDT 24
Peak memory 255532 kb
Host smart-8b7ad940-43ca-4a5c-88fc-18d42a20497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696634820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3696634820
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4280359221
Short name T572
Test name
Test status
Simulation time 4486560270 ps
CPU time 7.12 seconds
Started Aug 03 05:26:33 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 233512 kb
Host smart-3f9b5ff4-a788-4163-81b5-367b8a3b10d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280359221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4280359221
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3002566724
Short name T289
Test name
Test status
Simulation time 403873182 ps
CPU time 6.96 seconds
Started Aug 03 05:26:37 PM PDT 24
Finished Aug 03 05:26:44 PM PDT 24
Peak memory 225224 kb
Host smart-501b23d1-8277-4f34-9e5a-f36d8318c5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002566724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3002566724
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.469922405
Short name T401
Test name
Test status
Simulation time 47200216 ps
CPU time 1.09 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 217168 kb
Host smart-6ff6c8a4-1a44-46c5-893d-ef41367e42c1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469922405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.469922405
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4005463124
Short name T583
Test name
Test status
Simulation time 29609914745 ps
CPU time 31.2 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 225356 kb
Host smart-c17aa196-b303-4b19-acde-77fdcf95c9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005463124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4005463124
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.551070732
Short name T173
Test name
Test status
Simulation time 4280463760 ps
CPU time 6.5 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 233412 kb
Host smart-3f5a4aaa-a76b-4998-8e78-d3516bbbc562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551070732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.551070732
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1168083322
Short name T563
Test name
Test status
Simulation time 651525041 ps
CPU time 8.98 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:50 PM PDT 24
Peak memory 223592 kb
Host smart-1c7a58bf-c641-4bcd-abfe-5149878b07b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1168083322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1168083322
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.538902038
Short name T313
Test name
Test status
Simulation time 154800846188 ps
CPU time 489.69 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:34:47 PM PDT 24
Peak memory 287024 kb
Host smart-65e569d3-0ebe-475d-81ee-403c1414ab4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538902038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.538902038
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1491561858
Short name T570
Test name
Test status
Simulation time 1597889327 ps
CPU time 27.67 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 216988 kb
Host smart-46a3a969-09d1-46c4-81a7-f96f3f10d09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491561858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1491561858
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1659240017
Short name T346
Test name
Test status
Simulation time 2497558254 ps
CPU time 5.08 seconds
Started Aug 03 05:26:42 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 217216 kb
Host smart-d4d0cf46-c9f1-4644-9fb2-f1c50c3abeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659240017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1659240017
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.859377174
Short name T871
Test name
Test status
Simulation time 48764114 ps
CPU time 3.06 seconds
Started Aug 03 05:26:37 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 216860 kb
Host smart-ea4193e2-2183-4208-a030-75fb4a9f23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859377174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.859377174
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3511817722
Short name T456
Test name
Test status
Simulation time 46803036 ps
CPU time 0.81 seconds
Started Aug 03 05:26:24 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 206636 kb
Host smart-4c53c2b2-951a-4316-8d54-45f9c2196302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511817722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3511817722
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3209572155
Short name T881
Test name
Test status
Simulation time 516067455 ps
CPU time 4.09 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:26:38 PM PDT 24
Peak memory 233448 kb
Host smart-1728d6ea-c08a-4f81-b3ba-178c4773d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209572155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3209572155
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.154033890
Short name T632
Test name
Test status
Simulation time 14878691 ps
CPU time 0.75 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:26:35 PM PDT 24
Peak memory 205324 kb
Host smart-d8d3beec-360f-4795-bff6-0d89f0650287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154033890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.154033890
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1711142496
Short name T785
Test name
Test status
Simulation time 314237919 ps
CPU time 2.68 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 225228 kb
Host smart-cb11bc86-b1fd-429f-a106-1be3f33aaa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711142496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1711142496
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1343991150
Short name T782
Test name
Test status
Simulation time 36200533 ps
CPU time 0.82 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 207080 kb
Host smart-a73d7d2d-53f8-435e-ae98-43d07407f225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343991150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1343991150
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.613308778
Short name T211
Test name
Test status
Simulation time 7496668564 ps
CPU time 26.31 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 241784 kb
Host smart-878381be-1425-4f0e-aafc-19d3a370c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613308778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.613308778
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.876006083
Short name T220
Test name
Test status
Simulation time 4218709632 ps
CPU time 83.53 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:27:57 PM PDT 24
Peak memory 253824 kb
Host smart-a0e965f1-371e-46c2-8632-0c601e1666d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876006083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.876006083
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2805799810
Short name T964
Test name
Test status
Simulation time 289710452904 ps
CPU time 206.8 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:30:08 PM PDT 24
Peak memory 250736 kb
Host smart-674d6569-3b28-44c6-b343-9121836d119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805799810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2805799810
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2474502215
Short name T768
Test name
Test status
Simulation time 4100873691 ps
CPU time 17.11 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:26:57 PM PDT 24
Peak memory 233556 kb
Host smart-83cd47ff-1357-4cdf-bf96-7289091f8155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474502215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2474502215
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3914775913
Short name T826
Test name
Test status
Simulation time 1019504707 ps
CPU time 14.85 seconds
Started Aug 03 05:26:35 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 225268 kb
Host smart-8012fbbe-e29d-4061-a57a-956f09166fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914775913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3914775913
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.690333763
Short name T519
Test name
Test status
Simulation time 365205960 ps
CPU time 4.35 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:43 PM PDT 24
Peak memory 225216 kb
Host smart-26239598-366f-4cda-af0e-2ccbe5dedb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690333763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.690333763
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.999596566
Short name T541
Test name
Test status
Simulation time 4934300866 ps
CPU time 10.75 seconds
Started Aug 03 05:26:35 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 233560 kb
Host smart-fd37d328-c596-456e-8e68-a3a8bba8907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999596566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.999596566
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.975268314
Short name T494
Test name
Test status
Simulation time 18005330 ps
CPU time 1.09 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:26:37 PM PDT 24
Peak memory 217228 kb
Host smart-8f940e90-60e4-4384-847e-265558e05d43
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975268314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.975268314
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.522274543
Short name T882
Test name
Test status
Simulation time 284473978 ps
CPU time 2.48 seconds
Started Aug 03 05:26:32 PM PDT 24
Finished Aug 03 05:26:35 PM PDT 24
Peak memory 225196 kb
Host smart-87759eed-b5f0-4817-8110-03ebde24f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522274543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.522274543
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2718512407
Short name T774
Test name
Test status
Simulation time 4956960873 ps
CPU time 11.65 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 220996 kb
Host smart-adde4a42-2da9-49af-84e2-e573c637a464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2718512407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2718512407
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1816281207
Short name T21
Test name
Test status
Simulation time 23057209342 ps
CPU time 207.86 seconds
Started Aug 03 05:26:32 PM PDT 24
Finished Aug 03 05:30:00 PM PDT 24
Peak memory 256428 kb
Host smart-bf16b68c-1d2c-4df1-9f71-79b64721dcb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816281207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1816281207
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.171456605
Short name T331
Test name
Test status
Simulation time 2220008653 ps
CPU time 17.63 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:26:54 PM PDT 24
Peak memory 219152 kb
Host smart-dde419e7-f035-4d80-bc88-f8d067dd7ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171456605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.171456605
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2893945317
Short name T599
Test name
Test status
Simulation time 2317570134 ps
CPU time 7.07 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 217120 kb
Host smart-e5518d62-8b9a-498b-a50f-0c2798d4059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893945317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2893945317
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2364666136
Short name T873
Test name
Test status
Simulation time 29756577 ps
CPU time 1.14 seconds
Started Aug 03 05:26:33 PM PDT 24
Finished Aug 03 05:26:34 PM PDT 24
Peak memory 216896 kb
Host smart-fb9290c4-8f0a-47c8-9712-7a23db696db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364666136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2364666136
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3307476792
Short name T630
Test name
Test status
Simulation time 87378916 ps
CPU time 0.77 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:39 PM PDT 24
Peak memory 206540 kb
Host smart-824a65ad-d8e1-4c70-b11f-b6634bbe7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307476792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3307476792
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2926435508
Short name T1004
Test name
Test status
Simulation time 5805966529 ps
CPU time 22.51 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 233584 kb
Host smart-7f39cb5c-a383-4cfd-94a2-97031da9aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926435508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2926435508
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2643589027
Short name T580
Test name
Test status
Simulation time 17091656 ps
CPU time 0.71 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 205832 kb
Host smart-fcd6f51c-e268-4e78-ab24-d710f8b5f932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643589027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2643589027
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2270243191
Short name T439
Test name
Test status
Simulation time 2747757740 ps
CPU time 5.28 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:50 PM PDT 24
Peak memory 233500 kb
Host smart-3fc11fca-5d59-4f1e-9116-d85aa854fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270243191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2270243191
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.508481298
Short name T388
Test name
Test status
Simulation time 22954936 ps
CPU time 0.83 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 207092 kb
Host smart-83b03358-ebd3-40a0-b226-e8ab4c88fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508481298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.508481298
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4019491847
Short name T604
Test name
Test status
Simulation time 30145600332 ps
CPU time 58.56 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:27:39 PM PDT 24
Peak memory 237812 kb
Host smart-b29ef9f6-fa3a-4db6-b8dc-2eeef241b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019491847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4019491847
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.771983911
Short name T658
Test name
Test status
Simulation time 18226411596 ps
CPU time 112 seconds
Started Aug 03 05:26:34 PM PDT 24
Finished Aug 03 05:28:26 PM PDT 24
Peak memory 249960 kb
Host smart-e4f41610-a58a-4355-8fcc-561b5301f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771983911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.771983911
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1335257912
Short name T201
Test name
Test status
Simulation time 6882999940 ps
CPU time 110.42 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 256664 kb
Host smart-0147f829-a428-489c-a627-0e80c5c952b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335257912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1335257912
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.312124031
Short name T410
Test name
Test status
Simulation time 570524533 ps
CPU time 4.86 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:43 PM PDT 24
Peak memory 233532 kb
Host smart-4a891054-abf6-4106-82a2-eaef438eae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312124031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.312124031
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.822313082
Short name T305
Test name
Test status
Simulation time 16206050840 ps
CPU time 75.01 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 251316 kb
Host smart-21a176b8-9ae9-48c5-9f67-5ab0f889f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822313082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.822313082
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3150818272
Short name T875
Test name
Test status
Simulation time 933658048 ps
CPU time 9.12 seconds
Started Aug 03 05:26:42 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 233460 kb
Host smart-fc1545c6-e056-4ad5-865f-092cc3346117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150818272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3150818272
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1914383258
Short name T677
Test name
Test status
Simulation time 276685436 ps
CPU time 6.8 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 233500 kb
Host smart-1d3c6ef5-633e-4b2d-a494-aac1a713b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914383258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1914383258
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3909597980
Short name T643
Test name
Test status
Simulation time 55570253 ps
CPU time 1.03 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:53 PM PDT 24
Peak memory 217196 kb
Host smart-543b934d-f23d-4a08-8ab4-fa4975387166
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909597980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3909597980
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1450501711
Short name T847
Test name
Test status
Simulation time 684423571 ps
CPU time 8.98 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:54 PM PDT 24
Peak memory 225200 kb
Host smart-6a1afed4-e665-479b-859f-e3b0c15d95d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450501711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1450501711
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.105367016
Short name T579
Test name
Test status
Simulation time 10780741289 ps
CPU time 9.34 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:50 PM PDT 24
Peak memory 233584 kb
Host smart-4566661a-d30e-4d1d-b749-459bba005252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105367016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.105367016
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1332356052
Short name T509
Test name
Test status
Simulation time 23765664311 ps
CPU time 18.03 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 220936 kb
Host smart-e9985615-e87e-48ea-9174-a5ede667779b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332356052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1332356052
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1918593387
Short name T465
Test name
Test status
Simulation time 6444601443 ps
CPU time 21.06 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:59 PM PDT 24
Peak memory 216988 kb
Host smart-7002d822-95fd-4b75-ae07-b8c8e43372b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918593387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1918593387
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.659304816
Short name T581
Test name
Test status
Simulation time 20815469977 ps
CPU time 14.3 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:27:00 PM PDT 24
Peak memory 217052 kb
Host smart-c5b5ae30-aaed-4ea8-a55c-80f38f9a4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659304816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.659304816
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3933750010
Short name T637
Test name
Test status
Simulation time 30755554 ps
CPU time 0.88 seconds
Started Aug 03 05:26:50 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 207248 kb
Host smart-db1a5d01-b0f2-469b-9669-99350e081b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933750010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3933750010
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3937420910
Short name T418
Test name
Test status
Simulation time 57793975 ps
CPU time 0.9 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 206616 kb
Host smart-f974b12f-3076-4beb-9b10-d352f3d80b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937420910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3937420910
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3862382648
Short name T13
Test name
Test status
Simulation time 6827191533 ps
CPU time 22.16 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 233580 kb
Host smart-d2ef84f4-728e-4fd1-858f-3d7fcc4ca925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862382648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3862382648
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3799891027
Short name T427
Test name
Test status
Simulation time 66382319 ps
CPU time 0.72 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 206084 kb
Host smart-55c4944d-8f55-4a3b-a415-31ba785cc394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799891027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3799891027
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3958586130
Short name T447
Test name
Test status
Simulation time 404049599 ps
CPU time 2.4 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:44 PM PDT 24
Peak memory 225280 kb
Host smart-28e2a23a-bc9d-4613-9686-022ef4bd41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958586130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3958586130
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.862753296
Short name T765
Test name
Test status
Simulation time 33736118 ps
CPU time 0.8 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 207088 kb
Host smart-42e8eba0-13f6-4aff-8691-d05ed517eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862753296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.862753296
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4250829609
Short name T244
Test name
Test status
Simulation time 112765158219 ps
CPU time 121.48 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 249812 kb
Host smart-14ca86cd-9cab-46f0-8c9c-b455981ea5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250829609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4250829609
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.678209964
Short name T976
Test name
Test status
Simulation time 4277922651 ps
CPU time 62.44 seconds
Started Aug 03 05:26:37 PM PDT 24
Finished Aug 03 05:27:40 PM PDT 24
Peak memory 241760 kb
Host smart-c15dca57-8213-4f05-a9c5-7bdab748cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678209964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.678209964
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.81884983
Short name T622
Test name
Test status
Simulation time 4468930350 ps
CPU time 18.86 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 236668 kb
Host smart-ce707857-cbe4-47d2-bc19-110534e0039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81884983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.81884983
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2525196932
Short name T528
Test name
Test status
Simulation time 112913186 ps
CPU time 3.36 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 233516 kb
Host smart-5ae77626-829d-4c93-8fed-36732ad976a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525196932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2525196932
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1509533165
Short name T340
Test name
Test status
Simulation time 196869329 ps
CPU time 0.93 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:26:41 PM PDT 24
Peak memory 216680 kb
Host smart-734e10da-83fc-480d-b482-c9fc6894d019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509533165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1509533165
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2468782679
Short name T483
Test name
Test status
Simulation time 17667999727 ps
CPU time 17.32 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 230200 kb
Host smart-723874f2-79e6-4348-a6e6-a5a31adcd8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468782679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2468782679
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.73691848
Short name T273
Test name
Test status
Simulation time 738659557 ps
CPU time 10.77 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 225308 kb
Host smart-8f6b29a9-b207-4b08-8006-b31fdd6d4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73691848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.73691848
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3655257480
Short name T586
Test name
Test status
Simulation time 54061923 ps
CPU time 1.08 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:26:41 PM PDT 24
Peak memory 217208 kb
Host smart-13fdd00f-3067-4382-8076-f7742d4bc9f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655257480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3655257480
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1109266188
Short name T625
Test name
Test status
Simulation time 5325608225 ps
CPU time 7.51 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 225164 kb
Host smart-bcbb9568-9970-4054-a716-37646fd4b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109266188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1109266188
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3834876432
Short name T565
Test name
Test status
Simulation time 123845559 ps
CPU time 2.01 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 225212 kb
Host smart-eb3282eb-d326-4ef7-b2ec-625fd26a953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834876432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3834876432
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.854091278
Short name T835
Test name
Test status
Simulation time 282751489 ps
CPU time 3.43 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 222352 kb
Host smart-d2c94085-4ebc-4cba-aed3-a5ca518abcd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=854091278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.854091278
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.991442072
Short name T167
Test name
Test status
Simulation time 56515459443 ps
CPU time 292.46 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:31:36 PM PDT 24
Peak memory 266332 kb
Host smart-b5abd0aa-24ce-4cf8-95d3-efbcbff4684d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991442072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.991442072
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2777392253
Short name T720
Test name
Test status
Simulation time 4854153960 ps
CPU time 24.91 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:27:12 PM PDT 24
Peak memory 216984 kb
Host smart-ebc5df43-74b4-4965-b1a4-b8ca837a8963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777392253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2777392253
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3598522650
Short name T958
Test name
Test status
Simulation time 3783925496 ps
CPU time 14.13 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 216180 kb
Host smart-59aa8092-794a-477c-8000-7361777aa33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598522650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3598522650
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2112565579
Short name T922
Test name
Test status
Simulation time 257594702 ps
CPU time 1.15 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 217004 kb
Host smart-8a34fd39-dd3e-40a4-a4dd-5d17368f5aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112565579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2112565579
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.251653024
Short name T773
Test name
Test status
Simulation time 233682153 ps
CPU time 0.87 seconds
Started Aug 03 05:26:41 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 206640 kb
Host smart-7d1312a6-f755-489f-a5ac-d0e6baf4458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251653024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.251653024
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3231924615
Short name T699
Test name
Test status
Simulation time 1853900300 ps
CPU time 8.36 seconds
Started Aug 03 05:26:40 PM PDT 24
Finished Aug 03 05:26:48 PM PDT 24
Peak memory 233460 kb
Host smart-9405387d-8cb2-4570-9d25-e27d3d1c2cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231924615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3231924615
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1008959815
Short name T831
Test name
Test status
Simulation time 32425910 ps
CPU time 0.74 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:03 PM PDT 24
Peak memory 205312 kb
Host smart-b6ce60cd-b4b3-4829-b205-c854e63f98fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008959815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
008959815
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2377604608
Short name T481
Test name
Test status
Simulation time 16640253678 ps
CPU time 15.22 seconds
Started Aug 03 05:26:06 PM PDT 24
Finished Aug 03 05:26:22 PM PDT 24
Peak memory 225352 kb
Host smart-5debf497-60a1-479c-b02b-93f5391d90bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377604608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2377604608
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3524112409
Short name T357
Test name
Test status
Simulation time 47461841 ps
CPU time 0.75 seconds
Started Aug 03 05:25:58 PM PDT 24
Finished Aug 03 05:25:59 PM PDT 24
Peak memory 207092 kb
Host smart-94ab6a02-2609-4447-b158-fe4077a427c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524112409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3524112409
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1998761702
Short name T944
Test name
Test status
Simulation time 11591615747 ps
CPU time 18.06 seconds
Started Aug 03 05:25:43 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 225412 kb
Host smart-cb2ea139-ce50-4f8f-94b4-f80887542c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998761702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1998761702
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1963017159
Short name T321
Test name
Test status
Simulation time 2288694256 ps
CPU time 11.47 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:57 PM PDT 24
Peak memory 249312 kb
Host smart-bff5e1d1-e4b2-467a-8f62-7f4f344abc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963017159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1963017159
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.843617587
Short name T934
Test name
Test status
Simulation time 19082008129 ps
CPU time 123.52 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 249992 kb
Host smart-9d4f8922-9220-45b0-8b04-0a74fcb63814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843617587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
843617587
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1048950636
Short name T700
Test name
Test status
Simulation time 66435675 ps
CPU time 2.55 seconds
Started Aug 03 05:25:51 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 233084 kb
Host smart-e45d71c6-9c7e-449a-8353-297503a7490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048950636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1048950636
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1034688462
Short name T392
Test name
Test status
Simulation time 76644149 ps
CPU time 2.1 seconds
Started Aug 03 05:26:05 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 224796 kb
Host smart-2ce8e858-64ed-41ae-b310-9e77e42d978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034688462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1034688462
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1712020839
Short name T40
Test name
Test status
Simulation time 115954737 ps
CPU time 1.08 seconds
Started Aug 03 05:25:51 PM PDT 24
Finished Aug 03 05:25:53 PM PDT 24
Peak memory 217172 kb
Host smart-02045fb1-1d45-43a5-8c18-ceed7b2c3b44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712020839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1712020839
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1656797900
Short name T283
Test name
Test status
Simulation time 6201084529 ps
CPU time 12.92 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:26:03 PM PDT 24
Peak memory 235600 kb
Host smart-acb0d78c-fdd6-4e0d-ad0f-d14cc5b4e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656797900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1656797900
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4034250007
Short name T644
Test name
Test status
Simulation time 400984810 ps
CPU time 2.46 seconds
Started Aug 03 05:25:45 PM PDT 24
Finished Aug 03 05:25:48 PM PDT 24
Peak memory 225240 kb
Host smart-17b81e2a-5779-43e5-bfd6-bec1b76ba8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034250007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4034250007
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2568603322
Short name T508
Test name
Test status
Simulation time 2144955475 ps
CPU time 4.78 seconds
Started Aug 03 05:25:44 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 219416 kb
Host smart-6321f53b-8798-4cd9-9e1f-a8a03f4202b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568603322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2568603322
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3862199040
Short name T74
Test name
Test status
Simulation time 89023815 ps
CPU time 0.93 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:47 PM PDT 24
Peak memory 234952 kb
Host smart-6b5644b8-abcf-407a-aeba-fcadc6e509ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862199040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3862199040
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4042383883
Short name T402
Test name
Test status
Simulation time 869293998 ps
CPU time 18.22 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 238272 kb
Host smart-1b788282-11cf-42b4-a560-549119f956a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042383883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4042383883
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3912204470
Short name T327
Test name
Test status
Simulation time 5264434727 ps
CPU time 36.88 seconds
Started Aug 03 05:25:49 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 217036 kb
Host smart-85f4414e-25ae-4891-9251-2545665d96b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912204470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3912204470
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.918893352
Short name T888
Test name
Test status
Simulation time 2421949961 ps
CPU time 3.55 seconds
Started Aug 03 05:25:47 PM PDT 24
Finished Aug 03 05:25:50 PM PDT 24
Peak memory 217020 kb
Host smart-3b93762d-8757-4dbd-a2a4-0159edab425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918893352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.918893352
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.848532747
Short name T818
Test name
Test status
Simulation time 112073047 ps
CPU time 1.6 seconds
Started Aug 03 05:26:00 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 217044 kb
Host smart-8d10b6e0-f1a5-4e4e-a9be-c48e8e8c777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848532747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.848532747
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1939969362
Short name T92
Test name
Test status
Simulation time 186039800 ps
CPU time 0.83 seconds
Started Aug 03 05:25:59 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 206492 kb
Host smart-29fa7a7e-f193-44ea-9406-71d003e3b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939969362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1939969362
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3313053790
Short name T12
Test name
Test status
Simulation time 4186725353 ps
CPU time 10.23 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 225256 kb
Host smart-20e0a950-43b6-48b4-a3e7-f02b0f21d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313053790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3313053790
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1743300777
Short name T591
Test name
Test status
Simulation time 11404203 ps
CPU time 0.71 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 206244 kb
Host smart-e27b53b5-42f5-4aca-a4ca-9d40a3ae137b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743300777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1743300777
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1356696077
Short name T790
Test name
Test status
Simulation time 553681944 ps
CPU time 7.95 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 233492 kb
Host smart-7f7c0f03-bbfe-4f8e-b5ad-363dc2858912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356696077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1356696077
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1558792296
Short name T360
Test name
Test status
Simulation time 21803099 ps
CPU time 0.71 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:26:44 PM PDT 24
Peak memory 206416 kb
Host smart-8d342835-08b1-4054-9099-2c685c015659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558792296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1558792296
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1666205111
Short name T714
Test name
Test status
Simulation time 1481520663 ps
CPU time 6.06 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 225440 kb
Host smart-cc9b8aac-5f77-4490-a5c9-294491ecf494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666205111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1666205111
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2789516199
Short name T891
Test name
Test status
Simulation time 110670228164 ps
CPU time 248.61 seconds
Started Aug 03 05:26:42 PM PDT 24
Finished Aug 03 05:30:51 PM PDT 24
Peak memory 251068 kb
Host smart-7f04c1f3-ea83-40c6-8fd7-73899da16920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789516199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2789516199
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4194192123
Short name T648
Test name
Test status
Simulation time 94433565843 ps
CPU time 227.05 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:30:32 PM PDT 24
Peak memory 249884 kb
Host smart-656c677a-4052-4079-975c-de59ad1e0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194192123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4194192123
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3423735014
Short name T387
Test name
Test status
Simulation time 1820097946 ps
CPU time 18.24 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:58 PM PDT 24
Peak memory 244192 kb
Host smart-ef13ee93-0dea-4f8c-83eb-b968267657c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423735014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3423735014
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3661579252
Short name T804
Test name
Test status
Simulation time 44031631663 ps
CPU time 89.91 seconds
Started Aug 03 05:26:50 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 252528 kb
Host smart-667e66ad-e2ab-445c-8c71-bcb0471ee530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661579252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3661579252
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2926394787
Short name T582
Test name
Test status
Simulation time 182445918 ps
CPU time 5.11 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:50 PM PDT 24
Peak memory 233516 kb
Host smart-f723486c-7877-4340-81d8-7af5e57b503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926394787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2926394787
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4112574724
Short name T272
Test name
Test status
Simulation time 22105876515 ps
CPU time 75.3 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 233572 kb
Host smart-4bf64c68-3c65-4dff-a056-2f8dbe346859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112574724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4112574724
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3357931154
Short name T762
Test name
Test status
Simulation time 356369006 ps
CPU time 8.23 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 249784 kb
Host smart-cadae16f-fa69-442d-9f77-9b449e199e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357931154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3357931154
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2864565747
Short name T1025
Test name
Test status
Simulation time 291440317 ps
CPU time 2.95 seconds
Started Aug 03 05:26:37 PM PDT 24
Finished Aug 03 05:26:40 PM PDT 24
Peak memory 225188 kb
Host smart-48764344-23f6-4740-9a4a-5ea13bf4d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864565747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2864565747
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2208790839
Short name T64
Test name
Test status
Simulation time 1106132749 ps
CPU time 4.98 seconds
Started Aug 03 05:26:49 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 223868 kb
Host smart-bebcea85-672a-481e-8b08-6d89f8750c79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208790839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2208790839
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1268860988
Short name T734
Test name
Test status
Simulation time 15416236402 ps
CPU time 40.49 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:27:20 PM PDT 24
Peak memory 218556 kb
Host smart-86f11c34-3a9c-40dd-94ff-d937b6fdfe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268860988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1268860988
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3777460532
Short name T396
Test name
Test status
Simulation time 15920328636 ps
CPU time 12.87 seconds
Started Aug 03 05:26:39 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 217036 kb
Host smart-9dbf8569-6be0-419a-8197-07607c0a4e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777460532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3777460532
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2693028377
Short name T532
Test name
Test status
Simulation time 40565825 ps
CPU time 0.68 seconds
Started Aug 03 05:26:36 PM PDT 24
Finished Aug 03 05:26:37 PM PDT 24
Peak memory 206172 kb
Host smart-1d1e61ac-7e43-410a-88cd-8a9831f8399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693028377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2693028377
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1595635245
Short name T146
Test name
Test status
Simulation time 148222975 ps
CPU time 0.8 seconds
Started Aug 03 05:26:38 PM PDT 24
Finished Aug 03 05:26:39 PM PDT 24
Peak memory 206596 kb
Host smart-9fe70a17-e1cc-442f-bf3b-2b24c233240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595635245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1595635245
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2130702023
Short name T258
Test name
Test status
Simulation time 33955932850 ps
CPU time 27.35 seconds
Started Aug 03 05:26:50 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 241588 kb
Host smart-3ce3eb1d-d469-46ee-a4e6-a14c4e509807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130702023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2130702023
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3150801384
Short name T69
Test name
Test status
Simulation time 12020799 ps
CPU time 0.72 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:53 PM PDT 24
Peak memory 205300 kb
Host smart-4137f76e-0eb4-40d8-8e34-7d7e16399d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150801384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3150801384
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3354906
Short name T793
Test name
Test status
Simulation time 957753687 ps
CPU time 4.83 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:50 PM PDT 24
Peak memory 225308 kb
Host smart-e854e115-83bf-4ad4-ad30-4f898ee28e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3354906
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3599396122
Short name T915
Test name
Test status
Simulation time 76177327 ps
CPU time 0.81 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 207036 kb
Host smart-2a6b92b9-8116-4445-a48b-494b4becd04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599396122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3599396122
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3799281718
Short name T309
Test name
Test status
Simulation time 32748256670 ps
CPU time 203.95 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:30:15 PM PDT 24
Peak memory 252176 kb
Host smart-fa96f018-05ce-4ea9-bf33-48707a26d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799281718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3799281718
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1325563145
Short name T906
Test name
Test status
Simulation time 66240343100 ps
CPU time 280.82 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:31:32 PM PDT 24
Peak memory 256176 kb
Host smart-49b1b46d-3dec-4ed2-b7e5-11c1a9c016ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325563145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1325563145
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.375886686
Short name T38
Test name
Test status
Simulation time 109832804474 ps
CPU time 277.5 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:31:24 PM PDT 24
Peak memory 259360 kb
Host smart-af927f2c-0e95-492f-8e45-b4e0f18baab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375886686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.375886686
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2838260355
Short name T76
Test name
Test status
Simulation time 34845934 ps
CPU time 2.75 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:51 PM PDT 24
Peak memory 233420 kb
Host smart-bdb52baf-5150-49f3-aa52-658b619036e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838260355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2838260355
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4121714493
Short name T712
Test name
Test status
Simulation time 48739249 ps
CPU time 0.78 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 216480 kb
Host smart-c42d0464-585c-4e5e-96e2-e3f5c6d40481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121714493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4121714493
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2072368588
Short name T973
Test name
Test status
Simulation time 2694569261 ps
CPU time 12.38 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 225240 kb
Host smart-95652b6d-7027-4b50-88c2-d225af787879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072368588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2072368588
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1856742267
Short name T695
Test name
Test status
Simulation time 14250102768 ps
CPU time 30.12 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 225376 kb
Host smart-fc52d74c-f437-4498-8b2c-703025333a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856742267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1856742267
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.902028404
Short name T1009
Test name
Test status
Simulation time 2189308253 ps
CPU time 9.92 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 233520 kb
Host smart-b5d43db7-f798-4e5f-a357-12a51456e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902028404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.902028404
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.754974988
Short name T1003
Test name
Test status
Simulation time 1322521781 ps
CPU time 6.78 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 233480 kb
Host smart-b1b79739-8d53-4f1d-aa6d-db0d9ed7add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754974988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.754974988
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2322518011
Short name T362
Test name
Test status
Simulation time 406711362 ps
CPU time 5.03 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 223788 kb
Host smart-009c6eb0-48a7-4bd6-a3d6-86f9d30c86b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2322518011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2322518011
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1688865445
Short name T884
Test name
Test status
Simulation time 3994120500 ps
CPU time 28.5 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:27:11 PM PDT 24
Peak memory 218336 kb
Host smart-b9b6141c-f872-4d7c-b297-3910bb5df8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688865445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1688865445
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1945426146
Short name T383
Test name
Test status
Simulation time 68653308 ps
CPU time 0.7 seconds
Started Aug 03 05:26:43 PM PDT 24
Finished Aug 03 05:26:44 PM PDT 24
Peak memory 206580 kb
Host smart-c07d48d3-ae8f-41ce-84f7-6e84e292575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945426146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1945426146
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2790512374
Short name T58
Test name
Test status
Simulation time 1245946393 ps
CPU time 7.57 seconds
Started Aug 03 05:26:44 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 216932 kb
Host smart-6462591c-fe25-4533-970e-7b3d5dddc14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790512374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2790512374
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2817625774
Short name T931
Test name
Test status
Simulation time 16231024 ps
CPU time 0.98 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 208608 kb
Host smart-b4139fd9-6651-4f85-83e4-d483e765ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817625774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2817625774
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2775026653
Short name T397
Test name
Test status
Simulation time 26675871 ps
CPU time 0.82 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 206416 kb
Host smart-7c8a81e7-d064-4d2d-b8f3-c9abcdfab912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775026653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2775026653
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1976688738
Short name T531
Test name
Test status
Simulation time 309183652 ps
CPU time 2.46 seconds
Started Aug 03 05:26:47 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 225220 kb
Host smart-6c8e630c-4d5e-4ffe-b2e0-5beb77a667a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976688738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1976688738
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1667661653
Short name T491
Test name
Test status
Simulation time 14811827 ps
CPU time 0.72 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 205328 kb
Host smart-c2a6b46b-13c6-4296-a601-2eef8398d3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667661653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1667661653
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2862853398
Short name T288
Test name
Test status
Simulation time 316012402 ps
CPU time 4.37 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:57 PM PDT 24
Peak memory 233460 kb
Host smart-b8a89429-4923-4cb8-83d4-406ec114ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862853398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2862853398
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1982456028
Short name T966
Test name
Test status
Simulation time 64986721 ps
CPU time 0.79 seconds
Started Aug 03 05:26:46 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 207384 kb
Host smart-5848bdec-3cee-4a06-98bb-2083ad30ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982456028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1982456028
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2852770678
Short name T476
Test name
Test status
Simulation time 92746145795 ps
CPU time 167.81 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:29:39 PM PDT 24
Peak memory 249956 kb
Host smart-223791b7-aa81-4c2b-8b21-b73030921ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852770678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2852770678
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2197283590
Short name T739
Test name
Test status
Simulation time 93291436910 ps
CPU time 176.85 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:29:45 PM PDT 24
Peak memory 250024 kb
Host smart-3842ea77-22b3-4190-8dff-e6da79640abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197283590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2197283590
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1170447179
Short name T789
Test name
Test status
Simulation time 1410108617 ps
CPU time 8.67 seconds
Started Aug 03 05:26:49 PM PDT 24
Finished Aug 03 05:26:58 PM PDT 24
Peak memory 233492 kb
Host smart-f8005751-6156-4a59-89a8-9891f2fd42f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170447179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1170447179
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2013387832
Short name T840
Test name
Test status
Simulation time 16270517260 ps
CPU time 104.64 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 251372 kb
Host smart-a8cacdaa-d732-4c5c-b169-2b9ee1ddda8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013387832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2013387832
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.810470719
Short name T758
Test name
Test status
Simulation time 159934589 ps
CPU time 4.39 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 225292 kb
Host smart-b584119c-7e86-4939-b5bb-cf3fbcef6538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810470719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.810470719
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1455031595
Short name T800
Test name
Test status
Simulation time 779210460 ps
CPU time 5.52 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 233464 kb
Host smart-2484ffa2-bc6d-4a51-9d99-cb5f4e6ff62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455031595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1455031595
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.17927805
Short name T567
Test name
Test status
Simulation time 1668655649 ps
CPU time 8.13 seconds
Started Aug 03 05:26:46 PM PDT 24
Finished Aug 03 05:26:54 PM PDT 24
Peak memory 225192 kb
Host smart-e69c40d6-1e04-4272-b3aa-f9ff853d14ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17927805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.17927805
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3715796067
Short name T834
Test name
Test status
Simulation time 1971632796 ps
CPU time 13.7 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:59 PM PDT 24
Peak memory 234536 kb
Host smart-4032d288-c187-4865-a4cb-8a3708c98af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715796067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3715796067
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2177283333
Short name T1030
Test name
Test status
Simulation time 971768563 ps
CPU time 11.04 seconds
Started Aug 03 05:26:50 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 222608 kb
Host smart-9d2ca282-d779-43db-9fdd-399158844083
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177283333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2177283333
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4122428230
Short name T953
Test name
Test status
Simulation time 6731591086 ps
CPU time 35.24 seconds
Started Aug 03 05:26:46 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 217108 kb
Host smart-ce9395f3-f2fb-47eb-858f-97a37fb323bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122428230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4122428230
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.798306330
Short name T741
Test name
Test status
Simulation time 4783040818 ps
CPU time 7.68 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 216844 kb
Host smart-07b3e465-91b6-411f-ab17-7bb31224f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798306330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.798306330
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2687520177
Short name T333
Test name
Test status
Simulation time 63241377 ps
CPU time 1.16 seconds
Started Aug 03 05:26:45 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 208200 kb
Host smart-58f7aa84-2ce2-444f-aa8c-4bcc5b207220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687520177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2687520177
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.980645799
Short name T989
Test name
Test status
Simulation time 59136284 ps
CPU time 0.77 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 206600 kb
Host smart-fce41717-b05e-4d72-ad16-0e6900471d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980645799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.980645799
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1226226785
Short name T214
Test name
Test status
Simulation time 1409877798 ps
CPU time 9.52 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 225172 kb
Host smart-4105d988-87cf-4d1c-bd56-abe3fccb4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226226785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1226226785
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3563143774
Short name T687
Test name
Test status
Simulation time 25535567 ps
CPU time 0.69 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:53 PM PDT 24
Peak memory 205304 kb
Host smart-20a143d9-68e1-4ec6-b29d-6accdebb2007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563143774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3563143774
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.449841500
Short name T426
Test name
Test status
Simulation time 92576086 ps
CPU time 3.3 seconds
Started Aug 03 05:26:58 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 233416 kb
Host smart-78c17fd4-582d-4279-bad3-ab6f6fdbfb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449841500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.449841500
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.15614261
Short name T650
Test name
Test status
Simulation time 28193363 ps
CPU time 0.79 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:53 PM PDT 24
Peak memory 207104 kb
Host smart-aa67f4b1-7099-4b22-a6a5-c08df25f5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15614261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.15614261
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3143319672
Short name T1007
Test name
Test status
Simulation time 16687488494 ps
CPU time 55.28 seconds
Started Aug 03 05:26:58 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 249928 kb
Host smart-3ac35eb2-43ca-4b63-b14f-9c643fbf44f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143319672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3143319672
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2833666332
Short name T237
Test name
Test status
Simulation time 9519808243 ps
CPU time 65.85 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 250476 kb
Host smart-c6983877-f28a-4f6c-9ad3-24640e8ba750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833666332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2833666332
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2165215924
Short name T199
Test name
Test status
Simulation time 2700193212 ps
CPU time 38.23 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:27:33 PM PDT 24
Peak memory 225364 kb
Host smart-32f8bd2a-911c-413f-a483-ed1792420950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165215924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2165215924
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2315008414
Short name T769
Test name
Test status
Simulation time 527963639 ps
CPU time 4.25 seconds
Started Aug 03 05:26:56 PM PDT 24
Finished Aug 03 05:27:00 PM PDT 24
Peak memory 225292 kb
Host smart-0c33836b-6b62-4e85-9da7-5d587f3becf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315008414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2315008414
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1242605102
Short name T1031
Test name
Test status
Simulation time 32187323724 ps
CPU time 69.62 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 225184 kb
Host smart-545f1daf-4a2a-4abe-a880-e9a5014a4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242605102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1242605102
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3599176080
Short name T610
Test name
Test status
Simulation time 256044470 ps
CPU time 4.32 seconds
Started Aug 03 05:26:48 PM PDT 24
Finished Aug 03 05:26:52 PM PDT 24
Peak memory 233520 kb
Host smart-dcd2ad5b-880e-488c-8cdc-2349fd076d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599176080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3599176080
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2812378756
Short name T956
Test name
Test status
Simulation time 14510531194 ps
CPU time 35.67 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 233532 kb
Host smart-33b2a7ce-00e0-4063-9800-9672c9d96d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812378756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2812378756
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2697908420
Short name T690
Test name
Test status
Simulation time 1423102007 ps
CPU time 4.18 seconds
Started Aug 03 05:26:53 PM PDT 24
Finished Aug 03 05:26:57 PM PDT 24
Peak memory 225212 kb
Host smart-288103ef-dfff-4b81-b581-c7c5a0b2a821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697908420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2697908420
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1668196750
Short name T443
Test name
Test status
Simulation time 15277520593 ps
CPU time 12.14 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 233544 kb
Host smart-ff87a2a5-17bd-4ff1-8e38-4ccd756bd6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668196750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1668196750
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2856039643
Short name T612
Test name
Test status
Simulation time 63696407 ps
CPU time 3.62 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 223796 kb
Host smart-e2655e23-4314-4cd5-b43d-9d144fb9a0cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2856039643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2856039643
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2085566156
Short name T259
Test name
Test status
Simulation time 34598225571 ps
CPU time 162.45 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:29:38 PM PDT 24
Peak memory 267168 kb
Host smart-c9a16c30-8b03-4c23-b1ac-bcb6ff3d9c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085566156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2085566156
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1961109738
Short name T459
Test name
Test status
Simulation time 1611831357 ps
CPU time 10.21 seconds
Started Aug 03 05:26:53 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 217088 kb
Host smart-3d23ad64-8a57-4a4b-a8af-41c89935cf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961109738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1961109738
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2431826961
Short name T829
Test name
Test status
Simulation time 23660454599 ps
CPU time 16.49 seconds
Started Aug 03 05:26:51 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 217132 kb
Host smart-50e90bb7-cd8a-4e33-aba7-db08b5369b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431826961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2431826961
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4135689106
Short name T336
Test name
Test status
Simulation time 162817207 ps
CPU time 1.11 seconds
Started Aug 03 05:26:56 PM PDT 24
Finished Aug 03 05:26:57 PM PDT 24
Peak memory 207708 kb
Host smart-bebf5db7-6af3-4eca-a40c-365e69285d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135689106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4135689106
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1933306652
Short name T432
Test name
Test status
Simulation time 285486394 ps
CPU time 0.75 seconds
Started Aug 03 05:26:52 PM PDT 24
Finished Aug 03 05:26:53 PM PDT 24
Peak memory 206624 kb
Host smart-8742b1a6-58f1-4fdb-9f3e-c1e56d842fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933306652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1933306652
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3580415043
Short name T770
Test name
Test status
Simulation time 2288534331 ps
CPU time 9.86 seconds
Started Aug 03 05:26:56 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 233536 kb
Host smart-9e6f979b-ac27-46e2-b026-5765945f7afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580415043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3580415043
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.503217344
Short name T180
Test name
Test status
Simulation time 12948017 ps
CPU time 0.75 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 205324 kb
Host smart-cf5f0cb0-0cb2-4ea1-9406-d87843c5f4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503217344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.503217344
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2913485050
Short name T275
Test name
Test status
Simulation time 1034175184 ps
CPU time 9.66 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 233452 kb
Host smart-03a9a576-cb82-4625-a0ec-51f2a12ca155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913485050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2913485050
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1443519180
Short name T651
Test name
Test status
Simulation time 68417538 ps
CPU time 0.8 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 207044 kb
Host smart-99692c41-295c-4cb5-bf47-4f506c93a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443519180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1443519180
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3159371365
Short name T892
Test name
Test status
Simulation time 57160929 ps
CPU time 0.78 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 216492 kb
Host smart-aabe5bbe-6e4c-415b-91d0-4138f28ce018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159371365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3159371365
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.953894464
Short name T421
Test name
Test status
Simulation time 22935407876 ps
CPU time 220.6 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:30:41 PM PDT 24
Peak memory 252016 kb
Host smart-64a641a1-88bc-4e5d-8ad0-2c5a48a507ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953894464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.953894464
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3615153788
Short name T736
Test name
Test status
Simulation time 87196382098 ps
CPU time 222.84 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:30:43 PM PDT 24
Peak memory 250164 kb
Host smart-c28a7f6a-e2c4-4b78-b384-e083a2d4c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615153788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3615153788
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2637606659
Short name T550
Test name
Test status
Simulation time 1395183508 ps
CPU time 13.06 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:08 PM PDT 24
Peak memory 233492 kb
Host smart-20b01564-d2b3-4463-9e9b-189d6da17cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637606659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2637606659
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3023397274
Short name T894
Test name
Test status
Simulation time 16770146804 ps
CPU time 60.76 seconds
Started Aug 03 05:26:58 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 238752 kb
Host smart-98c6159a-1b64-44da-92fc-78538b8d929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023397274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3023397274
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3764595474
Short name T688
Test name
Test status
Simulation time 8692672661 ps
CPU time 8.62 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 233576 kb
Host smart-ce3cc562-c084-47bc-b912-9084bb443708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764595474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3764595474
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3272231366
Short name T381
Test name
Test status
Simulation time 34170719 ps
CPU time 2.32 seconds
Started Aug 03 05:26:58 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 233008 kb
Host smart-892afa30-aa37-4a62-b215-400f34b83491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272231366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3272231366
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1432974375
Short name T251
Test name
Test status
Simulation time 737403821 ps
CPU time 6.38 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 225328 kb
Host smart-36662b5c-672d-4d7e-8b81-9cfeea1f0115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432974375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1432974375
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1908874144
Short name T267
Test name
Test status
Simulation time 521422478 ps
CPU time 7.07 seconds
Started Aug 03 05:26:53 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 233404 kb
Host smart-2cf69c1b-66a7-43aa-8bed-6d9f0b15aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908874144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1908874144
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.116185382
Short name T874
Test name
Test status
Simulation time 5903004486 ps
CPU time 12.26 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 223672 kb
Host smart-285e2726-fc1b-45e1-a66b-995c2b0f3abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116185382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.116185382
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1555196901
Short name T930
Test name
Test status
Simulation time 18583684628 ps
CPU time 165.39 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:29:39 PM PDT 24
Peak memory 249136 kb
Host smart-0ba9de54-8142-4da3-872d-1704ceb4e1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555196901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1555196901
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1887450062
Short name T4
Test name
Test status
Simulation time 32123558978 ps
CPU time 43.32 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 217176 kb
Host smart-fc7babef-11d9-46a0-b472-869aca3af497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887450062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1887450062
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3638491655
Short name T348
Test name
Test status
Simulation time 30652106767 ps
CPU time 12.64 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 216980 kb
Host smart-0624bf7e-a115-4d3c-b780-4665b2368f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638491655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3638491655
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2885992665
Short name T1021
Test name
Test status
Simulation time 15273362 ps
CPU time 0.84 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:26:55 PM PDT 24
Peak memory 206572 kb
Host smart-3524f8c7-c8fb-4bbb-81aa-a5742046c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885992665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2885992665
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3859465259
Short name T655
Test name
Test status
Simulation time 147430148 ps
CPU time 0.71 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:56 PM PDT 24
Peak memory 206600 kb
Host smart-af7efae7-ea81-445d-85c1-0e8c9c382777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859465259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3859465259
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2276380597
Short name T144
Test name
Test status
Simulation time 7923131267 ps
CPU time 10.1 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 233540 kb
Host smart-77e3b08b-c34a-48f2-88a1-2fde4bcb48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276380597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2276380597
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.990700678
Short name T848
Test name
Test status
Simulation time 36591955 ps
CPU time 0.69 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 205324 kb
Host smart-7a36dd16-46b0-4a93-a5cc-52be46478131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990700678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.990700678
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.766010484
Short name T729
Test name
Test status
Simulation time 3669179045 ps
CPU time 7.66 seconds
Started Aug 03 05:26:59 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 225268 kb
Host smart-d8a21165-c416-4bad-aa13-0a5fa37011bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766010484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.766010484
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3861788927
Short name T376
Test name
Test status
Simulation time 21544210 ps
CPU time 0.82 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:27:02 PM PDT 24
Peak memory 206988 kb
Host smart-0d9f3fa4-3dcf-47ba-b708-aa4c16881165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861788927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3861788927
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2017201364
Short name T218
Test name
Test status
Simulation time 98721325736 ps
CPU time 331.62 seconds
Started Aug 03 05:26:59 PM PDT 24
Finished Aug 03 05:32:31 PM PDT 24
Peak memory 253664 kb
Host smart-eb908002-aba7-42b3-a49d-6afa8e1ae432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017201364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2017201364
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2286633044
Short name T955
Test name
Test status
Simulation time 44676595749 ps
CPU time 246.51 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:31:07 PM PDT 24
Peak memory 263748 kb
Host smart-ba1003c1-a8ae-4f0b-850a-077008be88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286633044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2286633044
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.15067610
Short name T299
Test name
Test status
Simulation time 1184429261 ps
CPU time 29.63 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:42 PM PDT 24
Peak memory 249956 kb
Host smart-52d0dba9-3e05-425d-afea-76aaa2a414a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15067610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.15067610
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3607195309
Short name T779
Test name
Test status
Simulation time 473188216 ps
CPU time 4.48 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 225176 kb
Host smart-f8ae9e73-65c3-4fe0-904a-fb1466fc9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607195309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3607195309
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1614671165
Short name T100
Test name
Test status
Simulation time 15632051049 ps
CPU time 88.25 seconds
Started Aug 03 05:26:59 PM PDT 24
Finished Aug 03 05:28:28 PM PDT 24
Peak memory 251812 kb
Host smart-c5ed5525-67d3-4b78-b20f-8555e4980d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614671165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1614671165
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2496962332
Short name T8
Test name
Test status
Simulation time 1276439296 ps
CPU time 8.27 seconds
Started Aug 03 05:27:03 PM PDT 24
Finished Aug 03 05:27:12 PM PDT 24
Peak memory 233488 kb
Host smart-cfa7aa7c-b444-4325-b058-1ba9bacbf399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496962332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2496962332
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.404601217
Short name T224
Test name
Test status
Simulation time 42557800864 ps
CPU time 115.12 seconds
Started Aug 03 05:26:59 PM PDT 24
Finished Aug 03 05:28:55 PM PDT 24
Peak memory 233612 kb
Host smart-7886b0b6-a314-4013-acc0-ae78e1d84a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404601217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.404601217
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3009860447
Short name T248
Test name
Test status
Simulation time 10724381102 ps
CPU time 10.15 seconds
Started Aug 03 05:27:03 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 233552 kb
Host smart-07066088-9af7-439c-b3df-a6c8d2b2b94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009860447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3009860447
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3057263706
Short name T499
Test name
Test status
Simulation time 1244253165 ps
CPU time 3.39 seconds
Started Aug 03 05:27:04 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 233468 kb
Host smart-f20bf1cb-24c0-48ea-8901-505b4a1da47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057263706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3057263706
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3082708065
Short name T358
Test name
Test status
Simulation time 627091733 ps
CPU time 3.46 seconds
Started Aug 03 05:27:02 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 219868 kb
Host smart-35c37595-1bb7-4f24-b5bc-e20a7bfd49ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3082708065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3082708065
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1405115812
Short name T527
Test name
Test status
Simulation time 9137163267 ps
CPU time 91.69 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:28:33 PM PDT 24
Peak memory 251984 kb
Host smart-13caf3d7-9330-4a66-91d3-d1f1f365460d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405115812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1405115812
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3131323651
Short name T332
Test name
Test status
Simulation time 30075319675 ps
CPU time 40.57 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 217104 kb
Host smart-d0efaf12-a062-4168-b001-27397a0385f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131323651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3131323651
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.684433150
Short name T908
Test name
Test status
Simulation time 19163412495 ps
CPU time 12.89 seconds
Started Aug 03 05:26:54 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 217116 kb
Host smart-510728d1-4046-4076-bf13-6e0030f3ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684433150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.684433150
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3604427840
Short name T869
Test name
Test status
Simulation time 107398910 ps
CPU time 1.73 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 216896 kb
Host smart-c7e24907-b238-46fa-92aa-fc3400e8fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604427840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3604427840
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1985742740
Short name T723
Test name
Test status
Simulation time 685476623 ps
CPU time 1.17 seconds
Started Aug 03 05:26:55 PM PDT 24
Finished Aug 03 05:26:57 PM PDT 24
Peak memory 207620 kb
Host smart-3c6a1eb5-a811-4a77-b236-a601d5cbdec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985742740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1985742740
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3552021671
Short name T181
Test name
Test status
Simulation time 5775124375 ps
CPU time 22.39 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 251012 kb
Host smart-a2f27e39-767a-472f-92c0-70af46b6d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552021671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3552021671
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2341369950
Short name T475
Test name
Test status
Simulation time 48616060 ps
CPU time 0.74 seconds
Started Aug 03 05:27:03 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 205800 kb
Host smart-59023bfa-74b7-48d6-baab-2027887498a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341369950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2341369950
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2892665787
Short name T291
Test name
Test status
Simulation time 74552235 ps
CPU time 2.52 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:16 PM PDT 24
Peak memory 233504 kb
Host smart-108560f5-9d75-4d7e-b1b0-4354d292dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892665787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2892665787
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1490913280
Short name T400
Test name
Test status
Simulation time 23846909 ps
CPU time 0.8 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 207100 kb
Host smart-747c6347-b0b6-4946-9000-aee11377dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490913280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1490913280
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.123473645
Short name T867
Test name
Test status
Simulation time 6024255338 ps
CPU time 12.72 seconds
Started Aug 03 05:27:02 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 241712 kb
Host smart-a7796175-9fc6-4fb4-97e8-3ffab13e8921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123473645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.123473645
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2743666653
Short name T813
Test name
Test status
Simulation time 56653330312 ps
CPU time 117.71 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:28:58 PM PDT 24
Peak memory 249988 kb
Host smart-2ff7874f-2d47-4784-9032-68cd44938eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743666653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2743666653
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2418047780
Short name T302
Test name
Test status
Simulation time 4925575367 ps
CPU time 55.51 seconds
Started Aug 03 05:27:03 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 249936 kb
Host smart-a36b26c0-06f8-491c-9699-f56dcf069db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418047780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2418047780
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.603654966
Short name T460
Test name
Test status
Simulation time 1510088526 ps
CPU time 20.16 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 225276 kb
Host smart-9d1bf383-db7b-47bb-af5b-ad189a7ae5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603654966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.603654966
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3439263781
Short name T215
Test name
Test status
Simulation time 3108497824 ps
CPU time 18.15 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:18 PM PDT 24
Peak memory 233524 kb
Host smart-0d099727-618c-4200-8b8f-27922447c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439263781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3439263781
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3954382773
Short name T284
Test name
Test status
Simulation time 4773770757 ps
CPU time 4.95 seconds
Started Aug 03 05:27:02 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 225288 kb
Host smart-b49ef8c2-f08b-47b0-b174-f0e497920502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954382773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3954382773
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2090995710
Short name T664
Test name
Test status
Simulation time 427337279 ps
CPU time 7.54 seconds
Started Aug 03 05:27:02 PM PDT 24
Finished Aug 03 05:27:09 PM PDT 24
Peak memory 233468 kb
Host smart-815224c9-b261-44de-a0e3-4dc4e97078af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090995710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2090995710
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2405631255
Short name T386
Test name
Test status
Simulation time 974571272 ps
CPU time 12.46 seconds
Started Aug 03 05:27:01 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 221156 kb
Host smart-94fad8fc-3f7c-4113-83b7-c15bf2adeb13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2405631255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2405631255
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2813331805
Short name T452
Test name
Test status
Simulation time 7177071366 ps
CPU time 26.22 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:39 PM PDT 24
Peak memory 233620 kb
Host smart-086f61c6-f910-479b-a4ac-8c8a4031f8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813331805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2813331805
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.385800530
Short name T457
Test name
Test status
Simulation time 441722355 ps
CPU time 5.07 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 217008 kb
Host smart-6e64371f-6daa-4cfb-9180-0332ff0990b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385800530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.385800530
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4272147489
Short name T905
Test name
Test status
Simulation time 16601314 ps
CPU time 0.71 seconds
Started Aug 03 05:26:59 PM PDT 24
Finished Aug 03 05:27:00 PM PDT 24
Peak memory 206212 kb
Host smart-b53226bf-12e0-4610-a33c-b0feb94032e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272147489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4272147489
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2324032487
Short name T659
Test name
Test status
Simulation time 567881403 ps
CPU time 3.93 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:04 PM PDT 24
Peak memory 216952 kb
Host smart-ce91c8b2-2ce8-4f2b-b0d7-8bb285657ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324032487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2324032487
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2436667069
Short name T987
Test name
Test status
Simulation time 231804330 ps
CPU time 0.88 seconds
Started Aug 03 05:27:02 PM PDT 24
Finished Aug 03 05:27:03 PM PDT 24
Peak memory 206508 kb
Host smart-1b6d7d73-4bce-4645-9fa1-903fdfcabd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436667069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2436667069
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2405575676
Short name T492
Test name
Test status
Simulation time 571222667 ps
CPU time 6.49 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:19 PM PDT 24
Peak memory 225268 kb
Host smart-9ee918d0-0425-4861-8d21-0e71589ae52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405575676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2405575676
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4035976729
Short name T617
Test name
Test status
Simulation time 13956676 ps
CPU time 0.74 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 206224 kb
Host smart-00f330e6-1cb4-4975-b1d9-663b4d582b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035976729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4035976729
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4260981284
Short name T787
Test name
Test status
Simulation time 3498441899 ps
CPU time 18.54 seconds
Started Aug 03 05:27:07 PM PDT 24
Finished Aug 03 05:27:25 PM PDT 24
Peak memory 233544 kb
Host smart-2e43eba7-8fa6-44c5-9070-5eb3c410bae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260981284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4260981284
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1591016410
Short name T523
Test name
Test status
Simulation time 17897783 ps
CPU time 0.83 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 207076 kb
Host smart-a73119fe-4266-4446-aad0-c9b954383ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591016410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1591016410
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2274544984
Short name T913
Test name
Test status
Simulation time 21817097037 ps
CPU time 122.48 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:29:16 PM PDT 24
Peak memory 254188 kb
Host smart-1c6f1d3f-ab85-43c0-8e0a-f42095a44419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274544984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2274544984
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.204167359
Short name T233
Test name
Test status
Simulation time 26265195345 ps
CPU time 297.89 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:32:03 PM PDT 24
Peak memory 273440 kb
Host smart-12ad7891-c09a-4087-b9e2-deb5d9548911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204167359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.204167359
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1892526062
Short name T51
Test name
Test status
Simulation time 6005328305 ps
CPU time 73.3 seconds
Started Aug 03 05:27:07 PM PDT 24
Finished Aug 03 05:28:21 PM PDT 24
Peak memory 257748 kb
Host smart-3254f140-34d8-4ee8-9cf0-d3a258ed3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892526062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1892526062
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1330029444
Short name T323
Test name
Test status
Simulation time 594040583 ps
CPU time 11.22 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 233496 kb
Host smart-4f1469a1-e97f-4ed6-b7e5-71fbf5bc91f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330029444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1330029444
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.89952565
Short name T482
Test name
Test status
Simulation time 45480302 ps
CPU time 0.88 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 216748 kb
Host smart-b9d3a61a-7cb1-4c42-bde1-060224af9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89952565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.89952565
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3238117036
Short name T77
Test name
Test status
Simulation time 2428211576 ps
CPU time 25.09 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 233580 kb
Host smart-62df1bf5-fe1e-46e7-bfb0-67e88e6ab5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238117036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3238117036
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1459618920
Short name T885
Test name
Test status
Simulation time 53061976957 ps
CPU time 81.71 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:28:28 PM PDT 24
Peak memory 250464 kb
Host smart-ca5a2db3-febd-4dd9-b9a8-a93f2f8fd7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459618920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1459618920
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.527356008
Short name T963
Test name
Test status
Simulation time 1160369758 ps
CPU time 6.22 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:12 PM PDT 24
Peak memory 225240 kb
Host smart-382fb67b-ae96-4d4a-86e3-edf2d1d54c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527356008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.527356008
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1112447334
Short name T78
Test name
Test status
Simulation time 605349179 ps
CPU time 3.75 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:10 PM PDT 24
Peak memory 233464 kb
Host smart-0db59829-537d-446e-addc-0e8a776e9563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112447334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1112447334
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.142841012
Short name T678
Test name
Test status
Simulation time 261603699 ps
CPU time 5.57 seconds
Started Aug 03 05:27:08 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 223392 kb
Host smart-6ec1e3c1-95e4-4076-bbd7-5df4738241c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=142841012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.142841012
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1544362480
Short name T708
Test name
Test status
Simulation time 39957316 ps
CPU time 0.85 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:07 PM PDT 24
Peak memory 206400 kb
Host smart-8295db32-04ad-46ba-8bec-a78085dca589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544362480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1544362480
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3028273281
Short name T329
Test name
Test status
Simulation time 3894937478 ps
CPU time 28.03 seconds
Started Aug 03 05:27:08 PM PDT 24
Finished Aug 03 05:27:36 PM PDT 24
Peak memory 221212 kb
Host smart-a76beee2-5661-4a61-be32-56b9565177bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028273281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3028273281
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.899250907
Short name T759
Test name
Test status
Simulation time 1315111367 ps
CPU time 6.71 seconds
Started Aug 03 05:27:00 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 216932 kb
Host smart-f0ec6144-a36f-4377-85a7-dd6be7cd7bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899250907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.899250907
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.554051578
Short name T967
Test name
Test status
Simulation time 48132022 ps
CPU time 1.72 seconds
Started Aug 03 05:27:08 PM PDT 24
Finished Aug 03 05:27:09 PM PDT 24
Peak memory 216928 kb
Host smart-6f4457bf-3a25-4750-a415-8b0e82dd1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554051578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.554051578
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3530807911
Short name T639
Test name
Test status
Simulation time 37283440 ps
CPU time 0.8 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:11 PM PDT 24
Peak memory 206540 kb
Host smart-290c9873-af6b-4a57-8ae1-25563d026278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530807911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3530807911
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4233606995
Short name T696
Test name
Test status
Simulation time 41037005 ps
CPU time 2.32 seconds
Started Aug 03 05:27:08 PM PDT 24
Finished Aug 03 05:27:10 PM PDT 24
Peak memory 224844 kb
Host smart-eaa42ad1-af01-4405-93a8-136a1492ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233606995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4233606995
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.243913987
Short name T923
Test name
Test status
Simulation time 23557125 ps
CPU time 0.7 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 204836 kb
Host smart-75a1934d-04ba-4ad1-bc51-ab2409e20c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243913987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.243913987
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2813037375
Short name T605
Test name
Test status
Simulation time 12341633451 ps
CPU time 11.53 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 233488 kb
Host smart-79bea867-ebf0-4dd4-953e-c81fe6dd6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813037375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2813037375
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.745801268
Short name T385
Test name
Test status
Simulation time 18811455 ps
CPU time 0.81 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 207096 kb
Host smart-927f316a-348b-4f66-8953-ea0d87ee6b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745801268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.745801268
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2036534755
Short name T183
Test name
Test status
Simulation time 160349212378 ps
CPU time 248.55 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:31:19 PM PDT 24
Peak memory 260724 kb
Host smart-80859c44-0347-4fc0-bf75-7e932feb427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036534755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2036534755
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1196826045
Short name T208
Test name
Test status
Simulation time 69995681418 ps
CPU time 162.17 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:29:55 PM PDT 24
Peak memory 254200 kb
Host smart-b1e5aeb9-9c32-4696-b527-2e01f08d5998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196826045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1196826045
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3143837644
Short name T32
Test name
Test status
Simulation time 54037674925 ps
CPU time 109.57 seconds
Started Aug 03 05:27:14 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 249948 kb
Host smart-34bdc317-3f92-4e1c-ac0b-0b72deb52161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143837644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3143837644
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1740658529
Short name T624
Test name
Test status
Simulation time 655434920 ps
CPU time 7.54 seconds
Started Aug 03 05:27:07 PM PDT 24
Finished Aug 03 05:27:15 PM PDT 24
Peak memory 238152 kb
Host smart-ebca94cc-fe9f-4230-9297-8821621ee072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740658529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1740658529
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2436042112
Short name T857
Test name
Test status
Simulation time 34102487983 ps
CPU time 141.6 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:29:27 PM PDT 24
Peak memory 256572 kb
Host smart-7e34224f-36cb-4902-9561-8e3c7e8cdc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436042112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2436042112
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.737817819
Short name T268
Test name
Test status
Simulation time 1156712868 ps
CPU time 5.03 seconds
Started Aug 03 05:27:09 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 233496 kb
Host smart-53ce901e-957f-4b38-b583-b41e3276d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737817819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.737817819
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2367581313
Short name T827
Test name
Test status
Simulation time 92614935 ps
CPU time 2.47 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:09 PM PDT 24
Peak memory 233136 kb
Host smart-a28509b8-fce0-47a9-a198-a88bb0a4f8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367581313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2367581313
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3978257982
Short name T526
Test name
Test status
Simulation time 9361917788 ps
CPU time 14.86 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:25 PM PDT 24
Peak memory 225316 kb
Host smart-889f47e2-ddc2-4e00-ac55-75a612069f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978257982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3978257982
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4189902756
Short name T551
Test name
Test status
Simulation time 8755938895 ps
CPU time 15.17 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 233552 kb
Host smart-d0a68667-9cab-4908-9d43-1244c979a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189902756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4189902756
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4289970742
Short name T370
Test name
Test status
Simulation time 2220556778 ps
CPU time 11.26 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 222744 kb
Host smart-ba0afc39-a25f-4a0d-b57e-9d677a0bae63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289970742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4289970742
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1579358021
Short name T972
Test name
Test status
Simulation time 27118675109 ps
CPU time 61.2 seconds
Started Aug 03 05:27:14 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 250164 kb
Host smart-abf92248-98ce-4146-8c91-b0321bf586c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579358021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1579358021
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1686028612
Short name T466
Test name
Test status
Simulation time 645205988 ps
CPU time 5.55 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:16 PM PDT 24
Peak memory 217180 kb
Host smart-c161696b-36c1-4274-b299-d8c5e3e90762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686028612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1686028612
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4089111259
Short name T629
Test name
Test status
Simulation time 1743231613 ps
CPU time 6.42 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:11 PM PDT 24
Peak memory 216976 kb
Host smart-e7ea7e47-e87b-445b-811c-54963b75a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089111259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4089111259
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.99111902
Short name T384
Test name
Test status
Simulation time 70314396 ps
CPU time 1.24 seconds
Started Aug 03 05:27:08 PM PDT 24
Finished Aug 03 05:27:10 PM PDT 24
Peak memory 208748 kb
Host smart-1b91864f-bf43-426a-b3e1-843d86a5e1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99111902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.99111902
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.944954186
Short name T665
Test name
Test status
Simulation time 190749369 ps
CPU time 0.76 seconds
Started Aug 03 05:27:05 PM PDT 24
Finished Aug 03 05:27:06 PM PDT 24
Peak memory 206644 kb
Host smart-c7214bc2-d4a1-4aac-ab35-9c6ccfb0f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944954186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.944954186
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4010221204
Short name T890
Test name
Test status
Simulation time 691660357 ps
CPU time 4.74 seconds
Started Aug 03 05:27:06 PM PDT 24
Finished Aug 03 05:27:11 PM PDT 24
Peak memory 233512 kb
Host smart-686db4f0-8538-49c9-baee-511bf41beaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010221204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4010221204
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2599981987
Short name T815
Test name
Test status
Simulation time 37934696 ps
CPU time 0.73 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 205320 kb
Host smart-9b671619-f38d-4ffc-844c-5e3e863b4fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599981987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2599981987
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.15035630
Short name T98
Test name
Test status
Simulation time 137422606 ps
CPU time 2.63 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 225292 kb
Host smart-5e57f3fd-ed55-4fbd-b5b9-6bb709e3ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15035630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.15035630
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.881589496
Short name T981
Test name
Test status
Simulation time 15107520 ps
CPU time 0.81 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 207068 kb
Host smart-ed923511-bbc1-42bf-aaeb-644e3e758e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881589496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.881589496
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.388779339
Short name T924
Test name
Test status
Simulation time 97519408653 ps
CPU time 233.3 seconds
Started Aug 03 05:27:11 PM PDT 24
Finished Aug 03 05:31:04 PM PDT 24
Peak memory 267192 kb
Host smart-c0d337e5-0705-4dae-b72f-af2a85449571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388779339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.388779339
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1427696258
Short name T230
Test name
Test status
Simulation time 4683260446 ps
CPU time 65.08 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:28:18 PM PDT 24
Peak memory 254856 kb
Host smart-6931faa9-894d-4b8a-8a71-895b7bfb8dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427696258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1427696258
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4152837080
Short name T312
Test name
Test status
Simulation time 6865871152 ps
CPU time 124.93 seconds
Started Aug 03 05:27:15 PM PDT 24
Finished Aug 03 05:29:20 PM PDT 24
Peak memory 255076 kb
Host smart-84cef5f0-7add-4bbe-b296-046d47ecbc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152837080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4152837080
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1572423782
Short name T849
Test name
Test status
Simulation time 2591609294 ps
CPU time 6.37 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 233524 kb
Host smart-a27fdb2b-cffd-4bc3-acf0-48552115baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572423782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1572423782
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.184461925
Short name T761
Test name
Test status
Simulation time 84300979745 ps
CPU time 156.96 seconds
Started Aug 03 05:27:11 PM PDT 24
Finished Aug 03 05:29:48 PM PDT 24
Peak memory 249840 kb
Host smart-a1683571-db90-4fb2-be7f-0c7afda1da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184461925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.184461925
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3906633048
Short name T575
Test name
Test status
Simulation time 3071017248 ps
CPU time 11.7 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:24 PM PDT 24
Peak memory 225340 kb
Host smart-30481412-0846-4006-9a64-0139156214f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906633048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3906633048
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1174317113
Short name T686
Test name
Test status
Simulation time 2735466650 ps
CPU time 45.95 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 235504 kb
Host smart-a67690f7-5a03-4d6f-83a6-06ed3508ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174317113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1174317113
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.807200331
Short name T693
Test name
Test status
Simulation time 30118490 ps
CPU time 2.38 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 233048 kb
Host smart-18599385-cabf-4b26-a0d9-2b84cf35e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807200331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.807200331
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.683839194
Short name T951
Test name
Test status
Simulation time 2813472708 ps
CPU time 5.54 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:18 PM PDT 24
Peak memory 225316 kb
Host smart-ab19632f-3203-47c8-b468-f3076902278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683839194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.683839194
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.123251192
Short name T442
Test name
Test status
Simulation time 10114014703 ps
CPU time 4.52 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 220660 kb
Host smart-15a2b9d5-5968-4416-af74-c9ad81013b96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123251192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.123251192
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.760817186
Short name T308
Test name
Test status
Simulation time 34722922095 ps
CPU time 338.87 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:32:52 PM PDT 24
Peak memory 254968 kb
Host smart-7c41b534-167c-4dca-83c3-f38facde52db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760817186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.760817186
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1968224303
Short name T559
Test name
Test status
Simulation time 42873005413 ps
CPU time 23.84 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:40 PM PDT 24
Peak memory 217092 kb
Host smart-d3419889-bfa8-4e8f-8a0e-33be9272fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968224303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1968224303
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3967505145
Short name T545
Test name
Test status
Simulation time 424757953 ps
CPU time 4.1 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 216960 kb
Host smart-346bd7c5-785a-4a80-ac1a-79dee1b25402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967505145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3967505145
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.442725029
Short name T1010
Test name
Test status
Simulation time 246765117 ps
CPU time 1.01 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:17 PM PDT 24
Peak memory 207776 kb
Host smart-d0e9f4b3-b9e2-4695-abca-c46665bc8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442725029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.442725029
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2802222937
Short name T497
Test name
Test status
Simulation time 18084480 ps
CPU time 0.77 seconds
Started Aug 03 05:27:13 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 206588 kb
Host smart-85701680-cacf-4668-b290-3dcd793ec6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802222937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2802222937
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.804164731
Short name T63
Test name
Test status
Simulation time 83297681 ps
CPU time 2.76 seconds
Started Aug 03 05:27:11 PM PDT 24
Finished Aug 03 05:27:14 PM PDT 24
Peak memory 233492 kb
Host smart-8058d324-010e-4a5f-b275-7ba38a57838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804164731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.804164731
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2499975098
Short name T390
Test name
Test status
Simulation time 13906065 ps
CPU time 0.7 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:25:55 PM PDT 24
Peak memory 205300 kb
Host smart-617881f0-8a4a-4e71-9379-442cc649b43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499975098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
499975098
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3640874135
Short name T717
Test name
Test status
Simulation time 61500499 ps
CPU time 2.12 seconds
Started Aug 03 05:25:47 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 225264 kb
Host smart-db07cde4-a326-4953-be47-660db8804325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640874135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3640874135
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1583062839
Short name T883
Test name
Test status
Simulation time 15535752 ps
CPU time 0.76 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 207076 kb
Host smart-22b4e813-05d4-48c5-b0e0-9fe20e759e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583062839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1583062839
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.165584156
Short name T657
Test name
Test status
Simulation time 29236802245 ps
CPU time 127.34 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:28:01 PM PDT 24
Peak memory 249948 kb
Host smart-4fedcb64-2461-469b-a0e3-20ebea99e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165584156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.165584156
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3942072801
Short name T444
Test name
Test status
Simulation time 14209806657 ps
CPU time 71.11 seconds
Started Aug 03 05:26:10 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 251976 kb
Host smart-10250523-680f-4e62-9083-a85d6f3607bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942072801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3942072801
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4294715349
Short name T502
Test name
Test status
Simulation time 569413150 ps
CPU time 13.64 seconds
Started Aug 03 05:25:59 PM PDT 24
Finished Aug 03 05:26:13 PM PDT 24
Peak memory 239292 kb
Host smart-c87dcda0-df94-45e1-8cfd-210f18c36cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294715349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4294715349
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.949793168
Short name T184
Test name
Test status
Simulation time 221197407 ps
CPU time 5.42 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:25:55 PM PDT 24
Peak memory 237432 kb
Host smart-90d9d033-49bc-49e6-a9e0-72e4f26c8919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949793168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.949793168
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.799229541
Short name T474
Test name
Test status
Simulation time 1848205566 ps
CPU time 22.6 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:26:12 PM PDT 24
Peak memory 225284 kb
Host smart-44ae82a2-611e-4596-933e-08c2ba49691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799229541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
799229541
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3370869848
Short name T419
Test name
Test status
Simulation time 1185667150 ps
CPU time 4.14 seconds
Started Aug 03 05:25:45 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 233508 kb
Host smart-1113396c-1610-4cfe-a0be-b9ad4f5dc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370869848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3370869848
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2609913592
Short name T515
Test name
Test status
Simulation time 2727969851 ps
CPU time 36.11 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 233492 kb
Host smart-138438c0-26ed-4d3a-92fd-9d6a20d7a2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609913592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2609913592
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2802134661
Short name T653
Test name
Test status
Simulation time 51574416 ps
CPU time 1.1 seconds
Started Aug 03 05:25:48 PM PDT 24
Finished Aug 03 05:25:50 PM PDT 24
Peak memory 217204 kb
Host smart-036dafe6-c1e5-434d-b958-f1ad2f74c793
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802134661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2802134661
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2537412788
Short name T341
Test name
Test status
Simulation time 110658538 ps
CPU time 2.55 seconds
Started Aug 03 05:25:59 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 233060 kb
Host smart-f2803e3f-587c-41fb-888f-9fccdc861322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537412788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2537412788
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1422645021
Short name T620
Test name
Test status
Simulation time 3563632194 ps
CPU time 6.81 seconds
Started Aug 03 05:25:47 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 225332 kb
Host smart-ad7daf0d-dbe0-4b43-9157-248420bec4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422645021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1422645021
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.150987203
Short name T992
Test name
Test status
Simulation time 355213439 ps
CPU time 4.39 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 223620 kb
Host smart-4d18b500-8c76-4cf6-94c2-6cf47042f00b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=150987203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.150987203
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2309491342
Short name T71
Test name
Test status
Simulation time 214428775 ps
CPU time 1.18 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 236624 kb
Host smart-6fe684da-aac5-449c-8284-5d7bd9ac2572
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309491342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2309491342
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.353772481
Short name T171
Test name
Test status
Simulation time 60385028 ps
CPU time 1.09 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 207604 kb
Host smart-2d2cdcc5-b2aa-4ceb-a97a-2ebcf4128fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353772481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.353772481
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3481957906
Short name T501
Test name
Test status
Simulation time 1252436290 ps
CPU time 18.35 seconds
Started Aug 03 05:25:48 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 217020 kb
Host smart-c8f0b2fd-231b-465f-8c12-03235b521032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481957906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3481957906
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.53322269
Short name T338
Test name
Test status
Simulation time 4952847020 ps
CPU time 7.76 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 217080 kb
Host smart-9c53a50a-94ea-4d51-b38d-8daa28761540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53322269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.53322269
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1641554734
Short name T918
Test name
Test status
Simulation time 162495193 ps
CPU time 5.83 seconds
Started Aug 03 05:25:46 PM PDT 24
Finished Aug 03 05:25:52 PM PDT 24
Peak memory 217012 kb
Host smart-e46d4389-d80d-4581-a630-c648ab365a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641554734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1641554734
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2947357208
Short name T667
Test name
Test status
Simulation time 104407331 ps
CPU time 0.98 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 207020 kb
Host smart-bb5fd3e2-a7f8-44f3-9071-5eb9a376d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947357208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2947357208
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1301516178
Short name T914
Test name
Test status
Simulation time 6166488016 ps
CPU time 11.1 seconds
Started Aug 03 05:25:45 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 225380 kb
Host smart-c1c4fda6-c454-4edd-94a5-f20824422b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301516178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1301516178
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.624871022
Short name T862
Test name
Test status
Simulation time 26394741 ps
CPU time 0.71 seconds
Started Aug 03 05:27:17 PM PDT 24
Finished Aug 03 05:27:18 PM PDT 24
Peak memory 205872 kb
Host smart-393180d1-47cc-4896-b0e7-256b175b334f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624871022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.624871022
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1822736659
Short name T801
Test name
Test status
Simulation time 3081463738 ps
CPU time 11.41 seconds
Started Aug 03 05:27:17 PM PDT 24
Finished Aug 03 05:27:29 PM PDT 24
Peak memory 225292 kb
Host smart-a52aa0aa-3848-4fd4-87d5-b264c099fbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822736659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1822736659
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.61574794
Short name T1019
Test name
Test status
Simulation time 15122629 ps
CPU time 0.76 seconds
Started Aug 03 05:27:11 PM PDT 24
Finished Aug 03 05:27:12 PM PDT 24
Peak memory 207080 kb
Host smart-0143e7be-dfc7-4caa-9ba4-b3a0188b6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61574794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.61574794
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.337772433
Short name T279
Test name
Test status
Simulation time 14480679247 ps
CPU time 36.65 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:55 PM PDT 24
Peak memory 237600 kb
Host smart-f3488cb3-6430-499b-b34d-f89aaaf3ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337772433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.337772433
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.870730851
Short name T314
Test name
Test status
Simulation time 10587424695 ps
CPU time 171.7 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:30:08 PM PDT 24
Peak memory 272460 kb
Host smart-9df9e276-52de-497c-8f06-dab3239da763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870730851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.870730851
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1461430635
Short name T555
Test name
Test status
Simulation time 115304933807 ps
CPU time 86.75 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:28:43 PM PDT 24
Peak memory 249992 kb
Host smart-1e2e8601-c581-43d3-969b-a62f26e02361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461430635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1461430635
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.318640614
Short name T355
Test name
Test status
Simulation time 220673070 ps
CPU time 3.12 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 225280 kb
Host smart-fdf0eb5f-3337-4484-b1cc-1db4ee792447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318640614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.318640614
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1495779261
Short name T666
Test name
Test status
Simulation time 1461504602 ps
CPU time 26.33 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:42 PM PDT 24
Peak memory 252452 kb
Host smart-57c6b1b4-8e9a-4076-84a5-f5daea5e64e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495779261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1495779261
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3059704805
Short name T226
Test name
Test status
Simulation time 97882392 ps
CPU time 3.92 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 233516 kb
Host smart-befaacbd-9674-46c1-9c26-586f8b4f55b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059704805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3059704805
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2506802357
Short name T177
Test name
Test status
Simulation time 2583285160 ps
CPU time 36.8 seconds
Started Aug 03 05:27:20 PM PDT 24
Finished Aug 03 05:27:57 PM PDT 24
Peak memory 225312 kb
Host smart-771f04ae-e541-477e-97c5-8e79d432d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506802357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2506802357
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1637613
Short name T315
Test name
Test status
Simulation time 2153321349 ps
CPU time 10.15 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:29 PM PDT 24
Peak memory 233388 kb
Host smart-02c349e9-bb1e-4a2a-b0e2-8264cb660450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1637613
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3424667645
Short name T1033
Test name
Test status
Simulation time 4188970052 ps
CPU time 9.9 seconds
Started Aug 03 05:27:11 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 241356 kb
Host smart-f3cd855d-2f8d-446e-b84a-e859c18423a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424667645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3424667645
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4065003713
Short name T445
Test name
Test status
Simulation time 892738239 ps
CPU time 12.3 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:31 PM PDT 24
Peak memory 222732 kb
Host smart-372572a2-184c-47d0-b86b-948a978115f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4065003713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4065003713
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.396389120
Short name T328
Test name
Test status
Simulation time 23423194269 ps
CPU time 15.36 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 217104 kb
Host smart-3a5ba942-2c99-4bd7-bf64-84659284dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396389120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.396389120
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2254222094
Short name T969
Test name
Test status
Simulation time 9140229063 ps
CPU time 7.07 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:19 PM PDT 24
Peak memory 217024 kb
Host smart-9edc1312-10fc-4ce3-8d15-c3f29dff75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254222094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2254222094
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1060956993
Short name T1000
Test name
Test status
Simulation time 17056817 ps
CPU time 0.85 seconds
Started Aug 03 05:27:10 PM PDT 24
Finished Aug 03 05:27:11 PM PDT 24
Peak memory 207392 kb
Host smart-5fac5870-af16-4cbd-920e-8288be27681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060956993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1060956993
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4202261274
Short name T571
Test name
Test status
Simulation time 107517046 ps
CPU time 0.79 seconds
Started Aug 03 05:27:12 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 206076 kb
Host smart-40ce3db8-c6ee-4d2e-8346-9f310a10e55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202261274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4202261274
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.155759287
Short name T109
Test name
Test status
Simulation time 6616240917 ps
CPU time 6.2 seconds
Started Aug 03 05:27:17 PM PDT 24
Finished Aug 03 05:27:24 PM PDT 24
Peak memory 225300 kb
Host smart-dfae89b5-4e6c-4511-9928-60c614021254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155759287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.155759287
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3409307421
Short name T354
Test name
Test status
Simulation time 14800365 ps
CPU time 0.76 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:27:24 PM PDT 24
Peak memory 206180 kb
Host smart-73f3e081-83c3-4ebd-80e7-5446994b32e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409307421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3409307421
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1508830866
Short name T264
Test name
Test status
Simulation time 1116210874 ps
CPU time 8.88 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 225236 kb
Host smart-ff71643c-c2e1-4e2f-bdca-f455e085ed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508830866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1508830866
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1364456935
Short name T694
Test name
Test status
Simulation time 30540374 ps
CPU time 0.77 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:19 PM PDT 24
Peak memory 206060 kb
Host smart-ff769f90-5316-4420-bc90-5a293a7689d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364456935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1364456935
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3760164817
Short name T642
Test name
Test status
Simulation time 10524362 ps
CPU time 0.77 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:19 PM PDT 24
Peak memory 216504 kb
Host smart-2df649b2-4c2e-4923-b4ea-4b438c9953c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760164817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3760164817
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.617401618
Short name T1005
Test name
Test status
Simulation time 5750400920 ps
CPU time 136.57 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:29:39 PM PDT 24
Peak memory 273688 kb
Host smart-ae548dee-5c65-48d9-abb5-c54af9a94508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617401618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.617401618
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3087542256
Short name T141
Test name
Test status
Simulation time 1427507228 ps
CPU time 26.24 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:46 PM PDT 24
Peak memory 225272 kb
Host smart-e4edb5a3-5832-4849-8a73-43edc8367b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087542256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3087542256
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3793381973
Short name T250
Test name
Test status
Simulation time 954780359 ps
CPU time 6.39 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 225264 kb
Host smart-3e109c67-dc65-4769-bde0-0827afc019ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793381973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3793381973
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1954986837
Short name T434
Test name
Test status
Simulation time 654562019 ps
CPU time 15.26 seconds
Started Aug 03 05:27:20 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 250688 kb
Host smart-e4f6421b-df89-4acb-ba25-6cd92c65498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954986837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1954986837
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1313064801
Short name T548
Test name
Test status
Simulation time 888511107 ps
CPU time 4.55 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 233456 kb
Host smart-18877c2e-41b0-48a9-bb8d-69f0ac581607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313064801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1313064801
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1132312189
Short name T231
Test name
Test status
Simulation time 225239492 ps
CPU time 3.46 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:19 PM PDT 24
Peak memory 225240 kb
Host smart-f9e3917e-3911-4a7c-8fd8-61d4fdab3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132312189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1132312189
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.81021720
Short name T878
Test name
Test status
Simulation time 183362895 ps
CPU time 5.3 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:24 PM PDT 24
Peak memory 221216 kb
Host smart-045698f2-8626-4248-a716-5cdad3247fcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81021720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direc
t.81021720
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1595683101
Short name T304
Test name
Test status
Simulation time 32833203852 ps
CPU time 148.23 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:29:53 PM PDT 24
Peak memory 255708 kb
Host smart-a6fd0304-159e-4981-ac99-2427c19ce254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595683101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1595683101
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.145439190
Short name T919
Test name
Test status
Simulation time 1823948803 ps
CPU time 9.02 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:27 PM PDT 24
Peak memory 217168 kb
Host smart-54c52502-482f-46b4-ac7a-31403dfd1e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145439190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.145439190
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.417326405
Short name T691
Test name
Test status
Simulation time 4815653590 ps
CPU time 15.54 seconds
Started Aug 03 05:27:18 PM PDT 24
Finished Aug 03 05:27:34 PM PDT 24
Peak memory 216980 kb
Host smart-297e1aec-d6d0-4d25-9a50-53f7c267152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417326405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.417326405
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2504533997
Short name T921
Test name
Test status
Simulation time 31419673 ps
CPU time 0.74 seconds
Started Aug 03 05:27:19 PM PDT 24
Finished Aug 03 05:27:20 PM PDT 24
Peak memory 206104 kb
Host smart-968964a4-fbf3-44b5-9da7-87b48e7a4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504533997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2504533997
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.191206121
Short name T611
Test name
Test status
Simulation time 39400938 ps
CPU time 0.93 seconds
Started Aug 03 05:27:20 PM PDT 24
Finished Aug 03 05:27:21 PM PDT 24
Peak memory 206540 kb
Host smart-ed746e41-2fd3-4fc4-868d-047c1ccfec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191206121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.191206121
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2895085384
Short name T932
Test name
Test status
Simulation time 5550524589 ps
CPU time 11.42 seconds
Started Aug 03 05:27:16 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 225340 kb
Host smart-8daf62eb-3f56-4dce-9b87-2f5c23455696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895085384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2895085384
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2615069631
Short name T59
Test name
Test status
Simulation time 15984432 ps
CPU time 0.78 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:23 PM PDT 24
Peak memory 205748 kb
Host smart-7d58d280-959c-4d73-9cac-70930d6415e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615069631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2615069631
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2031332146
Short name T1022
Test name
Test status
Simulation time 15737138 ps
CPU time 0.77 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 206940 kb
Host smart-8dcbc88d-7ccc-4489-8be1-45fd5fe078c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031332146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2031332146
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2450324585
Short name T303
Test name
Test status
Simulation time 19127693074 ps
CPU time 129.53 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:29:35 PM PDT 24
Peak memory 249936 kb
Host smart-237c2f9d-08c5-405c-b284-e71284fcd5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450324585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2450324585
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3437130424
Short name T788
Test name
Test status
Simulation time 5105740113 ps
CPU time 72.82 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:28:35 PM PDT 24
Peak memory 251360 kb
Host smart-368261b3-66b2-43e7-98dd-5a29a9d64fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437130424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3437130424
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1526385438
Short name T995
Test name
Test status
Simulation time 67533512993 ps
CPU time 357.76 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:33:21 PM PDT 24
Peak memory 255900 kb
Host smart-bbdcfad8-400a-4e71-aab6-a3603f8cdaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526385438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1526385438
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.774299853
Short name T433
Test name
Test status
Simulation time 115596162 ps
CPU time 2.18 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 225196 kb
Host smart-c8043e37-05f4-4b33-94cf-5d0e0197ab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774299853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.774299853
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3792715677
Short name T253
Test name
Test status
Simulation time 5447964467 ps
CPU time 14.73 seconds
Started Aug 03 05:27:20 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 233596 kb
Host smart-87041467-4868-491d-a37e-95df516afc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792715677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3792715677
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4258698141
Short name T47
Test name
Test status
Simulation time 31224184189 ps
CPU time 121.03 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:29:26 PM PDT 24
Peak memory 233568 kb
Host smart-a1d1b2f7-d2f7-4699-a8fd-4a77a92ee05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258698141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4258698141
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1258679140
Short name T679
Test name
Test status
Simulation time 922805079 ps
CPU time 3.46 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:25 PM PDT 24
Peak memory 225252 kb
Host smart-4ddf7aac-082f-4bf3-80c0-ce6993845e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258679140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1258679140
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1295509660
Short name T996
Test name
Test status
Simulation time 171477440 ps
CPU time 4.26 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:27:27 PM PDT 24
Peak memory 233500 kb
Host smart-2c4a8cd4-7033-47f9-a5ea-d1166cdb5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295509660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1295509660
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3146786859
Short name T594
Test name
Test status
Simulation time 645737349 ps
CPU time 4.15 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 219912 kb
Host smart-9c82c0ba-1514-4c55-8a38-85ead66d18cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3146786859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3146786859
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.505276884
Short name T295
Test name
Test status
Simulation time 43135565220 ps
CPU time 124.72 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:29:29 PM PDT 24
Peak memory 274216 kb
Host smart-827c00c2-c84c-43f0-99a9-5e5fe411a53b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505276884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.505276884
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1180093275
Short name T489
Test name
Test status
Simulation time 1004955914 ps
CPU time 5.93 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:27:31 PM PDT 24
Peak memory 216924 kb
Host smart-7e260ef1-42ce-45b5-b15d-1eb72a5aae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180093275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1180093275
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2482109832
Short name T941
Test name
Test status
Simulation time 7712133253 ps
CPU time 11.57 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:33 PM PDT 24
Peak memory 217020 kb
Host smart-86b32363-db73-4add-a9bb-d6158fa838cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482109832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2482109832
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3411344431
Short name T504
Test name
Test status
Simulation time 807296007 ps
CPU time 3.19 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 216996 kb
Host smart-f03f87dc-b7ea-4016-8772-b98a6454ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411344431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3411344431
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3262736718
Short name T600
Test name
Test status
Simulation time 159209487 ps
CPU time 0.89 seconds
Started Aug 03 05:27:21 PM PDT 24
Finished Aug 03 05:27:22 PM PDT 24
Peak memory 206508 kb
Host smart-189f6db2-705b-4143-bb46-10ca575b5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262736718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3262736718
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1551141029
Short name T408
Test name
Test status
Simulation time 466685560 ps
CPU time 6.07 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 225324 kb
Host smart-03e29121-9cea-45c4-b572-29b7ff3ef780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551141029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1551141029
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1402036969
Short name T928
Test name
Test status
Simulation time 50913551 ps
CPU time 0.73 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 205808 kb
Host smart-3cdcd003-646f-4a10-92cc-9699a77bdc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402036969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1402036969
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2493273233
Short name T661
Test name
Test status
Simulation time 17069800073 ps
CPU time 24.87 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 225292 kb
Host smart-b1fb8d06-409a-47c0-8d8d-76f5070ae0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493273233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2493273233
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3309324611
Short name T814
Test name
Test status
Simulation time 40296110 ps
CPU time 0.72 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 205928 kb
Host smart-410f7529-3620-4093-8e6b-1c9da2c46c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309324611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3309324611
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3453562553
Short name T952
Test name
Test status
Simulation time 43159634 ps
CPU time 0.76 seconds
Started Aug 03 05:27:31 PM PDT 24
Finished Aug 03 05:27:32 PM PDT 24
Peak memory 216492 kb
Host smart-7ec4f611-0952-4f01-a56a-ef183c94fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453562553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3453562553
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3605594622
Short name T478
Test name
Test status
Simulation time 14536901085 ps
CPU time 140.11 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 249992 kb
Host smart-48c13841-224a-4b7f-9c97-d29930dc9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605594622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3605594622
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1002166423
Short name T44
Test name
Test status
Simulation time 1317923959 ps
CPU time 14.62 seconds
Started Aug 03 05:27:33 PM PDT 24
Finished Aug 03 05:27:47 PM PDT 24
Peak memory 233520 kb
Host smart-ed3e4631-b2c6-4a60-8cca-6077c1097923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002166423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1002166423
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3036274223
Short name T301
Test name
Test status
Simulation time 5783351675 ps
CPU time 61.39 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 258000 kb
Host smart-4b932865-db92-4023-8408-9ca1ea56b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036274223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3036274223
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3422570429
Short name T925
Test name
Test status
Simulation time 259225247 ps
CPU time 3.24 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:33 PM PDT 24
Peak memory 233512 kb
Host smart-98c41af9-2754-4a55-ac75-9f9f3fc7f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422570429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3422570429
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2654502226
Short name T260
Test name
Test status
Simulation time 1535673304 ps
CPU time 8.78 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:37 PM PDT 24
Peak memory 233460 kb
Host smart-a054c1ca-633f-4268-a194-7b31363755f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654502226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2654502226
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3649597453
Short name T455
Test name
Test status
Simulation time 22806656076 ps
CPU time 16.58 seconds
Started Aug 03 05:27:25 PM PDT 24
Finished Aug 03 05:27:42 PM PDT 24
Peak memory 225244 kb
Host smart-ef11a1ef-db44-43e6-83c2-9691d59bd0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649597453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3649597453
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.902341643
Short name T856
Test name
Test status
Simulation time 1246201303 ps
CPU time 6.06 seconds
Started Aug 03 05:27:22 PM PDT 24
Finished Aug 03 05:27:28 PM PDT 24
Peak memory 225264 kb
Host smart-04ce10d8-1f8c-4362-9bc3-fc5530a25dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902341643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.902341643
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1800544362
Short name T697
Test name
Test status
Simulation time 89757427 ps
CPU time 3.93 seconds
Started Aug 03 05:27:32 PM PDT 24
Finished Aug 03 05:27:36 PM PDT 24
Peak memory 223636 kb
Host smart-dbac8019-31b5-4a6a-ae8a-26584321f7c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1800544362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1800544362
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.444545027
Short name T330
Test name
Test status
Simulation time 8871369087 ps
CPU time 40.74 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:28:05 PM PDT 24
Peak memory 216952 kb
Host smart-77b2ab53-e4f4-4634-8ba2-229f7b5e7bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444545027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.444545027
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.623133948
Short name T413
Test name
Test status
Simulation time 1601091443 ps
CPU time 6.6 seconds
Started Aug 03 05:27:26 PM PDT 24
Finished Aug 03 05:27:32 PM PDT 24
Peak memory 216896 kb
Host smart-be241573-a97e-41c3-82a5-17ae3518f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623133948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.623133948
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3699921764
Short name T52
Test name
Test status
Simulation time 142796317 ps
CPU time 3.47 seconds
Started Aug 03 05:27:23 PM PDT 24
Finished Aug 03 05:27:26 PM PDT 24
Peak memory 216940 kb
Host smart-55259263-61e2-4fa6-91d3-5d6fca2cc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699921764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3699921764
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1116269952
Short name T799
Test name
Test status
Simulation time 14542640 ps
CPU time 0.69 seconds
Started Aug 03 05:27:24 PM PDT 24
Finished Aug 03 05:27:25 PM PDT 24
Peak memory 206472 kb
Host smart-5116255d-23f6-4724-9296-7ba37b3743b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116269952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1116269952
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2775258362
Short name T518
Test name
Test status
Simulation time 2822250069 ps
CPU time 11.45 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:40 PM PDT 24
Peak memory 225348 kb
Host smart-17db428e-e473-4936-a700-3a0d06fe85e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775258362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2775258362
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4035440939
Short name T417
Test name
Test status
Simulation time 12084040 ps
CPU time 0.73 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 205320 kb
Host smart-afbe755d-68ad-46d8-8b7e-c41762db8673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035440939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4035440939
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1252990844
Short name T959
Test name
Test status
Simulation time 54651278 ps
CPU time 2.26 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 233440 kb
Host smart-ad30ce2f-3c3e-4b0a-95e3-9ee0232bbd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252990844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1252990844
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2765377579
Short name T791
Test name
Test status
Simulation time 46711616 ps
CPU time 0.82 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 207076 kb
Host smart-3c4680f3-2b4a-4709-8fb1-922fb673786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765377579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2765377579
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2136721069
Short name T495
Test name
Test status
Simulation time 29532882434 ps
CPU time 207.57 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:30:56 PM PDT 24
Peak memory 250900 kb
Host smart-f90dc1f0-d264-458b-8a1f-3fa0000f32a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136721069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2136721069
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.875679431
Short name T461
Test name
Test status
Simulation time 30882006449 ps
CPU time 117.87 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:29:28 PM PDT 24
Peak memory 266344 kb
Host smart-57db4301-e296-4583-b5e4-c3b71db7155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875679431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.875679431
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.739571510
Short name T217
Test name
Test status
Simulation time 18249278187 ps
CPU time 53.09 seconds
Started Aug 03 05:27:27 PM PDT 24
Finished Aug 03 05:28:21 PM PDT 24
Peak memory 249932 kb
Host smart-680b79ea-c331-4ea8-a186-a1c4fdb070b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739571510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.739571510
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.234128723
Short name T95
Test name
Test status
Simulation time 2835577038 ps
CPU time 10.29 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:39 PM PDT 24
Peak memory 236248 kb
Host smart-fbcaf578-cfda-44c9-b2c8-0dd00685ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234128723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.234128723
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1779686076
Short name T50
Test name
Test status
Simulation time 22421107470 ps
CPU time 153.27 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:30:03 PM PDT 24
Peak memory 253028 kb
Host smart-c40fe0e4-5665-418d-a46c-7e8bff70dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779686076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1779686076
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1783674546
Short name T628
Test name
Test status
Simulation time 1251523669 ps
CPU time 14.56 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 233368 kb
Host smart-b0ae28b6-08d1-45ce-ac72-240564af3832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783674546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1783674546
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.593536394
Short name T652
Test name
Test status
Simulation time 7065972972 ps
CPU time 15.94 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:45 PM PDT 24
Peak memory 233472 kb
Host smart-dd09e098-2c7f-4b03-bea6-ace185af84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593536394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.593536394
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4156785994
Short name T438
Test name
Test status
Simulation time 1600573809 ps
CPU time 5.93 seconds
Started Aug 03 05:27:27 PM PDT 24
Finished Aug 03 05:27:33 PM PDT 24
Peak memory 225244 kb
Host smart-99fd3804-0790-4ef4-b497-f72971f1fcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156785994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4156785994
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3250635947
Short name T395
Test name
Test status
Simulation time 466668965 ps
CPU time 4.64 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:33 PM PDT 24
Peak memory 225260 kb
Host smart-bba536de-04eb-4950-a84c-c66e911e2b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250635947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3250635947
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4279199237
Short name T367
Test name
Test status
Simulation time 615448647 ps
CPU time 8.56 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 220864 kb
Host smart-1419a47a-b12f-49e2-9cc5-34ea2447f552
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4279199237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4279199237
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4262897521
Short name T978
Test name
Test status
Simulation time 7903293135 ps
CPU time 30.79 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 241796 kb
Host smart-19f87c50-f4c5-43cd-bb87-978613f967be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262897521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4262897521
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4054465120
Short name T542
Test name
Test status
Simulation time 25516748312 ps
CPU time 37.74 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:28:07 PM PDT 24
Peak memory 217128 kb
Host smart-9c554a85-9d7b-45f2-bb27-bd15360b24b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054465120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4054465120
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1986970843
Short name T937
Test name
Test status
Simulation time 3517963133 ps
CPU time 11.38 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:27:41 PM PDT 24
Peak memory 217072 kb
Host smart-55d8345c-932a-48b8-bbdb-5b395fd818c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986970843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1986970843
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4126809531
Short name T368
Test name
Test status
Simulation time 25138993 ps
CPU time 0.82 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 206756 kb
Host smart-2f79026e-c475-4791-876d-80f19ead7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126809531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4126809531
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4275835997
Short name T503
Test name
Test status
Simulation time 438887399 ps
CPU time 0.84 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:29 PM PDT 24
Peak memory 206640 kb
Host smart-cdadd31c-dca1-45f7-8422-a56aeb12e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275835997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4275835997
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3986590241
Short name T241
Test name
Test status
Simulation time 557797161 ps
CPU time 7.28 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 225192 kb
Host smart-fc5fa84a-ef4c-4cef-8096-127b7e15894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986590241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3986590241
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3999795056
Short name T711
Test name
Test status
Simulation time 51198434 ps
CPU time 0.76 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:27:36 PM PDT 24
Peak memory 205904 kb
Host smart-57cbab93-b90f-4c96-ad5e-64e6e4960c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999795056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3999795056
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4101546731
Short name T28
Test name
Test status
Simulation time 529768110 ps
CPU time 6.41 seconds
Started Aug 03 05:27:41 PM PDT 24
Finished Aug 03 05:27:47 PM PDT 24
Peak memory 225316 kb
Host smart-b6b49419-76ca-463e-818a-046f89612b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101546731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4101546731
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3189860613
Short name T175
Test name
Test status
Simulation time 53979271 ps
CPU time 0.79 seconds
Started Aug 03 05:27:29 PM PDT 24
Finished Aug 03 05:27:30 PM PDT 24
Peak memory 207056 kb
Host smart-38bf2467-36d3-4728-bfa5-8cd40379699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189860613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3189860613
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.729367589
Short name T751
Test name
Test status
Simulation time 3521189346 ps
CPU time 20.02 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:56 PM PDT 24
Peak memory 235316 kb
Host smart-21185289-b864-4004-b488-8b0766c4ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729367589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.729367589
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2284315917
Short name T334
Test name
Test status
Simulation time 2810798201 ps
CPU time 55.24 seconds
Started Aug 03 05:27:37 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 249872 kb
Host smart-73952d7d-309e-448e-828a-2c87da3e8313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284315917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2284315917
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1843144311
Short name T37
Test name
Test status
Simulation time 36232392978 ps
CPU time 190.98 seconds
Started Aug 03 05:27:38 PM PDT 24
Finished Aug 03 05:30:49 PM PDT 24
Peak memory 250084 kb
Host smart-b9bce746-7f8e-409a-9913-2a716c897bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843144311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1843144311
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1915543099
Short name T900
Test name
Test status
Simulation time 3204977022 ps
CPU time 46.87 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:28:22 PM PDT 24
Peak memory 250724 kb
Host smart-fabf7ea5-f312-404c-98be-4a0f04efc67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915543099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1915543099
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2608439414
Short name T1014
Test name
Test status
Simulation time 12473212444 ps
CPU time 90.41 seconds
Started Aug 03 05:27:38 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 249944 kb
Host smart-2ed16ce5-e75a-45c4-8ed4-4a1cdca7311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608439414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2608439414
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3168668879
Short name T911
Test name
Test status
Simulation time 28006111978 ps
CPU time 22.47 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 233492 kb
Host smart-5904cd0e-d3e4-4761-8169-b1868d7d957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168668879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3168668879
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2415452888
Short name T205
Test name
Test status
Simulation time 12936575548 ps
CPU time 42.05 seconds
Started Aug 03 05:27:34 PM PDT 24
Finished Aug 03 05:28:16 PM PDT 24
Peak memory 233536 kb
Host smart-dac2c4aa-762e-4a7b-817a-d7694fb55228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415452888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2415452888
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.956114096
Short name T811
Test name
Test status
Simulation time 1305136982 ps
CPU time 6.69 seconds
Started Aug 03 05:27:38 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 233496 kb
Host smart-238207ba-2105-4a94-a6f6-e77eaa19f095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956114096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.956114096
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2102055658
Short name T841
Test name
Test status
Simulation time 1136816636 ps
CPU time 6.7 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:43 PM PDT 24
Peak memory 225392 kb
Host smart-e962c1d4-ead7-4c61-bff8-e4ce502c553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102055658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2102055658
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2356940975
Short name T721
Test name
Test status
Simulation time 806850022 ps
CPU time 4.28 seconds
Started Aug 03 05:27:34 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 219776 kb
Host smart-a781f3fe-74be-493e-9a8b-8117f12ac45d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2356940975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2356940975
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3398113029
Short name T796
Test name
Test status
Simulation time 45240393795 ps
CPU time 353.78 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:33:29 PM PDT 24
Peak memory 261308 kb
Host smart-2681bf01-bfc5-448d-9bc6-89e7b9dd8556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398113029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3398113029
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1447378946
Short name T1001
Test name
Test status
Simulation time 30339459058 ps
CPU time 24.17 seconds
Started Aug 03 05:27:28 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 217052 kb
Host smart-ec08f008-0dfd-46ee-b3cb-283c10fb0c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447378946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1447378946
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1510258026
Short name T539
Test name
Test status
Simulation time 51139221409 ps
CPU time 19.14 seconds
Started Aug 03 05:27:30 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 218252 kb
Host smart-98cf4192-df6e-4b5c-bec8-e4804a87e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510258026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1510258026
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1280899592
Short name T353
Test name
Test status
Simulation time 172265036 ps
CPU time 0.94 seconds
Started Aug 03 05:27:33 PM PDT 24
Finished Aug 03 05:27:34 PM PDT 24
Peak memory 207352 kb
Host smart-72e250ea-d453-4e05-b726-ad2e80295748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280899592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1280899592
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1808718841
Short name T889
Test name
Test status
Simulation time 53362967 ps
CPU time 0.84 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:37 PM PDT 24
Peak memory 206624 kb
Host smart-ab2bf349-b6f3-4009-a606-dd208c3dc629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808718841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1808718841
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.549096251
Short name T458
Test name
Test status
Simulation time 10779962897 ps
CPU time 12.34 seconds
Started Aug 03 05:27:37 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 233520 kb
Host smart-286481a5-055c-47b7-96ec-6af7f941f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549096251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.549096251
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3476216164
Short name T926
Test name
Test status
Simulation time 36854088 ps
CPU time 0.73 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:45 PM PDT 24
Peak memory 205308 kb
Host smart-ad5ee4e9-2608-4711-852a-4bc7abb738bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476216164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3476216164
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.948046445
Short name T838
Test name
Test status
Simulation time 149910318 ps
CPU time 2.46 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 225196 kb
Host smart-85b8f806-4218-429c-9001-cd016636e4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948046445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.948046445
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3020185222
Short name T66
Test name
Test status
Simulation time 14115893 ps
CPU time 0.79 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:37 PM PDT 24
Peak memory 207392 kb
Host smart-e4104019-6781-496c-906b-01eb45a91263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020185222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3020185222
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4181577929
Short name T912
Test name
Test status
Simulation time 58272942560 ps
CPU time 41.1 seconds
Started Aug 03 05:27:41 PM PDT 24
Finished Aug 03 05:28:23 PM PDT 24
Peak memory 225364 kb
Host smart-57d38ee0-9e45-4aab-bfed-48ca04f2275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181577929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4181577929
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3370187250
Short name T776
Test name
Test status
Simulation time 1127376094 ps
CPU time 17.2 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 224256 kb
Host smart-ff9e6f7b-d234-4fa4-8bed-bc159861ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370187250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3370187250
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1284368742
Short name T453
Test name
Test status
Simulation time 327184973 ps
CPU time 4.68 seconds
Started Aug 03 05:27:34 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 234912 kb
Host smart-f9f920fd-c934-47e9-845c-8dc46c9cb9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284368742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1284368742
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2228051240
Short name T399
Test name
Test status
Simulation time 2001114657 ps
CPU time 15.11 seconds
Started Aug 03 05:27:37 PM PDT 24
Finished Aug 03 05:27:52 PM PDT 24
Peak memory 238124 kb
Host smart-d0d16d20-63a7-4fce-909a-4cc983617c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228051240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2228051240
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1763659574
Short name T510
Test name
Test status
Simulation time 1000884524 ps
CPU time 5.44 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:42 PM PDT 24
Peak memory 225320 kb
Host smart-1de52899-39bb-4b00-9d98-d36cf2646844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763659574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1763659574
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2506681195
Short name T663
Test name
Test status
Simulation time 3400756822 ps
CPU time 33.33 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:28:09 PM PDT 24
Peak memory 241284 kb
Host smart-57459df6-a86d-4016-893b-c524749bf8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506681195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2506681195
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.617485462
Short name T306
Test name
Test status
Simulation time 245087718 ps
CPU time 4.59 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:41 PM PDT 24
Peak memory 233468 kb
Host smart-fdf1f5a3-8ecf-4dc5-ab88-390cb852d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617485462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.617485462
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1919698158
Short name T819
Test name
Test status
Simulation time 460641910 ps
CPU time 8.2 seconds
Started Aug 03 05:27:40 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 241516 kb
Host smart-170b0dc8-77d2-4a73-91af-9f75780c0df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919698158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1919698158
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2574225758
Short name T812
Test name
Test status
Simulation time 1826326007 ps
CPU time 8.36 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:27:43 PM PDT 24
Peak memory 223728 kb
Host smart-8fb4dc52-95f7-438b-92b1-f0d1eaa4ef5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2574225758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2574225758
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.205156131
Short name T307
Test name
Test status
Simulation time 35042882020 ps
CPU time 118.51 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 255392 kb
Host smart-1479d492-ffda-4a6c-844b-c159aa3cf8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205156131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.205156131
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1499430553
Short name T371
Test name
Test status
Simulation time 26172911 ps
CPU time 0.74 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:37 PM PDT 24
Peak memory 206224 kb
Host smart-59bb1305-41c3-4ea5-aab3-486e9cda0b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499430553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1499430553
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4150496096
Short name T832
Test name
Test status
Simulation time 876625322 ps
CPU time 1.92 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:38 PM PDT 24
Peak memory 216804 kb
Host smart-e63a174e-9d02-4a13-8a37-35315fe804cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150496096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4150496096
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4244284506
Short name T11
Test name
Test status
Simulation time 97948049 ps
CPU time 2.89 seconds
Started Aug 03 05:27:36 PM PDT 24
Finished Aug 03 05:27:40 PM PDT 24
Peak memory 217008 kb
Host smart-8d52f83e-3b97-4e74-9f77-be2bdc8804f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244284506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4244284506
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1624719511
Short name T766
Test name
Test status
Simulation time 31174640 ps
CPU time 0.8 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:27:36 PM PDT 24
Peak memory 206608 kb
Host smart-fdbe856b-5969-4eb6-aeb4-067304046d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624719511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1624719511
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.952368151
Short name T896
Test name
Test status
Simulation time 436071732 ps
CPU time 3.51 seconds
Started Aug 03 05:27:35 PM PDT 24
Finished Aug 03 05:27:39 PM PDT 24
Peak memory 225200 kb
Host smart-7e11a933-032c-4d95-a58f-004bda595fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952368151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.952368151
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3421483552
Short name T608
Test name
Test status
Simulation time 47839459 ps
CPU time 0.74 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:27:47 PM PDT 24
Peak memory 205196 kb
Host smart-df636df1-15dd-453d-b847-80d42e655299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421483552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3421483552
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1649401505
Short name T25
Test name
Test status
Simulation time 99431908 ps
CPU time 2.67 seconds
Started Aug 03 05:27:41 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 233408 kb
Host smart-4cfe50c4-01e4-4095-9176-698215fc3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649401505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1649401505
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.688424732
Short name T645
Test name
Test status
Simulation time 40260415 ps
CPU time 0.84 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:46 PM PDT 24
Peak memory 207092 kb
Host smart-e2abdea4-d18b-4fb2-95ba-98c96ac9709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688424732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.688424732
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.215955627
Short name T294
Test name
Test status
Simulation time 69847274913 ps
CPU time 222.25 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:31:25 PM PDT 24
Peak memory 252712 kb
Host smart-f08d0ae7-cba4-4109-82c7-81ce893d5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215955627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.215955627
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3792292500
Short name T880
Test name
Test status
Simulation time 9719943881 ps
CPU time 117.96 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 249908 kb
Host smart-18816964-e8d8-4cb2-a17f-ac29b1505da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792292500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3792292500
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3444214832
Short name T724
Test name
Test status
Simulation time 2645014356 ps
CPU time 5.49 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 230336 kb
Host smart-e4ed3c5e-5961-4fab-9a4c-3cb0f4be273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444214832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3444214832
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.386535910
Short name T298
Test name
Test status
Simulation time 30993070130 ps
CPU time 65.33 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:28:49 PM PDT 24
Peak memory 250960 kb
Host smart-a74ed535-d295-4ceb-853a-69761dc99967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386535910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.386535910
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2117369619
Short name T671
Test name
Test status
Simulation time 195159564 ps
CPU time 4.59 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 233480 kb
Host smart-231530a9-a7fc-4350-9785-b13d202c726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117369619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2117369619
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3277215347
Short name T626
Test name
Test status
Simulation time 619357847 ps
CPU time 4.48 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:50 PM PDT 24
Peak memory 233540 kb
Host smart-e6d2b3d5-bbcf-4968-b076-e5a22ec78fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277215347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3277215347
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2204928386
Short name T680
Test name
Test status
Simulation time 32547596 ps
CPU time 2.26 seconds
Started Aug 03 05:27:42 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 233088 kb
Host smart-6ecea31f-f54e-4e7b-ae77-4c8974a6c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204928386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2204928386
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.304396229
Short name T730
Test name
Test status
Simulation time 16515540182 ps
CPU time 10.03 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 225340 kb
Host smart-75d3b9b8-9e79-4d1c-a504-a1f5def85df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304396229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.304396229
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.426531519
Short name T614
Test name
Test status
Simulation time 897457236 ps
CPU time 3.8 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 220008 kb
Host smart-957c56bc-9ff3-4fe3-86b1-181bae63bdb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=426531519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.426531519
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3332328441
Short name T168
Test name
Test status
Simulation time 10366422799 ps
CPU time 70.64 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:28:54 PM PDT 24
Peak memory 261048 kb
Host smart-8e54fc99-f488-416d-944a-bc39cbedc098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332328441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3332328441
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1756671068
Short name T471
Test name
Test status
Simulation time 1569832805 ps
CPU time 18.89 seconds
Started Aug 03 05:27:41 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 217228 kb
Host smart-13714ae1-f833-48e2-b9eb-2d54f403d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756671068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1756671068
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.173484500
Short name T556
Test name
Test status
Simulation time 10170027116 ps
CPU time 23.41 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:28:10 PM PDT 24
Peak memory 217064 kb
Host smart-a1d58f7e-c4ca-40a7-a913-4a28c43b3755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173484500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.173484500
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2144286552
Short name T405
Test name
Test status
Simulation time 38669360 ps
CPU time 0.72 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:46 PM PDT 24
Peak memory 206136 kb
Host smart-7af946ad-cdc7-408e-b327-61c12334cacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144286552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2144286552
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1852613194
Short name T379
Test name
Test status
Simulation time 54259375 ps
CPU time 0.94 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 206488 kb
Host smart-f3007a76-690a-4e19-88f8-afab7ad9cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852613194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1852613194
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2067848413
Short name T713
Test name
Test status
Simulation time 330460270 ps
CPU time 2.73 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:46 PM PDT 24
Peak memory 225192 kb
Host smart-82bc1e43-2740-4bac-ab61-e417ef2bb29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067848413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2067848413
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1342779228
Short name T809
Test name
Test status
Simulation time 85177778 ps
CPU time 0.74 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 206244 kb
Host smart-089cb282-7292-4428-bd9b-0dbe5fef259c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342779228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1342779228
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1278835655
Short name T424
Test name
Test status
Simulation time 223792632 ps
CPU time 4.22 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:27:51 PM PDT 24
Peak memory 233376 kb
Host smart-11274640-e757-4b56-b7da-54483ff3bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278835655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1278835655
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3727709562
Short name T356
Test name
Test status
Simulation time 21430979 ps
CPU time 0.81 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:27:45 PM PDT 24
Peak memory 207084 kb
Host smart-07f921bb-c63f-4eb2-9e4d-b4a54169f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727709562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3727709562
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2668517834
Short name T808
Test name
Test status
Simulation time 6407694522 ps
CPU time 69.44 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:28:53 PM PDT 24
Peak memory 257000 kb
Host smart-afc9582b-4f66-4eb1-a179-c76207005c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668517834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2668517834
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1678483003
Short name T318
Test name
Test status
Simulation time 364989187973 ps
CPU time 752.6 seconds
Started Aug 03 05:27:42 PM PDT 24
Finished Aug 03 05:40:15 PM PDT 24
Peak memory 260876 kb
Host smart-ee1fc8f1-8a7c-4c99-99f4-bef0ddd0bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678483003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1678483003
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2303139344
Short name T45
Test name
Test status
Simulation time 364657804 ps
CPU time 7.67 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:51 PM PDT 24
Peak memory 233496 kb
Host smart-94f7f6b3-10a3-42aa-848a-013ee54476af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303139344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2303139344
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4281609040
Short name T485
Test name
Test status
Simulation time 101425878286 ps
CPU time 67.27 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:28:51 PM PDT 24
Peak memory 225376 kb
Host smart-bb82e48b-deeb-4983-9d64-5a4402bc72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281609040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4281609040
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1377230073
Short name T219
Test name
Test status
Simulation time 958780182 ps
CPU time 6.23 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 233492 kb
Host smart-69825276-cd53-4a25-adff-70faa5e6a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377230073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1377230073
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3705727555
Short name T142
Test name
Test status
Simulation time 2049600852 ps
CPU time 28 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 249696 kb
Host smart-0912d8ef-54a9-44d5-8c78-9fcbfaf76fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705727555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3705727555
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1573620274
Short name T618
Test name
Test status
Simulation time 516109088 ps
CPU time 3.73 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:50 PM PDT 24
Peak memory 225216 kb
Host smart-21071e0c-8574-441b-bff9-3b62ea30d5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573620274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1573620274
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3600207965
Short name T486
Test name
Test status
Simulation time 4416146248 ps
CPU time 8.66 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 225348 kb
Host smart-cb52f149-32d8-4e52-9efa-5bb1f6daec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600207965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3600207965
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2612779103
Short name T422
Test name
Test status
Simulation time 1175176656 ps
CPU time 7.55 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:51 PM PDT 24
Peak memory 219404 kb
Host smart-ed737e64-f8e4-4d2a-af5e-8c701c264bd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2612779103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2612779103
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3974550912
Short name T505
Test name
Test status
Simulation time 28172268270 ps
CPU time 41.11 seconds
Started Aug 03 05:27:42 PM PDT 24
Finished Aug 03 05:28:24 PM PDT 24
Peak memory 217048 kb
Host smart-7f71ed31-5068-44b5-844d-cb58d547d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974550912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3974550912
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.492052713
Short name T844
Test name
Test status
Simulation time 1322574394 ps
CPU time 4.19 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 216968 kb
Host smart-13d75222-c7a1-4c61-825c-d093c2c893b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492052713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.492052713
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2751828792
Short name T745
Test name
Test status
Simulation time 36064089 ps
CPU time 0.7 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:45 PM PDT 24
Peak memory 206132 kb
Host smart-007e5036-b6ec-4175-91c3-3d17be171ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751828792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2751828792
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3532120701
Short name T836
Test name
Test status
Simulation time 13300268 ps
CPU time 0.68 seconds
Started Aug 03 05:27:40 PM PDT 24
Finished Aug 03 05:27:40 PM PDT 24
Peak memory 206064 kb
Host smart-d2906eff-2f1b-4e45-a3b8-9af6d31ab66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532120701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3532120701
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2868624907
Short name T646
Test name
Test status
Simulation time 368611623 ps
CPU time 3.79 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:50 PM PDT 24
Peak memory 233492 kb
Host smart-0c3fa0d4-8bc4-491a-ac39-a2bad6498087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868624907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2868624907
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1826313012
Short name T940
Test name
Test status
Simulation time 25459314 ps
CPU time 0.72 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:47 PM PDT 24
Peak memory 205884 kb
Host smart-65b5330a-f439-411e-b9b1-83c04ff3b73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826313012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1826313012
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3021292933
Short name T781
Test name
Test status
Simulation time 450300872 ps
CPU time 2.53 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 225140 kb
Host smart-057f4be1-b4f5-42e6-a4ce-dac403627859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021292933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3021292933
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.511881816
Short name T837
Test name
Test status
Simulation time 20659964 ps
CPU time 0.82 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:27:44 PM PDT 24
Peak memory 207080 kb
Host smart-eb6866d0-36e9-451e-af96-db265f34d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511881816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.511881816
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3321428820
Short name T254
Test name
Test status
Simulation time 26531474489 ps
CPU time 92.58 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:29:20 PM PDT 24
Peak memory 241744 kb
Host smart-f1e141ec-b06d-4bf2-a822-86cf9fbdfe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321428820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3321428820
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2609455298
Short name T473
Test name
Test status
Simulation time 1392428926 ps
CPU time 14.5 seconds
Started Aug 03 05:27:48 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 241052 kb
Host smart-ccd48694-8bcc-4e0a-8a72-86b0eaf44c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609455298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2609455298
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.737046569
Short name T647
Test name
Test status
Simulation time 29742102557 ps
CPU time 117.36 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:29:44 PM PDT 24
Peak memory 250020 kb
Host smart-32a3f716-f65c-405d-96c4-b167a63de3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737046569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.737046569
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1724717525
Short name T60
Test name
Test status
Simulation time 264131478 ps
CPU time 7.11 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 233520 kb
Host smart-754a4dc2-ca9c-4731-b3b8-e77083271324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724717525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1724717525
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2296350824
Short name T971
Test name
Test status
Simulation time 32007118567 ps
CPU time 150.29 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:30:16 PM PDT 24
Peak memory 249960 kb
Host smart-4b9aba1a-0915-400a-add4-12337e5080c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296350824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2296350824
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.481084447
Short name T681
Test name
Test status
Simulation time 1540241716 ps
CPU time 7.58 seconds
Started Aug 03 05:27:48 PM PDT 24
Finished Aug 03 05:27:56 PM PDT 24
Peak memory 225296 kb
Host smart-3f9c4e9b-ca34-49a6-9ddb-8fc78d231cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481084447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.481084447
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.654079306
Short name T772
Test name
Test status
Simulation time 328955875 ps
CPU time 2.41 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 224936 kb
Host smart-b617e961-4dde-4303-bdfd-91589af9c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654079306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.654079306
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1531311845
Short name T593
Test name
Test status
Simulation time 3688001260 ps
CPU time 5.77 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:52 PM PDT 24
Peak memory 219628 kb
Host smart-90055771-20ae-49f4-921d-c9105274ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531311845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1531311845
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.21669435
Short name T1
Test name
Test status
Simulation time 114225081 ps
CPU time 2.46 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:47 PM PDT 24
Peak memory 233136 kb
Host smart-21bb3701-97ba-4c96-bcaf-d3a31dd6aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21669435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.21669435
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1416666430
Short name T155
Test name
Test status
Simulation time 388572765 ps
CPU time 4.22 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:27:57 PM PDT 24
Peak memory 219444 kb
Host smart-4196a288-d913-4497-896e-a3746bc8e5ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1416666430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1416666430
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3802875416
Short name T771
Test name
Test status
Simulation time 85752129086 ps
CPU time 344.52 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:33:32 PM PDT 24
Peak memory 266396 kb
Host smart-bebe3f0c-78c5-40dd-b281-827e8c122403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802875416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3802875416
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.329953270
Short name T514
Test name
Test status
Simulation time 7771890049 ps
CPU time 25.27 seconds
Started Aug 03 05:27:43 PM PDT 24
Finished Aug 03 05:28:09 PM PDT 24
Peak memory 217236 kb
Host smart-59ede8e6-ffe6-4886-8d94-2fda29af1072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329953270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.329953270
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1928003420
Short name T613
Test name
Test status
Simulation time 17438134835 ps
CPU time 14.47 seconds
Started Aug 03 05:27:45 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 217048 kb
Host smart-9297f9f2-a8aa-45e5-b775-01473cb8f087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928003420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1928003420
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.87906572
Short name T916
Test name
Test status
Simulation time 124380340 ps
CPU time 2.41 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:27:56 PM PDT 24
Peak memory 216948 kb
Host smart-bd3c424f-850d-4b3a-b89a-d3213f45f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87906572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.87906572
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2927636803
Short name T30
Test name
Test status
Simulation time 202284518 ps
CPU time 1.06 seconds
Started Aug 03 05:27:41 PM PDT 24
Finished Aug 03 05:27:43 PM PDT 24
Peak memory 206552 kb
Host smart-9853c74b-acd7-468d-8ff3-6e8cee9210fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927636803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2927636803
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3507102360
Short name T222
Test name
Test status
Simulation time 8361248452 ps
CPU time 14.89 seconds
Started Aug 03 05:27:44 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 219316 kb
Host smart-22e85f96-4fb0-49d8-8976-92cccf3d2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507102360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3507102360
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1575453360
Short name T753
Test name
Test status
Simulation time 25925161 ps
CPU time 0.72 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:25:55 PM PDT 24
Peak memory 205896 kb
Host smart-2488563c-4114-4c52-80c0-03bdd7671792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575453360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
575453360
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3754997004
Short name T391
Test name
Test status
Simulation time 122445988 ps
CPU time 2.56 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:25:53 PM PDT 24
Peak memory 233080 kb
Host smart-b17c64c6-c1a7-4df0-8eaa-dc7d6138d2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754997004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3754997004
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1861067024
Short name T858
Test name
Test status
Simulation time 15667993 ps
CPU time 0.75 seconds
Started Aug 03 05:26:03 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 206372 kb
Host smart-cce7ee09-8cbd-40b5-8334-86b3201de5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861067024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1861067024
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.568855288
Short name T552
Test name
Test status
Simulation time 716547240 ps
CPU time 15.84 seconds
Started Aug 03 05:25:51 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 237964 kb
Host smart-584d85b7-2452-4508-83a4-084d14bacaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568855288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.568855288
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3326277274
Short name T854
Test name
Test status
Simulation time 3413167384 ps
CPU time 75.64 seconds
Started Aug 03 05:25:49 PM PDT 24
Finished Aug 03 05:27:05 PM PDT 24
Peak memory 265804 kb
Host smart-f69f5bfb-2570-4bd7-88c2-69010d7d9514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326277274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3326277274
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.669264767
Short name T1006
Test name
Test status
Simulation time 21128537183 ps
CPU time 225.01 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 258148 kb
Host smart-b5539697-4c13-482c-a576-94bb6c362e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669264767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
669264767
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3386901235
Short name T578
Test name
Test status
Simulation time 3190399464 ps
CPU time 33.95 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 249960 kb
Host smart-0eef7469-39f9-4f55-90f7-5d7e8f8afdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386901235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3386901235
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4001167143
Short name T764
Test name
Test status
Simulation time 56009903587 ps
CPU time 387.53 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:32:21 PM PDT 24
Peak memory 255632 kb
Host smart-47395ee0-ddc8-4528-8ff3-a98cabc3189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001167143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4001167143
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4198514634
Short name T1012
Test name
Test status
Simulation time 434667550 ps
CPU time 7.96 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 233488 kb
Host smart-acd51946-8fce-440c-a152-289a1b76fdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198514634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4198514634
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1193667665
Short name T707
Test name
Test status
Simulation time 750658103 ps
CPU time 8.94 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:26:06 PM PDT 24
Peak memory 233468 kb
Host smart-33e3f1f9-1a23-41d7-9e47-538667c8717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193667665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1193667665
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3727790820
Short name T57
Test name
Test status
Simulation time 108616989 ps
CPU time 1.1 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 217204 kb
Host smart-25ad47bf-41a9-4486-8dce-aca9423d07ef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727790820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3727790820
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.493597626
Short name T807
Test name
Test status
Simulation time 5206648555 ps
CPU time 17.67 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:26:10 PM PDT 24
Peak memory 233536 kb
Host smart-7fae0bd9-384e-4b2a-bcb9-8cda8a819dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493597626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
493597626
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1945149446
Short name T290
Test name
Test status
Simulation time 4161567623 ps
CPU time 8.31 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 233520 kb
Host smart-8bfff9f4-937a-4065-b22f-e741e2ffcf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945149446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1945149446
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3190349960
Short name T863
Test name
Test status
Simulation time 732059649 ps
CPU time 10.11 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 223296 kb
Host smart-a987daaf-f6c8-4c12-97b9-9f8246ba2065
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3190349960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3190349960
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2963717409
Short name T73
Test name
Test status
Simulation time 62850246 ps
CPU time 1.06 seconds
Started Aug 03 05:25:52 PM PDT 24
Finished Aug 03 05:25:53 PM PDT 24
Peak memory 235612 kb
Host smart-d2afa471-549f-480c-a7b5-6cdfe7086007
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963717409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2963717409
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4120950145
Short name T361
Test name
Test status
Simulation time 26096103 ps
CPU time 0.74 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 206188 kb
Host smart-c6c0f77c-52b6-4f3c-a30d-0776947d1814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120950145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4120950145
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3671748586
Short name T984
Test name
Test status
Simulation time 111506672868 ps
CPU time 13.65 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:10 PM PDT 24
Peak memory 217196 kb
Host smart-2a9f3d71-b33c-4a41-982f-8fa35be5e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671748586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3671748586
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1806436006
Short name T335
Test name
Test status
Simulation time 122266183 ps
CPU time 4.81 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 217220 kb
Host smart-4bb03dbd-8c6f-4364-87df-8c176e9aa7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806436006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1806436006
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1931029301
Short name T339
Test name
Test status
Simulation time 39163547 ps
CPU time 0.8 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:25:54 PM PDT 24
Peak memory 206644 kb
Host smart-a2558988-7bc2-47b3-91f3-03183a21d64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931029301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1931029301
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.138886752
Short name T935
Test name
Test status
Simulation time 4520215777 ps
CPU time 15.97 seconds
Started Aug 03 05:25:53 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 231604 kb
Host smart-9fdd2a95-a1c7-48e2-b90f-a8fbe42eb984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138886752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.138886752
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3654486373
Short name T479
Test name
Test status
Simulation time 116055827 ps
CPU time 0.75 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 206128 kb
Host smart-f37b0765-a5c4-4230-ab7f-18cfb2d75f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654486373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3654486373
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4097040888
Short name T635
Test name
Test status
Simulation time 341260224 ps
CPU time 2.45 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:27:56 PM PDT 24
Peak memory 225192 kb
Host smart-2bfeff18-8449-4b3d-a17c-6e0d1362f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097040888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4097040888
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2546351297
Short name T449
Test name
Test status
Simulation time 18129983 ps
CPU time 0.75 seconds
Started Aug 03 05:27:47 PM PDT 24
Finished Aug 03 05:27:48 PM PDT 24
Peak memory 206088 kb
Host smart-e4ee2c04-39f2-4f3a-a222-7df690c0a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546351297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2546351297
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2338896523
Short name T947
Test name
Test status
Simulation time 56700542628 ps
CPU time 307.87 seconds
Started Aug 03 05:27:50 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 250980 kb
Host smart-2bf66209-755b-42a2-a08a-baf011e824d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338896523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2338896523
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.564080795
Short name T903
Test name
Test status
Simulation time 5833767233 ps
CPU time 22.71 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:28:14 PM PDT 24
Peak memory 218320 kb
Host smart-34b2ef90-2c17-426f-b6d8-1a93bbc06c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564080795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.564080795
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2300916842
Short name T674
Test name
Test status
Simulation time 2206102005 ps
CPU time 28.23 seconds
Started Aug 03 05:27:50 PM PDT 24
Finished Aug 03 05:28:18 PM PDT 24
Peak memory 233552 kb
Host smart-f63e132f-21cd-4964-8078-37d9b6a5d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300916842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2300916842
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3537266652
Short name T709
Test name
Test status
Simulation time 2505389810 ps
CPU time 13.42 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 241772 kb
Host smart-6dd6879d-8fc5-4872-8d7e-25c1402c85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537266652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3537266652
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2335255234
Short name T538
Test name
Test status
Simulation time 820015689 ps
CPU time 5.7 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:52 PM PDT 24
Peak memory 225316 kb
Host smart-ac70ba86-6f1a-48a6-95cf-cc712a399128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335255234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2335255234
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.692251237
Short name T393
Test name
Test status
Simulation time 729472844 ps
CPU time 4 seconds
Started Aug 03 05:27:49 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 225172 kb
Host smart-042b4070-707e-41f2-bc31-2ed45701a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692251237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.692251237
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3866456833
Short name T378
Test name
Test status
Simulation time 96034715 ps
CPU time 2.36 seconds
Started Aug 03 05:27:49 PM PDT 24
Finished Aug 03 05:27:51 PM PDT 24
Peak memory 233112 kb
Host smart-6f8578be-a57e-4be5-b9bd-1b198ce403fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866456833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3866456833
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3456549510
Short name T516
Test name
Test status
Simulation time 2667378951 ps
CPU time 5.41 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:52 PM PDT 24
Peak memory 225312 kb
Host smart-720b5d1f-d1d6-4984-adb6-a3a39fffe638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456549510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3456549510
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1080487635
Short name T850
Test name
Test status
Simulation time 4437715327 ps
CPU time 11.77 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 220928 kb
Host smart-73b83d66-0ce9-4ecd-8f2d-63d32ef1ae8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1080487635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1080487635
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2446230551
Short name T411
Test name
Test status
Simulation time 10177042267 ps
CPU time 83.76 seconds
Started Aug 03 05:27:48 PM PDT 24
Finished Aug 03 05:29:11 PM PDT 24
Peak memory 251012 kb
Host smart-e2991e28-d1b4-422d-8a16-40b4b278b477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446230551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2446230551
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.862421536
Short name T997
Test name
Test status
Simulation time 11760459228 ps
CPU time 19.46 seconds
Started Aug 03 05:27:48 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 218736 kb
Host smart-d1061da3-7862-4e27-9db2-82b44374c8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862421536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.862421536
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2962919202
Short name T7
Test name
Test status
Simulation time 397909131 ps
CPU time 2.99 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:27:49 PM PDT 24
Peak memory 216916 kb
Host smart-b85d49ee-a4c7-4279-872c-7e5b44d013fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962919202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2962919202
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2451301192
Short name T641
Test name
Test status
Simulation time 819847805 ps
CPU time 1.32 seconds
Started Aug 03 05:27:50 PM PDT 24
Finished Aug 03 05:27:51 PM PDT 24
Peak memory 217028 kb
Host smart-9f76a2e0-90fd-4b3f-8caa-428135616e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451301192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2451301192
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4112054108
Short name T359
Test name
Test status
Simulation time 21884103 ps
CPU time 0.75 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 206516 kb
Host smart-0d1c888e-e47f-43ec-b228-404ea8b8d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112054108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4112054108
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.5808234
Short name T266
Test name
Test status
Simulation time 92828216 ps
CPU time 3.34 seconds
Started Aug 03 05:27:49 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 233456 kb
Host smart-381e497a-b119-4d54-be8e-7b4a874aca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5808234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.5808234
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.731872031
Short name T369
Test name
Test status
Simulation time 13548511 ps
CPU time 0.7 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 205876 kb
Host smart-f5d7bc8d-b391-43db-9ceb-9d463c90c76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731872031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.731872031
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2027133767
Short name T511
Test name
Test status
Simulation time 685458080 ps
CPU time 7.47 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 225320 kb
Host smart-19bbb23d-884b-4e39-b588-42f1b6cc3c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027133767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2027133767
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4092849835
Short name T425
Test name
Test status
Simulation time 44900590 ps
CPU time 0.82 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:27:53 PM PDT 24
Peak memory 207124 kb
Host smart-f881ce91-956e-4e9a-8174-0883c65d1cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092849835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4092849835
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3517337604
Short name T148
Test name
Test status
Simulation time 11188579023 ps
CPU time 75.14 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 257192 kb
Host smart-6aea7b0c-dc9d-4975-9bda-5fe75c104a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517337604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3517337604
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.182583542
Short name T468
Test name
Test status
Simulation time 6891678802 ps
CPU time 11.95 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 249936 kb
Host smart-0f9edaac-02ee-445d-a013-f99ac5ed2852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182583542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.182583542
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3504862028
Short name T948
Test name
Test status
Simulation time 732420215 ps
CPU time 15.99 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 237528 kb
Host smart-99289a7b-061a-4658-b0d7-fab2987e8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504862028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3504862028
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1233630716
Short name T732
Test name
Test status
Simulation time 2550804068 ps
CPU time 43.63 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:42 PM PDT 24
Peak memory 249944 kb
Host smart-7d7eb1b1-012a-4950-ad32-72e8a68164fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233630716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1233630716
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3791006989
Short name T97
Test name
Test status
Simulation time 2119101621 ps
CPU time 6.45 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 233396 kb
Host smart-852baec9-a0bc-4a55-9f07-670bbfdff6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791006989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3791006989
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1220863968
Short name T797
Test name
Test status
Simulation time 29843469647 ps
CPU time 54.86 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:53 PM PDT 24
Peak memory 234376 kb
Host smart-5682537f-3545-45c6-b883-4441e8b243a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220863968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1220863968
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2825138835
Short name T454
Test name
Test status
Simulation time 17229919692 ps
CPU time 15.67 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:28:10 PM PDT 24
Peak memory 233572 kb
Host smart-d409fece-583d-4111-827f-1b813106a177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825138835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2825138835
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2053425167
Short name T754
Test name
Test status
Simulation time 3676437906 ps
CPU time 7.33 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:28:01 PM PDT 24
Peak memory 225272 kb
Host smart-71912ed3-3583-479e-89bd-23afd8c1cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053425167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2053425167
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.75232857
Short name T436
Test name
Test status
Simulation time 1213505170 ps
CPU time 16.32 seconds
Started Aug 03 05:27:52 PM PDT 24
Finished Aug 03 05:28:09 PM PDT 24
Peak memory 223236 kb
Host smart-4fe2fc0d-3d41-47a4-90d8-e64b018814a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75232857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.75232857
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1874951719
Short name T513
Test name
Test status
Simulation time 13764188723 ps
CPU time 38.72 seconds
Started Aug 03 05:27:46 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 216988 kb
Host smart-537f90ae-1d5c-4d7a-a380-c67866702283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874951719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1874951719
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2388668017
Short name T416
Test name
Test status
Simulation time 1031096584 ps
CPU time 6.21 seconds
Started Aug 03 05:27:49 PM PDT 24
Finished Aug 03 05:27:55 PM PDT 24
Peak memory 216996 kb
Host smart-2f9a2006-763a-4d3f-8649-19931a1dc4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388668017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2388668017
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3015888032
Short name T373
Test name
Test status
Simulation time 78534793 ps
CPU time 3.59 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:27:55 PM PDT 24
Peak memory 217000 kb
Host smart-eb6d7d0b-77b1-42d5-ba02-0a9c67684b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015888032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3015888032
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2106810814
Short name T469
Test name
Test status
Simulation time 23135126 ps
CPU time 0.81 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 206516 kb
Host smart-46d81a50-2d2d-4718-ac43-5f0d7b5f0bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106810814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2106810814
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.103923537
Short name T178
Test name
Test status
Simulation time 6988065551 ps
CPU time 27.77 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:28:21 PM PDT 24
Peak memory 233544 kb
Host smart-b39253cb-8380-4baf-a735-8ffecb1a7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103923537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.103923537
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1820267014
Short name T67
Test name
Test status
Simulation time 26676309 ps
CPU time 0.76 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 205868 kb
Host smart-46834338-585f-4464-9905-653b7f362f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820267014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1820267014
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3551342270
Short name T740
Test name
Test status
Simulation time 1570485133 ps
CPU time 6.59 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:04 PM PDT 24
Peak memory 233484 kb
Host smart-df474bbf-c4b3-4449-81ef-e019c30f8470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551342270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3551342270
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3936797152
Short name T350
Test name
Test status
Simulation time 66705049 ps
CPU time 0.75 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 207440 kb
Host smart-6c50fdd1-f698-4a7e-917e-2202b6fa4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936797152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3936797152
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3193366929
Short name T238
Test name
Test status
Simulation time 40189195743 ps
CPU time 200.22 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:31:19 PM PDT 24
Peak memory 256792 kb
Host smart-18cdead0-40ac-4a8d-8a8c-6a2e0cf04f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193366929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3193366929
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1032314694
Short name T623
Test name
Test status
Simulation time 37455689459 ps
CPU time 68.09 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:29:07 PM PDT 24
Peak memory 252796 kb
Host smart-eb006b92-5a46-43c2-80f4-325a3cc4a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032314694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1032314694
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1731232245
Short name T207
Test name
Test status
Simulation time 3697428971 ps
CPU time 86.36 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:29:23 PM PDT 24
Peak memory 258132 kb
Host smart-ce75b122-66a9-4f40-a286-f5f7533e99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731232245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1731232245
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3008543666
Short name T842
Test name
Test status
Simulation time 118378422 ps
CPU time 2.39 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:27:57 PM PDT 24
Peak memory 225252 kb
Host smart-ee4dc8dd-8cdb-4f95-9a53-6dc2ee91b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008543666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3008543666
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3856821122
Short name T80
Test name
Test status
Simulation time 19347106582 ps
CPU time 194.95 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:31:13 PM PDT 24
Peak memory 270856 kb
Host smart-b1685d83-6c50-49b3-a610-2f997b7ba151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856821122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3856821122
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2381273990
Short name T588
Test name
Test status
Simulation time 294747563 ps
CPU time 4.51 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 233540 kb
Host smart-db3f5455-8c3c-4225-9cd1-cce848639a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381273990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2381273990
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.980122791
Short name T488
Test name
Test status
Simulation time 4580537520 ps
CPU time 37.03 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 233520 kb
Host smart-5301be13-6302-498d-967b-8a90632fd03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980122791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.980122791
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2059740710
Short name T2
Test name
Test status
Simulation time 19886456323 ps
CPU time 18.08 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 241076 kb
Host smart-8cb0f3e4-7fb7-4d35-9c6e-32cd4bcf0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059740710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2059740710
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4026915339
Short name T830
Test name
Test status
Simulation time 2315469629 ps
CPU time 5.81 seconds
Started Aug 03 05:27:51 PM PDT 24
Finished Aug 03 05:27:57 PM PDT 24
Peak memory 233544 kb
Host smart-4bc9086b-05c6-4928-a13d-afaed8f26725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026915339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4026915339
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3747906183
Short name T448
Test name
Test status
Simulation time 276446042 ps
CPU time 3.84 seconds
Started Aug 03 05:27:56 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 223180 kb
Host smart-893061d0-96a5-4f3d-9c3b-ccf8ba71e93f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3747906183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3747906183
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3986986736
Short name T946
Test name
Test status
Simulation time 41575362150 ps
CPU time 163.61 seconds
Started Aug 03 05:27:55 PM PDT 24
Finished Aug 03 05:30:39 PM PDT 24
Peak memory 266328 kb
Host smart-1f786b12-4ca0-4469-83f7-3d7d075772ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986986736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3986986736
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.170828605
Short name T592
Test name
Test status
Simulation time 3826715460 ps
CPU time 12.74 seconds
Started Aug 03 05:27:55 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 217056 kb
Host smart-ec12f566-f120-4e97-a4a5-9cbebb7771da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170828605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.170828605
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3761828301
Short name T861
Test name
Test status
Simulation time 12194877558 ps
CPU time 15.52 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:28:09 PM PDT 24
Peak memory 217084 kb
Host smart-cc9362ae-67f7-43a7-bc05-9c57181b9d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761828301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3761828301
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.871768995
Short name T398
Test name
Test status
Simulation time 28827904 ps
CPU time 1.18 seconds
Started Aug 03 05:27:53 PM PDT 24
Finished Aug 03 05:27:54 PM PDT 24
Peak memory 216748 kb
Host smart-d892adf0-5277-46ad-8064-7b1dfd053418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871768995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.871768995
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1563618473
Short name T986
Test name
Test status
Simulation time 70830183 ps
CPU time 0.95 seconds
Started Aug 03 05:27:54 PM PDT 24
Finished Aug 03 05:27:55 PM PDT 24
Peak memory 207632 kb
Host smart-ac4bec2b-1a5d-41a4-9e86-97454b434f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563618473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1563618473
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2821790203
Short name T879
Test name
Test status
Simulation time 1358040855 ps
CPU time 6.05 seconds
Started Aug 03 05:27:56 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 233444 kb
Host smart-99145d79-2068-47d7-bad7-67bf85e7c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821790203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2821790203
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3617218064
Short name T83
Test name
Test status
Simulation time 20486732 ps
CPU time 0.75 seconds
Started Aug 03 05:28:02 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 205316 kb
Host smart-1486d092-b649-4909-b957-8dfae518a6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617218064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3617218064
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3089490123
Short name T852
Test name
Test status
Simulation time 177001638 ps
CPU time 2.41 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 233396 kb
Host smart-a1b6dee4-29bf-4a2c-848d-756e50835e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089490123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3089490123
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2126151712
Short name T382
Test name
Test status
Simulation time 64148222 ps
CPU time 0.76 seconds
Started Aug 03 05:28:02 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 207088 kb
Host smart-975d9b37-2bc7-4b65-a9d4-a62ccd384a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126151712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2126151712
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2510673751
Short name T742
Test name
Test status
Simulation time 73490645108 ps
CPU time 298.38 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 255108 kb
Host smart-16d5c7ef-82ee-4a6f-97c7-5cb52c86f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510673751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2510673751
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.6160666
Short name T247
Test name
Test status
Simulation time 16030361873 ps
CPU time 172.67 seconds
Started Aug 03 05:28:00 PM PDT 24
Finished Aug 03 05:30:52 PM PDT 24
Peak memory 257372 kb
Host smart-61c600d0-4e82-4262-996e-798bb9c80644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6160666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.6160666
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4001799024
Short name T429
Test name
Test status
Simulation time 31791894116 ps
CPU time 79.13 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:29:17 PM PDT 24
Peak memory 255444 kb
Host smart-3525c4c5-96be-4120-9607-7c4eee0239dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001799024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4001799024
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2837808713
Short name T557
Test name
Test status
Simulation time 322083392 ps
CPU time 3.58 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:28:01 PM PDT 24
Peak memory 225172 kb
Host smart-30b205a4-13be-4cc3-b6de-9ea46b1a1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837808713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2837808713
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2250495343
Short name T1011
Test name
Test status
Simulation time 3922798161 ps
CPU time 36.7 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:28:35 PM PDT 24
Peak memory 241760 kb
Host smart-756fdbb5-b4a9-45bd-bd0a-e813062792e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250495343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2250495343
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.105073603
Short name T701
Test name
Test status
Simulation time 538436257 ps
CPU time 8.15 seconds
Started Aug 03 05:28:02 PM PDT 24
Finished Aug 03 05:28:11 PM PDT 24
Peak memory 232484 kb
Host smart-ec388d60-b77d-4d32-9196-784b447be305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105073603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.105073603
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3812606166
Short name T234
Test name
Test status
Simulation time 945617265 ps
CPU time 22.67 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:28:22 PM PDT 24
Peak memory 225172 kb
Host smart-1d4333ac-a832-4bc2-95c4-1a5717552cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812606166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3812606166
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2419773196
Short name T872
Test name
Test status
Simulation time 761336029 ps
CPU time 4.75 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 241456 kb
Host smart-77cc8924-5e74-44ae-ab86-91f8278b8c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419773196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2419773196
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1735918287
Short name T735
Test name
Test status
Simulation time 8540728126 ps
CPU time 15.5 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 236496 kb
Host smart-aec29f49-1de3-4654-a9cc-514366536695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735918287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1735918287
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4177688659
Short name T467
Test name
Test status
Simulation time 1812971891 ps
CPU time 16.36 seconds
Started Aug 03 05:28:03 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 222728 kb
Host smart-d5d1f696-8d0b-45c6-bbb8-580aba333572
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4177688659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4177688659
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1205296852
Short name T235
Test name
Test status
Simulation time 3500184984 ps
CPU time 57.31 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:29:02 PM PDT 24
Peak memory 256620 kb
Host smart-88440e33-2131-4753-95b5-cd99173d67c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205296852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1205296852
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.931615310
Short name T749
Test name
Test status
Simulation time 5387189506 ps
CPU time 25.95 seconds
Started Aug 03 05:28:02 PM PDT 24
Finished Aug 03 05:28:28 PM PDT 24
Peak memory 215680 kb
Host smart-08ccc4d6-6db5-4425-9d8b-d031a49972dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931615310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.931615310
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2283415144
Short name T668
Test name
Test status
Simulation time 3021541651 ps
CPU time 6.66 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 217116 kb
Host smart-992ee100-7fb1-41ab-84ad-073f7ac24538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283415144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2283415144
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3483948228
Short name T53
Test name
Test status
Simulation time 101366689 ps
CPU time 0.98 seconds
Started Aug 03 05:28:04 PM PDT 24
Finished Aug 03 05:28:05 PM PDT 24
Peak memory 207812 kb
Host smart-bce31120-da52-443c-8923-b8ba46df2db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483948228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3483948228
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.295985001
Short name T950
Test name
Test status
Simulation time 16884457 ps
CPU time 0.76 seconds
Started Aug 03 05:28:01 PM PDT 24
Finished Aug 03 05:28:02 PM PDT 24
Peak memory 206580 kb
Host smart-d0d86358-1748-4131-8154-31e98ed45bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295985001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.295985001
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1404462151
Short name T441
Test name
Test status
Simulation time 20805650527 ps
CPU time 13.88 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:28:11 PM PDT 24
Peak memory 229388 kb
Host smart-77e587fb-090c-4597-8921-cddd5a35dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404462151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1404462151
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2096417674
Short name T374
Test name
Test status
Simulation time 45214496 ps
CPU time 0.74 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 206204 kb
Host smart-67035cd4-8267-4aa6-b2e3-2ffc01bb3708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096417674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2096417674
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2255278681
Short name T292
Test name
Test status
Simulation time 465486644 ps
CPU time 5.52 seconds
Started Aug 03 05:28:14 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 233484 kb
Host smart-23d992ca-ed33-405e-a404-a0f26f314697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255278681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2255278681
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3275566839
Short name T407
Test name
Test status
Simulation time 13645805 ps
CPU time 0.78 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:27:59 PM PDT 24
Peak memory 207416 kb
Host smart-9e50c814-9a05-4107-a61c-594a3ea39668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275566839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3275566839
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3701338879
Short name T589
Test name
Test status
Simulation time 3237732071 ps
CPU time 20.3 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:29 PM PDT 24
Peak memory 225288 kb
Host smart-edd40726-1c1d-4e9c-b43a-aebb742b3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701338879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3701338879
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3759993605
Short name T197
Test name
Test status
Simulation time 33965315221 ps
CPU time 75.56 seconds
Started Aug 03 05:28:08 PM PDT 24
Finished Aug 03 05:29:23 PM PDT 24
Peak memory 256508 kb
Host smart-ec79cb2e-4ea9-4eac-974a-cf56dec2a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759993605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3759993605
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2032450242
Short name T242
Test name
Test status
Simulation time 5057643452 ps
CPU time 89.07 seconds
Started Aug 03 05:28:08 PM PDT 24
Finished Aug 03 05:29:37 PM PDT 24
Peak memory 252780 kb
Host smart-c3a39082-0208-44cb-96e1-e922dbf1b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032450242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2032450242
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3838419919
Short name T236
Test name
Test status
Simulation time 587814992 ps
CPU time 8.92 seconds
Started Aug 03 05:28:06 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 225236 kb
Host smart-ac103a46-2b96-4b3b-89f9-f0154199fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838419919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3838419919
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1400466406
Short name T99
Test name
Test status
Simulation time 68447545727 ps
CPU time 132 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:30:17 PM PDT 24
Peak memory 253968 kb
Host smart-6ef36301-8251-4fcd-b513-01e3cf908db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400466406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1400466406
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.117873555
Short name T806
Test name
Test status
Simulation time 1445108893 ps
CPU time 6.08 seconds
Started Aug 03 05:28:07 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 233464 kb
Host smart-0deb8474-853b-4b1a-a52c-7c0110071d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117873555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.117873555
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4269855744
Short name T798
Test name
Test status
Simulation time 12756200713 ps
CPU time 33.32 seconds
Started Aug 03 05:28:04 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 229620 kb
Host smart-683ed884-665a-43df-af14-08e564666c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269855744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4269855744
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2909536907
Short name T536
Test name
Test status
Simulation time 10470384009 ps
CPU time 15.55 seconds
Started Aug 03 05:28:14 PM PDT 24
Finished Aug 03 05:28:30 PM PDT 24
Peak memory 225244 kb
Host smart-e917f15d-9e48-4689-85ed-4bdfdc7de038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909536907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2909536907
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2880964302
Short name T101
Test name
Test status
Simulation time 2576349381 ps
CPU time 2.45 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 225340 kb
Host smart-74a0b2ea-e04a-4b77-a6af-795146e0b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880964302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2880964302
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1008401758
Short name T660
Test name
Test status
Simulation time 1133470097 ps
CPU time 12.4 seconds
Started Aug 03 05:28:14 PM PDT 24
Finished Aug 03 05:28:26 PM PDT 24
Peak memory 223196 kb
Host smart-b0d44360-e18a-4595-a145-1f6060c2918c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008401758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1008401758
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3588095764
Short name T34
Test name
Test status
Simulation time 320959527805 ps
CPU time 689.5 seconds
Started Aug 03 05:28:06 PM PDT 24
Finished Aug 03 05:39:36 PM PDT 24
Peak memory 266396 kb
Host smart-90ceef73-cb52-41bf-8215-9d89e642e0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588095764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3588095764
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1505971212
Short name T540
Test name
Test status
Simulation time 617549593 ps
CPU time 7.92 seconds
Started Aug 03 05:27:58 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 218904 kb
Host smart-f4abe582-f48a-4245-9310-2281b888cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505971212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1505971212
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1456831879
Short name T512
Test name
Test status
Simulation time 848399920 ps
CPU time 4.01 seconds
Started Aug 03 05:27:57 PM PDT 24
Finished Aug 03 05:28:01 PM PDT 24
Peak memory 216944 kb
Host smart-e4a6f75c-db1f-48c3-bbdf-5a8e582a3399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456831879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1456831879
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3495005834
Short name T587
Test name
Test status
Simulation time 11816873 ps
CPU time 0.77 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:06 PM PDT 24
Peak memory 206140 kb
Host smart-c8b73314-c2ba-4930-895a-b28c27c9a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495005834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3495005834
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1464748484
Short name T689
Test name
Test status
Simulation time 41115637 ps
CPU time 0.68 seconds
Started Aug 03 05:27:59 PM PDT 24
Finished Aug 03 05:28:00 PM PDT 24
Peak memory 206144 kb
Host smart-3e08dffa-b7ca-4135-b001-65ed98b82e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464748484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1464748484
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4129993726
Short name T521
Test name
Test status
Simulation time 13493964897 ps
CPU time 14.43 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:19 PM PDT 24
Peak memory 233472 kb
Host smart-d7549b61-47e0-428b-949c-a1ac598585f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129993726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4129993726
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2579839940
Short name T743
Test name
Test status
Simulation time 12960269 ps
CPU time 0.71 seconds
Started Aug 03 05:28:15 PM PDT 24
Finished Aug 03 05:28:16 PM PDT 24
Peak memory 205296 kb
Host smart-95a13ee7-80e8-4c53-a3f9-0ba7eec8b964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579839940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2579839940
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3318118837
Short name T347
Test name
Test status
Simulation time 162987645 ps
CPU time 4.3 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 233496 kb
Host smart-6967973b-3e72-482c-8332-0fdbf8d2e8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318118837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3318118837
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3538433530
Short name T477
Test name
Test status
Simulation time 19191553 ps
CPU time 0.77 seconds
Started Aug 03 05:28:07 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 207324 kb
Host smart-487c26d6-71e1-4fe8-a669-81f47cb210d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538433530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3538433530
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2260743572
Short name T26
Test name
Test status
Simulation time 2008039048 ps
CPU time 39.31 seconds
Started Aug 03 05:28:15 PM PDT 24
Finished Aug 03 05:28:54 PM PDT 24
Peak memory 256252 kb
Host smart-43e2b08c-9eff-4517-9783-c2118d34fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260743572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2260743572
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1711857412
Short name T206
Test name
Test status
Simulation time 47540211236 ps
CPU time 67.64 seconds
Started Aug 03 05:28:06 PM PDT 24
Finished Aug 03 05:29:14 PM PDT 24
Peak memory 265952 kb
Host smart-8d0d60d3-9a53-4a82-aa6f-ccc3e4dab5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711857412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1711857412
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1005525729
Short name T942
Test name
Test status
Simulation time 89816997895 ps
CPU time 149.07 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:30:35 PM PDT 24
Peak memory 253208 kb
Host smart-52682e83-c0f4-47a7-aad9-911d14ccda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005525729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1005525729
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2090193078
Short name T595
Test name
Test status
Simulation time 36524160030 ps
CPU time 30.24 seconds
Started Aug 03 05:28:08 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 235252 kb
Host smart-c0ae2173-ab56-47e5-a588-641116acf716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090193078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2090193078
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.307967011
Short name T865
Test name
Test status
Simulation time 72849557271 ps
CPU time 134.43 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:30:20 PM PDT 24
Peak memory 249956 kb
Host smart-2b191303-073b-4996-8eae-33ff486814fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307967011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.307967011
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1854432138
Short name T704
Test name
Test status
Simulation time 355410760 ps
CPU time 3.14 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 233500 kb
Host smart-5a2225fa-b00b-4355-af50-2f8ea0b715d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854432138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1854432138
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3783154706
Short name T558
Test name
Test status
Simulation time 10644451589 ps
CPU time 93.16 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:29:38 PM PDT 24
Peak memory 241768 kb
Host smart-3d530aaf-2258-4a2a-82ba-32042ddf9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783154706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3783154706
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3094231223
Short name T706
Test name
Test status
Simulation time 1164991202 ps
CPU time 5.04 seconds
Started Aug 03 05:28:06 PM PDT 24
Finished Aug 03 05:28:11 PM PDT 24
Peak memory 241384 kb
Host smart-e7375658-98ce-4112-9de9-bca6b800e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094231223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3094231223
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2546122596
Short name T715
Test name
Test status
Simulation time 1045252402 ps
CPU time 5.46 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 233460 kb
Host smart-31171727-e368-4dbc-8e2d-b394f017ab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546122596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2546122596
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2043118886
Short name T794
Test name
Test status
Simulation time 696475096 ps
CPU time 6.8 seconds
Started Aug 03 05:28:08 PM PDT 24
Finished Aug 03 05:28:14 PM PDT 24
Peak memory 223792 kb
Host smart-a83421ca-5145-4e83-b1a7-98374de2a3bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2043118886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2043118886
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3927162440
Short name T170
Test name
Test status
Simulation time 59175130 ps
CPU time 1.1 seconds
Started Aug 03 05:28:06 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 207460 kb
Host smart-72084456-24a7-4055-a00f-633f9a35c284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927162440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3927162440
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1821400565
Short name T487
Test name
Test status
Simulation time 11439305942 ps
CPU time 54.43 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:29:00 PM PDT 24
Peak memory 217036 kb
Host smart-493b2e10-5c16-4fe8-86ce-d46afcd310ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821400565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1821400565
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2156058325
Short name T1027
Test name
Test status
Simulation time 3866628347 ps
CPU time 10.55 seconds
Started Aug 03 05:28:15 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 217116 kb
Host smart-a57190c8-1f28-4c07-a823-be7a648bf1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156058325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2156058325
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2055597928
Short name T927
Test name
Test status
Simulation time 116882343 ps
CPU time 1.52 seconds
Started Aug 03 05:28:13 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 217032 kb
Host smart-a1b065c8-1d8b-4e7d-83c1-c5c547c053fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055597928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2055597928
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3520195335
Short name T901
Test name
Test status
Simulation time 452996045 ps
CPU time 1.04 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:07 PM PDT 24
Peak memory 207560 kb
Host smart-bfc756d4-3007-4915-bc61-79337d58fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520195335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3520195335
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3241591864
Short name T227
Test name
Test status
Simulation time 16788720836 ps
CPU time 34.09 seconds
Started Aug 03 05:28:07 PM PDT 24
Finished Aug 03 05:28:41 PM PDT 24
Peak memory 225276 kb
Host smart-e01ea17f-6cca-4e60-8a19-a034e38bc723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241591864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3241591864
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4100689616
Short name T675
Test name
Test status
Simulation time 61931947 ps
CPU time 0.69 seconds
Started Aug 03 05:28:13 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 205324 kb
Host smart-e31990cf-40dd-474e-b271-14d25043514d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100689616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4100689616
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.33489188
Short name T553
Test name
Test status
Simulation time 3339730328 ps
CPU time 15.04 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:24 PM PDT 24
Peak memory 225252 kb
Host smart-25e6ff36-417b-496a-a62d-a86faf593eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33489188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.33489188
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3412168710
Short name T627
Test name
Test status
Simulation time 62499272 ps
CPU time 0.77 seconds
Started Aug 03 05:28:05 PM PDT 24
Finished Aug 03 05:28:05 PM PDT 24
Peak memory 207052 kb
Host smart-27c55afc-c05c-489a-bc01-af6bd3bcc548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412168710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3412168710
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.611399680
Short name T342
Test name
Test status
Simulation time 19617936 ps
CPU time 0.76 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 216488 kb
Host smart-47ea27c6-17d2-4ced-b316-46163e0fa827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611399680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.611399680
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4147995267
Short name T522
Test name
Test status
Simulation time 1771512483 ps
CPU time 23.87 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:35 PM PDT 24
Peak memory 253504 kb
Host smart-b4cb4455-a70a-452b-9293-370d91c84470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147995267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4147995267
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1801120535
Short name T917
Test name
Test status
Simulation time 52274531623 ps
CPU time 472.42 seconds
Started Aug 03 05:28:12 PM PDT 24
Finished Aug 03 05:36:04 PM PDT 24
Peak memory 251012 kb
Host smart-01f8a060-c8b7-4ec9-9307-126e7bff6188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801120535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1801120535
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.589518084
Short name T649
Test name
Test status
Simulation time 2953871407 ps
CPU time 6.88 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:16 PM PDT 24
Peak memory 233528 kb
Host smart-e3dd5b2f-f211-4a39-bd33-78dabf5be13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589518084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.589518084
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.924223252
Short name T193
Test name
Test status
Simulation time 6333887637 ps
CPU time 81.9 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:29:32 PM PDT 24
Peak memory 266156 kb
Host smart-21ff7c91-8019-4f6f-8270-e37015e3e994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924223252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.924223252
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3286347468
Short name T702
Test name
Test status
Simulation time 353564351 ps
CPU time 5.05 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 233456 kb
Host smart-239be712-419b-4167-bd9a-9922ed9457a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286347468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3286347468
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.112192994
Short name T507
Test name
Test status
Simulation time 12171694042 ps
CPU time 21.47 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 225336 kb
Host smart-821ced88-8462-4470-b4a9-5f66cbbaefc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112192994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.112192994
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.367989603
Short name T577
Test name
Test status
Simulation time 64155965 ps
CPU time 2.58 seconds
Started Aug 03 05:28:13 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 233480 kb
Host smart-52e0c0b6-5e9f-4146-9615-c327a82da84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367989603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.367989603
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.307276350
Short name T822
Test name
Test status
Simulation time 236103219 ps
CPU time 3.98 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:14 PM PDT 24
Peak memory 225280 kb
Host smart-2aee4a2d-d078-45fc-b356-3826a3000bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307276350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.307276350
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1061952466
Short name T525
Test name
Test status
Simulation time 2201522081 ps
CPU time 6.43 seconds
Started Aug 03 05:28:09 PM PDT 24
Finished Aug 03 05:28:15 PM PDT 24
Peak memory 219760 kb
Host smart-815b1fdb-b4fd-4cca-8d0b-db4a9995678a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1061952466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1061952466
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1471290059
Short name T245
Test name
Test status
Simulation time 29953099782 ps
CPU time 105.95 seconds
Started Aug 03 05:28:12 PM PDT 24
Finished Aug 03 05:29:58 PM PDT 24
Peak memory 249964 kb
Host smart-24daee56-7376-4cab-971e-df9ea4620116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471290059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1471290059
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2123854247
Short name T722
Test name
Test status
Simulation time 1348893942 ps
CPU time 14.83 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 217288 kb
Host smart-052bdabf-430a-4099-9046-28536eece9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123854247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2123854247
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2822416756
Short name T560
Test name
Test status
Simulation time 18261830829 ps
CPU time 14.56 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 217132 kb
Host smart-594f6a82-7048-42ea-af11-2fd860e3d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822416756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2822416756
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.109737025
Short name T750
Test name
Test status
Simulation time 10457058 ps
CPU time 0.7 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:11 PM PDT 24
Peak memory 206104 kb
Host smart-63390787-1307-40d5-ace6-d397fed632c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109737025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.109737025
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2907457973
Short name T349
Test name
Test status
Simulation time 88528234 ps
CPU time 0.77 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 206600 kb
Host smart-ae7bcdbc-a91e-4f68-95f7-97c2c350bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907457973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2907457973
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3169391277
Short name T216
Test name
Test status
Simulation time 30178934886 ps
CPU time 20.67 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 225364 kb
Host smart-df0eb1ae-83db-4e20-965c-3f4062181d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169391277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3169391277
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.200740893
Short name T710
Test name
Test status
Simulation time 22190829 ps
CPU time 0.71 seconds
Started Aug 03 05:28:18 PM PDT 24
Finished Aug 03 05:28:19 PM PDT 24
Peak memory 205896 kb
Host smart-55599c96-cdb1-4bc2-97f7-5760237e4f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200740893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.200740893
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3293655100
Short name T195
Test name
Test status
Simulation time 163102827 ps
CPU time 2.56 seconds
Started Aug 03 05:28:18 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 225236 kb
Host smart-bb39bdba-a485-4a06-ba5f-ea82dcfed9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293655100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3293655100
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2357565571
Short name T606
Test name
Test status
Simulation time 14507761 ps
CPU time 0.78 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:12 PM PDT 24
Peak memory 207092 kb
Host smart-6660d4e5-52e2-45fa-b2d4-28810b82cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357565571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2357565571
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1520537944
Short name T983
Test name
Test status
Simulation time 4767201943 ps
CPU time 21.85 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 225340 kb
Host smart-c36016f4-0697-4e3b-b185-742a4562a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520537944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1520537944
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.453801416
Short name T1034
Test name
Test status
Simulation time 109984321370 ps
CPU time 222.18 seconds
Started Aug 03 05:28:15 PM PDT 24
Finished Aug 03 05:31:58 PM PDT 24
Peak memory 250472 kb
Host smart-b96e6275-3f89-4a71-92a6-2e1c59e1272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453801416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.453801416
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3108307611
Short name T823
Test name
Test status
Simulation time 29867566810 ps
CPU time 62.45 seconds
Started Aug 03 05:28:20 PM PDT 24
Finished Aug 03 05:29:23 PM PDT 24
Peak memory 240812 kb
Host smart-b5b43e10-c6c1-4da8-87ed-5946395847c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108307611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3108307611
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_intercept.630063320
Short name T249
Test name
Test status
Simulation time 374577353 ps
CPU time 3.7 seconds
Started Aug 03 05:28:19 PM PDT 24
Finished Aug 03 05:28:23 PM PDT 24
Peak memory 233452 kb
Host smart-11101623-8b87-4e7e-b201-f63aa1546ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630063320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.630063320
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2748192349
Short name T29
Test name
Test status
Simulation time 14737845665 ps
CPU time 70.93 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:29:28 PM PDT 24
Peak memory 249916 kb
Host smart-77105ab4-3107-4b5a-9c32-e1cc494ed1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748192349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2748192349
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2548878293
Short name T9
Test name
Test status
Simulation time 3300743285 ps
CPU time 10.23 seconds
Started Aug 03 05:28:16 PM PDT 24
Finished Aug 03 05:28:27 PM PDT 24
Peak memory 233484 kb
Host smart-e74e4eaa-4920-458b-afe2-60dfaabdb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548878293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2548878293
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2800335931
Short name T274
Test name
Test status
Simulation time 270130996 ps
CPU time 5.57 seconds
Started Aug 03 05:28:18 PM PDT 24
Finished Aug 03 05:28:24 PM PDT 24
Peak memory 241304 kb
Host smart-29e49bdc-ea2e-4cf7-a5c9-198308a0a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800335931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2800335931
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1136723583
Short name T158
Test name
Test status
Simulation time 3545477613 ps
CPU time 12.46 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:28:29 PM PDT 24
Peak memory 221916 kb
Host smart-e53538de-986c-41f3-acb8-48f33f3954e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136723583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1136723583
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2115739032
Short name T843
Test name
Test status
Simulation time 17280028181 ps
CPU time 48.22 seconds
Started Aug 03 05:28:15 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 225364 kb
Host smart-dac43e27-427f-4def-8d6a-68951e36909f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115739032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2115739032
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2927049189
Short name T325
Test name
Test status
Simulation time 13170311018 ps
CPU time 25.88 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 217244 kb
Host smart-4d630041-98e5-4bfd-9b0d-0e3460405197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927049189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2927049189
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2562841634
Short name T654
Test name
Test status
Simulation time 2372499235 ps
CPU time 2.22 seconds
Started Aug 03 05:28:11 PM PDT 24
Finished Aug 03 05:28:13 PM PDT 24
Peak memory 208604 kb
Host smart-ce9eb0c4-48a2-4e85-a9a9-2c6bb2e5f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562841634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2562841634
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1011209972
Short name T763
Test name
Test status
Simulation time 47812586 ps
CPU time 1.33 seconds
Started Aug 03 05:28:19 PM PDT 24
Finished Aug 03 05:28:21 PM PDT 24
Peak memory 217012 kb
Host smart-c62638f6-0292-4eb5-8ad7-ad928525e0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011209972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1011209972
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.706237330
Short name T792
Test name
Test status
Simulation time 20693667 ps
CPU time 0.77 seconds
Started Aug 03 05:28:10 PM PDT 24
Finished Aug 03 05:28:11 PM PDT 24
Peak memory 206612 kb
Host smart-d93d49b1-02d2-4135-84f3-a9aef7533078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706237330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.706237330
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.344988122
Short name T638
Test name
Test status
Simulation time 11854575533 ps
CPU time 13.58 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 233560 kb
Host smart-2a0d773e-0821-4289-a701-ff09640806b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344988122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.344988122
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1852223279
Short name T140
Test name
Test status
Simulation time 63406710 ps
CPU time 0.73 seconds
Started Aug 03 05:28:22 PM PDT 24
Finished Aug 03 05:28:23 PM PDT 24
Peak memory 206228 kb
Host smart-1b6ac24d-4e75-47bb-ac2a-2053af27f814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852223279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1852223279
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1852450075
Short name T1024
Test name
Test status
Simulation time 2438670260 ps
CPU time 6.16 seconds
Started Aug 03 05:28:18 PM PDT 24
Finished Aug 03 05:28:24 PM PDT 24
Peak memory 233644 kb
Host smart-bd34192d-d0fc-4eff-9dec-5e5b1dcba7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852450075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1852450075
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3193096858
Short name T726
Test name
Test status
Simulation time 52000835 ps
CPU time 0.77 seconds
Started Aug 03 05:28:19 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 207016 kb
Host smart-9e3c82c3-e95b-473c-9ab5-9e4555800435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193096858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3193096858
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2952585640
Short name T756
Test name
Test status
Simulation time 12747346 ps
CPU time 0.77 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:28:22 PM PDT 24
Peak memory 216632 kb
Host smart-a5cf8dd1-c8c2-4b10-9832-67305c847616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952585640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2952585640
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3697383320
Short name T270
Test name
Test status
Simulation time 97043388555 ps
CPU time 289.16 seconds
Started Aug 03 05:28:23 PM PDT 24
Finished Aug 03 05:33:13 PM PDT 24
Peak memory 262740 kb
Host smart-2b6bff2f-07fe-46b8-aa40-7a9b4441ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697383320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3697383320
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.21809205
Short name T672
Test name
Test status
Simulation time 6094779443 ps
CPU time 29.09 seconds
Started Aug 03 05:28:20 PM PDT 24
Finished Aug 03 05:28:49 PM PDT 24
Peak memory 225340 kb
Host smart-d18284fd-40c8-4d61-94f7-bd5a8ad90b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21809205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.21809205
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4240682026
Short name T93
Test name
Test status
Simulation time 1838274357 ps
CPU time 18.47 seconds
Started Aug 03 05:28:16 PM PDT 24
Finished Aug 03 05:28:35 PM PDT 24
Peak memory 225268 kb
Host smart-09274626-5aba-41d9-a69c-795da645ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240682026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4240682026
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3476300239
Short name T55
Test name
Test status
Simulation time 111996159448 ps
CPU time 202.3 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:31:44 PM PDT 24
Peak memory 258100 kb
Host smart-66b0a83d-9e56-46df-961d-4f3a627c3bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476300239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3476300239
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3177095218
Short name T537
Test name
Test status
Simulation time 108181779 ps
CPU time 2.47 seconds
Started Aug 03 05:28:16 PM PDT 24
Finished Aug 03 05:28:19 PM PDT 24
Peak memory 225276 kb
Host smart-3bf2396f-c2c9-4369-ae09-c79d493156a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177095218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3177095218
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3206703476
Short name T853
Test name
Test status
Simulation time 103395866 ps
CPU time 2.3 seconds
Started Aug 03 05:28:19 PM PDT 24
Finished Aug 03 05:28:22 PM PDT 24
Peak memory 223756 kb
Host smart-6873f57d-8a86-4bf9-b3f4-0bd296c46568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206703476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3206703476
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2280952456
Short name T991
Test name
Test status
Simulation time 14823828847 ps
CPU time 13.04 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 233420 kb
Host smart-7ae10df6-1b71-4b53-90e8-0532f04cdb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280952456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2280952456
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3970431307
Short name T1008
Test name
Test status
Simulation time 1717570257 ps
CPU time 8.09 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 240772 kb
Host smart-537c70a0-21b2-41c9-bd0b-4f8be759ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970431307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3970431307
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3300641993
Short name T375
Test name
Test status
Simulation time 1957267354 ps
CPU time 5.59 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:28:27 PM PDT 24
Peak memory 223736 kb
Host smart-a73e36c9-782a-42d3-8000-0302d2f6daea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3300641993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3300641993
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2699963330
Short name T337
Test name
Test status
Simulation time 17179991125 ps
CPU time 26.35 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:28:43 PM PDT 24
Peak memory 216972 kb
Host smart-871295db-5ed8-49a1-92ce-3468ea46914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699963330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2699963330
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1548770573
Short name T450
Test name
Test status
Simulation time 1377277317 ps
CPU time 4.41 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:28 PM PDT 24
Peak memory 216764 kb
Host smart-ab41eab1-dddf-413d-83c9-824afd7ca912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548770573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1548770573
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2593535568
Short name T81
Test name
Test status
Simulation time 59066649 ps
CPU time 0.67 seconds
Started Aug 03 05:28:16 PM PDT 24
Finished Aug 03 05:28:17 PM PDT 24
Peak memory 206116 kb
Host smart-753424d0-67ad-42eb-b6f0-0c8c52daad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593535568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2593535568
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3652807798
Short name T344
Test name
Test status
Simulation time 40649077 ps
CPU time 0.84 seconds
Started Aug 03 05:28:20 PM PDT 24
Finished Aug 03 05:28:20 PM PDT 24
Peak memory 206600 kb
Host smart-1336c778-2b63-427e-9d5d-0329ebca4f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652807798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3652807798
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3584988217
Short name T446
Test name
Test status
Simulation time 56848060537 ps
CPU time 36.85 seconds
Started Aug 03 05:28:17 PM PDT 24
Finished Aug 03 05:28:54 PM PDT 24
Peak memory 233508 kb
Host smart-a5457953-456d-4ef0-8ac2-d91fe3b30d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584988217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3584988217
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4001198964
Short name T480
Test name
Test status
Simulation time 59683991 ps
CPU time 0.76 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:28:30 PM PDT 24
Peak memory 205860 kb
Host smart-1497a20d-1c9b-4d71-b354-94e243e9a817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001198964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4001198964
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3487771985
Short name T656
Test name
Test status
Simulation time 1381887328 ps
CPU time 12.63 seconds
Started Aug 03 05:28:23 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 225256 kb
Host smart-d9452802-08a4-4253-ad6f-850402482c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487771985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3487771985
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3142504310
Short name T998
Test name
Test status
Simulation time 34827680 ps
CPU time 0.77 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:28:30 PM PDT 24
Peak memory 207384 kb
Host smart-107e3cae-ed59-4600-a7c6-d2479a101021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142504310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3142504310
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2553299324
Short name T1018
Test name
Test status
Simulation time 25426970782 ps
CPU time 97.54 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:29:59 PM PDT 24
Peak memory 264844 kb
Host smart-49180d38-8bdc-4c86-be60-a40b808696b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553299324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2553299324
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4221426388
Short name T999
Test name
Test status
Simulation time 49271643130 ps
CPU time 272.32 seconds
Started Aug 03 05:28:22 PM PDT 24
Finished Aug 03 05:32:54 PM PDT 24
Peak memory 268620 kb
Host smart-7b00266e-d1b0-4cea-8aff-99310a09a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221426388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4221426388
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4112228433
Short name T569
Test name
Test status
Simulation time 53396904067 ps
CPU time 104.76 seconds
Started Aug 03 05:28:22 PM PDT 24
Finished Aug 03 05:30:07 PM PDT 24
Peak memory 249992 kb
Host smart-930aadb9-6cd9-49e9-97a3-3186596ad10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112228433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4112228433
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.286971925
Short name T568
Test name
Test status
Simulation time 2792101902 ps
CPU time 13.82 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:28:49 PM PDT 24
Peak memory 225356 kb
Host smart-af8af585-7d77-4744-b483-2ffb58e5d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286971925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.286971925
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1875655831
Short name T94
Test name
Test status
Simulation time 6330653122 ps
CPU time 10.78 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:35 PM PDT 24
Peak memory 235652 kb
Host smart-b3544acd-4a4a-4964-abb1-f6831012e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875655831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1875655831
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.133299126
Short name T744
Test name
Test status
Simulation time 2105418107 ps
CPU time 8.41 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:28:30 PM PDT 24
Peak memory 225264 kb
Host smart-15e8b408-3951-4a00-912a-06378fb01731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133299126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.133299126
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1601353148
Short name T257
Test name
Test status
Simulation time 4477923531 ps
CPU time 42.68 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 240360 kb
Host smart-02f4f189-2380-49ae-99dd-e13e2c5310da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601353148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1601353148
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.465206897
Short name T277
Test name
Test status
Simulation time 6913590383 ps
CPU time 7.77 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 233464 kb
Host smart-351f5aa2-a0cb-4b41-86b0-071a989af273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465206897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.465206897
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.221141559
Short name T265
Test name
Test status
Simulation time 54274836 ps
CPU time 2.85 seconds
Started Aug 03 05:28:22 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 233460 kb
Host smart-052b689f-afe5-4a60-a73e-49203fa81b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221141559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.221141559
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.599915904
Short name T833
Test name
Test status
Simulation time 1138291096 ps
CPU time 9.31 seconds
Started Aug 03 05:28:20 PM PDT 24
Finished Aug 03 05:28:30 PM PDT 24
Peak memory 223776 kb
Host smart-38de493b-307a-4de4-871b-5716374da1b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599915904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.599915904
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2029965157
Short name T319
Test name
Test status
Simulation time 37043429705 ps
CPU time 343.01 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:34:12 PM PDT 24
Peak memory 258156 kb
Host smart-56fdcb21-13f9-4a03-b98a-5f2474f8ef2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029965157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2029965157
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2644658648
Short name T855
Test name
Test status
Simulation time 22401267506 ps
CPU time 31.18 seconds
Started Aug 03 05:28:22 PM PDT 24
Finished Aug 03 05:28:53 PM PDT 24
Peak memory 217060 kb
Host smart-366b2879-78e2-491c-98be-febe5a5af862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644658648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2644658648
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3976392777
Short name T727
Test name
Test status
Simulation time 3486917073 ps
CPU time 5.77 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:28:27 PM PDT 24
Peak memory 217012 kb
Host smart-5438f706-acbe-4e1f-ada2-dd2bbd9bd0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976392777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3976392777
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.571613941
Short name T490
Test name
Test status
Simulation time 772447851 ps
CPU time 1.68 seconds
Started Aug 03 05:28:21 PM PDT 24
Finished Aug 03 05:28:22 PM PDT 24
Peak memory 216952 kb
Host smart-057931fa-a9ae-44b3-8a41-a7e973d3e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571613941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.571613941
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.581692388
Short name T420
Test name
Test status
Simulation time 40498519 ps
CPU time 0.83 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:28:25 PM PDT 24
Peak memory 206612 kb
Host smart-d9e1b113-0cc1-4ef5-a908-04d09b6f36c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581692388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.581692388
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.223997561
Short name T500
Test name
Test status
Simulation time 1313562238 ps
CPU time 8.32 seconds
Started Aug 03 05:28:25 PM PDT 24
Finished Aug 03 05:28:33 PM PDT 24
Peak memory 233516 kb
Host smart-347dbe24-9c24-42d0-b2de-85179a05ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223997561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.223997561
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1781865722
Short name T603
Test name
Test status
Simulation time 14521266 ps
CPU time 0.75 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:08 PM PDT 24
Peak memory 205284 kb
Host smart-064e74ef-7cd3-4ab8-8e2d-ba0f9afc52a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781865722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
781865722
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3691852108
Short name T271
Test name
Test status
Simulation time 29499012923 ps
CPU time 20.84 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:29 PM PDT 24
Peak memory 233384 kb
Host smart-0b7fb48e-f7ca-4622-abaf-a5fc225b90b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691852108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3691852108
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.135940706
Short name T145
Test name
Test status
Simulation time 75034856 ps
CPU time 0.79 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:25:56 PM PDT 24
Peak memory 205964 kb
Host smart-47857a06-e995-4502-b2df-294d050698d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135940706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.135940706
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3902571725
Short name T994
Test name
Test status
Simulation time 7294405437 ps
CPU time 135.27 seconds
Started Aug 03 05:26:04 PM PDT 24
Finished Aug 03 05:28:24 PM PDT 24
Peak memory 257684 kb
Host smart-54f34618-a209-4d86-bc8e-f42312402623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902571725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3902571725
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3787197250
Short name T212
Test name
Test status
Simulation time 7122227947 ps
CPU time 12.67 seconds
Started Aug 03 05:25:58 PM PDT 24
Finished Aug 03 05:26:11 PM PDT 24
Peak memory 250024 kb
Host smart-b2493980-78a7-424f-ba70-03ce299c86e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787197250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3787197250
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3828078072
Short name T209
Test name
Test status
Simulation time 89376594012 ps
CPU time 335 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:31:31 PM PDT 24
Peak memory 256592 kb
Host smart-1c49ed80-9e7f-4fe8-a470-2c8c476a75ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828078072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3828078072
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.426380333
Short name T938
Test name
Test status
Simulation time 1457145064 ps
CPU time 23.23 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 241696 kb
Host smart-146cad4d-dcb4-462f-8e68-6150b1b02f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426380333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.426380333
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.382001337
Short name T198
Test name
Test status
Simulation time 20343718215 ps
CPU time 137.99 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 233712 kb
Host smart-1a6259e8-c55e-4cbe-bf5a-b620f9ea5f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382001337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
382001337
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1194301875
Short name T462
Test name
Test status
Simulation time 763452452 ps
CPU time 4.65 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 220404 kb
Host smart-de414906-8578-463f-ac58-b525f38636f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194301875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1194301875
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1009867487
Short name T533
Test name
Test status
Simulation time 16951292062 ps
CPU time 33.6 seconds
Started Aug 03 05:26:03 PM PDT 24
Finished Aug 03 05:26:37 PM PDT 24
Peak memory 249852 kb
Host smart-417043d5-ba1b-4ca8-8b2f-3e4ab38e478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009867487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1009867487
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4238065822
Short name T1015
Test name
Test status
Simulation time 95246553 ps
CPU time 1.03 seconds
Started Aug 03 05:25:51 PM PDT 24
Finished Aug 03 05:25:52 PM PDT 24
Peak memory 218528 kb
Host smart-facbadc8-5cd1-45f1-9965-408d99853c02
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238065822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4238065822
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1241765612
Short name T985
Test name
Test status
Simulation time 919154728 ps
CPU time 7.68 seconds
Started Aug 03 05:25:50 PM PDT 24
Finished Aug 03 05:25:57 PM PDT 24
Peak memory 233408 kb
Host smart-622c874e-49c1-4b8f-90ee-f627d56b7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241765612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1241765612
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3197327401
Short name T412
Test name
Test status
Simulation time 74966575 ps
CPU time 2.05 seconds
Started Aug 03 05:26:04 PM PDT 24
Finished Aug 03 05:26:06 PM PDT 24
Peak memory 223480 kb
Host smart-44c7d505-574a-477e-9b23-c6c2adbe4e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197327401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3197327401
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.166500197
Short name T493
Test name
Test status
Simulation time 1092097179 ps
CPU time 12.35 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 219564 kb
Host smart-9ba5f429-4ed5-4e7d-923d-1b4302ec3ea7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=166500197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.166500197
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.620405823
Short name T778
Test name
Test status
Simulation time 8666102693 ps
CPU time 152.71 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:28:27 PM PDT 24
Peak memory 271976 kb
Host smart-7369dd8a-a275-4f1e-9ca6-5e805395f517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620405823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.620405823
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1184490359
Short name T684
Test name
Test status
Simulation time 5491942400 ps
CPU time 31.03 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 217116 kb
Host smart-80fbf464-a31e-4485-b68b-5a9cec3b508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184490359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1184490359
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.762318199
Short name T780
Test name
Test status
Simulation time 793129624 ps
CPU time 3.14 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:25:57 PM PDT 24
Peak memory 208512 kb
Host smart-b0490abb-4c70-4c98-a1ef-cfc5daad8b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762318199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.762318199
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3978484564
Short name T345
Test name
Test status
Simulation time 203992588 ps
CPU time 1.49 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 216940 kb
Host smart-9402627a-726c-49a3-8095-d1b16a5f092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978484564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3978484564
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2794962482
Short name T364
Test name
Test status
Simulation time 99928410 ps
CPU time 0.76 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 206580 kb
Host smart-d8f161bc-30cd-4a94-b779-9633f72e451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794962482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2794962482
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1308411629
Short name T414
Test name
Test status
Simulation time 63790271 ps
CPU time 2.05 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:25:59 PM PDT 24
Peak memory 224828 kb
Host smart-a98eaf71-6e98-44fe-9635-5ecd59ab8b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308411629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1308411629
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3451453208
Short name T939
Test name
Test status
Simulation time 25078908 ps
CPU time 0.79 seconds
Started Aug 03 05:26:06 PM PDT 24
Finished Aug 03 05:26:07 PM PDT 24
Peak memory 206372 kb
Host smart-00c4efa6-ccc2-4b23-b7ef-c8a81cb0f656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451453208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
451453208
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.929569295
Short name T821
Test name
Test status
Simulation time 153382150 ps
CPU time 2.56 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 233464 kb
Host smart-27cb83f0-554b-41b6-aa78-c240ea23b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929569295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.929569295
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.639075190
Short name T737
Test name
Test status
Simulation time 15234589 ps
CPU time 0.84 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 207064 kb
Host smart-dbc5c889-6bb6-42c3-b3ec-018f24a89afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639075190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.639075190
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3186641162
Short name T317
Test name
Test status
Simulation time 7598480730 ps
CPU time 22.87 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 235928 kb
Host smart-73200ed7-2a3b-4f40-8f2b-a8585dc7dc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186641162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3186641162
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.506495644
Short name T42
Test name
Test status
Simulation time 16909828902 ps
CPU time 77.49 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:27:13 PM PDT 24
Peak memory 255020 kb
Host smart-d36253ab-c6b3-43dd-8bad-6eca732b1d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506495644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.506495644
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2579374299
Short name T310
Test name
Test status
Simulation time 5708962456 ps
CPU time 98.56 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:27:35 PM PDT 24
Peak memory 266348 kb
Host smart-ac4a77a3-4263-4ce0-a236-c01746dd2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579374299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2579374299
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2298159443
Short name T719
Test name
Test status
Simulation time 16046692956 ps
CPU time 49.47 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:46 PM PDT 24
Peak memory 253524 kb
Host smart-32b8f361-39d0-4dc2-a10e-2cdbff5d2be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298159443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2298159443
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1404553155
Short name T1032
Test name
Test status
Simulation time 626264862 ps
CPU time 2.94 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 228724 kb
Host smart-f5bdab34-58f3-454c-80e7-77ee2a7adb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404553155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1404553155
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.81445208
Short name T945
Test name
Test status
Simulation time 20161915652 ps
CPU time 32.24 seconds
Started Aug 03 05:26:00 PM PDT 24
Finished Aug 03 05:26:32 PM PDT 24
Peak memory 233468 kb
Host smart-97560ab8-8922-4e77-a9ff-5e2fa9f9b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81445208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.81445208
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.695350925
Short name T584
Test name
Test status
Simulation time 91142482 ps
CPU time 1.03 seconds
Started Aug 03 05:26:10 PM PDT 24
Finished Aug 03 05:26:11 PM PDT 24
Peak memory 217232 kb
Host smart-0b298dc7-c545-441d-9b44-fd44a2b84f15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695350925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.695350925
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3771886239
Short name T228
Test name
Test status
Simulation time 944215369 ps
CPU time 3.97 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 233384 kb
Host smart-13c82d99-8fd3-48d8-8f30-4a047e673ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771886239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3771886239
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.288909019
Short name T554
Test name
Test status
Simulation time 2654920291 ps
CPU time 5.54 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 233572 kb
Host smart-f221faed-3cea-422b-8080-19873c493ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288909019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.288909019
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3260125435
Short name T868
Test name
Test status
Simulation time 723072097 ps
CPU time 3.84 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 219360 kb
Host smart-6ef7a0f4-8e5a-4d49-8ec3-e79a7bbab877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260125435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3260125435
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2686248694
Short name T169
Test name
Test status
Simulation time 155098645782 ps
CPU time 295.06 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:30:52 PM PDT 24
Peak memory 257656 kb
Host smart-35c6f284-979f-48fc-8f70-5e8dc7cf3929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686248694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2686248694
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2010154447
Short name T430
Test name
Test status
Simulation time 5234354855 ps
CPU time 28 seconds
Started Aug 03 05:25:58 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 217108 kb
Host smart-28ae447a-3cea-4f0e-bf5e-9889973fdf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010154447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2010154447
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2371060536
Short name T82
Test name
Test status
Simulation time 3470186787 ps
CPU time 13.56 seconds
Started Aug 03 05:26:06 PM PDT 24
Finished Aug 03 05:26:20 PM PDT 24
Peak memory 217008 kb
Host smart-389b5f2e-bf36-49c0-8e0c-d020dd7dc1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371060536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2371060536
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2418562249
Short name T961
Test name
Test status
Simulation time 2553556367 ps
CPU time 2.37 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 217028 kb
Host smart-5a9b6099-5cf9-4b59-a1be-7c75ffbe179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418562249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2418562249
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.114602042
Short name T431
Test name
Test status
Simulation time 85962245 ps
CPU time 0.79 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 206552 kb
Host smart-0e6e57f0-8c3b-4ba8-ba8c-a26def6f009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114602042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.114602042
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4125175451
Short name T366
Test name
Test status
Simulation time 1404195522 ps
CPU time 4.22 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:11 PM PDT 24
Peak memory 225236 kb
Host smart-30a9976a-97d3-4eb4-8614-0188429d0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125175451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4125175451
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1384243661
Short name T409
Test name
Test status
Simulation time 13636619 ps
CPU time 0.78 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:12 PM PDT 24
Peak memory 205864 kb
Host smart-2c95a670-3faf-4ebd-8948-b9e56447ae5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384243661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
384243661
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2409243640
Short name T255
Test name
Test status
Simulation time 142508100 ps
CPU time 3.53 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:06 PM PDT 24
Peak memory 233468 kb
Host smart-f8f8b8d3-df00-497d-98dd-425d3cef63e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409243640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2409243640
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.872652994
Short name T943
Test name
Test status
Simulation time 20460483 ps
CPU time 0.79 seconds
Started Aug 03 05:26:00 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 207024 kb
Host smart-3e264176-0f2d-4b7c-aa85-7d55a8611098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872652994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.872652994
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2704570515
Short name T1023
Test name
Test status
Simulation time 9903118553 ps
CPU time 55.76 seconds
Started Aug 03 05:26:12 PM PDT 24
Finished Aug 03 05:27:08 PM PDT 24
Peak memory 255024 kb
Host smart-0c1761cf-0d21-41cf-8d92-8047b0e637f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704570515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2704570515
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2886723535
Short name T851
Test name
Test status
Simulation time 11561907429 ps
CPU time 44.62 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 250008 kb
Host smart-e1f83510-7f42-4918-bc53-b8386db078bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886723535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2886723535
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.810563557
Short name T609
Test name
Test status
Simulation time 7961162761 ps
CPU time 59.95 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:27:08 PM PDT 24
Peak memory 250992 kb
Host smart-0a942550-0430-436a-a44b-4fa9206908bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810563557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
810563557
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3811774805
Short name T1016
Test name
Test status
Simulation time 5058759936 ps
CPU time 48.63 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:49 PM PDT 24
Peak memory 254124 kb
Host smart-1146e441-9dc3-4b4c-b036-7ec5a56b9a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811774805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3811774805
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4211413507
Short name T191
Test name
Test status
Simulation time 62333559789 ps
CPU time 122.37 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:28:03 PM PDT 24
Peak memory 249844 kb
Host smart-3f3fd594-26a4-418b-b657-bca030ad48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211413507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4211413507
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2198289570
Short name T825
Test name
Test status
Simulation time 1527259530 ps
CPU time 6.09 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 225268 kb
Host smart-70f632a9-2622-46ec-a3f9-e8b27bcab61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198289570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2198289570
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3489138441
Short name T544
Test name
Test status
Simulation time 331113859 ps
CPU time 6.64 seconds
Started Aug 03 05:25:59 PM PDT 24
Finished Aug 03 05:26:06 PM PDT 24
Peak memory 233432 kb
Host smart-02d6acf5-924c-4e8c-b312-8fed12c9eee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489138441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3489138441
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3500502862
Short name T977
Test name
Test status
Simulation time 64383117 ps
CPU time 1.11 seconds
Started Aug 03 05:25:59 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 217188 kb
Host smart-740e65d4-65a7-4527-9c26-ca15c86f6423
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500502862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3500502862
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2769412897
Short name T276
Test name
Test status
Simulation time 788490072 ps
CPU time 5.5 seconds
Started Aug 03 05:25:54 PM PDT 24
Finished Aug 03 05:26:00 PM PDT 24
Peak memory 233456 kb
Host smart-46bbc23e-b469-485e-ac3a-f4cf0b296dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769412897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2769412897
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3008561344
Short name T876
Test name
Test status
Simulation time 1798604604 ps
CPU time 7.57 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 225212 kb
Host smart-f6ac5d89-5a57-4542-b5cf-b9e4a017641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008561344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3008561344
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1156785022
Short name T566
Test name
Test status
Simulation time 26465829666 ps
CPU time 16.49 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:30 PM PDT 24
Peak memory 223796 kb
Host smart-2c1fdcf4-2a03-428c-998d-19326cadb8d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1156785022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1156785022
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.389533563
Short name T795
Test name
Test status
Simulation time 29563131200 ps
CPU time 100.7 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:27:43 PM PDT 24
Peak memory 252732 kb
Host smart-a6239b90-ba4a-4900-a1d7-3f91ecbb3e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389533563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.389533563
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1268289901
Short name T406
Test name
Test status
Simulation time 481222388 ps
CPU time 3.62 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:26:01 PM PDT 24
Peak memory 217064 kb
Host smart-77f1efd9-c1f8-4c49-b628-6b0ca5ab46b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268289901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1268289901
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1728450748
Short name T980
Test name
Test status
Simulation time 96349201182 ps
CPU time 17.3 seconds
Started Aug 03 05:25:55 PM PDT 24
Finished Aug 03 05:26:12 PM PDT 24
Peak memory 216812 kb
Host smart-ff2eb150-8799-4400-874e-614294d8f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728450748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1728450748
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3471193084
Short name T634
Test name
Test status
Simulation time 22170417 ps
CPU time 0.84 seconds
Started Aug 03 05:26:04 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 207536 kb
Host smart-b4c28031-cee7-46b5-b39e-2df4ba705280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471193084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3471193084
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.603445285
Short name T733
Test name
Test status
Simulation time 109204340 ps
CPU time 0.81 seconds
Started Aug 03 05:25:57 PM PDT 24
Finished Aug 03 05:25:58 PM PDT 24
Peak memory 206584 kb
Host smart-4f1d99c9-3ed4-47d3-98bf-53bf9bc69fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603445285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.603445285
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2046413984
Short name T423
Test name
Test status
Simulation time 444863609 ps
CPU time 7.99 seconds
Started Aug 03 05:25:56 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 225320 kb
Host smart-2e631b78-0ecc-4fbf-873c-048e5858da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046413984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2046413984
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.185575683
Short name T472
Test name
Test status
Simulation time 43295111 ps
CPU time 0.72 seconds
Started Aug 03 05:26:07 PM PDT 24
Finished Aug 03 05:26:08 PM PDT 24
Peak memory 205884 kb
Host smart-dcca0f70-8e83-4e47-8b72-1e9f71f00a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185575683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.185575683
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.885908066
Short name T954
Test name
Test status
Simulation time 6875357781 ps
CPU time 12.42 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:14 PM PDT 24
Peak memory 233480 kb
Host smart-d88b8598-7737-4a23-97cd-26308a3f66f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885908066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.885908066
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1590692257
Short name T65
Test name
Test status
Simulation time 40665074 ps
CPU time 0.78 seconds
Started Aug 03 05:26:04 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 207048 kb
Host smart-0765eb2c-8795-4d69-8402-989f4bc21967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590692257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1590692257
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2645178934
Short name T293
Test name
Test status
Simulation time 594269804 ps
CPU time 14.67 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:35 PM PDT 24
Peak memory 251464 kb
Host smart-b54fb2fc-6b4e-4528-9634-5da0a8b66a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645178934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2645178934
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.457765590
Short name T910
Test name
Test status
Simulation time 31649303941 ps
CPU time 148.77 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:28:52 PM PDT 24
Peak memory 241424 kb
Host smart-0a40ce12-e7d4-4618-a573-928210cb4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457765590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
457765590
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4026827206
Short name T535
Test name
Test status
Simulation time 638737875 ps
CPU time 7.51 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 250160 kb
Host smart-6f61fbd3-bfe6-44fd-9c10-0cc0ee46e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026827206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4026827206
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3301551434
Short name T920
Test name
Test status
Simulation time 4171566815 ps
CPU time 45.43 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:54 PM PDT 24
Peak memory 257976 kb
Host smart-ce8df927-6721-40cf-a8a3-c15deab72612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301551434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3301551434
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2717047906
Short name T607
Test name
Test status
Simulation time 48945041948 ps
CPU time 23.33 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:37 PM PDT 24
Peak memory 225244 kb
Host smart-b09914a2-7f2e-4d36-9413-78f4c5588d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717047906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2717047906
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.764596139
Short name T574
Test name
Test status
Simulation time 1430889693 ps
CPU time 22.02 seconds
Started Aug 03 05:26:03 PM PDT 24
Finished Aug 03 05:26:25 PM PDT 24
Peak memory 233532 kb
Host smart-75443913-15af-48c0-87b5-68c643ee8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764596139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.764596139
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.801713087
Short name T546
Test name
Test status
Simulation time 35468872 ps
CPU time 1.18 seconds
Started Aug 03 05:26:01 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 217168 kb
Host smart-586359cc-0f4b-4c38-a257-1670d4446ac1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801713087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.801713087
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4244411946
Short name T562
Test name
Test status
Simulation time 37092857 ps
CPU time 2.56 seconds
Started Aug 03 05:26:03 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 233080 kb
Host smart-9d54f6cb-c4d7-4bd2-a657-caf506901ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244411946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4244411946
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3084570213
Short name T683
Test name
Test status
Simulation time 207049525 ps
CPU time 3.63 seconds
Started Aug 03 05:26:00 PM PDT 24
Finished Aug 03 05:26:04 PM PDT 24
Peak memory 219596 kb
Host smart-caaa49d0-02a5-497e-bdf0-2c788692aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084570213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3084570213
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.504468747
Short name T731
Test name
Test status
Simulation time 300455159 ps
CPU time 3.91 seconds
Started Aug 03 05:26:09 PM PDT 24
Finished Aug 03 05:26:13 PM PDT 24
Peak memory 220908 kb
Host smart-cda71fa2-3656-4561-a374-963ca0ea87c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=504468747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.504468747
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.334792556
Short name T974
Test name
Test status
Simulation time 554002965548 ps
CPU time 505.97 seconds
Started Aug 03 05:26:15 PM PDT 24
Finished Aug 03 05:34:42 PM PDT 24
Peak memory 306564 kb
Host smart-89281e68-6028-45bf-b32d-1d2fa154db43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334792556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.334792556
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2651278023
Short name T147
Test name
Test status
Simulation time 5530191557 ps
CPU time 15.65 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:26 PM PDT 24
Peak memory 217020 kb
Host smart-abc6bf9d-3f0f-4808-a175-c13f91bdca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651278023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2651278023
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3104156329
Short name T877
Test name
Test status
Simulation time 8867840263 ps
CPU time 15.34 seconds
Started Aug 03 05:26:00 PM PDT 24
Finished Aug 03 05:26:15 PM PDT 24
Peak memory 217060 kb
Host smart-cc78dc0b-7979-4df9-8061-240b9f3d33f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104156329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3104156329
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2803387616
Short name T590
Test name
Test status
Simulation time 72519268 ps
CPU time 3.32 seconds
Started Aug 03 05:26:02 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 217056 kb
Host smart-470af467-ad85-4f29-8a10-6bd3fb4bc536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803387616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2803387616
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.686720803
Short name T437
Test name
Test status
Simulation time 29878426 ps
CPU time 0.86 seconds
Started Aug 03 05:26:04 PM PDT 24
Finished Aug 03 05:26:05 PM PDT 24
Peak memory 206500 kb
Host smart-2fc0f138-1828-42d4-b554-8f1b63ae2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686720803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.686720803
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3664740842
Short name T496
Test name
Test status
Simulation time 546025054 ps
CPU time 5.98 seconds
Started Aug 03 05:26:03 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 240168 kb
Host smart-3d470b0c-e73c-4dea-99ac-d9df06677510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664740842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3664740842
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.430224104
Short name T524
Test name
Test status
Simulation time 49906649 ps
CPU time 0.7 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 205316 kb
Host smart-23c6715a-5d8b-4784-821c-eda80e371438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430224104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.430224104
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4199573579
Short name T975
Test name
Test status
Simulation time 410463718 ps
CPU time 6.82 seconds
Started Aug 03 05:26:14 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 225228 kb
Host smart-da47ae75-6f71-497c-95b4-b607af03f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199573579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4199573579
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1651276657
Short name T517
Test name
Test status
Simulation time 67889019 ps
CPU time 0.77 seconds
Started Aug 03 05:26:17 PM PDT 24
Finished Aug 03 05:26:17 PM PDT 24
Peak memory 206368 kb
Host smart-93f6cc22-9a75-47d7-8f4c-05cbc4ee9e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651276657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1651276657
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4256321058
Short name T232
Test name
Test status
Simulation time 54555071492 ps
CPU time 128.46 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:28:17 PM PDT 24
Peak memory 266332 kb
Host smart-efedbfb3-dfac-49c6-86f4-2213eefb9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256321058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4256321058
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1105256942
Short name T1017
Test name
Test status
Simulation time 10661142854 ps
CPU time 40.77 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 240872 kb
Host smart-a6a5048e-0d59-4296-9bf3-21bcd548ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105256942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1105256942
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.881659218
Short name T210
Test name
Test status
Simulation time 4025491415 ps
CPU time 89.78 seconds
Started Aug 03 05:26:06 PM PDT 24
Finished Aug 03 05:27:36 PM PDT 24
Peak memory 257876 kb
Host smart-6fb7594d-1509-40b2-ad59-da8c37bee908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881659218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
881659218
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1571832182
Short name T43
Test name
Test status
Simulation time 8998560097 ps
CPU time 21.11 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:45 PM PDT 24
Peak memory 233552 kb
Host smart-2f6fd5ac-9060-4738-8cd5-2a38cac454b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571832182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1571832182
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.887919195
Short name T404
Test name
Test status
Simulation time 26491316 ps
CPU time 0.8 seconds
Started Aug 03 05:26:20 PM PDT 24
Finished Aug 03 05:26:21 PM PDT 24
Peak memory 216480 kb
Host smart-437d86b3-bdad-4224-8fa9-14ade0f62505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887919195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
887919195
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1414554287
Short name T221
Test name
Test status
Simulation time 1871306848 ps
CPU time 16.65 seconds
Started Aug 03 05:26:11 PM PDT 24
Finished Aug 03 05:26:28 PM PDT 24
Peak memory 225204 kb
Host smart-31e47434-eeab-4ae4-a854-1d7687c4ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414554287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1414554287
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3459909553
Short name T239
Test name
Test status
Simulation time 2102152174 ps
CPU time 11.92 seconds
Started Aug 03 05:26:19 PM PDT 24
Finished Aug 03 05:26:31 PM PDT 24
Peak memory 233492 kb
Host smart-0f844aab-e012-462e-92bb-7d441879719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459909553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3459909553
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2118558660
Short name T602
Test name
Test status
Simulation time 14372396 ps
CPU time 0.99 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 218536 kb
Host smart-3a313c1d-5dcb-481f-8f2d-221927e8b584
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118558660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2118558660
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3649022652
Short name T464
Test name
Test status
Simulation time 17433175316 ps
CPU time 7.63 seconds
Started Aug 03 05:26:09 PM PDT 24
Finished Aug 03 05:26:17 PM PDT 24
Peak memory 237700 kb
Host smart-c0727de5-da65-4593-b686-185e7ca1284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649022652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3649022652
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1280875272
Short name T899
Test name
Test status
Simulation time 8817111844 ps
CPU time 5.16 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:24 PM PDT 24
Peak memory 225308 kb
Host smart-eb793cc4-d61a-47c6-a856-8d6678f5be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280875272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1280875272
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1138512217
Short name T784
Test name
Test status
Simulation time 1499397685 ps
CPU time 18.53 seconds
Started Aug 03 05:26:23 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 221276 kb
Host smart-56e023c8-f445-456e-a8e5-7b713d23bde9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138512217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1138512217
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1444579481
Short name T166
Test name
Test status
Simulation time 2354762376 ps
CPU time 39.21 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 239832 kb
Host smart-67abb7b7-2dc6-4f38-949b-fa19cc452a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444579481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1444579481
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2384012523
Short name T907
Test name
Test status
Simulation time 2219616253 ps
CPU time 14.48 seconds
Started Aug 03 05:26:09 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 217084 kb
Host smart-df317bda-42e0-4c54-81a4-c0fd7ecb48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384012523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2384012523
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3689486798
Short name T585
Test name
Test status
Simulation time 3583656443 ps
CPU time 10.92 seconds
Started Aug 03 05:26:18 PM PDT 24
Finished Aug 03 05:26:29 PM PDT 24
Peak memory 217032 kb
Host smart-e5788a02-faf9-415e-b5be-0ebd0661ff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689486798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3689486798
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1600668620
Short name T692
Test name
Test status
Simulation time 179094993 ps
CPU time 2.01 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:23 PM PDT 24
Peak memory 216992 kb
Host smart-640b7349-5b70-4371-b133-605bbca67e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600668620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1600668620
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.455426983
Short name T601
Test name
Test status
Simulation time 685369863 ps
CPU time 0.85 seconds
Started Aug 03 05:26:08 PM PDT 24
Finished Aug 03 05:26:09 PM PDT 24
Peak memory 206580 kb
Host smart-006b2186-b152-4f08-b952-1c5092bc12a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455426983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.455426983
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3395884836
Short name T252
Test name
Test status
Simulation time 742530466 ps
CPU time 7.18 seconds
Started Aug 03 05:26:21 PM PDT 24
Finished Aug 03 05:26:29 PM PDT 24
Peak memory 241352 kb
Host smart-8a975cbd-06f1-4ccb-81dd-c0d1118e4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395884836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3395884836
Directory /workspace/9.spi_device_upload/latest
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