Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2630611	1			T1	2		T3	1		T4	1
all_values[1]	2630611	1			T1	2		T3	1		T4	1
all_values[2]	2630611	1			T1	2		T3	1		T4	1
all_values[3]	2630611	1			T1	2		T3	1		T4	1
all_values[4]	2630611	1			T1	2		T3	1		T4	1
all_values[5]	2630611	1			T1	2		T3	1		T4	1
all_values[6]	2630611	1			T1	2		T3	1		T4	1
all_values[7]	2630611	1			T1	2		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20334950

1

T1

16

T3

8

T4

8

auto[1]

709938

1

T15

316830

T66

30

T16

73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21020198

1

T1

16

T3

8

T4

8

auto[1]

24690

1

T12

75

T13

76

T32

124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2527728	1			T1	2		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	10641	1			T12	26		T13	44		T32	62
all_values[0]	auto[1]	auto[0]	91497	1			T15	45072		T66	2		T16	7
all_values[0]	auto[1]	auto[1]	745	1			T15	189		T66	3		T16	6
all_values[1]	auto[0]	auto[0]	2597510	1			T1	2		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	7398	1			T12	25		T13	20		T32	62
all_values[1]	auto[1]	auto[0]	25271	1			T66	4		T16	6		T67	2
all_values[1]	auto[1]	auto[1]	432	1			T15	3		T16	2		T67	2
all_values[2]	auto[0]	auto[0]	2543904	1			T1	2		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2860	1			T12	24		T13	12		T33	6
all_values[2]	auto[1]	auto[0]	83387	1			T15	45216		T66	2		T16	4
all_values[2]	auto[1]	auto[1]	460	1			T15	46		T66	2		T16	4
all_values[3]	auto[0]	auto[0]	2496077	1			T1	2		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	236	1			T15	1		T66	1		T16	5
all_values[3]	auto[1]	auto[0]	134092	1			T15	45261		T66	2		T16	1
all_values[3]	auto[1]	auto[1]	206	1			T15	1		T66	3		T16	5
all_values[4]	auto[0]	auto[0]	2545184	1			T1	2		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	239	1			T15	2		T66	1		T16	4
all_values[4]	auto[1]	auto[0]	84975	1			T15	45258		T66	3		T16	4
all_values[4]	auto[1]	auto[1]	213	1			T15	2		T66	2		T16	2
all_values[5]	auto[0]	auto[0]	2553116	1			T1	2		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	207	1			T15	2		T66	1		T16	2
all_values[5]	auto[1]	auto[0]	77064	1			T15	45259		T16	5		T67	2820
all_values[5]	auto[1]	auto[1]	224	1			T66	2		T16	5		T67	1
all_values[6]	auto[0]	auto[0]	2561012	1			T1	2		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	212	1			T66	1		T16	3		T67	1
all_values[6]	auto[1]	auto[0]	69169	1			T15	45259		T66	3		T16	8
all_values[6]	auto[1]	auto[1]	218	1			T15	2		T66	2		T67	2
all_values[7]	auto[0]	auto[0]	2488432	1			T1	2		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	194	1			T15	2		T66	3		T16	2
all_values[7]	auto[1]	auto[0]	141780	1			T15	45259		T16	7		T67	2825
all_values[7]	auto[1]	auto[1]	205	1			T15	3		T16	7		T19	4