Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31082	1			T4	6		T5	42		T8	327
auto[SpiFlashAddrCfg]	6985	1			T4	2		T5	26		T8	31
auto[SpiFlashAddr3b]	8550	1			T1	2		T4	12		T5	33
auto[SpiFlashAddr4b]	7236	1			T4	2		T5	19		T8	38

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31560

1

T1

2

T5

72

T8

214

auto[1]

22293

1

T4

22

T5

48

T8

224

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28935

1

T1

2

T4

6

T5

71

auto[1]

24918

1

T4

16

T5

49

T8

270

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35358	1			T4	12		T5	51		T8	354
values[1]	1002	1			T8	1		T13	4		T32	1
values[2]	1368	1			T5	6		T8	10		T12	8
values[3]	1381	1			T8	3		T11	2		T12	5
values[4]	1370	1			T5	6		T8	7		T12	5
values[5]	1365	1			T4	2		T5	3		T8	12
values[6]	1348	1			T5	8		T8	6		T9	6
values[7]	1452	1			T4	2		T5	4		T8	3
values[8]	9209	1			T1	2		T4	6		T5	42

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28552

1

T4

22

T8

438

T9

14

auto[1]

25301

1

T1

2

T5

120

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

50895

1

T1

2

T4

20

T5

116

write

2958

1

T4

2

T5

4

T8

22

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17948

1

T1

2

T4

6

T5

70

valids[0x1]

35905

1

T4

16

T5

50

T8

351

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1494	1			T5	2		T8	7		T12	5
internal_process_ops[0x5a]	1437	1			T4	2		T5	3		T8	5
internal_process_ops[0x05]	18286	1			T4	2		T5	6		T8	263
internal_process_ops[0x35]	1499	1			T4	2		T5	2		T8	4
internal_process_ops[0x15]	1418	1			T4	2		T5	4		T8	6
internal_process_ops[0x03]	1055	1			T5	2		T8	9		T11	2
internal_process_ops[0x0b]	1006	1			T4	6		T5	2		T8	10
internal_process_ops[0x3b]	1044	1			T8	9		T11	2		T12	3
internal_process_ops[0x6b]	1001	1			T4	2		T5	3		T8	11
internal_process_ops[0xbb]	980	1			T5	2		T8	7		T12	6
internal_process_ops[0xeb]	1049	1			T1	2		T5	4		T8	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52401

1

T1

2

T4

20

T5

118

auto[1]

1452

1

T4

2

T5

2

T8

14

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51782

1

T1

2

T4

22

T5

116

auto[1]

2071

1

T5

4

T8

14

T12

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9314

1

T8

162

T12

32

T13

78

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5117

1

T4

6

T8

155

T9

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2031

1

T8

13

T12

10

T13

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1827

1

T4

2

T8

14

T12

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2586

1

T8

18

T11

4

T12

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2119

1

T4

12

T8

21

T9

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2061

1

T8

11

T12

12

T13

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1941

1

T8

22

T9

4

T12

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

115

1

T8

3

T74

2

T22

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T8

2

T12

1

T15

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

72

1

T8

1

T33

1

T85

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T8

4

T33

2

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

78

1

T8

1

T33

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T8

2

T12

1

T13

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

100

1

T12

2

T13

5

T64

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T8

1

T33

3

T15

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

134

1

T8

1

T12

1

T13

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

73

1

T15

2

T179

1

T180

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

82

1

T13

4

T48

1

T15

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T8

2

T12

1

T51

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

136

1

T8

1

T13

1

T33

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T13

1

T33

5

T48

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T8

1

T13

4

T33

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T4

2

T8

3

T9

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9950

1

T5

29

T32

35

T27

108

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5933

1

T5

13

T32

12

T27

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1218

1

T5

14

T32

4

T50

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1185

1

T5

12

T32

4

T181

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1674

1

T1

2

T5

19

T14

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1458

1

T5

10

T32

3

T27

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1226

1

T5

10

T32

5

T27

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1255

1

T5

9

T32

4

T27

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T27

2

T181

1

T66

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T181

2

T66

3

T109

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T181

1

T182

1

T66

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T181

4

T66

3

T67

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T182

3

T66

1

T183

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T182

2

T174

3

T67

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T182

1

T66

2

T16

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T27

2

T181

3

T66

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T109

2

T16

2

T67

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T27

1

T181

1

T66

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T5

2

T32

1

T181

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

68

1

T5

2

T32

1

T184

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

70

1

T109

1

T67

2

T73

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T66

1

T184

1

T109

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

75

1

T182

2

T66

2

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

79

1

T32

4

T66

4

T67

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3756	1			T4	2		T8	38		T12	28
auto[0]	values[0]	valids[0x1]	13555	1			T4	10		T8	316		T9	4
auto[0]	values[1]	valids[0x1]	576	1			T8	1		T13	4		T33	5
auto[0]	values[2]	valids[0x0]	523	1			T8	4		T12	8		T13	1
auto[0]	values[2]	valids[0x1]	289	1			T8	6		T13	4		T33	2
auto[0]	values[3]	valids[0x0]	557	1			T8	1		T11	2		T12	2
auto[0]	values[3]	valids[0x1]	291	1			T8	2		T12	3		T13	1
auto[0]	values[4]	valids[0x0]	583	1			T8	5		T12	5		T13	3
auto[0]	values[4]	valids[0x1]	264	1			T8	2		T13	5		T33	2
auto[0]	values[5]	valids[0x0]	550	1			T4	2		T8	11		T9	2
auto[0]	values[5]	valids[0x1]	292	1			T8	1		T12	1		T13	2
auto[0]	values[6]	valids[0x0]	482	1			T8	3		T9	2		T12	3
auto[0]	values[6]	valids[0x1]	286	1			T8	3		T9	4		T12	2
auto[0]	values[7]	valids[0x0]	608	1			T4	2		T8	3		T12	4
auto[0]	values[7]	valids[0x1]	342	1			T13	2		T64	2		T15	3
auto[0]	values[8]	valids[0x0]	3594	1			T8	22		T9	2		T12	25
auto[0]	values[8]	valids[0x1]	2004	1			T4	6		T8	20		T11	2
auto[1]	values[0]	valids[0x0]	3235	1			T5	24		T32	9		T27	11
auto[1]	values[0]	valids[0x1]	14812	1			T5	27		T32	42		T27	110
auto[1]	values[1]	valids[0x1]	426	1			T32	1		T27	1		T181	1
auto[1]	values[2]	valids[0x0]	328	1			T5	1		T32	1		T27	1
auto[1]	values[2]	valids[0x1]	228	1			T5	5		T27	1		T181	4
auto[1]	values[3]	valids[0x0]	321	1			T32	1		T182	2		T66	9
auto[1]	values[3]	valids[0x1]	212	1			T32	1		T27	4		T66	5
auto[1]	values[4]	valids[0x0]	313	1			T5	6		T32	3		T181	3
auto[1]	values[4]	valids[0x1]	210	1			T32	4		T27	2		T182	2
auto[1]	values[5]	valids[0x0]	319	1			T5	2		T182	2		T66	9
auto[1]	values[5]	valids[0x1]	204	1			T5	1		T66	7		T183	2
auto[1]	values[6]	valids[0x0]	368	1			T5	7		T32	1		T181	1
auto[1]	values[6]	valids[0x1]	212	1			T5	1		T181	3		T182	2
auto[1]	values[7]	valids[0x0]	279	1			T5	4		T32	1		T181	4
auto[1]	values[7]	valids[0x1]	223	1			T32	1		T27	2		T182	2
auto[1]	values[8]	valids[0x0]	2132	1			T1	2		T5	26		T32	10
auto[1]	values[8]	valids[0x1]	1479	1			T5	16		T14	1		T32	5