Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3201526

1

T1

2400

T4

1

T5

2473

auto[1]

26759

1

T5

180

T8

258

T12

11

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

894540

1

T1

2400

T4

1

T5

273

auto[1]

2333745

1

T5

2380

T8

8694

T12

9143

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	600970	1			T1	67		T4	1		T5	16
auto[524288:1048575]	435871	1			T5	17		T8	297		T12	43
auto[1048576:1572863]	380261	1			T1	204		T5	848		T8	3074
auto[1572864:2097151]	369630	1			T1	1057		T5	6		T8	624
auto[2097152:2621439]	356444	1			T1	921		T5	565		T8	163
auto[2621440:3145727]	348597	1			T5	557		T8	5		T11	366
auto[3145728:3670015]	341376	1			T1	53		T5	2		T8	278
auto[3670016:4194303]	395136	1			T1	98		T5	642		T8	137

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2366343

1

T1

19

T4

1

T5

2650

auto[1]

861942

1

T1

2381

T5

3

T8

15

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780703

1

T1

2400

T4

1

T5

1810

auto[1]

447582

1

T5

843

T8

815

T12

2329

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	206157	1			T1	67		T4	1		T5	12
auto[0]	auto[0]	auto[0:524287]	auto[1]	325108	1			T8	3998		T13	2911		T33	3212
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	96572	1			T5	17		T8	5		T12	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	271323	1			T8	141		T12	5		T13	703
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	111168	1			T1	204		T5	16		T8	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	221719	1			T5	4		T8	3073		T12	2041
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	106960	1			T1	1057		T5	4		T8	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	210725	1			T8	1		T13	2354		T32	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116174	1			T1	921		T5	47		T8	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	191701	1			T5	516		T8	129		T12	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	93670	1			T5	28		T11	366		T13	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	193232	1			T5	357		T8	5		T13	134
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	79629	1			T1	53		T5	2		T8	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207640	1			T8	257		T12	1473		T13	1638
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	72705	1			T1	98		T5	60		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	253966	1			T5	567		T8	128		T12	3038
auto[0]	auto[1]	auto[0:524287]	auto[0]	2111	1			T5	4		T8	3		T32	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	64433	1			T8	2		T33	1		T64	2982
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1447	1			T8	5		T48	2		T66	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	64318	1			T8	129		T12	35		T48	134
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	844	1			T5	56		T12	4		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	43176	1			T5	772		T13	4		T15	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	396	1			T8	1		T33	1		T64	18
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47472	1			T8	587		T33	128		T64	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	490	1			T5	2		T8	1		T13	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44890	1			T13	640		T15	5		T85	2485
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	945	1			T33	2		T53	1		T15	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	57213	1			T33	2395		T53	257		T15	2367
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1486	1			T12	2		T33	3		T48	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49565	1			T12	2287		T33	3072		T48	513
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	617	1			T5	9		T8	7		T13	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	63674	1			T13	257		T33	2573		T48	2994
auto[1]	auto[0]	auto[0:524287]	auto[0]	388	1			T8	6		T13	2		T33	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2407	1			T8	82		T13	74		T33	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	297	1			T8	2		T13	1		T33	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1615	1			T8	9		T13	6		T33	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	301	1			T12	1		T13	1		T15	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1901	1			T13	15		T15	3		T181	30
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	311	1			T5	2		T8	1		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3371	1			T8	29		T13	14		T32	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	292	1			T8	1		T32	1		T15	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2439	1			T8	31		T32	3		T15	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	306	1			T5	8		T13	3		T32	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2525	1			T5	164		T13	86		T32	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	315	1			T8	1		T12	1		T13	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2270	1			T8	16		T12	8		T13	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	325	1			T5	6		T13	1		T32	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3191	1			T13	9		T32	8		T33	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	86	1			T8	2		T33	1		T48	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	280	1			T8	72		T33	4		T48	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	57	1			T8	1		T48	1		T66	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	242	1			T8	5		T48	1		T73	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	108	1			T66	1		T183	4		T174	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1044	1			T66	4		T174	50		T67	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	51	1			T15	1		T67	1		T36	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	344	1			T67	4		T36	3		T165	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	68	1			T15	1		T16	1		T67	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	390	1			T16	5		T67	6		T236	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	94	1			T33	1		T181	2		T85	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	612	1			T33	2		T181	34		T85	41
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	72	1			T12	1		T48	1		T182	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	399	1			T182	8		T66	1		T73	13
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	98	1			T13	1		T48	2		T182	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	560	1			T13	9		T182	52		T66	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1900833	1			T1	19		T4	1		T5	1630
auto[0]	auto[0]	auto[1]	857616	1			T1	2381		T8	6		T11	24674
auto[0]	auto[1]	auto[0]	439365	1			T5	843		T8	733		T12	2328
auto[0]	auto[1]	auto[1]	3712	1			T8	2		T13	1		T181	1
auto[1]	auto[0]	auto[0]	21761	1			T5	177		T8	172		T12	10
auto[1]	auto[0]	auto[1]	493	1			T5	3		T8	6		T33	1
auto[1]	auto[1]	auto[0]	4384	1			T8	79		T12	1		T13	10
auto[1]	auto[1]	auto[1]	121	1			T8	1		T181	1		T85	1