Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2630611	1			T1	2		T3	1		T4	1
all_pins[1]	2630611	1			T1	2		T3	1		T4	1
all_pins[2]	2630611	1			T1	2		T3	1		T4	1
all_pins[3]	2630611	1			T1	2		T3	1		T4	1
all_pins[4]	2630611	1			T1	2		T3	1		T4	1
all_pins[5]	2630611	1			T1	2		T3	1		T4	1
all_pins[6]	2630611	1			T1	2		T3	1		T4	1
all_pins[7]	2630611	1			T1	2		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20979046	1			T1	16		T3	8		T4	8
values[0x1]	65842	1			T15	46186		T66	14		T16	31
transitions[0x0=>0x1]	63852	1			T15	45476		T66	10		T16	21
transitions[0x1=>0x0]	63866	1			T15	45477		T66	10		T16	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2629785	1			T1	2		T3	1		T4	1
all_pins[0]	values[0x1]	826	1			T15	207		T66	3		T16	6
all_pins[0]	transitions[0x0=>0x1]	616	1			T15	206		T66	3		T16	5
all_pins[0]	transitions[0x1=>0x0]	249	1			T15	2		T16	1		T67	1
all_pins[1]	values[0x0]	2630152	1			T1	2		T3	1		T4	1
all_pins[1]	values[0x1]	459	1			T15	3		T16	2		T67	2
all_pins[1]	transitions[0x0=>0x1]	362	1			T15	1		T16	1		T67	2
all_pins[1]	transitions[0x1=>0x0]	386	1			T15	49		T66	2		T16	3
all_pins[2]	values[0x0]	2630128	1			T1	2		T3	1		T4	1
all_pins[2]	values[0x1]	483	1			T15	51		T66	2		T16	4
all_pins[2]	transitions[0x0=>0x1]	435	1			T15	51		T16	2		T67	12
all_pins[2]	transitions[0x1=>0x0]	158	1			T15	1		T66	1		T16	3
all_pins[3]	values[0x0]	2630405	1			T1	2		T3	1		T4	1
all_pins[3]	values[0x1]	206	1			T15	1		T66	3		T16	5
all_pins[3]	transitions[0x0=>0x1]	152	1			T15	1		T66	1		T16	3
all_pins[3]	transitions[0x1=>0x0]	159	1			T15	2		T21	1		T22	4
all_pins[4]	values[0x0]	2630398	1			T1	2		T3	1		T4	1
all_pins[4]	values[0x1]	213	1			T15	2		T66	2		T16	2
all_pins[4]	transitions[0x0=>0x1]	165	1			T15	2		T66	2		T16	2
all_pins[4]	transitions[0x1=>0x0]	2071	1			T15	706		T66	2		T16	5
all_pins[5]	values[0x0]	2628492	1			T1	2		T3	1		T4	1
all_pins[5]	values[0x1]	2119	1			T15	706		T66	2		T16	5
all_pins[5]	transitions[0x0=>0x1]	705	1			T15	4		T66	2		T16	5
all_pins[5]	transitions[0x1=>0x0]	59917	1			T15	44511		T66	2		T67	2
all_pins[6]	values[0x0]	2569280	1			T1	2		T3	1		T4	1
all_pins[6]	values[0x1]	61331	1			T15	45213		T66	2		T67	2
all_pins[6]	transitions[0x0=>0x1]	61281	1			T15	45211		T66	2		T67	2
all_pins[6]	transitions[0x1=>0x0]	155	1			T15	1		T16	7		T19	4
all_pins[7]	values[0x0]	2630406	1			T1	2		T3	1		T4	1
all_pins[7]	values[0x1]	205	1			T15	3		T16	7		T19	4
all_pins[7]	transitions[0x0=>0x1]	136	1			T16	3		T19	4		T21	1
all_pins[7]	transitions[0x1=>0x0]	771	1			T15	205		T66	3		T16	2