Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16774

1

T8

214

T11

4

T12

68

auto[1]

11778

1

T4

22

T8

224

T9

14

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3647	1			T13	30		T97	14		T33	26
values[1]	3116	1			T9	14		T12	42		T13	29
values[2]	4248	1			T8	155		T11	4		T12	49
values[3]	3550	1			T8	66		T33	45		T129	4
values[4]	3423	1			T33	20		T64	40		T48	21
values[5]	3723	1			T8	26		T13	75		T33	30
values[6]	3150	1			T8	81		T12	40		T13	27
values[7]	3695	1			T4	22		T8	110		T13	27

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3417	1			T8	92		T12	20		T13	157
values[1]	3610	1			T8	219		T12	21		T13	55
values[2]	3922	1			T12	49		T13	45		T33	40
values[3]	3604	1			T4	22		T8	61		T9	14
values[4]	3752	1			T33	51		T64	20		T62	10
values[5]	3193	1			T11	4		T13	29		T64	20
values[6]	3237	1			T8	46		T12	21		T13	50
values[7]	3817	1			T8	20		T12	20		T13	54

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	220	1			T20	9		T239	13		T54	23
auto[0]	values[0]	values[1]	296	1			T20	11		T192	9		T253	20
auto[0]	values[0]	values[2]	222	1			T206	20		T254	57		T214	11
auto[0]	values[0]	values[3]	330	1			T38	12		T179	33		T234	21
auto[0]	values[0]	values[4]	361	1			T62	10		T202	11		T179	19
auto[0]	values[0]	values[5]	242	1			T22	26		T255	2		T256	22
auto[0]	values[0]	values[6]	390	1			T13	19		T15	12		T36	8
auto[0]	values[0]	values[7]	205	1			T33	12		T257	2		T20	11
auto[0]	values[1]	values[0]	202	1			T48	20		T20	51		T234	10
auto[0]	values[1]	values[1]	223	1			T12	9		T180	9		T164	23
auto[0]	values[1]	values[2]	216	1			T15	16		T226	14		T202	12
auto[0]	values[1]	values[3]	203	1			T33	11		T223	11		T258	2
auto[0]	values[1]	values[4]	276	1			T33	15		T53	15		T233	2
auto[0]	values[1]	values[5]	199	1			T13	11		T64	15		T234	35
auto[0]	values[1]	values[6]	323	1			T12	11		T259	41		T206	11
auto[0]	values[1]	values[7]	181	1			T107	10		T15	15		T202	12
auto[0]	values[2]	values[0]	230	1			T8	14		T13	8		T180	13
auto[0]	values[2]	values[1]	340	1			T8	75		T260	4		T234	11
auto[0]	values[2]	values[2]	472	1			T12	24		T13	38		T15	13
auto[0]	values[2]	values[3]	307	1			T261	2		T198	11		T232	54
auto[0]	values[2]	values[4]	232	1			T206	40		T89	14		T166	13
auto[0]	values[2]	values[5]	202	1			T11	4		T202	10		T234	24
auto[0]	values[2]	values[6]	247	1			T106	6		T262	4		T20	9
auto[0]	values[2]	values[7]	314	1			T48	13		T180	14		T234	12
auto[0]	values[3]	values[0]	119	1			T226	12		T22	7		T263	2
auto[0]	values[3]	values[1]	285	1			T8	6		T33	17		T15	7
auto[0]	values[3]	values[2]	212	1			T234	16		T206	11		T207	14
auto[0]	values[3]	values[3]	277	1			T33	14		T234	15		T264	2
auto[0]	values[3]	values[4]	353	1			T177	15		T74	47		T164	12
auto[0]	values[3]	values[5]	276	1			T129	4		T40	15		T177	8
auto[0]	values[3]	values[6]	168	1			T226	14		T196	8		T96	13
auto[0]	values[3]	values[7]	348	1			T180	11		T36	15		T265	4
auto[0]	values[4]	values[0]	314	1			T15	13		T202	20		T223	29
auto[0]	values[4]	values[1]	202	1			T179	17		T22	13		T37	12
auto[0]	values[4]	values[2]	204	1			T33	13		T15	7		T180	12
auto[0]	values[4]	values[3]	304	1			T48	17		T179	14		T180	10
auto[0]	values[4]	values[4]	216	1			T64	10		T15	10		T20	14
auto[0]	values[4]	values[5]	253	1			T57	6		T26	11		T22	16
auto[0]	values[4]	values[6]	186	1			T26	8		T192	10		T22	22
auto[0]	values[4]	values[7]	313	1			T64	10		T15	13		T198	26
auto[0]	values[5]	values[0]	287	1			T266	22		T239	20		T198	8
auto[0]	values[5]	values[1]	336	1			T13	12		T210	14		T232	27
auto[0]	values[5]	values[2]	402	1			T64	12		T48	15		T246	10
auto[0]	values[5]	values[3]	257	1			T85	65		T202	19		T180	15
auto[0]	values[5]	values[4]	257	1			T33	13		T229	14		T164	8
auto[0]	values[5]	values[5]	216	1			T15	13		T180	12		T36	34
auto[0]	values[5]	values[6]	216	1			T8	20		T13	11		T267	10
auto[0]	values[5]	values[7]	330	1			T47	65		T20	13		T192	14
auto[0]	values[6]	values[0]	266	1			T12	18		T179	13		T22	10
auto[0]	values[6]	values[1]	188	1			T108	2		T85	14		T268	6
auto[0]	values[6]	values[2]	218	1			T33	14		T179	11		T269	4
auto[0]	values[6]	values[3]	218	1			T8	8		T15	14		T226	12
auto[0]	values[6]	values[4]	211	1			T20	7		T192	12		T214	15
auto[0]	values[6]	values[5]	155	1			T199	6		T211	9		T270	9
auto[0]	values[6]	values[6]	238	1			T8	10		T15	18		T210	9
auto[0]	values[6]	values[7]	219	1			T12	6		T13	21		T22	13
auto[0]	values[7]	values[0]	223	1			T8	9		T271	20		T211	25
auto[0]	values[7]	values[1]	356	1			T8	59		T164	27		T214	7
auto[0]	values[7]	values[2]	281	1			T20	13		T272	4		T36	15
auto[0]	values[7]	values[3]	172	1			T226	13		T164	12		T54	17
auto[0]	values[7]	values[4]	360	1			T26	7		T202	13		T192	10
auto[0]	values[7]	values[5]	333	1			T23	18		T202	11		T206	11
auto[0]	values[7]	values[6]	204	1			T198	26		T207	13		T212	11
auto[0]	values[7]	values[7]	368	1			T8	13		T13	13		T199	13
auto[1]	values[0]	values[0]	174	1			T97	14		T20	57		T239	7
auto[1]	values[0]	values[1]	155	1			T20	9		T192	11		T211	10
auto[1]	values[0]	values[2]	177	1			T206	20		T254	8		T214	11
auto[1]	values[0]	values[3]	228	1			T38	8		T179	11		T234	4
auto[1]	values[0]	values[4]	196	1			T202	15		T179	11		T234	12
auto[1]	values[0]	values[5]	163	1			T22	10		T273	14		T274	11
auto[1]	values[0]	values[6]	107	1			T13	11		T15	9		T36	12
auto[1]	values[0]	values[7]	181	1			T33	14		T20	55		T275	6
auto[1]	values[1]	values[0]	145	1			T48	22		T20	6		T234	10
auto[1]	values[1]	values[1]	100	1			T12	12		T180	12		T164	7
auto[1]	values[1]	values[2]	91	1			T15	10		T226	15		T202	8
auto[1]	values[1]	values[3]	197	1			T9	14		T33	9		T223	37
auto[1]	values[1]	values[4]	257	1			T33	6		T53	5		T51	28
auto[1]	values[1]	values[5]	118	1			T13	18		T64	5		T234	15
auto[1]	values[1]	values[6]	206	1			T12	10		T206	12		T232	10
auto[1]	values[1]	values[7]	179	1			T15	5		T202	8		T232	8
auto[1]	values[2]	values[0]	382	1			T8	58		T13	149		T180	8
auto[1]	values[2]	values[1]	197	1			T8	8		T234	14		T164	7
auto[1]	values[2]	values[2]	436	1			T12	25		T13	7		T15	20
auto[1]	values[2]	values[3]	158	1			T198	9		T232	7		T211	10
auto[1]	values[2]	values[4]	131	1			T206	13		T166	17		T230	5
auto[1]	values[2]	values[5]	143	1			T202	10		T234	5		T22	11
auto[1]	values[2]	values[6]	259	1			T235	6		T20	79		T22	6
auto[1]	values[2]	values[7]	198	1			T48	9		T276	12		T180	6
auto[1]	values[3]	values[0]	88	1			T226	11		T22	13		T228	9
auto[1]	values[3]	values[1]	284	1			T8	60		T33	6		T15	24
auto[1]	values[3]	values[2]	203	1			T234	11		T206	12		T207	8
auto[1]	values[3]	values[3]	218	1			T33	8		T234	5		T277	4
auto[1]	values[3]	values[4]	183	1			T177	45		T164	11		T54	8
auto[1]	values[3]	values[5]	176	1			T40	6		T177	12		T193	8
auto[1]	values[3]	values[6]	79	1			T226	6		T278	2		T96	7
auto[1]	values[3]	values[7]	281	1			T180	9		T36	5		T232	10
auto[1]	values[4]	values[0]	154	1			T15	7		T202	4		T223	9
auto[1]	values[4]	values[1]	136	1			T179	3		T22	7		T37	10
auto[1]	values[4]	values[2]	181	1			T33	7		T15	17		T180	8
auto[1]	values[4]	values[3]	184	1			T48	4		T179	13		T180	10
auto[1]	values[4]	values[4]	179	1			T64	10		T15	10		T20	6
auto[1]	values[4]	values[5]	229	1			T26	9		T22	4		T96	13
auto[1]	values[4]	values[6]	185	1			T26	12		T192	10		T22	5
auto[1]	values[4]	values[7]	183	1			T64	10		T15	7		T198	14
auto[1]	values[5]	values[0]	238	1			T24	26		T239	20		T198	12
auto[1]	values[5]	values[1]	160	1			T13	43		T210	7		T232	19
auto[1]	values[5]	values[2]	258	1			T64	8		T48	8		T223	9
auto[1]	values[5]	values[3]	213	1			T85	10		T202	8		T180	10
auto[1]	values[5]	values[4]	178	1			T33	17		T164	12		T166	11
auto[1]	values[5]	values[5]	151	1			T15	7		T180	10		T36	13
auto[1]	values[5]	values[6]	67	1			T8	6		T13	9		T36	8
auto[1]	values[5]	values[7]	157	1			T20	7		T192	6		T212	6
auto[1]	values[6]	values[0]	234	1			T12	2		T179	7		T22	10
auto[1]	values[6]	values[1]	108	1			T85	6		T207	17		T232	14
auto[1]	values[6]	values[2]	198	1			T33	6		T249	22		T179	9
auto[1]	values[6]	values[3]	211	1			T8	53		T15	11		T226	8
auto[1]	values[6]	values[4]	164	1			T20	13		T192	8		T214	12
auto[1]	values[6]	values[5]	143	1			T199	50		T211	11		T270	11
auto[1]	values[6]	values[6]	204	1			T8	10		T15	6		T210	11
auto[1]	values[6]	values[7]	175	1			T12	14		T13	6		T22	7
auto[1]	values[7]	values[0]	141	1			T8	11		T211	6		T279	9
auto[1]	values[7]	values[1]	244	1			T8	11		T164	5		T214	16
auto[1]	values[7]	values[2]	151	1			T20	7		T36	5		T211	4
auto[1]	values[7]	values[3]	127	1			T4	22		T226	7		T164	16
auto[1]	values[7]	values[4]	198	1			T26	13		T202	21		T192	10
auto[1]	values[7]	values[5]	194	1			T202	9		T206	9		T217	8
auto[1]	values[7]	values[6]	158	1			T280	18		T198	14		T207	7
auto[1]	values[7]	values[7]	185	1			T8	7		T13	14		T199	7