Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	441	1			T8	1		T12	5		T13	3
auto[ReadAddrCrossIntoMailbox]	286	1			T8	4		T12	3		T13	5
auto[ReadAddrCrossOutOfMailbox]	322	1			T8	3		T12	3		T13	4
auto[ReadAddrCrossAllMailbox]	230	1			T8	2		T12	2		T13	3
auto[ReadAddrOutsideMailbox]	3531	1			T4	6		T8	40		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2449

1

T4

3

T8

26

T9

1

auto[1]

2361

1

T4

3

T8

24

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	868	1			T8	9		T11	2		T12	3
read_ops[0x0b]	764	1			T4	6		T8	10		T12	3
read_ops[0x3b]	827	1			T8	9		T11	2		T12	3
read_ops[0x6b]	799	1			T8	11		T12	4		T13	5
read_ops[0xbb]	755	1			T8	7		T12	6		T13	10
read_ops[0xeb]	797	1			T8	4		T9	2		T12	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T12	1		T15	1		T20	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T179	1		T20	2		T223	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T8	1		T12	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T8	1		T13	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T13	1		T33	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T13	1		T48	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T33	1		T226	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T13	1		T234	1		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T8	3		T11	1		T12	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T8	4		T11	1		T13	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T202	1		T281	1		T234	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T13	1		T281	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T8	1		T13	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T13	1		T15	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T8	2		T15	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T13	1		T48	1		T239	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T8	1		T202	1		T234	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T179	2		T20	1		T223	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T4	3		T8	6		T12	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T4	3		T13	2		T33	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T12	2		T226	1		T179	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T13	1		T64	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T8	1		T15	1		T226	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T48	1		T226	1		T180	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T15	1		T232	1		T282	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T226	1		T20	1		T239	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T26	1		T226	1		T281	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	1		T281	1		T239	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T8	3		T11	1		T33	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T8	5		T11	1		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T12	1		T48	1		T38	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T8	1		T20	2		T234	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T33	2		T281	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T281	1		T192	1		T239	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T12	1		T26	1		T22	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T239	1		T193	1		T214	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T12	1		T179	1		T177	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T20	1		T283	1		T198	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T8	3		T64	2		T48	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T8	7		T12	1		T13	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T12	1		T33	1		T180	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T38	1		T192	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T26	1		T226	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T13	2		T180	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T12	2		T15	1		T234	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T13	1		T226	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T26	1		T202	1		T179	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T8	1		T13	2		T223	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T8	1		T12	3		T48	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T8	5		T13	5		T33	7
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T198	1		T207	1		T232	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T13	1		T26	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T12	2		T15	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T20	1		T164	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T8	1		T192	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T15	1		T179	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T48	1		T20	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T202	1		T284	1		T228	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T8	3		T9	1		T13	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T9	1		T12	3		T13	1