Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3629	1			T4	22		T8	20		T12	29
values[1]	3581	1			T12	21		T48	42		T15	26
values[2]	3486	1			T8	173		T13	86		T97	14
values[3]	3758	1			T12	41		T33	20		T64	20
values[4]	3791	1			T8	92		T11	4		T33	47
values[5]	3296	1			T8	61		T13	184		T33	20
values[6]	3194	1			T12	40		T13	45		T33	30
values[7]	3817	1			T8	92		T9	14		T33	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3388	1			T8	151		T13	27		T97	14
values[1]	3521	1			T4	22		T13	47		T33	43
values[2]	3338	1			T8	86		T9	14		T12	61
values[3]	4031	1			T64	20		T48	21		T257	2
values[4]	3628	1			T13	29		T33	30		T129	4
values[5]	3620	1			T8	72		T33	20		T48	45
values[6]	3961	1			T8	20		T12	50		T13	30
values[7]	3065	1			T8	109		T11	4		T12	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27816

1

T4

20

T8

424

T9

12

auto[1]

736

1

T4

2

T8

14

T9

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	378	1			T202	27		T283	4		T244	19
auto[0]	values[0]	values[1]	724	1			T4	20		T13	20		T33	22
auto[0]	values[0]	values[2]	318	1			T8	20		T33	20		T108	2
auto[0]	values[0]	values[3]	428	1			T180	20		T206	20		T217	18
auto[0]	values[0]	values[4]	310	1			T217	37		T193	17		T232	20
auto[0]	values[0]	values[5]	510	1			T180	19		T36	20		T253	20
auto[0]	values[0]	values[6]	370	1			T12	28		T226	20		T180	25
auto[0]	values[0]	values[7]	489	1			T13	53		T15	19		T192	18
auto[0]	values[1]	values[0]	458	1			T276	8		T281	6		T180	20
auto[0]	values[1]	values[1]	371	1			T226	20		T202	25		T259	41
auto[0]	values[1]	values[2]	362	1			T12	20		T202	20		T199	20
auto[0]	values[1]	values[3]	320	1			T48	21		T40	21		T180	20
auto[0]	values[1]	values[4]	591	1			T48	21		T15	23		T38	20
auto[0]	values[1]	values[5]	513	1			T20	58		T164	20		T207	34
auto[0]	values[1]	values[6]	519	1			T226	20		T179	28		T254	65
auto[0]	values[1]	values[7]	337	1			T239	16		T54	59		T211	19
auto[0]	values[2]	values[0]	351	1			T8	87		T13	27		T97	14
auto[0]	values[2]	values[1]	412	1			T22	18		T229	14		T164	22
auto[0]	values[2]	values[2]	494	1			T47	65		T246	10		T20	20
auto[0]	values[2]	values[3]	598	1			T15	20		T202	18		T22	19
auto[0]	values[2]	values[4]	295	1			T13	29		T22	18		T164	23
auto[0]	values[2]	values[5]	192	1			T198	20		T285	37		T195	20
auto[0]	values[2]	values[6]	678	1			T13	30		T64	20		T20	66
auto[0]	values[2]	values[7]	399	1			T8	81		T85	20		T177	60
auto[0]	values[3]	values[0]	492	1			T267	10		T22	19		T88	20
auto[0]	values[3]	values[1]	298	1			T192	20		T239	20		T168	90
auto[0]	values[3]	values[2]	363	1			T235	6		T260	4		T232	20
auto[0]	values[3]	values[3]	525	1			T64	20		T257	2		T15	29
auto[0]	values[3]	values[4]	547	1			T15	19		T20	55		T22	24
auto[0]	values[3]	values[5]	424	1			T33	20		T107	10		T15	44
auto[0]	values[3]	values[6]	605	1			T12	21		T106	6		T249	14
auto[0]	values[3]	values[7]	404	1			T12	20		T179	20		T164	28
auto[0]	values[4]	values[0]	422	1			T239	20		T164	20		T210	20
auto[0]	values[4]	values[1]	405	1			T33	20		T57	6		T51	26
auto[0]	values[4]	values[2]	202	1			T202	20		T265	4		T286	18
auto[0]	values[4]	values[3]	500	1			T202	33		T207	20		T54	20
auto[0]	values[4]	values[4]	597	1			T48	21		T179	26		T287	22
auto[0]	values[4]	values[5]	588	1			T8	70		T48	21		T179	20
auto[0]	values[4]	values[6]	591	1			T8	20		T26	20		T266	22
auto[0]	values[4]	values[7]	404	1			T11	4		T33	23		T20	119
auto[0]	values[5]	values[0]	359	1			T8	59		T196	8		T288	20
auto[0]	values[5]	values[1]	371	1			T13	27		T223	20		T37	21
auto[0]	values[5]	values[2]	691	1			T13	155		T33	17		T15	23
auto[0]	values[5]	values[3]	421	1			T15	30		T269	4		T221	20
auto[0]	values[5]	values[4]	466	1			T85	75		T226	29		T234	23
auto[0]	values[5]	values[5]	300	1			T202	20		T22	19		T199	55
auto[0]	values[5]	values[6]	324	1			T234	19		T36	20		T211	28
auto[0]	values[5]	values[7]	279	1			T64	20		T234	20		T289	18
auto[0]	values[6]	values[0]	406	1			T223	20		T164	92		T193	20
auto[0]	values[6]	values[1]	392	1			T234	28		T164	23		T198	18
auto[0]	values[6]	values[2]	407	1			T12	39		T13	44		T262	4
auto[0]	values[6]	values[3]	538	1			T234	25		T261	2		T22	38
auto[0]	values[6]	values[4]	290	1			T33	24		T129	4		T20	86
auto[0]	values[6]	values[5]	573	1			T180	22		T234	26		T36	56
auto[0]	values[6]	values[6]	225	1			T206	20		T169	23		T290	14
auto[0]	values[6]	values[7]	271	1			T15	20		T180	20		T263	2
auto[0]	values[7]	values[0]	447	1			T23	18		T20	66		T234	20
auto[0]	values[7]	values[1]	458	1			T64	20		T53	20		T15	24
auto[0]	values[7]	values[2]	420	1			T8	63		T9	12		T33	23
auto[0]	values[7]	values[3]	611	1			T24	26		T234	25		T210	20
auto[0]	values[7]	values[4]	407	1			T202	20		T280	18		T291	8
auto[0]	values[7]	values[5]	441	1			T48	21		T226	23		T272	4
auto[0]	values[7]	values[6]	548	1			T62	10		T180	20		T192	18
auto[0]	values[7]	values[7]	387	1			T8	24		T26	20		T22	19
auto[1]	values[0]	values[0]	11	1			T244	1		T228	2		T200	1
auto[1]	values[0]	values[1]	20	1			T4	2		T15	1		T192	1
auto[1]	values[0]	values[2]	10	1			T56	2		T292	1		T293	2
auto[1]	values[0]	values[3]	8	1			T180	1		T217	2		T168	1
auto[1]	values[0]	values[4]	14	1			T217	1		T193	3		T294	4
auto[1]	values[0]	values[5]	15	1			T180	1		T210	1		T54	3
auto[1]	values[0]	values[6]	7	1			T12	1		T239	2		T206	2
auto[1]	values[0]	values[7]	17	1			T13	2		T15	1		T192	2
auto[1]	values[1]	values[0]	16	1			T276	4		T239	2		T169	1
auto[1]	values[1]	values[1]	11	1			T202	1		T195	1		T295	3
auto[1]	values[1]	values[2]	4	1			T12	1		T296	1		T297	2
auto[1]	values[1]	values[3]	11	1			T298	1		T195	2		T299	4
auto[1]	values[1]	values[4]	23	1			T15	3		T300	1		T301	1
auto[1]	values[1]	values[5]	10	1			T20	2		T232	1		T302	1
auto[1]	values[1]	values[6]	22	1			T179	2		T211	2		T214	2
auto[1]	values[1]	values[7]	13	1			T239	4		T54	1		T211	1
auto[1]	values[2]	values[0]	7	1			T8	3		T303	2		T201	1
auto[1]	values[2]	values[1]	11	1			T22	2		T164	1		T210	1
auto[1]	values[2]	values[2]	14	1			T198	2		T304	2		T305	1
auto[1]	values[2]	values[3]	11	1			T202	2		T22	1		T211	1
auto[1]	values[2]	values[4]	7	1			T22	2		T195	2		T306	2
auto[1]	values[2]	values[5]	2	1			T302	1		T307	1		-	-
auto[1]	values[2]	values[6]	9	1			T22	2		T145	2		T308	2
auto[1]	values[2]	values[7]	6	1			T8	2		T198	1		T225	2
auto[1]	values[3]	values[0]	10	1			T22	1		T309	2		T230	1
auto[1]	values[3]	values[1]	3	1			T168	3		-	-		-	-
auto[1]	values[3]	values[2]	9	1			T166	2		T288	2		T56	2
auto[1]	values[3]	values[3]	5	1			T15	2		T26	1		T232	2
auto[1]	values[3]	values[4]	25	1			T15	1		T20	2		T22	3
auto[1]	values[3]	values[5]	10	1			T223	1		T164	1		T310	4
auto[1]	values[3]	values[6]	22	1			T249	8		T164	2		T207	1
auto[1]	values[3]	values[7]	16	1			T207	1		T54	3		T302	1
auto[1]	values[4]	values[0]	10	1			T198	1		T300	1		T200	2
auto[1]	values[4]	values[1]	8	1			T33	1		T51	2		T223	1
auto[1]	values[4]	values[2]	3	1			T311	1		T312	2		-	-
auto[1]	values[4]	values[3]	10	1			T202	1		T212	1		T308	1
auto[1]	values[4]	values[4]	19	1			T179	1		T239	2		T282	3
auto[1]	values[4]	values[5]	9	1			T8	2		T48	1		T88	2
auto[1]	values[4]	values[6]	12	1			T36	1		T206	2		T96	2
auto[1]	values[4]	values[7]	11	1			T33	3		T20	5		T241	1
auto[1]	values[5]	values[0]	8	1			T8	2		T313	1		T314	2
auto[1]	values[5]	values[1]	17	1			T223	1		T37	1		T228	4
auto[1]	values[5]	values[2]	17	1			T13	2		T33	3		T15	1
auto[1]	values[5]	values[3]	15	1			T15	3		T54	2		T168	1
auto[1]	values[5]	values[4]	12	1			T313	3		T302	2		T200	1
auto[1]	values[5]	values[5]	4	1			T22	1		T199	1		T315	2
auto[1]	values[5]	values[6]	5	1			T234	1		T212	1		T230	2
auto[1]	values[5]	values[7]	7	1			T279	1		T295	1		T304	1
auto[1]	values[6]	values[0]	10	1			T211	1		T201	3		T305	1
auto[1]	values[6]	values[1]	9	1			T234	2		T198	2		T96	3
auto[1]	values[6]	values[2]	13	1			T12	1		T13	1		T179	2
auto[1]	values[6]	values[3]	15	1			T22	2		T207	2		T54	1
auto[1]	values[6]	values[4]	16	1			T33	6		T20	2		T146	2
auto[1]	values[6]	values[5]	17	1			T234	3		T36	1		T313	1
auto[1]	values[6]	values[6]	6	1			T169	2		T302	1		T56	1
auto[1]	values[6]	values[7]	6	1			T200	1		T145	1		T316	3
auto[1]	values[7]	values[0]	3	1			T317	1		T293	1		T318	1
auto[1]	values[7]	values[1]	11	1			T15	1		T210	4		T54	1
auto[1]	values[7]	values[2]	11	1			T8	3		T9	2		T198	1
auto[1]	values[7]	values[3]	15	1			T210	1		T201	1		T296	3
auto[1]	values[7]	values[4]	9	1			T274	2		T305	2		T148	2
auto[1]	values[7]	values[5]	12	1			T48	2		T223	3		T206	2
auto[1]	values[7]	values[6]	18	1			T180	1		T192	2		T223	1
auto[1]	values[7]	values[7]	19	1			T8	2		T22	3		T164	2