Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	907	1			T15	7		T66	4		T16	14
all_values[1]	907	1			T15	7		T66	4		T16	14
all_values[2]	907	1			T15	7		T66	4		T16	14
all_values[3]	907	1			T15	7		T66	4		T16	14
all_values[4]	907	1			T15	7		T66	4		T16	14
all_values[5]	907	1			T15	7		T66	4		T16	14
all_values[6]	907	1			T15	7		T66	4		T16	14
all_values[7]	907	1			T15	7		T66	4		T16	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3830

1

T15

26

T66

17

T16

63

auto[1]

3426

1

T15

30

T66

15

T16

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2825

1

T15

17

T66

10

T16

47

auto[1]

4431

1

T15

39

T66

22

T16

65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4102

1

T15

36

T66

17

T16

68

auto[1]

3154

1

T15

20

T66

15

T16

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	162	1			T66	1		T16	2		T67	2
all_values[0]	auto[0]	auto[0]	auto[1]	104	1			T15	2		T16	1		T67	2
all_values[0]	auto[0]	auto[1]	auto[0]	141	1			T16	3		T19	4		T21	1
all_values[0]	auto[0]	auto[1]	auto[1]	100	1			T15	2		T66	1		T16	2
all_values[0]	auto[1]	auto[0]	auto[1]	220	1			T15	2		T16	3		T19	4
all_values[0]	auto[1]	auto[1]	auto[1]	180	1			T15	1		T66	2		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	189	1			T66	3		T16	2		T67	1
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T15	1		T16	3		T67	2
all_values[1]	auto[0]	auto[1]	auto[0]	154	1			T66	1		T16	4		T67	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T15	3		T19	1		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	207	1			T15	1		T16	4		T67	1
all_values[1]	auto[1]	auto[1]	auto[1]	191	1			T15	2		T16	1		T67	3
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T66	2		T16	4		T19	4
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T15	1		T16	1		T67	1
all_values[2]	auto[0]	auto[1]	auto[0]	156	1			T15	2		T16	1		T67	3
all_values[2]	auto[0]	auto[1]	auto[1]	101	1			T15	2		T66	1		T16	2
all_values[2]	auto[1]	auto[0]	auto[1]	195	1			T15	1		T66	1		T16	4
all_values[2]	auto[1]	auto[1]	auto[1]	184	1			T15	1		T16	2		T67	3
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T15	1		T16	3		T67	2
all_values[3]	auto[0]	auto[0]	auto[1]	91	1			T15	1		T67	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T15	1		T67	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	98	1			T15	1		T66	1		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	229	1			T15	1		T66	1		T16	7
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T15	2		T66	2		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	162	1			T15	1		T16	6		T67	3
all_values[4]	auto[0]	auto[0]	auto[1]	97	1			T16	4		T19	2		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T15	1		T66	1		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T15	1		T66	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	224	1			T15	3		T66	2		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	183	1			T15	1		T16	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T15	4		T66	1		T16	5
all_values[5]	auto[0]	auto[1]	auto[0]	230	1			T15	1		T16	2		T67	1
all_values[5]	auto[1]	auto[0]	auto[1]	232	1			T15	2		T16	2		T67	2
all_values[5]	auto[1]	auto[1]	auto[1]	199	1			T66	3		T16	5		T67	1
all_values[6]	auto[0]	auto[0]	auto[0]	190	1			T15	3		T16	3		T67	3
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T16	1		T19	1		T21	2
all_values[6]	auto[0]	auto[1]	auto[0]	159	1			T15	2		T66	1		T16	6
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T15	1		T66	1		T67	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T66	2		T16	2		T67	2
all_values[6]	auto[1]	auto[1]	auto[1]	182	1			T15	1		T16	2		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	202	1			T16	1		T19	4		T21	3
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T15	2		T66	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	172	1			T15	1		T16	3		T67	5
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T15	2		T16	4		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T66	2		T16	3		T67	2
all_values[7]	auto[1]	auto[1]	auto[1]	179	1			T15	2		T16	2		T67	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal