Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1743

1

T3

2

T6

2

T12

12

auto[1]

1740

1

T3

4

T6

3

T12

14

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1919

1

T6

5

T12

26

T13

8

auto[1]

1564

1

T3

6

T29

44

T33

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2744

1

T3

6

T6

3

T12

20

auto[1]

739

1

T6

2

T12

6

T13

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	716	1			T3	2		T6	2		T12	7
valid[1]	705	1			T12	2		T29	11		T32	7
valid[2]	685	1			T3	3		T6	1		T12	9
valid[3]	717	1			T6	2		T12	5		T29	5
valid[4]	660	1			T3	1		T12	3		T29	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	114	1			T12	2		T13	1		T32	3
auto[0]	auto[0]	valid[0]	auto[1]	184	1			T3	1		T29	5		T33	2
auto[0]	auto[0]	valid[1]	auto[0]	117	1			T12	1		T32	3		T15	2
auto[0]	auto[0]	valid[1]	auto[1]	152	1			T29	6		T35	4		T87	2
auto[0]	auto[0]	valid[2]	auto[0]	112	1			T12	3		T32	2		T15	1
auto[0]	auto[0]	valid[2]	auto[1]	138	1			T29	3		T35	2		T87	2
auto[0]	auto[0]	valid[3]	auto[0]	126	1			T6	1		T12	1		T32	4
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T29	1		T34	1		T35	6
auto[0]	auto[0]	valid[4]	auto[0]	105	1			T12	2		T48	1		T15	2
auto[0]	auto[0]	valid[4]	auto[1]	143	1			T3	1		T29	7		T35	2
auto[0]	auto[1]	valid[0]	auto[0]	127	1			T12	4		T13	1		T32	1
auto[0]	auto[1]	valid[0]	auto[1]	149	1			T3	1		T29	4		T34	1
auto[0]	auto[1]	valid[1]	auto[0]	128	1			T32	2		T15	2		T66	2
auto[0]	auto[1]	valid[1]	auto[1]	149	1			T29	5		T41	2		T86	2
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T6	1		T12	4		T13	1
auto[0]	auto[1]	valid[2]	auto[1]	150	1			T3	3		T29	5		T34	1
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T6	1		T12	2		T13	2
auto[0]	auto[1]	valid[3]	auto[1]	170	1			T29	4		T35	3		T86	3
auto[0]	auto[1]	valid[4]	auto[0]	112	1			T12	1		T32	3		T48	1
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T29	4		T35	2		T41	5
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T6	1		T13	1		T48	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T12	1		T32	2		T48	1
auto[1]	auto[0]	valid[2]	auto[0]	91	1			T12	1		T32	1		T15	2
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T12	1		T15	1		T179	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T13	1		T48	1		T66	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T6	1		T12	1		T32	1
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T33	1		T15	2		T226	2
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T12	1		T13	1		T15	1
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T12	1		T15	1		T66	1
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T15	2		T66	1		T179	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal