Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48402

1

T6

75

T12

608

T30

2

auto[1]

15763

1

T3

48

T29

495

T33

78

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46783

1

T3

48

T6

44

T12

424

auto[1]

17382

1

T6

31

T12

184

T30

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32776	1			T3	25		T6	38		T12	300
others[1]	5608	1			T3	7		T6	6		T12	50
others[2]	5389	1			T3	6		T6	2		T12	51
others[3]	6221	1			T3	1		T6	10		T12	63
interest[1]	3502	1			T3	1		T6	4		T12	43
interest[4]	21691	1			T3	12		T6	27		T12	190
interest[64]	10669	1			T3	8		T6	15		T12	101

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15734	1			T6	25		T12	206		T13	68
auto[0]	auto[0]	others[1]	2683	1			T6	2		T12	38		T13	12
auto[0]	auto[0]	others[2]	2663	1			T12	38		T13	6		T32	27
auto[0]	auto[0]	others[3]	3036	1			T6	4		T12	43		T30	1
auto[0]	auto[0]	interest[1]	1629	1			T6	4		T12	32		T13	5
auto[0]	auto[0]	interest[4]	10375	1			T6	20		T12	134		T13	47
auto[0]	auto[0]	interest[64]	5275	1			T6	9		T12	67		T13	19
auto[0]	auto[1]	others[0]	8235	1			T3	25		T29	258		T33	38
auto[0]	auto[1]	others[1]	1402	1			T3	7		T29	42		T33	8
auto[0]	auto[1]	others[2]	1250	1			T3	6		T29	40		T33	13
auto[0]	auto[1]	others[3]	1485	1			T3	1		T29	47		T33	4
auto[0]	auto[1]	interest[1]	839	1			T3	1		T29	25		T33	6
auto[0]	auto[1]	interest[4]	5529	1			T3	12		T29	167		T33	23
auto[0]	auto[1]	interest[64]	2552	1			T3	8		T29	83		T33	9
auto[1]	auto[0]	others[0]	8807	1			T6	13		T12	94		T13	25
auto[1]	auto[0]	others[1]	1523	1			T6	4		T12	12		T13	6
auto[1]	auto[0]	others[2]	1476	1			T6	2		T12	13		T13	4
auto[1]	auto[0]	others[3]	1700	1			T6	6		T12	20		T13	4
auto[1]	auto[0]	interest[1]	1034	1			T12	11		T13	3		T32	7
auto[1]	auto[0]	interest[4]	5787	1			T6	7		T12	56		T13	21
auto[1]	auto[0]	interest[64]	2842	1			T6	6		T12	34		T30	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal