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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T1046 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3385622138 Aug 04 04:26:26 PM PDT 24 Aug 04 04:26:27 PM PDT 24 46080193 ps
T135 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3665617861 Aug 04 04:25:54 PM PDT 24 Aug 04 04:26:17 PM PDT 24 1465894078 ps
T105 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2827067281 Aug 04 04:26:26 PM PDT 24 Aug 04 04:26:29 PM PDT 24 84567293 ps
T104 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2512702049 Aug 04 04:26:37 PM PDT 24 Aug 04 04:26:40 PM PDT 24 48788201 ps
T136 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.964852686 Aug 04 04:25:47 PM PDT 24 Aug 04 04:26:11 PM PDT 24 1860695185 ps
T1047 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3658910308 Aug 04 04:26:35 PM PDT 24 Aug 04 04:26:36 PM PDT 24 149901329 ps
T127 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.175018849 Aug 04 04:26:44 PM PDT 24 Aug 04 04:26:51 PM PDT 24 358404751 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.538081209 Aug 04 04:26:17 PM PDT 24 Aug 04 04:26:18 PM PDT 24 89631988 ps
T1049 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.284949385 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:37 PM PDT 24 105443895 ps
T137 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3832819323 Aug 04 04:26:05 PM PDT 24 Aug 04 04:26:21 PM PDT 24 604353791 ps
T1050 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2054049757 Aug 04 04:26:44 PM PDT 24 Aug 04 04:26:45 PM PDT 24 31586295 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2310913450 Aug 04 04:26:51 PM PDT 24 Aug 04 04:26:51 PM PDT 24 19797604 ps
T1052 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2045665943 Aug 04 04:27:03 PM PDT 24 Aug 04 04:27:04 PM PDT 24 127213456 ps
T128 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3532844100 Aug 04 04:25:56 PM PDT 24 Aug 04 04:26:11 PM PDT 24 2552604963 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1602707329 Aug 04 04:26:11 PM PDT 24 Aug 04 04:26:17 PM PDT 24 306983692 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2134295479 Aug 04 04:26:13 PM PDT 24 Aug 04 04:26:14 PM PDT 24 71593379 ps
T111 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2824951975 Aug 04 04:26:11 PM PDT 24 Aug 04 04:26:14 PM PDT 24 120121002 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3387735886 Aug 04 04:26:35 PM PDT 24 Aug 04 04:26:35 PM PDT 24 16590490 ps
T1055 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3527634212 Aug 04 04:26:47 PM PDT 24 Aug 04 04:26:48 PM PDT 24 35905316 ps
T114 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4008350779 Aug 04 04:26:11 PM PDT 24 Aug 04 04:26:13 PM PDT 24 198063375 ps
T138 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2646159181 Aug 04 04:27:54 PM PDT 24 Aug 04 04:27:57 PM PDT 24 116696408 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.870941877 Aug 04 04:26:38 PM PDT 24 Aug 04 04:26:41 PM PDT 24 147847269 ps
T1057 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2310749696 Aug 04 04:26:41 PM PDT 24 Aug 04 04:26:42 PM PDT 24 41670396 ps
T113 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.557703605 Aug 04 04:26:45 PM PDT 24 Aug 04 04:26:46 PM PDT 24 27940943 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1151908404 Aug 04 04:25:53 PM PDT 24 Aug 04 04:25:54 PM PDT 24 12801386 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2179636937 Aug 04 04:26:40 PM PDT 24 Aug 04 04:26:44 PM PDT 24 63743403 ps
T112 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3167942496 Aug 04 04:26:39 PM PDT 24 Aug 04 04:26:43 PM PDT 24 700208173 ps
T119 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2140455040 Aug 04 04:26:47 PM PDT 24 Aug 04 04:26:51 PM PDT 24 998442498 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2973419948 Aug 04 04:26:22 PM PDT 24 Aug 04 04:26:23 PM PDT 24 49699904 ps
T1061 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3981592788 Aug 04 04:27:01 PM PDT 24 Aug 04 04:27:01 PM PDT 24 22794634 ps
T1062 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.469320798 Aug 04 04:26:47 PM PDT 24 Aug 04 04:26:48 PM PDT 24 46823712 ps
T1063 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.964174551 Aug 04 04:26:33 PM PDT 24 Aug 04 04:26:35 PM PDT 24 251879405 ps
T1064 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.886888455 Aug 04 04:26:42 PM PDT 24 Aug 04 04:26:42 PM PDT 24 43382996 ps
T159 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.686663187 Aug 04 04:26:31 PM PDT 24 Aug 04 04:26:50 PM PDT 24 1005492575 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2236005698 Aug 04 04:26:48 PM PDT 24 Aug 04 04:26:49 PM PDT 24 16858459 ps
T116 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2936771575 Aug 04 04:26:28 PM PDT 24 Aug 04 04:26:33 PM PDT 24 361411031 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2781078410 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:53 PM PDT 24 16965862 ps
T121 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.668275290 Aug 04 04:26:20 PM PDT 24 Aug 04 04:26:24 PM PDT 24 119491651 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1239530096 Aug 04 04:26:32 PM PDT 24 Aug 04 04:26:37 PM PDT 24 846375440 ps
T139 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.961672717 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:58 PM PDT 24 134444257 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3409953628 Aug 04 04:26:41 PM PDT 24 Aug 04 04:26:42 PM PDT 24 59134330 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4134614347 Aug 04 04:26:29 PM PDT 24 Aug 04 04:26:30 PM PDT 24 41754233 ps
T122 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.160052390 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:57 PM PDT 24 72511142 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4208600060 Aug 04 04:26:19 PM PDT 24 Aug 04 04:26:20 PM PDT 24 11931022 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1083419256 Aug 04 04:26:37 PM PDT 24 Aug 04 04:26:41 PM PDT 24 57568156 ps
T140 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3323438883 Aug 04 04:26:26 PM PDT 24 Aug 04 04:26:27 PM PDT 24 224320710 ps
T185 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2335091980 Aug 04 04:26:50 PM PDT 24 Aug 04 04:27:12 PM PDT 24 890478470 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3625090746 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:54 PM PDT 24 32664642 ps
T1071 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.587238592 Aug 04 04:26:40 PM PDT 24 Aug 04 04:26:41 PM PDT 24 41809781 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2915298186 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:54 PM PDT 24 66543046 ps
T1073 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3513107873 Aug 04 04:26:48 PM PDT 24 Aug 04 04:26:49 PM PDT 24 39551557 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2161674538 Aug 04 04:26:36 PM PDT 24 Aug 04 04:26:37 PM PDT 24 66231731 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3946105671 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:03 PM PDT 24 339358478 ps
T81 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3617425472 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:56 PM PDT 24 23369841 ps
T1076 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.572685160 Aug 04 04:26:38 PM PDT 24 Aug 04 04:26:39 PM PDT 24 35764863 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2817617490 Aug 04 04:26:31 PM PDT 24 Aug 04 04:26:33 PM PDT 24 63245729 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2115524408 Aug 04 04:26:32 PM PDT 24 Aug 04 04:26:53 PM PDT 24 1024521156 ps
T1078 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2982990517 Aug 04 04:26:47 PM PDT 24 Aug 04 04:26:47 PM PDT 24 42506868 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3932671075 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:37 PM PDT 24 61081920 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2017970900 Aug 04 04:26:24 PM PDT 24 Aug 04 04:26:27 PM PDT 24 54260876 ps
T82 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.148454021 Aug 04 04:26:39 PM PDT 24 Aug 04 04:26:40 PM PDT 24 86800125 ps
T1080 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3563720187 Aug 04 04:26:35 PM PDT 24 Aug 04 04:26:36 PM PDT 24 19712807 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2223301467 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:23 PM PDT 24 1034927800 ps
T1081 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1691638585 Aug 04 04:26:27 PM PDT 24 Aug 04 04:26:27 PM PDT 24 16065473 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3646146475 Aug 04 04:26:45 PM PDT 24 Aug 04 04:26:53 PM PDT 24 557858817 ps
T188 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1594919798 Aug 04 04:26:37 PM PDT 24 Aug 04 04:26:48 PM PDT 24 202724874 ps
T141 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.718359943 Aug 04 04:27:28 PM PDT 24 Aug 04 04:27:30 PM PDT 24 27887644 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3077203601 Aug 04 04:26:39 PM PDT 24 Aug 04 04:26:40 PM PDT 24 29303975 ps
T83 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1226616755 Aug 04 04:26:55 PM PDT 24 Aug 04 04:26:57 PM PDT 24 113089052 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.370223905 Aug 04 04:26:06 PM PDT 24 Aug 04 04:26:07 PM PDT 24 40700961 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3666956041 Aug 04 04:26:11 PM PDT 24 Aug 04 04:26:15 PM PDT 24 110819809 ps
T162 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1748418573 Aug 04 04:25:57 PM PDT 24 Aug 04 04:26:01 PM PDT 24 138238280 ps
T123 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2142894660 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:56 PM PDT 24 507326556 ps
T178 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4091858884 Aug 04 04:25:53 PM PDT 24 Aug 04 04:25:56 PM PDT 24 977574590 ps
T1086 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.298086231 Aug 04 04:27:49 PM PDT 24 Aug 04 04:27:50 PM PDT 24 51900840 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.902910247 Aug 04 04:26:54 PM PDT 24 Aug 04 04:27:02 PM PDT 24 108566032 ps
T1087 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4100745785 Aug 04 04:26:19 PM PDT 24 Aug 04 04:26:20 PM PDT 24 53922104 ps
T144 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1349360665 Aug 04 04:26:25 PM PDT 24 Aug 04 04:27:03 PM PDT 24 2722962692 ps
T1088 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3112406239 Aug 04 04:26:46 PM PDT 24 Aug 04 04:26:47 PM PDT 24 29127392 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1640727490 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:36 PM PDT 24 134047102 ps
T1090 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3996904925 Aug 04 04:27:32 PM PDT 24 Aug 04 04:27:33 PM PDT 24 14467837 ps
T1091 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3893411536 Aug 04 04:27:53 PM PDT 24 Aug 04 04:27:55 PM PDT 24 64629288 ps
T1092 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1592212627 Aug 04 04:26:17 PM PDT 24 Aug 04 04:26:18 PM PDT 24 71255951 ps
T84 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3966683252 Aug 04 04:26:10 PM PDT 24 Aug 04 04:26:11 PM PDT 24 386898667 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2976043440 Aug 04 04:26:29 PM PDT 24 Aug 04 04:26:30 PM PDT 24 50656279 ps
T124 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3919199835 Aug 04 04:26:33 PM PDT 24 Aug 04 04:26:36 PM PDT 24 572141157 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1457038277 Aug 04 04:26:12 PM PDT 24 Aug 04 04:26:14 PM PDT 24 240139320 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1513446081 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:57 PM PDT 24 192498493 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2837671910 Aug 04 04:26:24 PM PDT 24 Aug 04 04:26:25 PM PDT 24 20439176 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4037468304 Aug 04 04:25:57 PM PDT 24 Aug 04 04:26:20 PM PDT 24 322964661 ps
T1098 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1104140181 Aug 04 04:26:44 PM PDT 24 Aug 04 04:26:45 PM PDT 24 84710236 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2878348230 Aug 04 04:26:33 PM PDT 24 Aug 04 04:26:36 PM PDT 24 147952838 ps
T118 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3589191715 Aug 04 04:26:55 PM PDT 24 Aug 04 04:27:00 PM PDT 24 692860979 ps
T1100 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3558053554 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:34 PM PDT 24 39720927 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2261403403 Aug 04 04:26:27 PM PDT 24 Aug 04 04:26:28 PM PDT 24 54926074 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3793235081 Aug 04 04:26:38 PM PDT 24 Aug 04 04:26:41 PM PDT 24 117089817 ps
T1103 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.736216414 Aug 04 04:26:38 PM PDT 24 Aug 04 04:26:40 PM PDT 24 904620693 ps
T1104 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.99917200 Aug 04 04:27:25 PM PDT 24 Aug 04 04:27:26 PM PDT 24 52772813 ps
T1105 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2622113191 Aug 04 04:27:52 PM PDT 24 Aug 04 04:27:53 PM PDT 24 15677666 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3679095075 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:01 PM PDT 24 312231900 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.58938791 Aug 04 04:25:56 PM PDT 24 Aug 04 04:26:30 PM PDT 24 538421798 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.966661382 Aug 04 04:26:24 PM PDT 24 Aug 04 04:26:25 PM PDT 24 77801435 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3283099883 Aug 04 04:26:30 PM PDT 24 Aug 04 04:26:31 PM PDT 24 58563425 ps
T1110 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3931609628 Aug 04 04:26:43 PM PDT 24 Aug 04 04:26:46 PM PDT 24 998061039 ps
T1111 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3168012088 Aug 04 04:26:46 PM PDT 24 Aug 04 04:26:47 PM PDT 24 14506161 ps
T1112 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4228466258 Aug 04 04:26:43 PM PDT 24 Aug 04 04:26:45 PM PDT 24 309757284 ps
T1113 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4018113445 Aug 04 04:26:09 PM PDT 24 Aug 04 04:26:13 PM PDT 24 63530990 ps
T1114 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3735076241 Aug 04 04:26:45 PM PDT 24 Aug 04 04:26:48 PM PDT 24 193019693 ps
T1115 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.552394848 Aug 04 04:27:52 PM PDT 24 Aug 04 04:27:53 PM PDT 24 15346593 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.537506899 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:41 PM PDT 24 318450849 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.972869757 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:55 PM PDT 24 110900876 ps
T1118 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3114318953 Aug 04 04:26:41 PM PDT 24 Aug 04 04:26:42 PM PDT 24 41081112 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3664429547 Aug 04 04:26:02 PM PDT 24 Aug 04 04:26:03 PM PDT 24 11013080 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.206701119 Aug 04 04:26:50 PM PDT 24 Aug 04 04:27:22 PM PDT 24 5206904150 ps
T120 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2266092308 Aug 04 04:26:22 PM PDT 24 Aug 04 04:26:25 PM PDT 24 221311328 ps
T186 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.432520349 Aug 04 04:27:56 PM PDT 24 Aug 04 04:28:17 PM PDT 24 3524288143 ps
T1121 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.908252297 Aug 04 04:26:35 PM PDT 24 Aug 04 04:26:36 PM PDT 24 42303182 ps
T1122 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3868433531 Aug 04 04:26:36 PM PDT 24 Aug 04 04:26:43 PM PDT 24 147195454 ps
T1123 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3831665496 Aug 04 04:26:36 PM PDT 24 Aug 04 04:26:38 PM PDT 24 30121735 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2261012509 Aug 04 04:26:00 PM PDT 24 Aug 04 04:26:02 PM PDT 24 211392772 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4015423814 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:58 PM PDT 24 283500333 ps
T1126 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2633519342 Aug 04 04:27:49 PM PDT 24 Aug 04 04:27:53 PM PDT 24 58315717 ps
T1127 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.965409080 Aug 04 04:26:07 PM PDT 24 Aug 04 04:26:08 PM PDT 24 23664064 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2448050000 Aug 04 04:26:11 PM PDT 24 Aug 04 04:26:15 PM PDT 24 154721034 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.109976348 Aug 04 04:25:53 PM PDT 24 Aug 04 04:25:54 PM PDT 24 40463130 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.484150097 Aug 04 04:26:13 PM PDT 24 Aug 04 04:26:34 PM PDT 24 1270265506 ps
T189 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3344763754 Aug 04 04:26:35 PM PDT 24 Aug 04 04:26:49 PM PDT 24 1130541396 ps
T190 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1403623865 Aug 04 04:26:49 PM PDT 24 Aug 04 04:26:56 PM PDT 24 2781538961 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.535856192 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:58 PM PDT 24 589108154 ps
T1132 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3764701083 Aug 04 04:27:52 PM PDT 24 Aug 04 04:27:52 PM PDT 24 56989788 ps
T1133 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2245326473 Aug 04 04:26:48 PM PDT 24 Aug 04 04:26:51 PM PDT 24 490737490 ps
T191 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2458330916 Aug 04 04:26:40 PM PDT 24 Aug 04 04:26:51 PM PDT 24 191566085 ps
T1134 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3261443861 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 12961413 ps
T1135 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.22225471 Aug 04 04:27:40 PM PDT 24 Aug 04 04:27:41 PM PDT 24 11740339 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.905713890 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:56 PM PDT 24 303335115 ps
T1137 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2709744448 Aug 04 04:26:53 PM PDT 24 Aug 04 04:26:56 PM PDT 24 285622203 ps
T187 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.440053823 Aug 04 04:26:49 PM PDT 24 Aug 04 04:27:06 PM PDT 24 734757490 ps
T1138 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1135650373 Aug 04 04:26:46 PM PDT 24 Aug 04 04:26:47 PM PDT 24 115618136 ps
T1139 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.750891294 Aug 04 04:26:50 PM PDT 24 Aug 04 04:26:52 PM PDT 24 86120482 ps
T1140 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.512780615 Aug 04 04:25:55 PM PDT 24 Aug 04 04:26:07 PM PDT 24 2154223611 ps
T1141 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1234877718 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:59 PM PDT 24 37778957 ps
T1142 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.716465397 Aug 04 04:26:31 PM PDT 24 Aug 04 04:26:31 PM PDT 24 41498688 ps
T1143 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1658259224 Aug 04 04:26:41 PM PDT 24 Aug 04 04:26:43 PM PDT 24 213536948 ps
T1144 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2579370327 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:53 PM PDT 24 41250046 ps
T1145 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1128449561 Aug 04 04:26:42 PM PDT 24 Aug 04 04:26:46 PM PDT 24 74956547 ps
T1146 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1088099267 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:04 PM PDT 24 253498693 ps
T1147 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3199598375 Aug 04 04:26:27 PM PDT 24 Aug 04 04:26:29 PM PDT 24 197898711 ps
T1148 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.167944929 Aug 04 04:26:17 PM PDT 24 Aug 04 04:26:19 PM PDT 24 26779459 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3793217780 Aug 04 04:26:07 PM PDT 24 Aug 04 04:26:21 PM PDT 24 2119510379 ps
T1150 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1597604928 Aug 04 04:26:08 PM PDT 24 Aug 04 04:26:11 PM PDT 24 387431643 ps
T1151 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1380932290 Aug 04 04:26:38 PM PDT 24 Aug 04 04:26:38 PM PDT 24 13365950 ps

Test location /workspace/coverage/default/13.spi_device_flash_all.3578529688
Short name T8
Test name
Test status
Simulation time 29781333654 ps
CPU time 156.42 seconds
Started Aug 04 04:54:05 PM PDT 24
Finished Aug 04 04:56:42 PM PDT 24
Peak memory 252608 kb
Host smart-cbcd96dd-14fa-485f-8708-a2676b6e5f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578529688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3578529688
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.60637544
Short name T32
Test name
Test status
Simulation time 16261471300 ps
CPU time 53.9 seconds
Started Aug 04 04:53:31 PM PDT 24
Finished Aug 04 04:54:25 PM PDT 24
Peak memory 249732 kb
Host smart-36061129-4770-4dd0-ac2b-22f8888a32c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60637544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.60637544
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4136966269
Short name T15
Test name
Test status
Simulation time 548843148487 ps
CPU time 434.33 seconds
Started Aug 04 04:53:35 PM PDT 24
Finished Aug 04 05:00:50 PM PDT 24
Peak memory 266384 kb
Host smart-014c7f31-699c-412c-b0eb-99b41d3e2081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136966269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4136966269
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.142264712
Short name T103
Test name
Test status
Simulation time 9276666427 ps
CPU time 23.19 seconds
Started Aug 04 04:26:47 PM PDT 24
Finished Aug 04 04:27:10 PM PDT 24
Peak memory 215516 kb
Host smart-674d8a90-14ab-40a1-956b-66a8e908c6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142264712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.142264712
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3184160422
Short name T66
Test name
Test status
Simulation time 254667512880 ps
CPU time 305.44 seconds
Started Aug 04 04:55:52 PM PDT 24
Finished Aug 04 05:00:58 PM PDT 24
Peak memory 270892 kb
Host smart-bc73d40c-542d-465d-b522-5c9ce70b8f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184160422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3184160422
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3314396307
Short name T68
Test name
Test status
Simulation time 41478554 ps
CPU time 0.78 seconds
Started Aug 04 04:52:20 PM PDT 24
Finished Aug 04 04:52:21 PM PDT 24
Peak memory 216620 kb
Host smart-6d074a9d-766c-4eab-9b06-870c85d1a79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314396307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3314396307
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3162745931
Short name T20
Test name
Test status
Simulation time 15843736922 ps
CPU time 110.06 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:54:34 PM PDT 24
Peak memory 266368 kb
Host smart-f659fc73-670f-4540-aea2-197e32fc3af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162745931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3162745931
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3083387805
Short name T164
Test name
Test status
Simulation time 13407784073 ps
CPU time 93.28 seconds
Started Aug 04 04:56:01 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 257856 kb
Host smart-7194f75b-b911-418d-9eb9-8ffcdf7f4ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083387805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3083387805
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1119200149
Short name T36
Test name
Test status
Simulation time 38277904330 ps
CPU time 410.29 seconds
Started Aug 04 04:55:35 PM PDT 24
Finished Aug 04 05:02:26 PM PDT 24
Peak memory 264684 kb
Host smart-495d3a15-2f40-4eaa-9cf5-f16182c96b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119200149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1119200149
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3949501984
Short name T22
Test name
Test status
Simulation time 41016272579 ps
CPU time 173.93 seconds
Started Aug 04 04:52:50 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 266168 kb
Host smart-5533d123-e642-43af-b3c5-e81befcb4229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949501984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3949501984
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1955750140
Short name T33
Test name
Test status
Simulation time 28099766977 ps
CPU time 132.19 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:56:37 PM PDT 24
Peak memory 257300 kb
Host smart-897784eb-457a-4953-bee1-264be605253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955750140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1955750140
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.236968545
Short name T18
Test name
Test status
Simulation time 90169875 ps
CPU time 1.24 seconds
Started Aug 04 04:52:52 PM PDT 24
Finished Aug 04 04:52:53 PM PDT 24
Peak memory 236960 kb
Host smart-7c69c6da-930c-44a6-8e10-c6711197fb42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236968545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.236968545
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.357658672
Short name T50
Test name
Test status
Simulation time 2045395266 ps
CPU time 30.11 seconds
Started Aug 04 04:55:12 PM PDT 24
Finished Aug 04 04:55:43 PM PDT 24
Peak memory 225284 kb
Host smart-a916be6e-f05d-49a4-a95b-a71472d2b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357658672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.357658672
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1117974334
Short name T211
Test name
Test status
Simulation time 21697949524 ps
CPU time 243.27 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:58:28 PM PDT 24
Peak memory 285940 kb
Host smart-7c8afe9f-e572-47d9-99e9-2074af280e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117974334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1117974334
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1602707329
Short name T110
Test name
Test status
Simulation time 306983692 ps
CPU time 5.46 seconds
Started Aug 04 04:26:11 PM PDT 24
Finished Aug 04 04:26:17 PM PDT 24
Peak memory 215696 kb
Host smart-4e33286c-b85e-43c4-88d8-bf67444ee30f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602707329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
602707329
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4191108508
Short name T232
Test name
Test status
Simulation time 84958500255 ps
CPU time 480.58 seconds
Started Aug 04 04:54:53 PM PDT 24
Finished Aug 04 05:02:54 PM PDT 24
Peak memory 274496 kb
Host smart-08b395db-3ee0-458d-aaba-1f6b45c5d019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191108508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4191108508
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1939072567
Short name T195
Test name
Test status
Simulation time 18954533000 ps
CPU time 154.36 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 271708 kb
Host smart-1b542502-0680-4bba-b3bb-b9fa12b076bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939072567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1939072567
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3665617861
Short name T135
Test name
Test status
Simulation time 1465894078 ps
CPU time 22.75 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:26:17 PM PDT 24
Peak memory 207160 kb
Host smart-46f3c240-4636-4236-822d-52d7db0e77d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665617861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3665617861
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1513659856
Short name T302
Test name
Test status
Simulation time 37447849698 ps
CPU time 296.52 seconds
Started Aug 04 04:53:23 PM PDT 24
Finished Aug 04 04:58:19 PM PDT 24
Peak memory 256328 kb
Host smart-ef907ddf-f105-4946-a276-59dccfa4fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513659856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1513659856
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1443616959
Short name T234
Test name
Test status
Simulation time 78112542000 ps
CPU time 264.35 seconds
Started Aug 04 04:52:39 PM PDT 24
Finished Aug 04 04:57:04 PM PDT 24
Peak memory 249840 kb
Host smart-2c75786b-59e2-42df-8570-f1893e986db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443616959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1443616959
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2311636066
Short name T571
Test name
Test status
Simulation time 15838890 ps
CPU time 1.04 seconds
Started Aug 04 04:53:50 PM PDT 24
Finished Aug 04 04:53:51 PM PDT 24
Peak memory 217204 kb
Host smart-e3874127-f0f4-4595-8b66-01f612d8deef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311636066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2311636066
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1751320168
Short name T29
Test name
Test status
Simulation time 2323923307 ps
CPU time 6.19 seconds
Started Aug 04 04:56:08 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 217032 kb
Host smart-d73c1d2d-c402-44d1-ae5b-251ae17e490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751320168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1751320168
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3653873964
Short name T202
Test name
Test status
Simulation time 31745148507 ps
CPU time 130.43 seconds
Started Aug 04 04:52:58 PM PDT 24
Finished Aug 04 04:55:08 PM PDT 24
Peak memory 257944 kb
Host smart-4bed77d8-89ce-4680-bd11-adc4b5be4a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653873964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3653873964
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1077685334
Short name T180
Test name
Test status
Simulation time 172895374554 ps
CPU time 422.26 seconds
Started Aug 04 04:55:07 PM PDT 24
Finished Aug 04 05:02:09 PM PDT 24
Peak memory 265292 kb
Host smart-756b080c-2203-4861-b973-eb20db9273e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077685334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1077685334
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2161072928
Short name T305
Test name
Test status
Simulation time 25265607709 ps
CPU time 203.23 seconds
Started Aug 04 04:54:54 PM PDT 24
Finished Aug 04 04:58:17 PM PDT 24
Peak memory 274412 kb
Host smart-2ca12914-d053-439b-84de-481346a14c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161072928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2161072928
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2654008067
Short name T340
Test name
Test status
Simulation time 14132509 ps
CPU time 0.75 seconds
Started Aug 04 04:52:42 PM PDT 24
Finished Aug 04 04:52:43 PM PDT 24
Peak memory 205804 kb
Host smart-01a32717-a9f5-4464-8bab-d790f5c5e82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654008067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
654008067
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1322414502
Short name T169
Test name
Test status
Simulation time 506288939687 ps
CPU time 426.54 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 05:01:26 PM PDT 24
Peak memory 256304 kb
Host smart-15d61f61-a91c-4585-8925-655beed0cfcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322414502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1322414502
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2936771575
Short name T116
Test name
Test status
Simulation time 361411031 ps
CPU time 4.43 seconds
Started Aug 04 04:26:28 PM PDT 24
Finished Aug 04 04:26:33 PM PDT 24
Peak memory 215748 kb
Host smart-3dbc1663-5150-4540-9e33-959efa384396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936771575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2936771575
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.182404130
Short name T293
Test name
Test status
Simulation time 29953665379 ps
CPU time 183.04 seconds
Started Aug 04 04:54:48 PM PDT 24
Finished Aug 04 04:57:51 PM PDT 24
Peak memory 267048 kb
Host smart-5de214d6-f066-4cbc-a5ed-1aaef77dd265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182404130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.182404130
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1323545588
Short name T200
Test name
Test status
Simulation time 93987810097 ps
CPU time 321.89 seconds
Started Aug 04 04:54:58 PM PDT 24
Finished Aug 04 05:00:20 PM PDT 24
Peak memory 254100 kb
Host smart-44c0557d-569a-4bdb-b8f9-1242fbc028e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323545588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1323545588
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4140258786
Short name T95
Test name
Test status
Simulation time 269369555333 ps
CPU time 327.49 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 05:03:00 PM PDT 24
Peak memory 257160 kb
Host smart-70ca62da-739e-4458-8ab4-b306a44c6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140258786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4140258786
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3344763754
Short name T189
Test name
Test status
Simulation time 1130541396 ps
CPU time 13.58 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:49 PM PDT 24
Peak memory 215676 kb
Host smart-07d63c68-d9e3-4798-ba43-cd5f7c31810f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344763754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3344763754
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3831287221
Short name T636
Test name
Test status
Simulation time 64207254100 ps
CPU time 337.01 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 05:00:43 PM PDT 24
Peak memory 268848 kb
Host smart-1daca9e9-f2ba-4b09-a487-c7382a0dbfa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831287221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3831287221
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3575568969
Short name T295
Test name
Test status
Simulation time 5039837912 ps
CPU time 96.05 seconds
Started Aug 04 04:56:10 PM PDT 24
Finished Aug 04 04:57:46 PM PDT 24
Peak memory 263664 kb
Host smart-589b221b-c6fe-4890-bb65-31b964849065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575568969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3575568969
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3618780060
Short name T230
Test name
Test status
Simulation time 63803774829 ps
CPU time 660.48 seconds
Started Aug 04 04:56:25 PM PDT 24
Finished Aug 04 05:07:26 PM PDT 24
Peak memory 282000 kb
Host smart-c52024f2-66b6-47e7-be47-2c4004c2a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618780060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3618780060
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.992973555
Short name T322
Test name
Test status
Simulation time 2405985070 ps
CPU time 15.54 seconds
Started Aug 04 04:53:42 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 225528 kb
Host smart-540f730d-e8f0-4fe3-8732-84419011ae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992973555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.992973555
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.432520349
Short name T186
Test name
Test status
Simulation time 3524288143 ps
CPU time 21.04 seconds
Started Aug 04 04:27:56 PM PDT 24
Finished Aug 04 04:28:17 PM PDT 24
Peak memory 215584 kb
Host smart-f8794054-a772-4279-aa21-e9b7e1f8bb91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432520349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.432520349
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3406840128
Short name T241
Test name
Test status
Simulation time 72871835147 ps
CPU time 253.29 seconds
Started Aug 04 04:52:31 PM PDT 24
Finished Aug 04 04:56:44 PM PDT 24
Peak memory 258140 kb
Host smart-973c945e-3614-4159-b2d1-8d6e4598bc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406840128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3406840128
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1413388212
Short name T210
Test name
Test status
Simulation time 125820820304 ps
CPU time 287.62 seconds
Started Aug 04 04:53:55 PM PDT 24
Finished Aug 04 04:58:43 PM PDT 24
Peak memory 266372 kb
Host smart-ad509815-c0e7-4a3e-a1e0-9ac3f30459b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413388212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1413388212
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3109835269
Short name T311
Test name
Test status
Simulation time 6433324770 ps
CPU time 86.03 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:55:37 PM PDT 24
Peak memory 256552 kb
Host smart-3eae56ec-3a5c-455e-8b5b-d8adf014f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109835269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3109835269
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3963411898
Short name T239
Test name
Test status
Simulation time 79825079556 ps
CPU time 307.24 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:58:20 PM PDT 24
Peak memory 255856 kb
Host smart-ad982531-133e-43e9-9c1f-cffc45b63abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963411898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3963411898
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3295171121
Short name T89
Test name
Test status
Simulation time 5593658541 ps
CPU time 13.02 seconds
Started Aug 04 04:53:29 PM PDT 24
Finished Aug 04 04:53:42 PM PDT 24
Peak memory 225216 kb
Host smart-54372d54-7ce8-45dd-b6a2-56ec6b5b257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295171121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3295171121
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3202400588
Short name T109
Test name
Test status
Simulation time 39727973655 ps
CPU time 85.97 seconds
Started Aug 04 04:55:19 PM PDT 24
Finished Aug 04 04:56:45 PM PDT 24
Peak memory 251540 kb
Host smart-07d4fd14-9e4e-4328-b28b-e841afc7bc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202400588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3202400588
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1128449561
Short name T1145
Test name
Test status
Simulation time 74956547 ps
CPU time 4.01 seconds
Started Aug 04 04:26:42 PM PDT 24
Finished Aug 04 04:26:46 PM PDT 24
Peak memory 215544 kb
Host smart-54ca7a4e-3c3d-4b9a-a8b4-d8cafd7ebaea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128449561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1128449561
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1594919798
Short name T188
Test name
Test status
Simulation time 202724874 ps
CPU time 11.65 seconds
Started Aug 04 04:26:37 PM PDT 24
Finished Aug 04 04:26:48 PM PDT 24
Peak memory 215400 kb
Host smart-533bdf07-ff5d-4544-b62a-d1e97d15eaef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594919798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1594919798
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2458330916
Short name T191
Test name
Test status
Simulation time 191566085 ps
CPU time 10.55 seconds
Started Aug 04 04:26:40 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 222392 kb
Host smart-173454cd-a798-4049-b7ce-14d71ea9a687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458330916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2458330916
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3169790732
Short name T243
Test name
Test status
Simulation time 2029267304 ps
CPU time 11.21 seconds
Started Aug 04 04:52:28 PM PDT 24
Finished Aug 04 04:52:40 PM PDT 24
Peak memory 233660 kb
Host smart-4660f15e-a007-48ae-8798-b5e3d15e1ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169790732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3169790732
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.149876075
Short name T940
Test name
Test status
Simulation time 4645786854 ps
CPU time 71.09 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:55:12 PM PDT 24
Peak memory 249968 kb
Host smart-2f6512e4-a7a4-4383-969b-e7b8169d28cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149876075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.149876075
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3521526025
Short name T168
Test name
Test status
Simulation time 24183209143 ps
CPU time 187.07 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:58:05 PM PDT 24
Peak memory 273816 kb
Host smart-6ef9c698-3251-4c24-98ee-63ab91b12ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521526025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3521526025
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2992311097
Short name T12
Test name
Test status
Simulation time 5238556964 ps
CPU time 95.11 seconds
Started Aug 04 04:56:28 PM PDT 24
Finished Aug 04 04:58:03 PM PDT 24
Peak memory 255088 kb
Host smart-7d2eaab0-a732-4c25-9ecb-f7d6f85f46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992311097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2992311097
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2738488435
Short name T92
Test name
Test status
Simulation time 57697216 ps
CPU time 2.76 seconds
Started Aug 04 04:54:43 PM PDT 24
Finished Aug 04 04:54:46 PM PDT 24
Peak memory 233324 kb
Host smart-5c2e9524-7fd9-44bb-be38-25847250c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738488435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2738488435
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3847260532
Short name T353
Test name
Test status
Simulation time 17830602153 ps
CPU time 15.92 seconds
Started Aug 04 04:52:33 PM PDT 24
Finished Aug 04 04:52:49 PM PDT 24
Peak memory 233392 kb
Host smart-f0d02290-b351-44f7-95bf-368f27a1f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847260532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3847260532
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2941882999
Short name T75
Test name
Test status
Simulation time 630283826 ps
CPU time 5 seconds
Started Aug 04 04:54:20 PM PDT 24
Finished Aug 04 04:54:25 PM PDT 24
Peak memory 221020 kb
Host smart-941497de-25e7-4dac-a96c-dd73a71400e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2941882999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2941882999
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3617425472
Short name T81
Test name
Test status
Simulation time 23369841 ps
CPU time 1.3 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 216344 kb
Host smart-0b3eb0be-6642-4c48-9398-6b8c67640221
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617425472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3617425472
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1164926149
Short name T94
Test name
Test status
Simulation time 8867479463 ps
CPU time 112.32 seconds
Started Aug 04 04:54:39 PM PDT 24
Finished Aug 04 04:56:31 PM PDT 24
Peak memory 274580 kb
Host smart-c630b9fe-934a-4e51-b18f-96840cacbd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164926149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1164926149
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1239530096
Short name T115
Test name
Test status
Simulation time 846375440 ps
CPU time 4.76 seconds
Started Aug 04 04:26:32 PM PDT 24
Finished Aug 04 04:26:37 PM PDT 24
Peak memory 215672 kb
Host smart-8d5af21b-2a92-4823-ac20-fe4efe4f4e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239530096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
239530096
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2622006347
Short name T173
Test name
Test status
Simulation time 32978690 ps
CPU time 0.77 seconds
Started Aug 04 04:53:56 PM PDT 24
Finished Aug 04 04:53:56 PM PDT 24
Peak memory 207004 kb
Host smart-c1e09e84-80fc-4b3e-9c47-1d7be461d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622006347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2622006347
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2541298264
Short name T42
Test name
Test status
Simulation time 100576288947 ps
CPU time 244.78 seconds
Started Aug 04 04:56:33 PM PDT 24
Finished Aug 04 05:00:38 PM PDT 24
Peak memory 257776 kb
Host smart-ccc41e42-083e-43c7-bb13-53555fcfa960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541298264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2541298264
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.964852686
Short name T136
Test name
Test status
Simulation time 1860695185 ps
CPU time 24.27 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:26:11 PM PDT 24
Peak memory 215316 kb
Host smart-5a0f11c8-73c8-4b80-89bb-c7d12b674903
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964852686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.964852686
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.972869757
Short name T1117
Test name
Test status
Simulation time 110900876 ps
CPU time 2.73 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 216460 kb
Host smart-726a6632-fc82-4f3f-84c4-143db4c3dd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972869757 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.972869757
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1513446081
Short name T1095
Test name
Test status
Simulation time 192498493 ps
CPU time 1.27 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 207144 kb
Host smart-d9ce8be6-e4dc-4e9b-981e-bd6c84af29db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513446081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
513446081
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2781078410
Short name T1066
Test name
Test status
Simulation time 16965862 ps
CPU time 0.79 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 204196 kb
Host smart-059b7c57-3aec-4af7-9d13-b1b743c5e6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781078410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
781078410
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.961672717
Short name T139
Test name
Test status
Simulation time 134444257 ps
CPU time 2.19 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 215328 kb
Host smart-0cb31074-a2f1-42fa-9cff-687b8cbf2783
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961672717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.961672717
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1151908404
Short name T1058
Test name
Test status
Simulation time 12801386 ps
CPU time 0.67 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 203744 kb
Host smart-5be096ef-e639-46c2-88f0-625661ad5a8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151908404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1151908404
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4091858884
Short name T178
Test name
Test status
Simulation time 977574590 ps
CPU time 2.87 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 214708 kb
Host smart-6a3f46a0-421a-4d85-9bbe-88cdf6521c90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091858884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4091858884
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3898920216
Short name T125
Test name
Test status
Simulation time 302522645 ps
CPU time 18.04 seconds
Started Aug 04 04:25:46 PM PDT 24
Finished Aug 04 04:26:04 PM PDT 24
Peak memory 215304 kb
Host smart-09f81b4c-ee4d-4639-aefc-b41258daf6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898920216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3898920216
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3832819323
Short name T137
Test name
Test status
Simulation time 604353791 ps
CPU time 16.16 seconds
Started Aug 04 04:26:05 PM PDT 24
Finished Aug 04 04:26:21 PM PDT 24
Peak memory 207280 kb
Host smart-7e30fae6-c36c-4816-9476-a5efb18c2128
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832819323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3832819323
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.58938791
Short name T1107
Test name
Test status
Simulation time 538421798 ps
CPU time 34.41 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:26:30 PM PDT 24
Peak memory 215428 kb
Host smart-a222c372-b158-4e10-a649-ecad07b6b6f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58938791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.58938791
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2579370327
Short name T1144
Test name
Test status
Simulation time 41250046 ps
CPU time 1.47 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 207132 kb
Host smart-72fcbf79-e6c2-418c-bbe6-e551c0f3ee34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579370327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2579370327
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1234877718
Short name T1141
Test name
Test status
Simulation time 37778957 ps
CPU time 2.59 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:59 PM PDT 24
Peak memory 217188 kb
Host smart-9524f289-4ad8-4c0f-a00f-46de7388cfb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234877718 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1234877718
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4015423814
Short name T1125
Test name
Test status
Simulation time 283500333 ps
CPU time 2.02 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 215752 kb
Host smart-1b5141ea-2ab4-48a2-8150-46187111c5a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015423814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
015423814
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3261443861
Short name T1134
Test name
Test status
Simulation time 12961413 ps
CPU time 0.74 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 203836 kb
Host smart-d657dbd7-0228-44ba-8003-c86f3fd382d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261443861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
261443861
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3625090746
Short name T142
Test name
Test status
Simulation time 32664642 ps
CPU time 1.38 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 215376 kb
Host smart-ac765a90-5685-4312-b259-46757f2430bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625090746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3625090746
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.109976348
Short name T1129
Test name
Test status
Simulation time 40463130 ps
CPU time 0.66 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 203312 kb
Host smart-69ef8664-08bd-4c65-95ba-10f3b47f08b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109976348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.109976348
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.558112893
Short name T1037
Test name
Test status
Simulation time 220417053 ps
CPU time 3.64 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:26:58 PM PDT 24
Peak memory 215392 kb
Host smart-47138487-db02-48a9-9cdf-6c8e00e7b056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558112893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.558112893
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2261012509
Short name T1124
Test name
Test status
Simulation time 211392772 ps
CPU time 2.07 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:02 PM PDT 24
Peak memory 216668 kb
Host smart-9f34865d-49b5-4b37-81ab-19914654f763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261012509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
261012509
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2223301467
Short name T161
Test name
Test status
Simulation time 1034927800 ps
CPU time 22.93 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:23 PM PDT 24
Peak memory 221260 kb
Host smart-9eabdd9f-33f3-4372-b76f-e403e85c250e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223301467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2223301467
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3199598375
Short name T1147
Test name
Test status
Simulation time 197898711 ps
CPU time 1.61 seconds
Started Aug 04 04:26:27 PM PDT 24
Finished Aug 04 04:26:29 PM PDT 24
Peak memory 215448 kb
Host smart-698817c6-6c37-4015-9b8c-2c26749d3b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199598375 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3199598375
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3793235081
Short name T1102
Test name
Test status
Simulation time 117089817 ps
CPU time 2.71 seconds
Started Aug 04 04:26:38 PM PDT 24
Finished Aug 04 04:26:41 PM PDT 24
Peak memory 215276 kb
Host smart-01d021a8-f6a7-408a-b229-3d366b756012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793235081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3793235081
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4208600060
Short name T1069
Test name
Test status
Simulation time 11931022 ps
CPU time 0.66 seconds
Started Aug 04 04:26:19 PM PDT 24
Finished Aug 04 04:26:20 PM PDT 24
Peak memory 204168 kb
Host smart-153e60d5-d78d-49de-9935-fd6820dd82c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208600060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4208600060
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.284949385
Short name T1049
Test name
Test status
Simulation time 105443895 ps
CPU time 2.74 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:37 PM PDT 24
Peak memory 215376 kb
Host smart-e67b26a9-2a1c-467f-b61e-8392a6146008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284949385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.284949385
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.167944929
Short name T1148
Test name
Test status
Simulation time 26779459 ps
CPU time 1.51 seconds
Started Aug 04 04:26:17 PM PDT 24
Finished Aug 04 04:26:19 PM PDT 24
Peak memory 215624 kb
Host smart-29b166fa-8e62-4d09-93d7-d8d22a4d81c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167944929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.167944929
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.698586195
Short name T100
Test name
Test status
Simulation time 1673678705 ps
CPU time 18.3 seconds
Started Aug 04 04:26:22 PM PDT 24
Finished Aug 04 04:26:40 PM PDT 24
Peak memory 215748 kb
Host smart-e050a20a-66b6-4c1c-8c6e-f4fdc62eaffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698586195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.698586195
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4228466258
Short name T1112
Test name
Test status
Simulation time 309757284 ps
CPU time 2.38 seconds
Started Aug 04 04:26:43 PM PDT 24
Finished Aug 04 04:26:45 PM PDT 24
Peak memory 217560 kb
Host smart-c2adc252-e073-454d-9538-ca30467e8bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228466258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4228466258
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.966661382
Short name T1108
Test name
Test status
Simulation time 77801435 ps
CPU time 1.35 seconds
Started Aug 04 04:26:24 PM PDT 24
Finished Aug 04 04:26:25 PM PDT 24
Peak memory 207184 kb
Host smart-20dd6cfc-74e4-4df2-b3a2-2b0754a4c224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966661382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.966661382
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2973419948
Short name T1060
Test name
Test status
Simulation time 49699904 ps
CPU time 0.7 seconds
Started Aug 04 04:26:22 PM PDT 24
Finished Aug 04 04:26:23 PM PDT 24
Peak memory 203848 kb
Host smart-0d8c9056-7f1f-46d2-93cc-cedc1d3df25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973419948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2973419948
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2448050000
Short name T1128
Test name
Test status
Simulation time 154721034 ps
CPU time 3.91 seconds
Started Aug 04 04:26:11 PM PDT 24
Finished Aug 04 04:26:15 PM PDT 24
Peak memory 215140 kb
Host smart-0638e3bf-7595-4303-a90d-ac258294783e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448050000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2448050000
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.537130656
Short name T98
Test name
Test status
Simulation time 166682319 ps
CPU time 3.34 seconds
Started Aug 04 04:26:42 PM PDT 24
Finished Aug 04 04:26:45 PM PDT 24
Peak memory 215648 kb
Host smart-498c8c3c-0524-41b2-95e0-73d21f7199d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537130656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.537130656
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.686663187
Short name T159
Test name
Test status
Simulation time 1005492575 ps
CPU time 19.14 seconds
Started Aug 04 04:26:31 PM PDT 24
Finished Aug 04 04:26:50 PM PDT 24
Peak memory 215316 kb
Host smart-0dfe8262-7e27-43fd-9ffc-d8d7f5a0b4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686663187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.686663187
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3868433531
Short name T1122
Test name
Test status
Simulation time 147195454 ps
CPU time 2.33 seconds
Started Aug 04 04:26:36 PM PDT 24
Finished Aug 04 04:26:43 PM PDT 24
Peak memory 216704 kb
Host smart-c1e6b378-7362-403f-b594-3cd0b1d3047c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868433531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3868433531
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2648687701
Short name T1038
Test name
Test status
Simulation time 63910686 ps
CPU time 2.39 seconds
Started Aug 04 04:26:24 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 215320 kb
Host smart-ff1fea05-2e81-4cbf-b067-f1dfd8ad18ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648687701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2648687701
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3112406239
Short name T1088
Test name
Test status
Simulation time 29127392 ps
CPU time 0.72 seconds
Started Aug 04 04:26:46 PM PDT 24
Finished Aug 04 04:26:47 PM PDT 24
Peak memory 203836 kb
Host smart-06b087c1-7266-4556-9f46-a39f238d7f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112406239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3112406239
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3932671075
Short name T1079
Test name
Test status
Simulation time 61081920 ps
CPU time 3.7 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:37 PM PDT 24
Peak memory 215236 kb
Host smart-bb551de4-6643-4257-83f9-caf17fb4bf11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932671075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3932671075
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2824951975
Short name T111
Test name
Test status
Simulation time 120121002 ps
CPU time 2.98 seconds
Started Aug 04 04:26:11 PM PDT 24
Finished Aug 04 04:26:14 PM PDT 24
Peak memory 215836 kb
Host smart-ae5c9fd7-4993-44c1-a1c7-c9b1ffac7461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824951975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2824951975
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3409953628
Short name T1067
Test name
Test status
Simulation time 59134330 ps
CPU time 1.8 seconds
Started Aug 04 04:26:41 PM PDT 24
Finished Aug 04 04:26:42 PM PDT 24
Peak memory 216404 kb
Host smart-d1d5e644-b6c9-49aa-a44e-67974cc5039a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409953628 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3409953628
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1658259224
Short name T1143
Test name
Test status
Simulation time 213536948 ps
CPU time 1.31 seconds
Started Aug 04 04:26:41 PM PDT 24
Finished Aug 04 04:26:43 PM PDT 24
Peak memory 215388 kb
Host smart-43b6953b-f896-478d-91d1-275c0dd91390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658259224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1658259224
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3527634212
Short name T1055
Test name
Test status
Simulation time 35905316 ps
CPU time 0.7 seconds
Started Aug 04 04:26:47 PM PDT 24
Finished Aug 04 04:26:48 PM PDT 24
Peak memory 204172 kb
Host smart-6bd8da54-6c86-49d0-8c0b-35e826dc5f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527634212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3527634212
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1992758353
Short name T152
Test name
Test status
Simulation time 248031884 ps
CPU time 2.65 seconds
Started Aug 04 04:26:58 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 215724 kb
Host smart-76181ccc-288d-4320-b406-60fe1522be72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992758353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1992758353
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2335091980
Short name T185
Test name
Test status
Simulation time 890478470 ps
CPU time 21.44 seconds
Started Aug 04 04:26:50 PM PDT 24
Finished Aug 04 04:27:12 PM PDT 24
Peak memory 215364 kb
Host smart-1404e9ff-c868-436d-98e7-ff88e5df4218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335091980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2335091980
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3735076241
Short name T1114
Test name
Test status
Simulation time 193019693 ps
CPU time 3 seconds
Started Aug 04 04:26:45 PM PDT 24
Finished Aug 04 04:26:48 PM PDT 24
Peak memory 216920 kb
Host smart-2f9331b1-b9a0-4a1b-8405-0668967d6e92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735076241 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3735076241
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.718359943
Short name T141
Test name
Test status
Simulation time 27887644 ps
CPU time 1.87 seconds
Started Aug 04 04:27:28 PM PDT 24
Finished Aug 04 04:27:30 PM PDT 24
Peak memory 215400 kb
Host smart-06125217-0b21-461a-8494-eec67e92a5ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718359943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.718359943
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3387735886
Short name T1054
Test name
Test status
Simulation time 16590490 ps
CPU time 0.76 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:35 PM PDT 24
Peak memory 203840 kb
Host smart-e4f14028-d97d-422c-9889-de9115ae8836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387735886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3387735886
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.736216414
Short name T1103
Test name
Test status
Simulation time 904620693 ps
CPU time 1.66 seconds
Started Aug 04 04:26:38 PM PDT 24
Finished Aug 04 04:26:40 PM PDT 24
Peak memory 215344 kb
Host smart-eac22415-3b50-468d-b5c7-2a6ef9c3baac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736216414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.736216414
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1403623865
Short name T190
Test name
Test status
Simulation time 2781538961 ps
CPU time 7.54 seconds
Started Aug 04 04:26:49 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 215500 kb
Host smart-e7288f40-b493-42e8-99a9-41835fc0b5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403623865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1403623865
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2512702049
Short name T104
Test name
Test status
Simulation time 48788201 ps
CPU time 2.92 seconds
Started Aug 04 04:26:37 PM PDT 24
Finished Aug 04 04:26:40 PM PDT 24
Peak memory 217108 kb
Host smart-ae83d7d8-6081-4395-aff1-2eeba31e8da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512702049 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2512702049
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3893411536
Short name T1091
Test name
Test status
Simulation time 64629288 ps
CPU time 2.11 seconds
Started Aug 04 04:27:53 PM PDT 24
Finished Aug 04 04:27:55 PM PDT 24
Peak memory 215324 kb
Host smart-af3a5d67-778c-4550-987b-e284ec46bc4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893411536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3893411536
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2261403403
Short name T1101
Test name
Test status
Simulation time 54926074 ps
CPU time 0.72 seconds
Started Aug 04 04:26:27 PM PDT 24
Finished Aug 04 04:26:28 PM PDT 24
Peak memory 204184 kb
Host smart-b8aba4e2-b7a2-4490-ab70-da46718f44a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261403403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2261403403
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3831665496
Short name T1123
Test name
Test status
Simulation time 30121735 ps
CPU time 1.8 seconds
Started Aug 04 04:26:36 PM PDT 24
Finished Aug 04 04:26:38 PM PDT 24
Peak memory 207060 kb
Host smart-c4c73097-4c2f-432c-9ae5-b93a4d28ab79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831665496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3831665496
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3919199835
Short name T124
Test name
Test status
Simulation time 572141157 ps
CPU time 3.06 seconds
Started Aug 04 04:26:33 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 215648 kb
Host smart-ba97c694-fb9c-4658-99cd-763f63983963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919199835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3919199835
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.537506899
Short name T1116
Test name
Test status
Simulation time 318450849 ps
CPU time 6.83 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:41 PM PDT 24
Peak memory 215472 kb
Host smart-2e7d7b18-54fe-41a0-acfa-b170c007a996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537506899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.537506899
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1083419256
Short name T1070
Test name
Test status
Simulation time 57568156 ps
CPU time 3.96 seconds
Started Aug 04 04:26:37 PM PDT 24
Finished Aug 04 04:26:41 PM PDT 24
Peak memory 217664 kb
Host smart-c6e63e6e-ad56-4018-85b8-b081add2c8ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083419256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1083419256
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1640727490
Short name T1089
Test name
Test status
Simulation time 134047102 ps
CPU time 1.92 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 215392 kb
Host smart-0e3ccfa8-d37a-4fc5-8ef3-eaac261d2dc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640727490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1640727490
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2982990517
Short name T1078
Test name
Test status
Simulation time 42506868 ps
CPU time 0.71 seconds
Started Aug 04 04:26:47 PM PDT 24
Finished Aug 04 04:26:47 PM PDT 24
Peak memory 203848 kb
Host smart-4674faa6-b415-4a23-96ca-b7ae7336e42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982990517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2982990517
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.964174551
Short name T1063
Test name
Test status
Simulation time 251879405 ps
CPU time 1.82 seconds
Started Aug 04 04:26:33 PM PDT 24
Finished Aug 04 04:26:35 PM PDT 24
Peak memory 215288 kb
Host smart-74ca3ece-ba4b-499a-ae07-3367a7e2798e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964174551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.964174551
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.750891294
Short name T1139
Test name
Test status
Simulation time 86120482 ps
CPU time 1.62 seconds
Started Aug 04 04:26:50 PM PDT 24
Finished Aug 04 04:26:52 PM PDT 24
Peak memory 215456 kb
Host smart-837c6683-aeed-4b60-9876-577d8fb0a6df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750891294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.750891294
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2976043440
Short name T1093
Test name
Test status
Simulation time 50656279 ps
CPU time 1.58 seconds
Started Aug 04 04:26:29 PM PDT 24
Finished Aug 04 04:26:30 PM PDT 24
Peak memory 215368 kb
Host smart-b5686a19-167b-4cf3-ab3d-a0b73a43e4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976043440 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2976043440
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2709744448
Short name T1137
Test name
Test status
Simulation time 285622203 ps
CPU time 2.64 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 215324 kb
Host smart-2860f214-f768-439d-ab17-80f379f631a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709744448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2709744448
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4134614347
Short name T1068
Test name
Test status
Simulation time 41754233 ps
CPU time 0.68 seconds
Started Aug 04 04:26:29 PM PDT 24
Finished Aug 04 04:26:30 PM PDT 24
Peak memory 203816 kb
Host smart-70365561-713f-4608-9f03-50086e6aa194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134614347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4134614347
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1135650373
Short name T1138
Test name
Test status
Simulation time 115618136 ps
CPU time 1.67 seconds
Started Aug 04 04:26:46 PM PDT 24
Finished Aug 04 04:26:47 PM PDT 24
Peak memory 206960 kb
Host smart-31b07850-f875-49b6-b240-cf75ce353af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135650373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1135650373
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3589191715
Short name T118
Test name
Test status
Simulation time 692860979 ps
CPU time 4.56 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:27:00 PM PDT 24
Peak memory 216540 kb
Host smart-8eba0863-c7f0-42c5-bdc5-d996280aa7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589191715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3589191715
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3646146475
Short name T1082
Test name
Test status
Simulation time 557858817 ps
CPU time 7.64 seconds
Started Aug 04 04:26:45 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 215324 kb
Host smart-0bf91076-faad-4b26-84c5-e8c3686cd14c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646146475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3646146475
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2142894660
Short name T123
Test name
Test status
Simulation time 507326556 ps
CPU time 3.3 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:56 PM PDT 24
Peak memory 218176 kb
Host smart-56691e28-36e2-4e12-b4c1-85c31c8d7df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142894660 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2142894660
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2646159181
Short name T138
Test name
Test status
Simulation time 116696408 ps
CPU time 2.64 seconds
Started Aug 04 04:27:54 PM PDT 24
Finished Aug 04 04:27:57 PM PDT 24
Peak memory 207052 kb
Host smart-9c2c19f2-4209-48dd-b83f-07966e2c856d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646159181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2646159181
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3513107873
Short name T1073
Test name
Test status
Simulation time 39551557 ps
CPU time 0.7 seconds
Started Aug 04 04:26:48 PM PDT 24
Finished Aug 04 04:26:49 PM PDT 24
Peak memory 203848 kb
Host smart-8af6cdf2-8910-4635-92c9-2b0846f38a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513107873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3513107873
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2633519342
Short name T1126
Test name
Test status
Simulation time 58315717 ps
CPU time 3.66 seconds
Started Aug 04 04:27:49 PM PDT 24
Finished Aug 04 04:27:53 PM PDT 24
Peak memory 215388 kb
Host smart-ee0496e0-3339-4bd6-95dc-47c9bf9bd6d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633519342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2633519342
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2017970900
Short name T117
Test name
Test status
Simulation time 54260876 ps
CPU time 2.82 seconds
Started Aug 04 04:26:24 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 215528 kb
Host smart-a6c8bd0e-a862-40c6-aa05-ef81e3abe292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017970900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2017970900
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2245326473
Short name T1133
Test name
Test status
Simulation time 490737490 ps
CPU time 3.57 seconds
Started Aug 04 04:26:48 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 218012 kb
Host smart-58e1d66a-3848-4b88-b12a-b2eaa8545d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245326473 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2245326473
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1273077800
Short name T131
Test name
Test status
Simulation time 388651417 ps
CPU time 2.39 seconds
Started Aug 04 04:26:45 PM PDT 24
Finished Aug 04 04:26:48 PM PDT 24
Peak memory 207188 kb
Host smart-eb9762ce-62d4-4c0b-81fa-7f270342b689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273077800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1273077800
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2310913450
Short name T1051
Test name
Test status
Simulation time 19797604 ps
CPU time 0.74 seconds
Started Aug 04 04:26:51 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 204148 kb
Host smart-18f12634-7f22-4def-aefc-3321a54801da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310913450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2310913450
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2878348230
Short name T1099
Test name
Test status
Simulation time 147952838 ps
CPU time 3.08 seconds
Started Aug 04 04:26:33 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 215380 kb
Host smart-0860a401-c601-4df7-8972-093665019cf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878348230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2878348230
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.849030379
Short name T101
Test name
Test status
Simulation time 57963919 ps
CPU time 3.74 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:38 PM PDT 24
Peak memory 215568 kb
Host smart-227d02c1-8dc3-4cc4-b1db-4d70c34518d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849030379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.849030379
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.175018849
Short name T127
Test name
Test status
Simulation time 358404751 ps
CPU time 7.36 seconds
Started Aug 04 04:26:44 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 215264 kb
Host smart-779a8421-a394-425b-a909-e8bb151a888c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175018849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.175018849
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4037468304
Short name T1097
Test name
Test status
Simulation time 322964661 ps
CPU time 22.34 seconds
Started Aug 04 04:25:57 PM PDT 24
Finished Aug 04 04:26:20 PM PDT 24
Peak memory 215348 kb
Host smart-9a5b703d-7522-4e87-b82c-8becc615a94e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037468304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4037468304
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4053990401
Short name T132
Test name
Test status
Simulation time 393763502 ps
CPU time 22.28 seconds
Started Aug 04 04:26:41 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 207136 kb
Host smart-82256dc1-91f9-48cc-98a9-b7c75f8e191e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053990401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4053990401
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1226616755
Short name T83
Test name
Test status
Simulation time 113089052 ps
CPU time 1.18 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 216428 kb
Host smart-cac1a964-7d75-4e3c-8308-888ac392daa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226616755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1226616755
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1748418573
Short name T162
Test name
Test status
Simulation time 138238280 ps
CPU time 3.42 seconds
Started Aug 04 04:25:57 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 217300 kb
Host smart-5ba9fec4-66a1-4f9b-835e-93f01e8754ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748418573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1748418573
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3323438883
Short name T140
Test name
Test status
Simulation time 224320710 ps
CPU time 1.86 seconds
Started Aug 04 04:26:26 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 207184 kb
Host smart-18e850de-80dd-4d4a-91f8-63604c532d96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323438883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
323438883
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3570832417
Short name T1039
Test name
Test status
Simulation time 112612244 ps
CPU time 0.74 seconds
Started Aug 04 04:26:15 PM PDT 24
Finished Aug 04 04:26:16 PM PDT 24
Peak memory 203848 kb
Host smart-463a0646-7900-4916-a6d0-bc5de8725114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570832417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
570832417
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2837671910
Short name T1096
Test name
Test status
Simulation time 20439176 ps
CPU time 1.19 seconds
Started Aug 04 04:26:24 PM PDT 24
Finished Aug 04 04:26:25 PM PDT 24
Peak memory 215416 kb
Host smart-c8ff13dc-bf87-4227-86d9-2b5da51f3e42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837671910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2837671910
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3664429547
Short name T1119
Test name
Test status
Simulation time 11013080 ps
CPU time 0.69 seconds
Started Aug 04 04:26:02 PM PDT 24
Finished Aug 04 04:26:03 PM PDT 24
Peak memory 203716 kb
Host smart-2b2069d8-3a64-453f-9a10-5b0cf789b580
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664429547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3664429547
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4018113445
Short name T1113
Test name
Test status
Simulation time 63530990 ps
CPU time 3.83 seconds
Started Aug 04 04:26:09 PM PDT 24
Finished Aug 04 04:26:13 PM PDT 24
Peak memory 215368 kb
Host smart-c24f24ae-2044-454a-b58a-001115f892a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018113445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4018113445
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.535856192
Short name T1131
Test name
Test status
Simulation time 589108154 ps
CPU time 2.33 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 215604 kb
Host smart-7530e608-8688-4cdc-bbef-e77bdd847ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535856192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.535856192
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3532844100
Short name T128
Test name
Test status
Simulation time 2552604963 ps
CPU time 14.26 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:26:11 PM PDT 24
Peak memory 216116 kb
Host smart-554a4fdb-5fc8-4b43-b16e-7fab16020601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532844100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3532844100
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.908252297
Short name T1121
Test name
Test status
Simulation time 42303182 ps
CPU time 0.68 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 203844 kb
Host smart-e47e3bba-f449-43b8-86f6-c9184ac8427b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908252297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.908252297
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3658910308
Short name T1047
Test name
Test status
Simulation time 149901329 ps
CPU time 0.67 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 203844 kb
Host smart-4ad27245-c277-4648-aaf3-cdb331e184fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658910308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3658910308
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.198471343
Short name T1040
Test name
Test status
Simulation time 11941072 ps
CPU time 0.7 seconds
Started Aug 04 04:26:28 PM PDT 24
Finished Aug 04 04:26:28 PM PDT 24
Peak memory 203792 kb
Host smart-4a56e1ca-1e80-4aff-b0a5-4b4865138da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198471343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.198471343
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.99917200
Short name T1104
Test name
Test status
Simulation time 52772813 ps
CPU time 0.76 seconds
Started Aug 04 04:27:25 PM PDT 24
Finished Aug 04 04:27:26 PM PDT 24
Peak memory 203860 kb
Host smart-1f4c1e73-76ab-46c2-8df4-0c5a56bd1d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99917200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.99917200
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3114318953
Short name T1118
Test name
Test status
Simulation time 41081112 ps
CPU time 0.69 seconds
Started Aug 04 04:26:41 PM PDT 24
Finished Aug 04 04:26:42 PM PDT 24
Peak memory 203756 kb
Host smart-be8b817d-c382-4d03-8255-c0c7099cee23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114318953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3114318953
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2622113191
Short name T1105
Test name
Test status
Simulation time 15677666 ps
CPU time 0.81 seconds
Started Aug 04 04:27:52 PM PDT 24
Finished Aug 04 04:27:53 PM PDT 24
Peak memory 203832 kb
Host smart-164e520a-192f-4b17-bef6-9e3043e39454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622113191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2622113191
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3509421926
Short name T1045
Test name
Test status
Simulation time 39499803 ps
CPU time 0.76 seconds
Started Aug 04 04:26:49 PM PDT 24
Finished Aug 04 04:26:50 PM PDT 24
Peak memory 203852 kb
Host smart-069060b9-48eb-4d25-b027-5b2c14920f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509421926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3509421926
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3764701083
Short name T1132
Test name
Test status
Simulation time 56989788 ps
CPU time 0.74 seconds
Started Aug 04 04:27:52 PM PDT 24
Finished Aug 04 04:27:52 PM PDT 24
Peak memory 203844 kb
Host smart-b059b909-4459-4000-bea4-251b2c2f929d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764701083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3764701083
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1281971746
Short name T1042
Test name
Test status
Simulation time 31754393 ps
CPU time 0.74 seconds
Started Aug 04 04:26:50 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 203788 kb
Host smart-b01f2def-404d-4efc-acb4-e4e497c4bc80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281971746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1281971746
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3168012088
Short name T1111
Test name
Test status
Simulation time 14506161 ps
CPU time 0.71 seconds
Started Aug 04 04:26:46 PM PDT 24
Finished Aug 04 04:26:47 PM PDT 24
Peak memory 203792 kb
Host smart-de76cddd-7bda-4cc6-9a8f-42880026d8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168012088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3168012088
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.484150097
Short name T1130
Test name
Test status
Simulation time 1270265506 ps
CPU time 21.33 seconds
Started Aug 04 04:26:13 PM PDT 24
Finished Aug 04 04:26:34 PM PDT 24
Peak memory 215380 kb
Host smart-2b236763-28fd-459d-9623-b42e394f182a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484150097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.484150097
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1349360665
Short name T144
Test name
Test status
Simulation time 2722962692 ps
CPU time 37.6 seconds
Started Aug 04 04:26:25 PM PDT 24
Finished Aug 04 04:27:03 PM PDT 24
Peak memory 215384 kb
Host smart-f0e4e2dc-e3bd-4222-877c-13f0c1b14c34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349360665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1349360665
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.148454021
Short name T82
Test name
Test status
Simulation time 86800125 ps
CPU time 0.92 seconds
Started Aug 04 04:26:39 PM PDT 24
Finished Aug 04 04:26:40 PM PDT 24
Peak memory 206944 kb
Host smart-abef0bb3-3a4d-4037-9187-662fe3e4e2b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148454021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.148454021
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1597604928
Short name T1150
Test name
Test status
Simulation time 387431643 ps
CPU time 2.48 seconds
Started Aug 04 04:26:08 PM PDT 24
Finished Aug 04 04:26:11 PM PDT 24
Peak memory 217400 kb
Host smart-e6850d1d-2489-4144-9922-9b9948683f54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597604928 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1597604928
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.665980577
Short name T133
Test name
Test status
Simulation time 43846782 ps
CPU time 1.51 seconds
Started Aug 04 04:26:09 PM PDT 24
Finished Aug 04 04:26:11 PM PDT 24
Peak memory 207220 kb
Host smart-272a5641-15a3-4bb5-bd2b-2a021c40e5ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665980577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.665980577
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.538081209
Short name T1048
Test name
Test status
Simulation time 89631988 ps
CPU time 0.71 seconds
Started Aug 04 04:26:17 PM PDT 24
Finished Aug 04 04:26:18 PM PDT 24
Peak memory 203852 kb
Host smart-dccbfe1a-8f67-43dd-92a6-7e5d82a25157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538081209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.538081209
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.905713890
Short name T1136
Test name
Test status
Simulation time 303335115 ps
CPU time 1.79 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 215436 kb
Host smart-fbe7bbc6-c431-480a-b862-9caa3c7a790c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905713890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.905713890
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2131288495
Short name T1041
Test name
Test status
Simulation time 10338898 ps
CPU time 0.67 seconds
Started Aug 04 04:26:09 PM PDT 24
Finished Aug 04 04:26:10 PM PDT 24
Peak memory 203776 kb
Host smart-e1137612-b42c-4b0d-85aa-739837f09665
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131288495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2131288495
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1457038277
Short name T1094
Test name
Test status
Simulation time 240139320 ps
CPU time 1.81 seconds
Started Aug 04 04:26:12 PM PDT 24
Finished Aug 04 04:26:14 PM PDT 24
Peak memory 215400 kb
Host smart-b860d432-39ec-4e28-b225-61e62b25307c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457038277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1457038277
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2266092308
Short name T120
Test name
Test status
Simulation time 221311328 ps
CPU time 2.89 seconds
Started Aug 04 04:26:22 PM PDT 24
Finished Aug 04 04:26:25 PM PDT 24
Peak memory 215776 kb
Host smart-878aa52b-b332-495b-8b68-d1f1426b3c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266092308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
266092308
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.512780615
Short name T1140
Test name
Test status
Simulation time 2154223611 ps
CPU time 11.85 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:26:07 PM PDT 24
Peak memory 215948 kb
Host smart-8ec63932-db8a-4cc7-a96f-9a1d45832021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512780615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.512780615
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.639184639
Short name T1044
Test name
Test status
Simulation time 66215015 ps
CPU time 0.8 seconds
Started Aug 04 04:27:40 PM PDT 24
Finished Aug 04 04:27:41 PM PDT 24
Peak memory 203816 kb
Host smart-4e0fcdcd-8695-44e5-88c6-e419d573ab8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639184639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.639184639
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3385622138
Short name T1046
Test name
Test status
Simulation time 46080193 ps
CPU time 0.72 seconds
Started Aug 04 04:26:26 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 204124 kb
Host smart-7ea075d9-559c-4a87-8a7c-9cb2c57caf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385622138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3385622138
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.587238592
Short name T1071
Test name
Test status
Simulation time 41809781 ps
CPU time 0.76 seconds
Started Aug 04 04:26:40 PM PDT 24
Finished Aug 04 04:26:41 PM PDT 24
Peak memory 203800 kb
Host smart-c04744d3-c48e-4653-b212-0fb088ccc8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587238592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.587238592
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.572685160
Short name T1076
Test name
Test status
Simulation time 35764863 ps
CPU time 0.72 seconds
Started Aug 04 04:26:38 PM PDT 24
Finished Aug 04 04:26:39 PM PDT 24
Peak memory 204184 kb
Host smart-ecc9f873-3ff1-4d7f-a9e6-1f70b8357f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572685160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.572685160
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.22225471
Short name T1135
Test name
Test status
Simulation time 11740339 ps
CPU time 0.81 seconds
Started Aug 04 04:27:40 PM PDT 24
Finished Aug 04 04:27:41 PM PDT 24
Peak memory 203808 kb
Host smart-0ef5e1da-dd0d-4cd1-90b7-bccd92da3087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22225471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.22225471
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1104140181
Short name T1098
Test name
Test status
Simulation time 84710236 ps
CPU time 0.74 seconds
Started Aug 04 04:26:44 PM PDT 24
Finished Aug 04 04:26:45 PM PDT 24
Peak memory 203780 kb
Host smart-82a834bc-23c9-4617-9974-322df6bd4ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104140181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1104140181
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3558053554
Short name T1100
Test name
Test status
Simulation time 39720927 ps
CPU time 0.73 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:34 PM PDT 24
Peak memory 203856 kb
Host smart-8174e4b1-4812-47b4-8fdc-760340d60326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558053554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3558053554
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1950635211
Short name T1043
Test name
Test status
Simulation time 106878068 ps
CPU time 0.69 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 203848 kb
Host smart-b122d8e1-4ba8-46cd-a6f2-300de1a4ae19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950635211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1950635211
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3996904925
Short name T1090
Test name
Test status
Simulation time 14467837 ps
CPU time 0.78 seconds
Started Aug 04 04:27:32 PM PDT 24
Finished Aug 04 04:27:33 PM PDT 24
Peak memory 203888 kb
Host smart-5be3dbe5-c5a4-4107-8e38-37dbc7752165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996904925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3996904925
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1380932290
Short name T1151
Test name
Test status
Simulation time 13365950 ps
CPU time 0.71 seconds
Started Aug 04 04:26:38 PM PDT 24
Finished Aug 04 04:26:38 PM PDT 24
Peak memory 203792 kb
Host smart-acaa674b-dd7b-4432-a489-e3aadafa13ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380932290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1380932290
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.902910247
Short name T143
Test name
Test status
Simulation time 108566032 ps
CPU time 7.65 seconds
Started Aug 04 04:26:54 PM PDT 24
Finished Aug 04 04:27:02 PM PDT 24
Peak memory 215324 kb
Host smart-7649869a-1c27-4d92-8996-c3870d080f1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902910247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.902910247
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.206701119
Short name T1120
Test name
Test status
Simulation time 5206904150 ps
CPU time 31.1 seconds
Started Aug 04 04:26:50 PM PDT 24
Finished Aug 04 04:27:22 PM PDT 24
Peak memory 207200 kb
Host smart-72f244fa-df45-49fd-a267-214f8c0047f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206701119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.206701119
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3966683252
Short name T84
Test name
Test status
Simulation time 386898667 ps
CPU time 1.48 seconds
Started Aug 04 04:26:10 PM PDT 24
Finished Aug 04 04:26:11 PM PDT 24
Peak memory 216468 kb
Host smart-e96072cd-5217-420f-a364-0185f00c2aaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966683252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3966683252
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.121424685
Short name T126
Test name
Test status
Simulation time 160312355 ps
CPU time 3.56 seconds
Started Aug 04 04:26:03 PM PDT 24
Finished Aug 04 04:26:06 PM PDT 24
Peak memory 217472 kb
Host smart-44f7501c-314b-440c-8717-8ada868409d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121424685 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.121424685
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3679095075
Short name T1106
Test name
Test status
Simulation time 312231900 ps
CPU time 2.05 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 207208 kb
Host smart-0d019010-d513-43cc-9ac8-9e50f5ec8983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679095075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
679095075
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2915298186
Short name T1072
Test name
Test status
Simulation time 66543046 ps
CPU time 0.75 seconds
Started Aug 04 04:26:53 PM PDT 24
Finished Aug 04 04:26:54 PM PDT 24
Peak memory 203888 kb
Host smart-baacfbe7-1402-4ddd-bfe4-27acfb4c915e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915298186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
915298186
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3283099883
Short name T1109
Test name
Test status
Simulation time 58563425 ps
CPU time 1.15 seconds
Started Aug 04 04:26:30 PM PDT 24
Finished Aug 04 04:26:31 PM PDT 24
Peak memory 215308 kb
Host smart-a4155c02-8ddd-46e8-9d13-099bb5d274ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283099883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3283099883
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.370223905
Short name T1084
Test name
Test status
Simulation time 40700961 ps
CPU time 0.68 seconds
Started Aug 04 04:26:06 PM PDT 24
Finished Aug 04 04:26:07 PM PDT 24
Peak memory 203844 kb
Host smart-6cedd102-2d18-4518-8d29-8251b46f0841
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370223905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.370223905
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3946105671
Short name T1075
Test name
Test status
Simulation time 339358478 ps
CPU time 4 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:03 PM PDT 24
Peak memory 215716 kb
Host smart-8ba1a837-e579-4c8d-99a4-e6ae28b121fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946105671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3946105671
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3793217780
Short name T1149
Test name
Test status
Simulation time 2119510379 ps
CPU time 14.03 seconds
Started Aug 04 04:26:07 PM PDT 24
Finished Aug 04 04:26:21 PM PDT 24
Peak memory 215316 kb
Host smart-3df6402c-a730-4607-870f-7a347ff56572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793217780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3793217780
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.886888455
Short name T1064
Test name
Test status
Simulation time 43382996 ps
CPU time 0.74 seconds
Started Aug 04 04:26:42 PM PDT 24
Finished Aug 04 04:26:42 PM PDT 24
Peak memory 203844 kb
Host smart-251b22cc-8f7b-4c9c-921c-bafc717085b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886888455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.886888455
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1691638585
Short name T1081
Test name
Test status
Simulation time 16065473 ps
CPU time 0.69 seconds
Started Aug 04 04:26:27 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 203756 kb
Host smart-27e436af-2594-4c89-82df-8bb1d26811c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691638585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1691638585
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.298086231
Short name T1086
Test name
Test status
Simulation time 51900840 ps
CPU time 0.78 seconds
Started Aug 04 04:27:49 PM PDT 24
Finished Aug 04 04:27:50 PM PDT 24
Peak memory 203828 kb
Host smart-fba26aad-afa6-43ad-8241-f971624f40b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298086231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.298086231
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3563720187
Short name T1080
Test name
Test status
Simulation time 19712807 ps
CPU time 0.66 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:36 PM PDT 24
Peak memory 203816 kb
Host smart-e0298dbe-c220-427f-b09a-6332f8bc0a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563720187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3563720187
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2310749696
Short name T1057
Test name
Test status
Simulation time 41670396 ps
CPU time 0.71 seconds
Started Aug 04 04:26:41 PM PDT 24
Finished Aug 04 04:26:42 PM PDT 24
Peak memory 203840 kb
Host smart-e665b82d-795c-485b-bb21-9f0d0d0da356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310749696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2310749696
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2054049757
Short name T1050
Test name
Test status
Simulation time 31586295 ps
CPU time 0.72 seconds
Started Aug 04 04:26:44 PM PDT 24
Finished Aug 04 04:26:45 PM PDT 24
Peak memory 203840 kb
Host smart-b179c5bd-5f81-4c57-9df7-8190162a6580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054049757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2054049757
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2045665943
Short name T1052
Test name
Test status
Simulation time 127213456 ps
CPU time 0.73 seconds
Started Aug 04 04:27:03 PM PDT 24
Finished Aug 04 04:27:04 PM PDT 24
Peak memory 203772 kb
Host smart-99bce4e3-297f-44fe-8fd2-12874bc2e1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045665943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2045665943
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.469320798
Short name T1062
Test name
Test status
Simulation time 46823712 ps
CPU time 0.72 seconds
Started Aug 04 04:26:47 PM PDT 24
Finished Aug 04 04:26:48 PM PDT 24
Peak memory 203856 kb
Host smart-53a9f70c-a480-4642-ba98-b76743362872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469320798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.469320798
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3981592788
Short name T1061
Test name
Test status
Simulation time 22794634 ps
CPU time 0.72 seconds
Started Aug 04 04:27:01 PM PDT 24
Finished Aug 04 04:27:01 PM PDT 24
Peak memory 204252 kb
Host smart-a5e5a9f5-582c-4dd6-8085-15b5d19aec54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981592788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3981592788
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.552394848
Short name T1115
Test name
Test status
Simulation time 15346593 ps
CPU time 0.76 seconds
Started Aug 04 04:27:52 PM PDT 24
Finished Aug 04 04:27:53 PM PDT 24
Peak memory 204184 kb
Host smart-54624ea0-1359-4a5f-88d0-646b467cfdc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552394848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.552394848
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.668275290
Short name T121
Test name
Test status
Simulation time 119491651 ps
CPU time 4 seconds
Started Aug 04 04:26:20 PM PDT 24
Finished Aug 04 04:26:24 PM PDT 24
Peak memory 217428 kb
Host smart-ceeb8876-092c-4864-aeda-20733f980a04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668275290 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.668275290
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2161674538
Short name T1074
Test name
Test status
Simulation time 66231731 ps
CPU time 1.17 seconds
Started Aug 04 04:26:36 PM PDT 24
Finished Aug 04 04:26:37 PM PDT 24
Peak memory 207124 kb
Host smart-aa2eb233-b8ce-424d-aad2-014ba2720e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161674538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
161674538
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.965409080
Short name T1127
Test name
Test status
Simulation time 23664064 ps
CPU time 0.71 seconds
Started Aug 04 04:26:07 PM PDT 24
Finished Aug 04 04:26:08 PM PDT 24
Peak memory 204188 kb
Host smart-a06323f1-c83a-4c10-bc95-3bc072349157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965409080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.965409080
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2179636937
Short name T1059
Test name
Test status
Simulation time 63743403 ps
CPU time 3.76 seconds
Started Aug 04 04:26:40 PM PDT 24
Finished Aug 04 04:26:44 PM PDT 24
Peak memory 215320 kb
Host smart-cfb0f34a-eb19-413a-96fd-83d1e2fe1e0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179636937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2179636937
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1088099267
Short name T1146
Test name
Test status
Simulation time 253498693 ps
CPU time 4.41 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:04 PM PDT 24
Peak memory 215952 kb
Host smart-fab58b9e-87d5-4239-b9ec-4e010a572f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088099267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
088099267
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.440053823
Short name T187
Test name
Test status
Simulation time 734757490 ps
CPU time 16.67 seconds
Started Aug 04 04:26:49 PM PDT 24
Finished Aug 04 04:27:06 PM PDT 24
Peak memory 215472 kb
Host smart-9461742e-1f55-4bdc-b2de-1e7928474170
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440053823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.440053823
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4100745785
Short name T1087
Test name
Test status
Simulation time 53922104 ps
CPU time 1.7 seconds
Started Aug 04 04:26:19 PM PDT 24
Finished Aug 04 04:26:20 PM PDT 24
Peak memory 215500 kb
Host smart-52ba584e-5632-4085-92a3-2b1e1514a328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100745785 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4100745785
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2134295479
Short name T1053
Test name
Test status
Simulation time 71593379 ps
CPU time 1.28 seconds
Started Aug 04 04:26:13 PM PDT 24
Finished Aug 04 04:26:14 PM PDT 24
Peak memory 215424 kb
Host smart-25f17b28-3e34-4c16-a6cb-85c684a86910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134295479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
134295479
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2236005698
Short name T1065
Test name
Test status
Simulation time 16858459 ps
CPU time 0.72 seconds
Started Aug 04 04:26:48 PM PDT 24
Finished Aug 04 04:26:49 PM PDT 24
Peak memory 203768 kb
Host smart-7e9f4489-99c8-48c9-8824-77dc5b1108ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236005698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
236005698
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3666956041
Short name T1085
Test name
Test status
Simulation time 110819809 ps
CPU time 3.47 seconds
Started Aug 04 04:26:11 PM PDT 24
Finished Aug 04 04:26:15 PM PDT 24
Peak memory 215400 kb
Host smart-c6eaf6dc-0504-45e7-9929-b62a96cf7c5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666956041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3666956041
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3167942496
Short name T112
Test name
Test status
Simulation time 700208173 ps
CPU time 3.81 seconds
Started Aug 04 04:26:39 PM PDT 24
Finished Aug 04 04:26:43 PM PDT 24
Peak memory 215508 kb
Host smart-04736a01-af61-4633-b7b9-63b1de14ed97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167942496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
167942496
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2115524408
Short name T160
Test name
Test status
Simulation time 1024521156 ps
CPU time 21.25 seconds
Started Aug 04 04:26:32 PM PDT 24
Finished Aug 04 04:26:53 PM PDT 24
Peak memory 215752 kb
Host smart-7d56c9ea-708d-48c1-b1d2-8f3dd8ae8e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115524408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2115524408
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.653195967
Short name T102
Test name
Test status
Simulation time 68530658 ps
CPU time 1.63 seconds
Started Aug 04 04:26:50 PM PDT 24
Finished Aug 04 04:26:52 PM PDT 24
Peak memory 215552 kb
Host smart-3b3f030e-37fd-4036-b44b-0c9e08ad8d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653195967 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.653195967
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2821925969
Short name T130
Test name
Test status
Simulation time 73596982 ps
CPU time 1.26 seconds
Started Aug 04 04:26:37 PM PDT 24
Finished Aug 04 04:26:38 PM PDT 24
Peak memory 207200 kb
Host smart-42ff33c1-762d-4be9-b568-6e6879d27c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821925969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
821925969
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1592212627
Short name T1092
Test name
Test status
Simulation time 71255951 ps
CPU time 0.71 seconds
Started Aug 04 04:26:17 PM PDT 24
Finished Aug 04 04:26:18 PM PDT 24
Peak memory 203824 kb
Host smart-3ae9306c-dbf3-466d-bf6f-bcb288d9833f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592212627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
592212627
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3931609628
Short name T1110
Test name
Test status
Simulation time 998061039 ps
CPU time 2.93 seconds
Started Aug 04 04:26:43 PM PDT 24
Finished Aug 04 04:26:46 PM PDT 24
Peak memory 215396 kb
Host smart-0484454c-49e1-4a48-a864-a95dfaf470fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931609628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3931609628
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.557703605
Short name T113
Test name
Test status
Simulation time 27940943 ps
CPU time 1.71 seconds
Started Aug 04 04:26:45 PM PDT 24
Finished Aug 04 04:26:46 PM PDT 24
Peak memory 215624 kb
Host smart-a8cc530c-f39e-43c8-ba81-f2263c302f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557703605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.557703605
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2168387691
Short name T99
Test name
Test status
Simulation time 435340819 ps
CPU time 6.72 seconds
Started Aug 04 04:26:35 PM PDT 24
Finished Aug 04 04:26:42 PM PDT 24
Peak memory 215396 kb
Host smart-ade9e977-063a-422b-8c29-7d5b3b6fe99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168387691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2168387691
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2140455040
Short name T119
Test name
Test status
Simulation time 998442498 ps
CPU time 3.27 seconds
Started Aug 04 04:26:47 PM PDT 24
Finished Aug 04 04:26:51 PM PDT 24
Peak memory 217504 kb
Host smart-47dd6a4e-de38-4610-b595-7b88b7b059bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140455040 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2140455040
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3394168068
Short name T134
Test name
Test status
Simulation time 72242449 ps
CPU time 1.32 seconds
Started Aug 04 04:26:17 PM PDT 24
Finished Aug 04 04:26:18 PM PDT 24
Peak memory 215388 kb
Host smart-a53b4fef-2453-4194-ac97-9c80f8058508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394168068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
394168068
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.716465397
Short name T1142
Test name
Test status
Simulation time 41498688 ps
CPU time 0.67 seconds
Started Aug 04 04:26:31 PM PDT 24
Finished Aug 04 04:26:31 PM PDT 24
Peak memory 203728 kb
Host smart-7ed52822-82d7-4ed6-b805-17910a58c233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716465397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.716465397
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.870941877
Short name T1056
Test name
Test status
Simulation time 147847269 ps
CPU time 2.49 seconds
Started Aug 04 04:26:38 PM PDT 24
Finished Aug 04 04:26:41 PM PDT 24
Peak memory 215284 kb
Host smart-ce407a21-c41e-419b-b28a-30b9f923b6a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870941877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.870941877
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.160052390
Short name T122
Test name
Test status
Simulation time 72511142 ps
CPU time 2.34 seconds
Started Aug 04 04:26:55 PM PDT 24
Finished Aug 04 04:26:57 PM PDT 24
Peak memory 215528 kb
Host smart-a975ac77-5f16-4864-a2fc-470f326631eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160052390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.160052390
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2827067281
Short name T105
Test name
Test status
Simulation time 84567293 ps
CPU time 2.85 seconds
Started Aug 04 04:26:26 PM PDT 24
Finished Aug 04 04:26:29 PM PDT 24
Peak memory 216968 kb
Host smart-1f2703d3-b123-4e2b-b8b8-aaf6fa0fabc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827067281 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2827067281
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2773175118
Short name T151
Test name
Test status
Simulation time 26379005 ps
CPU time 1.67 seconds
Started Aug 04 04:26:42 PM PDT 24
Finished Aug 04 04:26:44 PM PDT 24
Peak memory 215184 kb
Host smart-f329035b-93db-4d2d-90b4-923707f72352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773175118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
773175118
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3077203601
Short name T1083
Test name
Test status
Simulation time 29303975 ps
CPU time 0.68 seconds
Started Aug 04 04:26:39 PM PDT 24
Finished Aug 04 04:26:40 PM PDT 24
Peak memory 203816 kb
Host smart-9f75dc1b-fabf-488c-abe2-035ae1a746b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077203601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
077203601
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2817617490
Short name T1077
Test name
Test status
Simulation time 63245729 ps
CPU time 1.83 seconds
Started Aug 04 04:26:31 PM PDT 24
Finished Aug 04 04:26:33 PM PDT 24
Peak memory 215260 kb
Host smart-f94e2f92-a0e7-443f-be5f-9d04debd01f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817617490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2817617490
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4008350779
Short name T114
Test name
Test status
Simulation time 198063375 ps
CPU time 2.33 seconds
Started Aug 04 04:26:11 PM PDT 24
Finished Aug 04 04:26:13 PM PDT 24
Peak memory 215668 kb
Host smart-e124b5d0-a5cd-472e-a203-68558e1c181e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008350779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
008350779
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2646334200
Short name T594
Test name
Test status
Simulation time 14617113 ps
CPU time 0.74 seconds
Started Aug 04 04:52:32 PM PDT 24
Finished Aug 04 04:52:32 PM PDT 24
Peak memory 205896 kb
Host smart-a18caa65-318a-42fb-bfd9-f5149e40e2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646334200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
646334200
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4147150018
Short name T556
Test name
Test status
Simulation time 251401022 ps
CPU time 3.43 seconds
Started Aug 04 04:52:27 PM PDT 24
Finished Aug 04 04:52:31 PM PDT 24
Peak memory 225228 kb
Host smart-4a5e1d11-77d9-4792-8d05-29186fcf53cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147150018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4147150018
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2277989807
Short name T1014
Test name
Test status
Simulation time 34964530 ps
CPU time 0.8 seconds
Started Aug 04 04:52:19 PM PDT 24
Finished Aug 04 04:52:20 PM PDT 24
Peak memory 207376 kb
Host smart-1d850f39-7991-490b-8469-775ef74c25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277989807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2277989807
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3228159528
Short name T917
Test name
Test status
Simulation time 12384623255 ps
CPU time 106.68 seconds
Started Aug 04 04:52:28 PM PDT 24
Finished Aug 04 04:54:15 PM PDT 24
Peak memory 250128 kb
Host smart-87beae96-db5a-4f6a-9153-7905e18908c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228159528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3228159528
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2280881093
Short name T85
Test name
Test status
Simulation time 864101645 ps
CPU time 20.45 seconds
Started Aug 04 04:52:32 PM PDT 24
Finished Aug 04 04:52:52 PM PDT 24
Peak memory 258116 kb
Host smart-3782b94b-e739-439e-9c1c-24f35c4dd909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280881093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2280881093
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4158092324
Short name T634
Test name
Test status
Simulation time 57242049 ps
CPU time 0.78 seconds
Started Aug 04 04:52:28 PM PDT 24
Finished Aug 04 04:52:29 PM PDT 24
Peak memory 216668 kb
Host smart-0025838a-b001-4c05-9d1f-0d91d4dad1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158092324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4158092324
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1842628636
Short name T417
Test name
Test status
Simulation time 2138835917 ps
CPU time 15.29 seconds
Started Aug 04 04:52:23 PM PDT 24
Finished Aug 04 04:52:38 PM PDT 24
Peak memory 225084 kb
Host smart-01596c57-7de6-4394-984e-b3d5e7a29088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842628636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1842628636
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.946368279
Short name T688
Test name
Test status
Simulation time 702682586 ps
CPU time 19.41 seconds
Started Aug 04 04:52:23 PM PDT 24
Finished Aug 04 04:52:43 PM PDT 24
Peak memory 241332 kb
Host smart-58070321-4a18-40e9-a7a5-aad54fda9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946368279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.946368279
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3817981731
Short name T817
Test name
Test status
Simulation time 30940496 ps
CPU time 1.03 seconds
Started Aug 04 04:52:21 PM PDT 24
Finished Aug 04 04:52:22 PM PDT 24
Peak memory 218368 kb
Host smart-759e46c1-d4cd-4336-8ddc-3e8de3a03ed3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817981731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3817981731
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4178217326
Short name T273
Test name
Test status
Simulation time 8725536310 ps
CPU time 13.88 seconds
Started Aug 04 04:52:23 PM PDT 24
Finished Aug 04 04:52:37 PM PDT 24
Peak memory 233424 kb
Host smart-efa78ce7-f1e0-4344-a492-500ee77cbc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178217326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4178217326
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3494549838
Short name T433
Test name
Test status
Simulation time 3714988657 ps
CPU time 17.08 seconds
Started Aug 04 04:52:23 PM PDT 24
Finished Aug 04 04:52:40 PM PDT 24
Peak memory 241484 kb
Host smart-641d596b-76bf-4db9-8269-05c075fdf0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494549838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3494549838
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3926514273
Short name T524
Test name
Test status
Simulation time 1670017723 ps
CPU time 15.25 seconds
Started Aug 04 04:52:26 PM PDT 24
Finished Aug 04 04:52:42 PM PDT 24
Peak memory 220728 kb
Host smart-0d446dd3-b4a9-4128-a2a2-9819254008e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3926514273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3926514273
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4255301439
Short name T70
Test name
Test status
Simulation time 87341794 ps
CPU time 1.27 seconds
Started Aug 04 04:52:32 PM PDT 24
Finished Aug 04 04:52:33 PM PDT 24
Peak memory 236660 kb
Host smart-2e284015-34ff-4520-8838-69f33a40f6de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255301439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4255301439
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3686522329
Short name T165
Test name
Test status
Simulation time 114473476891 ps
CPU time 228.96 seconds
Started Aug 04 04:52:31 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 257652 kb
Host smart-2b84fe3e-3b46-4fd0-9041-d9d468cda19a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686522329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3686522329
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.533953017
Short name T708
Test name
Test status
Simulation time 20106454215 ps
CPU time 39.63 seconds
Started Aug 04 04:52:19 PM PDT 24
Finished Aug 04 04:52:59 PM PDT 24
Peak memory 217232 kb
Host smart-ac2c2ba5-8953-4241-b122-85e25a4ee6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533953017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.533953017
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.79871136
Short name T399
Test name
Test status
Simulation time 971246700 ps
CPU time 2.51 seconds
Started Aug 04 04:52:21 PM PDT 24
Finished Aug 04 04:52:24 PM PDT 24
Peak memory 216944 kb
Host smart-6952e2e1-70b0-47b1-bcaa-1caf92b85901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79871136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.79871136
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.168164848
Short name T737
Test name
Test status
Simulation time 273153535 ps
CPU time 1.36 seconds
Started Aug 04 04:52:25 PM PDT 24
Finished Aug 04 04:52:26 PM PDT 24
Peak memory 208584 kb
Host smart-33d4e012-fded-455f-88f4-9c494230c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168164848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.168164848
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2852688536
Short name T912
Test name
Test status
Simulation time 95909651 ps
CPU time 0.72 seconds
Started Aug 04 04:52:23 PM PDT 24
Finished Aug 04 04:52:24 PM PDT 24
Peak memory 206508 kb
Host smart-43608842-5c95-4590-b862-504c02762074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852688536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2852688536
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.383846910
Short name T919
Test name
Test status
Simulation time 5784875808 ps
CPU time 9.44 seconds
Started Aug 04 04:52:29 PM PDT 24
Finished Aug 04 04:52:38 PM PDT 24
Peak memory 233508 kb
Host smart-d6ed0d6b-7710-4b1b-a9d5-9dd4bb0fb4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383846910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.383846910
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1170272908
Short name T626
Test name
Test status
Simulation time 479255367 ps
CPU time 4.89 seconds
Started Aug 04 04:52:40 PM PDT 24
Finished Aug 04 04:52:45 PM PDT 24
Peak memory 233344 kb
Host smart-67361633-4295-406a-9ca4-05ef88b6988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170272908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1170272908
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2669314472
Short name T797
Test name
Test status
Simulation time 88803210 ps
CPU time 0.83 seconds
Started Aug 04 04:52:30 PM PDT 24
Finished Aug 04 04:52:31 PM PDT 24
Peak memory 207252 kb
Host smart-2d506362-75fa-45f1-94d9-6185863c7147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669314472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2669314472
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3899411642
Short name T992
Test name
Test status
Simulation time 18122013 ps
CPU time 0.79 seconds
Started Aug 04 04:52:38 PM PDT 24
Finished Aug 04 04:52:39 PM PDT 24
Peak memory 216304 kb
Host smart-2f722d27-8f11-4ac3-9308-a1f233c0bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899411642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3899411642
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1778482249
Short name T27
Test name
Test status
Simulation time 35375461175 ps
CPU time 68.15 seconds
Started Aug 04 04:52:40 PM PDT 24
Finished Aug 04 04:53:48 PM PDT 24
Peak memory 241664 kb
Host smart-21b8eb4a-99bc-45aa-ac20-d0b8da47cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778482249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1778482249
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2811696640
Short name T426
Test name
Test status
Simulation time 496065761 ps
CPU time 8.14 seconds
Started Aug 04 04:52:40 PM PDT 24
Finished Aug 04 04:52:48 PM PDT 24
Peak memory 234992 kb
Host smart-14790bb3-c82d-4be0-ae60-c8ab776b08be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811696640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2811696640
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2132176356
Short name T846
Test name
Test status
Simulation time 26762072539 ps
CPU time 209.72 seconds
Started Aug 04 04:52:39 PM PDT 24
Finished Aug 04 04:56:09 PM PDT 24
Peak memory 257532 kb
Host smart-bf80b7af-483b-4195-a227-7af50eaa9f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132176356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2132176356
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3597902504
Short name T283
Test name
Test status
Simulation time 13830529329 ps
CPU time 44.21 seconds
Started Aug 04 04:52:38 PM PDT 24
Finished Aug 04 04:53:22 PM PDT 24
Peak memory 228760 kb
Host smart-048f6145-ca24-4d0b-9f91-f847eeb9e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597902504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3597902504
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2958759161
Short name T938
Test name
Test status
Simulation time 32075076 ps
CPU time 1.07 seconds
Started Aug 04 04:52:33 PM PDT 24
Finished Aug 04 04:52:34 PM PDT 24
Peak memory 217080 kb
Host smart-e5a22c9f-f6b4-48ee-a818-4501150530d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958759161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2958759161
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1588921946
Short name T986
Test name
Test status
Simulation time 4732560911 ps
CPU time 9.95 seconds
Started Aug 04 04:52:37 PM PDT 24
Finished Aug 04 04:52:47 PM PDT 24
Peak memory 233448 kb
Host smart-82c8604c-593b-42ab-8a06-6ac9da861212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588921946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1588921946
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2311689093
Short name T586
Test name
Test status
Simulation time 176563456 ps
CPU time 4.97 seconds
Started Aug 04 04:52:35 PM PDT 24
Finished Aug 04 04:52:40 PM PDT 24
Peak memory 233364 kb
Host smart-bae51e3b-2ae5-4414-a910-1ffbb2f1af1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311689093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2311689093
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.981320801
Short name T786
Test name
Test status
Simulation time 353989022 ps
CPU time 3.41 seconds
Started Aug 04 04:52:39 PM PDT 24
Finished Aug 04 04:52:43 PM PDT 24
Peak memory 219824 kb
Host smart-9fdb0e87-f448-4b7e-9146-5142f29347bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=981320801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.981320801
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4058714880
Short name T69
Test name
Test status
Simulation time 221017523 ps
CPU time 1.1 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:52:45 PM PDT 24
Peak memory 235632 kb
Host smart-f258c87b-7d27-477c-b341-dc522b12b16f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058714880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4058714880
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1612271686
Short name T424
Test name
Test status
Simulation time 2099233953 ps
CPU time 22.1 seconds
Started Aug 04 04:52:36 PM PDT 24
Finished Aug 04 04:52:58 PM PDT 24
Peak memory 217192 kb
Host smart-c78dd7ab-2047-4026-b895-fec4ee644a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612271686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1612271686
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.901651507
Short name T343
Test name
Test status
Simulation time 687372456 ps
CPU time 3.9 seconds
Started Aug 04 04:52:34 PM PDT 24
Finished Aug 04 04:52:37 PM PDT 24
Peak memory 216880 kb
Host smart-0420dd24-d8d9-4604-9700-1b9b6a0f898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901651507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.901651507
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3561945339
Short name T489
Test name
Test status
Simulation time 97865061 ps
CPU time 1.41 seconds
Started Aug 04 04:52:36 PM PDT 24
Finished Aug 04 04:52:37 PM PDT 24
Peak memory 216868 kb
Host smart-9e18fd93-65e5-45a2-abe7-8d62f3cb38a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561945339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3561945339
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3600106244
Short name T390
Test name
Test status
Simulation time 88729307 ps
CPU time 1.02 seconds
Started Aug 04 04:52:34 PM PDT 24
Finished Aug 04 04:52:35 PM PDT 24
Peak memory 206636 kb
Host smart-a6d31c75-b5b2-42d9-b54e-c9a831ac1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600106244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3600106244
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.211548273
Short name T976
Test name
Test status
Simulation time 3200310456 ps
CPU time 6.06 seconds
Started Aug 04 04:52:39 PM PDT 24
Finished Aug 04 04:52:45 PM PDT 24
Peak memory 240992 kb
Host smart-28e52bcc-d4cb-45ae-9c6a-760a395ff58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211548273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.211548273
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1686698234
Short name T363
Test name
Test status
Simulation time 19835431 ps
CPU time 0.72 seconds
Started Aug 04 04:53:50 PM PDT 24
Finished Aug 04 04:53:51 PM PDT 24
Peak memory 206260 kb
Host smart-1e817524-f57e-430a-bc44-d092a23ea512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686698234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1686698234
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3811855526
Short name T958
Test name
Test status
Simulation time 744513611 ps
CPU time 3.85 seconds
Started Aug 04 04:53:46 PM PDT 24
Finished Aug 04 04:53:50 PM PDT 24
Peak memory 233296 kb
Host smart-424cf31a-4473-4e0c-91fe-6bfabd7d7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811855526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3811855526
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3748026347
Short name T972
Test name
Test status
Simulation time 43688282 ps
CPU time 0.78 seconds
Started Aug 04 04:53:43 PM PDT 24
Finished Aug 04 04:53:44 PM PDT 24
Peak memory 206056 kb
Host smart-fc56e4f7-77ed-42e3-9b77-a6fb79438f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748026347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3748026347
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3202289603
Short name T685
Test name
Test status
Simulation time 8490156292 ps
CPU time 61.21 seconds
Started Aug 04 04:53:48 PM PDT 24
Finished Aug 04 04:54:49 PM PDT 24
Peak memory 241640 kb
Host smart-d3f2bee4-b58e-4601-8f38-53df0ab18775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202289603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3202289603
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.757390527
Short name T632
Test name
Test status
Simulation time 20976336399 ps
CPU time 183.13 seconds
Started Aug 04 04:53:51 PM PDT 24
Finished Aug 04 04:56:54 PM PDT 24
Peak memory 251040 kb
Host smart-f32a0086-d0a7-411b-b914-e4dcca978a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757390527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.757390527
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.888384961
Short name T385
Test name
Test status
Simulation time 14662458526 ps
CPU time 54.31 seconds
Started Aug 04 04:53:52 PM PDT 24
Finished Aug 04 04:54:46 PM PDT 24
Peak memory 252864 kb
Host smart-c0a7d2dc-5ec5-418f-934b-125ab90f73f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888384961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.888384961
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.167791045
Short name T725
Test name
Test status
Simulation time 8662576451 ps
CPU time 21.08 seconds
Started Aug 04 04:53:48 PM PDT 24
Finished Aug 04 04:54:09 PM PDT 24
Peak memory 236548 kb
Host smart-555410fa-693a-447e-a4db-b5356c20f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167791045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.167791045
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1729697054
Short name T537
Test name
Test status
Simulation time 141871473 ps
CPU time 0.86 seconds
Started Aug 04 04:53:47 PM PDT 24
Finished Aug 04 04:53:48 PM PDT 24
Peak memory 216908 kb
Host smart-b2aecd9e-9beb-4bce-991e-fccbaebac48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729697054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1729697054
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3146089986
Short name T401
Test name
Test status
Simulation time 207937559 ps
CPU time 2.67 seconds
Started Aug 04 04:53:49 PM PDT 24
Finished Aug 04 04:53:52 PM PDT 24
Peak memory 232976 kb
Host smart-c718b034-0f3b-41ba-8d87-3f7bcefc64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146089986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3146089986
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1707477535
Short name T355
Test name
Test status
Simulation time 4654342008 ps
CPU time 11.99 seconds
Started Aug 04 04:53:46 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 233328 kb
Host smart-1b0da04b-6200-4cf3-8bc6-33c7fb6223d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707477535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1707477535
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.288947685
Short name T882
Test name
Test status
Simulation time 33246308 ps
CPU time 1.09 seconds
Started Aug 04 04:53:45 PM PDT 24
Finished Aug 04 04:53:46 PM PDT 24
Peak memory 217164 kb
Host smart-f6165310-0e9d-4951-a4a8-83519facaea1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288947685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.288947685
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1426900959
Short name T765
Test name
Test status
Simulation time 157647480 ps
CPU time 2.84 seconds
Started Aug 04 04:53:43 PM PDT 24
Finished Aug 04 04:53:46 PM PDT 24
Peak memory 233004 kb
Host smart-de5e1f1e-1471-48b0-9f1b-804ac4220b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426900959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1426900959
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3887748775
Short name T583
Test name
Test status
Simulation time 213952030 ps
CPU time 2.52 seconds
Started Aug 04 04:53:43 PM PDT 24
Finished Aug 04 04:53:46 PM PDT 24
Peak memory 233328 kb
Host smart-80a8b79c-0c60-4bb3-882a-031a2862013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887748775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3887748775
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.351615059
Short name T606
Test name
Test status
Simulation time 197099339 ps
CPU time 4.04 seconds
Started Aug 04 04:53:48 PM PDT 24
Finished Aug 04 04:53:53 PM PDT 24
Peak memory 223000 kb
Host smart-b24db228-202d-49ad-8030-b8cbbaea50e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351615059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.351615059
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2990157255
Short name T735
Test name
Test status
Simulation time 158756526 ps
CPU time 1.1 seconds
Started Aug 04 04:53:51 PM PDT 24
Finished Aug 04 04:53:52 PM PDT 24
Peak memory 207484 kb
Host smart-fdf487e8-d928-495c-8b90-fac74db68077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990157255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2990157255
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2607493895
Short name T509
Test name
Test status
Simulation time 26669366 ps
CPU time 0.7 seconds
Started Aug 04 04:53:44 PM PDT 24
Finished Aug 04 04:53:45 PM PDT 24
Peak memory 206164 kb
Host smart-538d89dd-5b92-4e3b-bf30-e2a0cd46f563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607493895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2607493895
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3755526130
Short name T372
Test name
Test status
Simulation time 6072001764 ps
CPU time 19 seconds
Started Aug 04 04:53:45 PM PDT 24
Finished Aug 04 04:54:04 PM PDT 24
Peak memory 217000 kb
Host smart-387bc0f4-dbc5-412b-bde6-4deca3a47525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755526130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3755526130
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.470686618
Short name T505
Test name
Test status
Simulation time 130157945 ps
CPU time 1.3 seconds
Started Aug 04 04:53:44 PM PDT 24
Finished Aug 04 04:53:45 PM PDT 24
Peak memory 208476 kb
Host smart-b88e2191-38e1-4971-b8ce-04af71e99a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470686618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.470686618
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2124250353
Short name T694
Test name
Test status
Simulation time 164335166 ps
CPU time 0.85 seconds
Started Aug 04 04:53:44 PM PDT 24
Finished Aug 04 04:53:45 PM PDT 24
Peak memory 206636 kb
Host smart-206b3a2f-4fe3-4056-b4e8-f2a4ca3588dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124250353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2124250353
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2437407699
Short name T269
Test name
Test status
Simulation time 634475494 ps
CPU time 3.35 seconds
Started Aug 04 04:53:49 PM PDT 24
Finished Aug 04 04:53:52 PM PDT 24
Peak memory 233404 kb
Host smart-eaa309a2-4689-46ca-ad99-c519fb584192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437407699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2437407699
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.675853459
Short name T806
Test name
Test status
Simulation time 228838900 ps
CPU time 0.73 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:53:59 PM PDT 24
Peak memory 206092 kb
Host smart-0b8c8640-7182-4f7b-93df-9e15898f2026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675853459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.675853459
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.360877333
Short name T948
Test name
Test status
Simulation time 1020891699 ps
CPU time 3.94 seconds
Started Aug 04 04:53:54 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 233256 kb
Host smart-90485862-647f-415f-87c2-7ccc260a183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360877333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.360877333
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3955307280
Short name T780
Test name
Test status
Simulation time 52336247 ps
CPU time 0.77 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:53:53 PM PDT 24
Peak memory 207308 kb
Host smart-11a2257b-fb65-49c0-b175-4296750cb52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955307280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3955307280
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3911592288
Short name T228
Test name
Test status
Simulation time 38015801209 ps
CPU time 296.58 seconds
Started Aug 04 04:53:56 PM PDT 24
Finished Aug 04 04:58:53 PM PDT 24
Peak memory 268956 kb
Host smart-4d6f877c-4d2e-4b8e-b583-1e95a9ca664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911592288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3911592288
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2633781097
Short name T921
Test name
Test status
Simulation time 1858378191 ps
CPU time 14.81 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:54:12 PM PDT 24
Peak memory 241596 kb
Host smart-fbc08e6d-e815-4f91-bc88-8ab126dd0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633781097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2633781097
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1897596083
Short name T760
Test name
Test status
Simulation time 130144240976 ps
CPU time 206.48 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:57:20 PM PDT 24
Peak memory 249992 kb
Host smart-7948657e-01c2-4f12-811b-13997cf3390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897596083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1897596083
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2115949487
Short name T847
Test name
Test status
Simulation time 756586863 ps
CPU time 3.52 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:54:01 PM PDT 24
Peak memory 234948 kb
Host smart-7fa1a278-c2a2-4b2f-8245-f8b202ad8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115949487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2115949487
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3051371718
Short name T313
Test name
Test status
Simulation time 38342554382 ps
CPU time 279.93 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:58:37 PM PDT 24
Peak memory 253252 kb
Host smart-bc9bc005-3911-469a-b6cb-cc9d3471b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051371718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3051371718
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2352912862
Short name T1019
Test name
Test status
Simulation time 1244922102 ps
CPU time 16.01 seconds
Started Aug 04 04:53:55 PM PDT 24
Finished Aug 04 04:54:11 PM PDT 24
Peak memory 233304 kb
Host smart-0e7c4be1-3854-4a7e-b87e-6bc964759393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352912862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2352912862
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2912490726
Short name T681
Test name
Test status
Simulation time 5682014511 ps
CPU time 28.22 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:54:22 PM PDT 24
Peak memory 233540 kb
Host smart-47bc8379-7f99-460a-b631-ad3364b12b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912490726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2912490726
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3513311863
Short name T387
Test name
Test status
Simulation time 428858615 ps
CPU time 5.37 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 241672 kb
Host smart-651f42d5-20d1-496a-9320-1f9c4e24d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513311863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3513311863
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1621841523
Short name T287
Test name
Test status
Simulation time 6270227198 ps
CPU time 7.41 seconds
Started Aug 04 04:53:51 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 233364 kb
Host smart-4a10a770-5187-4885-915c-272f03ccad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621841523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1621841523
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.631492724
Short name T590
Test name
Test status
Simulation time 194737446 ps
CPU time 3.57 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:54:01 PM PDT 24
Peak memory 223712 kb
Host smart-0be6bd20-ec67-405b-b00b-244402ff3b00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=631492724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.631492724
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.516736701
Short name T822
Test name
Test status
Simulation time 10622290230 ps
CPU time 31.69 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:54:25 PM PDT 24
Peak memory 217096 kb
Host smart-5b7703c9-bd3a-44ec-97bc-4a047df655c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516736701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.516736701
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.953350733
Short name T1015
Test name
Test status
Simulation time 2001044337 ps
CPU time 6.91 seconds
Started Aug 04 04:53:53 PM PDT 24
Finished Aug 04 04:54:00 PM PDT 24
Peak memory 216840 kb
Host smart-b6512713-401c-48b2-b2d3-5ed0288e3ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953350733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.953350733
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3415531878
Short name T490
Test name
Test status
Simulation time 80578222 ps
CPU time 1.02 seconds
Started Aug 04 04:53:52 PM PDT 24
Finished Aug 04 04:53:53 PM PDT 24
Peak memory 207552 kb
Host smart-dac01df5-afbc-4c1c-8371-406f4436296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415531878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3415531878
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1183095661
Short name T697
Test name
Test status
Simulation time 61799008 ps
CPU time 1 seconds
Started Aug 04 04:53:51 PM PDT 24
Finished Aug 04 04:53:52 PM PDT 24
Peak memory 206480 kb
Host smart-3a4d1457-367a-44fa-b22f-5e4e361df43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183095661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1183095661
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3686583694
Short name T1017
Test name
Test status
Simulation time 605812323 ps
CPU time 3.26 seconds
Started Aug 04 04:53:55 PM PDT 24
Finished Aug 04 04:53:59 PM PDT 24
Peak memory 233328 kb
Host smart-7f5c7135-892f-483a-94a8-74dc8ac10d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686583694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3686583694
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.298808532
Short name T669
Test name
Test status
Simulation time 11115600 ps
CPU time 0.69 seconds
Started Aug 04 04:53:59 PM PDT 24
Finished Aug 04 04:54:00 PM PDT 24
Peak memory 205228 kb
Host smart-6db274ec-8015-41b9-ae19-5b40c182d255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298808532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.298808532
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2603656092
Short name T1006
Test name
Test status
Simulation time 326098576 ps
CPU time 2.29 seconds
Started Aug 04 04:53:59 PM PDT 24
Finished Aug 04 04:54:01 PM PDT 24
Peak memory 225148 kb
Host smart-a0e77fe9-b86a-4492-8263-9946a84b5b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603656092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2603656092
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2789683642
Short name T561
Test name
Test status
Simulation time 2729425719 ps
CPU time 27.21 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:54:28 PM PDT 24
Peak memory 241596 kb
Host smart-b4d31a97-ac22-4f59-8fe8-aae04948848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789683642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2789683642
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3291259482
Short name T941
Test name
Test status
Simulation time 1493308240 ps
CPU time 9.93 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:54:11 PM PDT 24
Peak memory 218364 kb
Host smart-a2ccff1d-8d1b-4dc6-a40d-63677efd0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291259482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3291259482
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1698470544
Short name T367
Test name
Test status
Simulation time 4597522582 ps
CPU time 13.39 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:54:11 PM PDT 24
Peak memory 235272 kb
Host smart-47a694bb-58ba-411f-81fe-6b81d912ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698470544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1698470544
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3104800170
Short name T668
Test name
Test status
Simulation time 286682982 ps
CPU time 2.39 seconds
Started Aug 04 04:54:00 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 224304 kb
Host smart-eaee3532-b92b-4f30-9966-ec1901d8b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104800170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3104800170
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2913998490
Short name T998
Test name
Test status
Simulation time 69060724237 ps
CPU time 45.73 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:54:43 PM PDT 24
Peak memory 233424 kb
Host smart-bfe38f31-7f32-4b35-b914-3a94459905cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913998490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2913998490
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3157574284
Short name T46
Test name
Test status
Simulation time 25321117 ps
CPU time 1.06 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 217068 kb
Host smart-87a3f418-e7df-4d7a-8df5-94385739eacf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157574284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3157574284
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3620714585
Short name T789
Test name
Test status
Simulation time 3894162186 ps
CPU time 3.61 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 225244 kb
Host smart-9efbd287-0d00-43e1-a56e-38185e218c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620714585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3620714585
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.677791932
Short name T79
Test name
Test status
Simulation time 4242854777 ps
CPU time 6.27 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:54:04 PM PDT 24
Peak memory 225180 kb
Host smart-6de25aa0-34a5-43aa-a931-423f457dd1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677791932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.677791932
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2089223527
Short name T723
Test name
Test status
Simulation time 775444851 ps
CPU time 3.93 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 222248 kb
Host smart-07c6c6fc-304b-4507-82df-e286eaaef750
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089223527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2089223527
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.493421621
Short name T166
Test name
Test status
Simulation time 793517028134 ps
CPU time 452.8 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 05:01:34 PM PDT 24
Peak memory 273612 kb
Host smart-d1cd28b1-3723-498f-b3a2-045c4dbf9e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493421621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.493421621
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.710848991
Short name T330
Test name
Test status
Simulation time 13651133627 ps
CPU time 36.4 seconds
Started Aug 04 04:53:56 PM PDT 24
Finished Aug 04 04:54:32 PM PDT 24
Peak memory 217020 kb
Host smart-39f5634c-0eac-4534-854e-75ac503fe957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710848991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.710848991
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1920378918
Short name T541
Test name
Test status
Simulation time 186099515 ps
CPU time 1.7 seconds
Started Aug 04 04:53:55 PM PDT 24
Finished Aug 04 04:53:57 PM PDT 24
Peak memory 216700 kb
Host smart-16fe12bb-4498-413b-961a-c5ccf7f303cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920378918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1920378918
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2392579208
Short name T886
Test name
Test status
Simulation time 100234910 ps
CPU time 1.91 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:54:00 PM PDT 24
Peak memory 216888 kb
Host smart-ab66fd2e-327b-4e08-b64a-eb94426ff769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392579208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2392579208
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.649092901
Short name T360
Test name
Test status
Simulation time 97101195 ps
CPU time 0.87 seconds
Started Aug 04 04:53:57 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 206256 kb
Host smart-052ffd80-458e-43bd-9278-9b0a43f01bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649092901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.649092901
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.280022386
Short name T599
Test name
Test status
Simulation time 502141287 ps
CPU time 4.13 seconds
Started Aug 04 04:53:58 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 225132 kb
Host smart-df692a0d-c1cc-4b90-ae4c-f27c261047c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280022386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.280022386
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2910376761
Short name T751
Test name
Test status
Simulation time 33735976 ps
CPU time 0.75 seconds
Started Aug 04 04:54:06 PM PDT 24
Finished Aug 04 04:54:07 PM PDT 24
Peak memory 205788 kb
Host smart-a528363b-a362-4986-9772-5b35426830f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910376761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2910376761
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2702613643
Short name T721
Test name
Test status
Simulation time 2234055948 ps
CPU time 6.78 seconds
Started Aug 04 04:54:09 PM PDT 24
Finished Aug 04 04:54:16 PM PDT 24
Peak memory 233360 kb
Host smart-8739af32-88de-4a03-bd2d-7296524b1b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702613643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2702613643
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1551755035
Short name T428
Test name
Test status
Simulation time 27252733 ps
CPU time 0.78 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 207444 kb
Host smart-6e9a2b8a-a332-481c-bed4-5ae1e10967e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551755035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1551755035
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2674296743
Short name T40
Test name
Test status
Simulation time 12810770926 ps
CPU time 33.49 seconds
Started Aug 04 04:54:04 PM PDT 24
Finished Aug 04 04:54:38 PM PDT 24
Peak memory 225292 kb
Host smart-e5c8003c-1a46-4e97-b2e9-52e50fc357e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674296743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2674296743
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2710356440
Short name T321
Test name
Test status
Simulation time 4196358240 ps
CPU time 12.69 seconds
Started Aug 04 04:54:05 PM PDT 24
Finished Aug 04 04:54:18 PM PDT 24
Peak memory 225224 kb
Host smart-fee3776a-5bb3-4af6-b78d-cba11d6f0ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710356440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2710356440
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2361160248
Short name T342
Test name
Test status
Simulation time 480344165 ps
CPU time 0.95 seconds
Started Aug 04 04:54:03 PM PDT 24
Finished Aug 04 04:54:04 PM PDT 24
Peak memory 216596 kb
Host smart-648bdd93-76a5-4b73-80d6-d7963bf458da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361160248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2361160248
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3659986611
Short name T596
Test name
Test status
Simulation time 398211499 ps
CPU time 4.75 seconds
Started Aug 04 04:54:02 PM PDT 24
Finished Aug 04 04:54:07 PM PDT 24
Peak memory 225300 kb
Host smart-55e1ed52-1099-4a55-9259-efd246385d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659986611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3659986611
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4247816490
Short name T821
Test name
Test status
Simulation time 4229203729 ps
CPU time 17.48 seconds
Started Aug 04 04:54:09 PM PDT 24
Finished Aug 04 04:54:27 PM PDT 24
Peak memory 233368 kb
Host smart-92562374-8247-4b63-82a3-9581e7e260fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247816490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4247816490
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.937366764
Short name T559
Test name
Test status
Simulation time 30055827 ps
CPU time 1.2 seconds
Started Aug 04 04:54:00 PM PDT 24
Finished Aug 04 04:54:01 PM PDT 24
Peak memory 217128 kb
Host smart-9f48f08e-38b1-4020-8480-dee80dbfe6de
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937366764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.937366764
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1286507299
Short name T9
Test name
Test status
Simulation time 2338847286 ps
CPU time 4.81 seconds
Started Aug 04 04:54:02 PM PDT 24
Finished Aug 04 04:54:07 PM PDT 24
Peak memory 225208 kb
Host smart-b2a92662-0f69-4022-b2bf-dec29fd953fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286507299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1286507299
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1644255780
Short name T832
Test name
Test status
Simulation time 16361015934 ps
CPU time 17.45 seconds
Started Aug 04 04:54:00 PM PDT 24
Finished Aug 04 04:54:18 PM PDT 24
Peak memory 233428 kb
Host smart-309261b3-55ce-4fd0-a385-c45fbede7298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644255780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1644255780
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1831360593
Short name T578
Test name
Test status
Simulation time 156780168 ps
CPU time 3.87 seconds
Started Aug 04 04:54:05 PM PDT 24
Finished Aug 04 04:54:09 PM PDT 24
Peak memory 221444 kb
Host smart-c6900bc3-2cfd-416f-9161-791d3284debb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831360593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1831360593
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2951942377
Short name T686
Test name
Test status
Simulation time 26973955058 ps
CPU time 157.79 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:56:49 PM PDT 24
Peak memory 249856 kb
Host smart-ebfbacd0-ba33-4dbf-90e8-2bfe918009fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951942377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2951942377
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2291604402
Short name T422
Test name
Test status
Simulation time 1422391318 ps
CPU time 24.94 seconds
Started Aug 04 04:54:02 PM PDT 24
Finished Aug 04 04:54:27 PM PDT 24
Peak memory 217056 kb
Host smart-dccb345c-616d-4889-b2db-15b50cde62f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291604402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2291604402
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2549720243
Short name T670
Test name
Test status
Simulation time 426073150 ps
CPU time 1.55 seconds
Started Aug 04 04:54:02 PM PDT 24
Finished Aug 04 04:54:03 PM PDT 24
Peak memory 208564 kb
Host smart-6b70f689-44fc-481c-baa6-b47adc7833b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549720243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2549720243
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2133841202
Short name T892
Test name
Test status
Simulation time 36393053 ps
CPU time 1.08 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 207544 kb
Host smart-077bff2b-f75d-4b9a-8139-a79da62e5c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133841202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2133841202
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1815524137
Short name T87
Test name
Test status
Simulation time 44475857 ps
CPU time 0.86 seconds
Started Aug 04 04:54:01 PM PDT 24
Finished Aug 04 04:54:02 PM PDT 24
Peak memory 206476 kb
Host smart-520f44b1-4f24-4faa-83b6-01da371b98dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815524137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1815524137
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3120055772
Short name T1009
Test name
Test status
Simulation time 201135319 ps
CPU time 2.35 seconds
Started Aug 04 04:54:02 PM PDT 24
Finished Aug 04 04:54:04 PM PDT 24
Peak memory 223740 kb
Host smart-8697e377-7bc3-47c8-a894-136164667e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120055772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3120055772
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2170486862
Short name T929
Test name
Test status
Simulation time 11833830 ps
CPU time 0.77 seconds
Started Aug 04 04:54:13 PM PDT 24
Finished Aug 04 04:54:14 PM PDT 24
Peak memory 205512 kb
Host smart-d7083369-699f-44b2-9d66-137ba058fa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170486862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2170486862
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2205203110
Short name T783
Test name
Test status
Simulation time 84914410 ps
CPU time 2.8 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:54:13 PM PDT 24
Peak memory 225108 kb
Host smart-064edaad-cb3b-4d43-a587-28c6c4c9a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205203110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2205203110
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4076672825
Short name T849
Test name
Test status
Simulation time 27717966 ps
CPU time 0.81 seconds
Started Aug 04 04:54:09 PM PDT 24
Finished Aug 04 04:54:10 PM PDT 24
Peak memory 206948 kb
Host smart-d0ab9af9-8346-495c-be85-c2b54bf1a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076672825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4076672825
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.577709433
Short name T238
Test name
Test status
Simulation time 13739920681 ps
CPU time 66 seconds
Started Aug 04 04:54:12 PM PDT 24
Finished Aug 04 04:55:18 PM PDT 24
Peak memory 249776 kb
Host smart-678192fe-8148-4a20-95d1-82ebf0bcbc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577709433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.577709433
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2436082860
Short name T813
Test name
Test status
Simulation time 72300441699 ps
CPU time 125.19 seconds
Started Aug 04 04:54:14 PM PDT 24
Finished Aug 04 04:56:19 PM PDT 24
Peak memory 239224 kb
Host smart-749f7c1a-0293-428b-864b-3bed37213814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436082860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2436082860
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2336882814
Short name T738
Test name
Test status
Simulation time 1064559950 ps
CPU time 22.81 seconds
Started Aug 04 04:54:13 PM PDT 24
Finished Aug 04 04:54:36 PM PDT 24
Peak memory 241636 kb
Host smart-77464c08-5720-4b73-9c19-07b14b10d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336882814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2336882814
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2608054749
Short name T554
Test name
Test status
Simulation time 467600437 ps
CPU time 10.58 seconds
Started Aug 04 04:54:13 PM PDT 24
Finished Aug 04 04:54:23 PM PDT 24
Peak memory 233488 kb
Host smart-910ba2a7-c27b-4c01-ab94-c6d4c80907ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608054749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2608054749
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.4010861581
Short name T292
Test name
Test status
Simulation time 8619894717 ps
CPU time 46.58 seconds
Started Aug 04 04:54:13 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 252884 kb
Host smart-995f9943-184e-4fb8-b156-ed76d7038ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010861581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.4010861581
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2032514326
Short name T696
Test name
Test status
Simulation time 456419279 ps
CPU time 6.31 seconds
Started Aug 04 04:54:08 PM PDT 24
Finished Aug 04 04:54:15 PM PDT 24
Peak memory 225148 kb
Host smart-2b4f07e9-21ac-413e-bfe2-124e3b605a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032514326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2032514326
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.777186287
Short name T673
Test name
Test status
Simulation time 6910127814 ps
CPU time 17.4 seconds
Started Aug 04 04:54:08 PM PDT 24
Finished Aug 04 04:54:26 PM PDT 24
Peak memory 233404 kb
Host smart-785321db-5631-4ff6-ba1b-3b48e3f39d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777186287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.777186287
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2035371135
Short name T176
Test name
Test status
Simulation time 60938075 ps
CPU time 1.1 seconds
Started Aug 04 04:54:04 PM PDT 24
Finished Aug 04 04:54:05 PM PDT 24
Peak memory 217252 kb
Host smart-25611e09-22d3-4f85-a37a-bf301322a14d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035371135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2035371135
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2702110808
Short name T1024
Test name
Test status
Simulation time 3099080731 ps
CPU time 3.46 seconds
Started Aug 04 04:54:09 PM PDT 24
Finished Aug 04 04:54:13 PM PDT 24
Peak memory 233432 kb
Host smart-c3b920d7-4a27-4e86-8912-4e2d1f44c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702110808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2702110808
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.426284621
Short name T662
Test name
Test status
Simulation time 5686532655 ps
CPU time 6.91 seconds
Started Aug 04 04:54:10 PM PDT 24
Finished Aug 04 04:54:17 PM PDT 24
Peak memory 225252 kb
Host smart-445600b4-e138-40f5-a522-2f5d7d301eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426284621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.426284621
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4062631952
Short name T527
Test name
Test status
Simulation time 9456839784 ps
CPU time 11.79 seconds
Started Aug 04 04:54:12 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 221164 kb
Host smart-6ebc207a-a2b8-4e02-a8e0-042f0fc31e68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4062631952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4062631952
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1480219997
Short name T67
Test name
Test status
Simulation time 8522704704 ps
CPU time 184.02 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:57:15 PM PDT 24
Peak memory 266352 kb
Host smart-45032ebb-93a9-4abe-9eab-d37f18fd17aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480219997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1480219997
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1352183951
Short name T863
Test name
Test status
Simulation time 1322625555 ps
CPU time 7.86 seconds
Started Aug 04 04:54:04 PM PDT 24
Finished Aug 04 04:54:12 PM PDT 24
Peak memory 216872 kb
Host smart-8d99e15a-65af-4e94-935c-9297f7262612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352183951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1352183951
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.629830185
Short name T337
Test name
Test status
Simulation time 53937276 ps
CPU time 0.72 seconds
Started Aug 04 04:54:05 PM PDT 24
Finished Aug 04 04:54:06 PM PDT 24
Peak memory 206096 kb
Host smart-60b4fdec-7e17-49ca-87d7-59f47dcdf24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629830185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.629830185
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4130249521
Short name T880
Test name
Test status
Simulation time 10536944 ps
CPU time 0.7 seconds
Started Aug 04 04:54:08 PM PDT 24
Finished Aug 04 04:54:08 PM PDT 24
Peak memory 206000 kb
Host smart-bd082adb-9310-48c4-b5b2-cd5416ca2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130249521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4130249521
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.617873986
Short name T513
Test name
Test status
Simulation time 115726032 ps
CPU time 0.74 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:54:12 PM PDT 24
Peak memory 206468 kb
Host smart-0cb539e5-d605-4c7b-b204-43457d316773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617873986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.617873986
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.593099319
Short name T881
Test name
Test status
Simulation time 2140670078 ps
CPU time 7.24 seconds
Started Aug 04 04:54:08 PM PDT 24
Finished Aug 04 04:54:15 PM PDT 24
Peak memory 233424 kb
Host smart-da7f48aa-264d-4a89-908b-019905378b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593099319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.593099319
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3624898275
Short name T724
Test name
Test status
Simulation time 28999217 ps
CPU time 0.67 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 04:54:20 PM PDT 24
Peak memory 205328 kb
Host smart-20feee4a-c1d8-4255-80a3-023ac43dbedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624898275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3624898275
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.826842772
Short name T58
Test name
Test status
Simulation time 3717639452 ps
CPU time 8.92 seconds
Started Aug 04 04:54:15 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 233556 kb
Host smart-293e315d-b869-4be0-a6ab-1d04afea9430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826842772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.826842772
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.430344192
Short name T542
Test name
Test status
Simulation time 23067086 ps
CPU time 0.82 seconds
Started Aug 04 04:54:12 PM PDT 24
Finished Aug 04 04:54:12 PM PDT 24
Peak memory 206920 kb
Host smart-768928f0-d6c4-40bf-85de-5472285437de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430344192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.430344192
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2965967353
Short name T274
Test name
Test status
Simulation time 35037596832 ps
CPU time 240.25 seconds
Started Aug 04 04:54:18 PM PDT 24
Finished Aug 04 04:58:19 PM PDT 24
Peak memory 258048 kb
Host smart-12f52750-0f4b-4815-8a36-8590eb60f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965967353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2965967353
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3817428607
Short name T73
Test name
Test status
Simulation time 17076861871 ps
CPU time 113.14 seconds
Started Aug 04 04:54:22 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 233588 kb
Host smart-33d86546-7b80-462c-aee1-b371e8b5e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817428607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3817428607
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1123619595
Short name T148
Test name
Test status
Simulation time 24851901967 ps
CPU time 156.73 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 04:56:56 PM PDT 24
Peak memory 254972 kb
Host smart-8263bc3b-af36-45f8-9a19-5021c71c6e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123619595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1123619595
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1340129846
Short name T512
Test name
Test status
Simulation time 290467169 ps
CPU time 7.64 seconds
Started Aug 04 04:54:16 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 225176 kb
Host smart-5e4012f7-5a2a-4266-a652-2fd74df0410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340129846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1340129846
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1662759773
Short name T192
Test name
Test status
Simulation time 21259332845 ps
CPU time 114.27 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 04:56:14 PM PDT 24
Peak memory 256964 kb
Host smart-b1f80ad5-ef27-44d4-a699-db9dcf8ecb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662759773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1662759773
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.313574858
Short name T683
Test name
Test status
Simulation time 217436862 ps
CPU time 2.83 seconds
Started Aug 04 04:54:14 PM PDT 24
Finished Aug 04 04:54:17 PM PDT 24
Peak memory 225280 kb
Host smart-e89642f5-e35b-4ce9-a5dc-3285232d2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313574858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.313574858
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1952744830
Short name T460
Test name
Test status
Simulation time 53173421 ps
CPU time 2.67 seconds
Started Aug 04 04:54:15 PM PDT 24
Finished Aug 04 04:54:17 PM PDT 24
Peak memory 233048 kb
Host smart-63e53ff5-0a4a-4555-b954-fc173e010c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952744830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1952744830
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3420639175
Short name T44
Test name
Test status
Simulation time 62949664 ps
CPU time 1.09 seconds
Started Aug 04 04:54:12 PM PDT 24
Finished Aug 04 04:54:13 PM PDT 24
Peak memory 218480 kb
Host smart-ff179fcd-9440-4ea1-82b0-d81f744fcb76
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420639175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3420639175
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1629244645
Short name T218
Test name
Test status
Simulation time 19985664747 ps
CPU time 32.27 seconds
Started Aug 04 04:54:15 PM PDT 24
Finished Aug 04 04:54:48 PM PDT 24
Peak memory 241636 kb
Host smart-bacfe8df-f73b-4c40-8bd9-a181ea1e2f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629244645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1629244645
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2109215638
Short name T776
Test name
Test status
Simulation time 2661434233 ps
CPU time 3 seconds
Started Aug 04 04:54:15 PM PDT 24
Finished Aug 04 04:54:18 PM PDT 24
Peak memory 233492 kb
Host smart-08c2c545-0c46-4480-8bdd-12dd255ceacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109215638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2109215638
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3873793200
Short name T402
Test name
Test status
Simulation time 440107377 ps
CPU time 4.38 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 04:54:23 PM PDT 24
Peak memory 223212 kb
Host smart-f4871eca-a8dc-40d7-ba11-23f2904262cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873793200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3873793200
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3153866596
Short name T744
Test name
Test status
Simulation time 6357329706 ps
CPU time 31.55 seconds
Started Aug 04 04:54:13 PM PDT 24
Finished Aug 04 04:54:44 PM PDT 24
Peak memory 220628 kb
Host smart-c582f996-2a59-4157-8556-03573be34c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153866596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3153866596
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1230280788
Short name T434
Test name
Test status
Simulation time 5874582823 ps
CPU time 4.55 seconds
Started Aug 04 04:54:11 PM PDT 24
Finished Aug 04 04:54:16 PM PDT 24
Peak memory 216912 kb
Host smart-394ec239-0afc-4f58-8fb2-3119dce37b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230280788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1230280788
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.265318658
Short name T1005
Test name
Test status
Simulation time 121708797 ps
CPU time 3.71 seconds
Started Aug 04 04:54:14 PM PDT 24
Finished Aug 04 04:54:18 PM PDT 24
Peak memory 216928 kb
Host smart-4b6c9442-f6b7-436b-bc51-561f6db56128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265318658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.265318658
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2320933302
Short name T716
Test name
Test status
Simulation time 302110841 ps
CPU time 0.89 seconds
Started Aug 04 04:54:14 PM PDT 24
Finished Aug 04 04:54:15 PM PDT 24
Peak memory 206604 kb
Host smart-82862b63-dce0-4fd7-8bdd-bfd34ddc5dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320933302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2320933302
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2627153995
Short name T253
Test name
Test status
Simulation time 15202993473 ps
CPU time 16.22 seconds
Started Aug 04 04:54:16 PM PDT 24
Finished Aug 04 04:54:32 PM PDT 24
Peak memory 233472 kb
Host smart-3f5db7ba-28b5-4039-8343-9f9d44c382ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627153995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2627153995
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1334824047
Short name T920
Test name
Test status
Simulation time 10563878 ps
CPU time 0.74 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:54:25 PM PDT 24
Peak memory 205184 kb
Host smart-551b326a-76be-45dd-b784-653f3854403b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334824047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1334824047
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2423297774
Short name T826
Test name
Test status
Simulation time 512598427 ps
CPU time 8.87 seconds
Started Aug 04 04:54:21 PM PDT 24
Finished Aug 04 04:54:30 PM PDT 24
Peak memory 233304 kb
Host smart-a645a183-e499-4a46-912d-1d7c9d773829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423297774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2423297774
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2328415531
Short name T910
Test name
Test status
Simulation time 47047907 ps
CPU time 0.79 seconds
Started Aug 04 04:54:17 PM PDT 24
Finished Aug 04 04:54:17 PM PDT 24
Peak memory 206020 kb
Host smart-d1a4fc83-7293-4a94-964a-e23e19951a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328415531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2328415531
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1858498097
Short name T587
Test name
Test status
Simulation time 106804706209 ps
CPU time 183.93 seconds
Started Aug 04 04:54:24 PM PDT 24
Finished Aug 04 04:57:28 PM PDT 24
Peak memory 251228 kb
Host smart-ccf61875-240a-4d1d-8258-af8e1e6a93ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858498097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1858498097
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1051919742
Short name T643
Test name
Test status
Simulation time 10560834643 ps
CPU time 109.77 seconds
Started Aug 04 04:54:34 PM PDT 24
Finished Aug 04 04:56:24 PM PDT 24
Peak memory 258032 kb
Host smart-a6719986-1a7c-407f-b488-dacb691ebf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051919742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1051919742
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1541191726
Short name T511
Test name
Test status
Simulation time 58164457 ps
CPU time 3.01 seconds
Started Aug 04 04:54:23 PM PDT 24
Finished Aug 04 04:54:26 PM PDT 24
Peak memory 233400 kb
Host smart-e5c6cd04-df00-4fb4-a3d5-14c266d3ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541191726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1541191726
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.9445095
Short name T955
Test name
Test status
Simulation time 1765477689 ps
CPU time 17.25 seconds
Started Aug 04 04:54:23 PM PDT 24
Finished Aug 04 04:54:40 PM PDT 24
Peak memory 241660 kb
Host smart-86221ccf-dc8e-467f-bc3c-902c96bd20c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9445095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.9445095
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2978251673
Short name T607
Test name
Test status
Simulation time 695004443 ps
CPU time 4.04 seconds
Started Aug 04 04:54:20 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 233476 kb
Host smart-ddfdabb9-367d-4b3b-b1f5-072f3da98ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978251673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2978251673
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3050085401
Short name T544
Test name
Test status
Simulation time 30752547819 ps
CPU time 81.64 seconds
Started Aug 04 04:54:22 PM PDT 24
Finished Aug 04 04:55:43 PM PDT 24
Peak memory 233336 kb
Host smart-3e6920c4-bb58-43f4-9405-8ec117ddd125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050085401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3050085401
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3728018075
Short name T984
Test name
Test status
Simulation time 16702370 ps
CPU time 1.03 seconds
Started Aug 04 04:54:20 PM PDT 24
Finished Aug 04 04:54:21 PM PDT 24
Peak memory 218460 kb
Host smart-cb8e067f-880e-44e7-9859-578c5402022f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728018075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3728018075
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2352915332
Short name T506
Test name
Test status
Simulation time 35629861 ps
CPU time 2.68 seconds
Started Aug 04 04:54:22 PM PDT 24
Finished Aug 04 04:54:25 PM PDT 24
Peak memory 232976 kb
Host smart-dd75bacc-3ce7-4ef2-be08-b906de03dee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352915332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2352915332
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1490604253
Short name T679
Test name
Test status
Simulation time 165289861 ps
CPU time 2.32 seconds
Started Aug 04 04:54:22 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 224440 kb
Host smart-9a5f4d91-a59c-4e9c-9d2a-8f9d5e2a95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490604253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1490604253
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1539764173
Short name T436
Test name
Test status
Simulation time 15267444032 ps
CPU time 8.23 seconds
Started Aug 04 04:54:20 PM PDT 24
Finished Aug 04 04:54:28 PM PDT 24
Peak memory 217044 kb
Host smart-0eebf107-de51-487b-b5b3-10f708c96bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539764173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1539764173
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1765435884
Short name T487
Test name
Test status
Simulation time 1987941729 ps
CPU time 3.93 seconds
Started Aug 04 04:54:22 PM PDT 24
Finished Aug 04 04:54:26 PM PDT 24
Peak memory 216908 kb
Host smart-df17c927-37dd-4e35-92ef-fab5e3c2e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765435884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1765435884
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.789888805
Short name T491
Test name
Test status
Simulation time 44960201 ps
CPU time 1.32 seconds
Started Aug 04 04:54:20 PM PDT 24
Finished Aug 04 04:54:22 PM PDT 24
Peak memory 208744 kb
Host smart-936e9068-57f8-4596-b4ad-2d8f5d183b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789888805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.789888805
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2765065103
Short name T651
Test name
Test status
Simulation time 131402727 ps
CPU time 0.79 seconds
Started Aug 04 04:54:19 PM PDT 24
Finished Aug 04 04:54:20 PM PDT 24
Peak memory 206600 kb
Host smart-a31e0f9b-8127-4733-af5d-6efcc44aca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765065103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2765065103
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3235732954
Short name T904
Test name
Test status
Simulation time 27795275871 ps
CPU time 14.5 seconds
Started Aug 04 04:54:24 PM PDT 24
Finished Aug 04 04:54:39 PM PDT 24
Peak memory 228396 kb
Host smart-63e65932-a5f1-4054-be9a-0e0e47a22c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235732954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3235732954
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.583957004
Short name T349
Test name
Test status
Simulation time 134728305 ps
CPU time 0.76 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 205760 kb
Host smart-a2bbf8be-68f1-4fbb-921e-9334f734a43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583957004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.583957004
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3869354152
Short name T657
Test name
Test status
Simulation time 38521079 ps
CPU time 2.44 seconds
Started Aug 04 04:54:30 PM PDT 24
Finished Aug 04 04:54:32 PM PDT 24
Peak memory 233356 kb
Host smart-077bfaf0-75f2-413c-8698-3f87bb0a01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869354152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3869354152
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1358028300
Short name T538
Test name
Test status
Simulation time 102016811 ps
CPU time 0.75 seconds
Started Aug 04 04:54:28 PM PDT 24
Finished Aug 04 04:54:29 PM PDT 24
Peak memory 205992 kb
Host smart-a40ef6e7-cd7a-43aa-9320-832330ace4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358028300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1358028300
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1483264219
Short name T1010
Test name
Test status
Simulation time 41412873311 ps
CPU time 147.63 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:57:04 PM PDT 24
Peak memory 256608 kb
Host smart-edb50fb3-5186-4c8d-87a3-81d64b87e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483264219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1483264219
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2842631478
Short name T851
Test name
Test status
Simulation time 16938109160 ps
CPU time 114.83 seconds
Started Aug 04 04:54:37 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 252860 kb
Host smart-6506e7db-1ee6-4edf-9af6-a6a41d3f1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842631478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2842631478
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2934811183
Short name T979
Test name
Test status
Simulation time 19413879972 ps
CPU time 72.89 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:55:51 PM PDT 24
Peak memory 241640 kb
Host smart-ba3f6e99-3a7a-4ae2-9884-4bdb61b8d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934811183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2934811183
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3445786458
Short name T320
Test name
Test status
Simulation time 317553050 ps
CPU time 6.78 seconds
Started Aug 04 04:54:29 PM PDT 24
Finished Aug 04 04:54:35 PM PDT 24
Peak memory 241324 kb
Host smart-405a08b6-ee88-49b4-958e-a13bcb53461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445786458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3445786458
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2505544320
Short name T212
Test name
Test status
Simulation time 62321290049 ps
CPU time 224.25 seconds
Started Aug 04 04:54:32 PM PDT 24
Finished Aug 04 04:58:16 PM PDT 24
Peak memory 250920 kb
Host smart-ff039759-7b67-4779-8b06-3e1099ba0765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505544320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2505544320
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2538544764
Short name T472
Test name
Test status
Simulation time 11185016603 ps
CPU time 12.11 seconds
Started Aug 04 04:54:24 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 225492 kb
Host smart-03571cd6-ef58-4623-b419-5b73de6016e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538544764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2538544764
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.114164859
Short name T905
Test name
Test status
Simulation time 1987905756 ps
CPU time 13.74 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:54:39 PM PDT 24
Peak memory 240752 kb
Host smart-c8659dd3-aa32-468a-93e6-22830634a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114164859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.114164859
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2074227728
Short name T1011
Test name
Test status
Simulation time 62506452 ps
CPU time 1.1 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:54:26 PM PDT 24
Peak memory 217148 kb
Host smart-cee15d09-7e2c-49d5-ac85-de8b32bdbe28
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074227728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2074227728
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.938325263
Short name T397
Test name
Test status
Simulation time 5052611689 ps
CPU time 16.19 seconds
Started Aug 04 04:54:26 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 225180 kb
Host smart-bd3cef67-aaa5-44cc-97c2-33fdbbb61138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938325263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.938325263
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3039567480
Short name T616
Test name
Test status
Simulation time 1216152845 ps
CPU time 6.21 seconds
Started Aug 04 04:54:27 PM PDT 24
Finished Aug 04 04:54:33 PM PDT 24
Peak memory 240384 kb
Host smart-f180ee6a-b254-43e4-a87d-76dd0b477fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039567480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3039567480
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3722821295
Short name T884
Test name
Test status
Simulation time 1206957690 ps
CPU time 13.69 seconds
Started Aug 04 04:54:31 PM PDT 24
Finished Aug 04 04:54:44 PM PDT 24
Peak memory 222956 kb
Host smart-72766070-803e-4159-9274-d44752faf8b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722821295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3722821295
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.971028606
Short name T17
Test name
Test status
Simulation time 26265140487 ps
CPU time 137.35 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 253076 kb
Host smart-c738089f-925c-47ed-80db-6762c201e2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971028606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.971028606
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1212235062
Short name T771
Test name
Test status
Simulation time 2853491176 ps
CPU time 18.72 seconds
Started Aug 04 04:54:25 PM PDT 24
Finished Aug 04 04:54:43 PM PDT 24
Peak memory 217012 kb
Host smart-ce8eedf4-e4b7-467e-bbcb-db4e8163a41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212235062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1212235062
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.830293407
Short name T351
Test name
Test status
Simulation time 3329796634 ps
CPU time 12.36 seconds
Started Aug 04 04:54:24 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 217076 kb
Host smart-180e621f-d63a-4e57-8fd8-117b9073ca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830293407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.830293407
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.876196109
Short name T861
Test name
Test status
Simulation time 200898579 ps
CPU time 2 seconds
Started Aug 04 04:54:24 PM PDT 24
Finished Aug 04 04:54:27 PM PDT 24
Peak memory 216872 kb
Host smart-a8145bbe-6421-43aa-b49f-6ca686e7c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876196109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.876196109
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.569466502
Short name T350
Test name
Test status
Simulation time 668343259 ps
CPU time 0.93 seconds
Started Aug 04 04:54:27 PM PDT 24
Finished Aug 04 04:54:28 PM PDT 24
Peak memory 207648 kb
Host smart-12ede0a6-7bb3-4629-a5fc-32afc4ba3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569466502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.569466502
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2587346170
Short name T853
Test name
Test status
Simulation time 14938076733 ps
CPU time 16.42 seconds
Started Aug 04 04:54:31 PM PDT 24
Finished Aug 04 04:54:48 PM PDT 24
Peak memory 249828 kb
Host smart-6a64de4c-2a88-4ef4-9968-4690d3f3c826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587346170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2587346170
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.679577738
Short name T2
Test name
Test status
Simulation time 13863181 ps
CPU time 0.71 seconds
Started Aug 04 04:54:40 PM PDT 24
Finished Aug 04 04:54:41 PM PDT 24
Peak memory 205748 kb
Host smart-ff2e18fd-1c5b-4571-af47-c97aaefaf6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679577738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.679577738
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3456004043
Short name T467
Test name
Test status
Simulation time 398543628 ps
CPU time 4.55 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 233620 kb
Host smart-227b72d4-516f-43a2-95be-c396a36da634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456004043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3456004043
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.762130197
Short name T39
Test name
Test status
Simulation time 137393767 ps
CPU time 0.82 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:54:39 PM PDT 24
Peak memory 206040 kb
Host smart-da5af1bc-6c24-42f8-885e-8b5c6e153601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762130197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.762130197
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4107705256
Short name T625
Test name
Test status
Simulation time 1905092180 ps
CPU time 10.86 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:54:49 PM PDT 24
Peak memory 225132 kb
Host smart-cf37e21f-6371-4922-bbd2-a6a44e21fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107705256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4107705256
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2059975780
Short name T275
Test name
Test status
Simulation time 1187165155 ps
CPU time 21.36 seconds
Started Aug 04 04:54:39 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 222272 kb
Host smart-e960bcf1-4383-4922-bd6b-0b1122e6630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059975780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2059975780
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2172332862
Short name T891
Test name
Test status
Simulation time 357085539 ps
CPU time 5.99 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:54:44 PM PDT 24
Peak memory 225060 kb
Host smart-e08c5bb6-d85a-4ea1-80f5-7cd21d96533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172332862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2172332862
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.880176140
Short name T213
Test name
Test status
Simulation time 92896981461 ps
CPU time 199.14 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:57:57 PM PDT 24
Peak memory 258084 kb
Host smart-f7021671-0ac6-4146-b12b-a708c04b0cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880176140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.880176140
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4155734272
Short name T448
Test name
Test status
Simulation time 565136045 ps
CPU time 5.19 seconds
Started Aug 04 04:54:39 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 233324 kb
Host smart-53098db4-9da3-43a3-b650-39051a0ede8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155734272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4155734272
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2675649978
Short name T548
Test name
Test status
Simulation time 1858131833 ps
CPU time 16.92 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:54:53 PM PDT 24
Peak memory 233388 kb
Host smart-5cd6d5f6-684a-4ca9-ac4b-89974b4e8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675649978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2675649978
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2243076727
Short name T45
Test name
Test status
Simulation time 151598055 ps
CPU time 1.11 seconds
Started Aug 04 04:54:37 PM PDT 24
Finished Aug 04 04:54:38 PM PDT 24
Peak memory 217248 kb
Host smart-9abbd3ad-ab26-4548-a3b3-e9421fc3dbbb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243076727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2243076727
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2994978572
Short name T310
Test name
Test status
Simulation time 294773919 ps
CPU time 6.59 seconds
Started Aug 04 04:54:37 PM PDT 24
Finished Aug 04 04:54:44 PM PDT 24
Peak memory 233328 kb
Host smart-ebcce43a-9d42-4d6a-814b-18a8e84fc6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994978572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2994978572
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1590892926
Short name T931
Test name
Test status
Simulation time 415098630 ps
CPU time 3.41 seconds
Started Aug 04 04:54:39 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 228496 kb
Host smart-5e562b54-1fdd-4adb-845b-e8a92186c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590892926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1590892926
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2030110656
Short name T877
Test name
Test status
Simulation time 4821959746 ps
CPU time 12.58 seconds
Started Aug 04 04:54:38 PM PDT 24
Finished Aug 04 04:54:51 PM PDT 24
Peak memory 222580 kb
Host smart-ab546ab7-9b97-4bca-a6b4-ea0ba8e9cb2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030110656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2030110656
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.351661634
Short name T167
Test name
Test status
Simulation time 12707210244 ps
CPU time 64.52 seconds
Started Aug 04 04:54:40 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 250524 kb
Host smart-6a99972c-a419-4f02-a5ea-1a8164eebd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351661634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.351661634
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1097266059
Short name T418
Test name
Test status
Simulation time 36450311 ps
CPU time 0.71 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 206580 kb
Host smart-fbce2eba-9f18-442f-a162-6060ed695383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097266059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1097266059
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4029825412
Short name T653
Test name
Test status
Simulation time 5832927789 ps
CPU time 4.34 seconds
Started Aug 04 04:54:37 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 216972 kb
Host smart-75082afd-acb8-4885-9e97-b79a1b1c75d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029825412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4029825412
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.322032264
Short name T715
Test name
Test status
Simulation time 86052002 ps
CPU time 1.55 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 216980 kb
Host smart-f2ad8e5f-f5be-43a5-bcce-1f958ba30b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322032264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.322032264
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2924570546
Short name T870
Test name
Test status
Simulation time 54551108 ps
CPU time 0.81 seconds
Started Aug 04 04:54:40 PM PDT 24
Finished Aug 04 04:54:41 PM PDT 24
Peak memory 206444 kb
Host smart-06e32ce1-53fc-4c34-aa46-48579bb3e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924570546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2924570546
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3531215084
Short name T435
Test name
Test status
Simulation time 203769504 ps
CPU time 4.91 seconds
Started Aug 04 04:54:36 PM PDT 24
Finished Aug 04 04:54:41 PM PDT 24
Peak memory 239928 kb
Host smart-fc87c3ac-511d-4b30-8285-1a856412bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531215084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3531215084
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2312975691
Short name T775
Test name
Test status
Simulation time 12448027 ps
CPU time 0.75 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 205880 kb
Host smart-063ecd80-6640-4b18-b196-bdd65ebab651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312975691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2312975691
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2276834927
Short name T816
Test name
Test status
Simulation time 176646140 ps
CPU time 2.61 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 225192 kb
Host smart-2b20c19f-ecd6-4d90-925c-73d11e27c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276834927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2276834927
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1623227131
Short name T339
Test name
Test status
Simulation time 18905823 ps
CPU time 0.78 seconds
Started Aug 04 04:54:37 PM PDT 24
Finished Aug 04 04:54:38 PM PDT 24
Peak memory 206932 kb
Host smart-3edca620-904d-4d2b-95a8-c12cf5905cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623227131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1623227131
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4155090431
Short name T488
Test name
Test status
Simulation time 44309897517 ps
CPU time 164.68 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 250988 kb
Host smart-fafd1ee1-486e-425f-b67f-685108c05e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155090431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4155090431
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1082625569
Short name T734
Test name
Test status
Simulation time 41218637890 ps
CPU time 130.8 seconds
Started Aug 04 04:54:40 PM PDT 24
Finished Aug 04 04:56:51 PM PDT 24
Peak memory 262640 kb
Host smart-ad8ae18b-ac51-4efd-b225-0ab8300e110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082625569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1082625569
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3084524417
Short name T936
Test name
Test status
Simulation time 52180375738 ps
CPU time 232.97 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:58:34 PM PDT 24
Peak memory 250044 kb
Host smart-12408e39-c147-4c6c-8669-5bbc7bc50257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084524417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3084524417
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1379887461
Short name T324
Test name
Test status
Simulation time 2011198930 ps
CPU time 31.36 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:55:13 PM PDT 24
Peak memory 233496 kb
Host smart-0368158b-ae9f-4e53-b24c-039ec077bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379887461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1379887461
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3430411796
Short name T5
Test name
Test status
Simulation time 24966311618 ps
CPU time 40.29 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 241724 kb
Host smart-fd3c1c8c-d82a-4c9e-9573-dfe0643725c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430411796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3430411796
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.636157082
Short name T376
Test name
Test status
Simulation time 530144539 ps
CPU time 2.8 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 233032 kb
Host smart-1715ae5d-e301-4f60-b771-51c10aa8cfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636157082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.636157082
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3340203132
Short name T256
Test name
Test status
Simulation time 4863737618 ps
CPU time 38.45 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 233428 kb
Host smart-dee1318e-3957-4e86-bd1f-8fbc3886e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340203132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3340203132
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.202314466
Short name T810
Test name
Test status
Simulation time 110883405 ps
CPU time 1.11 seconds
Started Aug 04 04:54:43 PM PDT 24
Finished Aug 04 04:54:44 PM PDT 24
Peak memory 217116 kb
Host smart-51379882-41ab-44fb-aaca-d5d45d81b1c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202314466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.202314466
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1993561498
Short name T791
Test name
Test status
Simulation time 429693564 ps
CPU time 5.66 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:54:47 PM PDT 24
Peak memory 241068 kb
Host smart-8b4b7aa3-4f4c-4236-b6c2-adbacc0312ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993561498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1993561498
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2712262341
Short name T907
Test name
Test status
Simulation time 156960458 ps
CPU time 2.42 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 232932 kb
Host smart-c321d5be-12c0-480b-845e-35b8f1329a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712262341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2712262341
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1362627823
Short name T845
Test name
Test status
Simulation time 2591637704 ps
CPU time 15.81 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:58 PM PDT 24
Peak memory 221660 kb
Host smart-4a879478-245d-4baa-8d25-1deafe1d864e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1362627823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1362627823
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.122552080
Short name T977
Test name
Test status
Simulation time 4895559761 ps
CPU time 65.45 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 249872 kb
Host smart-4316c7f1-e589-4090-9504-b8b6a4d4c17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122552080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.122552080
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3584371603
Short name T63
Test name
Test status
Simulation time 44599373 ps
CPU time 0.75 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 206444 kb
Host smart-28e49e25-d2bc-4940-b3eb-1f627b626f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584371603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3584371603
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.20295734
Short name T763
Test name
Test status
Simulation time 5229106930 ps
CPU time 4.16 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:54:48 PM PDT 24
Peak memory 218268 kb
Host smart-15310998-2518-4888-a9d4-eb4fcf5eca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20295734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.20295734
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.849344583
Short name T331
Test name
Test status
Simulation time 176303766 ps
CPU time 1.28 seconds
Started Aug 04 04:54:41 PM PDT 24
Finished Aug 04 04:54:43 PM PDT 24
Peak memory 208440 kb
Host smart-5aaa0e7a-c4bd-4c87-bbc3-d9cfa06eae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849344583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.849344583
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3398009004
Short name T77
Test name
Test status
Simulation time 41113639 ps
CPU time 0.79 seconds
Started Aug 04 04:54:42 PM PDT 24
Finished Aug 04 04:54:43 PM PDT 24
Peak memory 206508 kb
Host smart-f4ddbdb9-9031-4a56-8cc5-669c53ab5a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398009004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3398009004
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.94380526
Short name T574
Test name
Test status
Simulation time 12704771483 ps
CPU time 12.03 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:54:57 PM PDT 24
Peak memory 225288 kb
Host smart-2a793668-5812-4cb6-816b-8129c5f22afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94380526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.94380526
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3518971124
Short name T1020
Test name
Test status
Simulation time 31079921 ps
CPU time 0.75 seconds
Started Aug 04 04:52:52 PM PDT 24
Finished Aug 04 04:52:53 PM PDT 24
Peak memory 205860 kb
Host smart-1d097bca-b464-440e-b674-562546e21451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518971124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
518971124
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3372686448
Short name T380
Test name
Test status
Simulation time 34687899 ps
CPU time 2.45 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:52:47 PM PDT 24
Peak memory 232984 kb
Host smart-57cee565-5c1c-44be-9421-0f9005408884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372686448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3372686448
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.902646479
Short name T7
Test name
Test status
Simulation time 15665185 ps
CPU time 0.78 seconds
Started Aug 04 04:52:45 PM PDT 24
Finished Aug 04 04:52:46 PM PDT 24
Peak memory 205968 kb
Host smart-8ca47d1d-197f-4515-a593-5eddb3d22a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902646479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.902646479
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2764437956
Short name T468
Test name
Test status
Simulation time 3802450399 ps
CPU time 35.87 seconds
Started Aug 04 04:52:46 PM PDT 24
Finished Aug 04 04:53:22 PM PDT 24
Peak memory 238820 kb
Host smart-5574bdae-7b8b-4666-9563-c304baa9c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764437956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2764437956
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.336997736
Short name T937
Test name
Test status
Simulation time 87404626605 ps
CPU time 407.51 seconds
Started Aug 04 04:52:49 PM PDT 24
Finished Aug 04 04:59:37 PM PDT 24
Peak memory 263568 kb
Host smart-03aa14ab-fedd-4427-80d4-6c6a4a64720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336997736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.336997736
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2547900670
Short name T307
Test name
Test status
Simulation time 4230901329 ps
CPU time 109.59 seconds
Started Aug 04 04:52:50 PM PDT 24
Finished Aug 04 04:54:40 PM PDT 24
Peak memory 258180 kb
Host smart-88aa7cee-dc76-4441-99c2-fe2ef5bfcba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547900670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2547900670
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2740221650
Short name T154
Test name
Test status
Simulation time 1379354983 ps
CPU time 19.28 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:53:03 PM PDT 24
Peak memory 233424 kb
Host smart-76269b88-f0df-4042-80df-fe7cf0f36ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740221650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2740221650
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.805689910
Short name T240
Test name
Test status
Simulation time 1522938730 ps
CPU time 22.28 seconds
Started Aug 04 04:52:45 PM PDT 24
Finished Aug 04 04:53:07 PM PDT 24
Peak memory 233900 kb
Host smart-7a955fba-ffdd-43fd-98b4-f3c16c8437c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805689910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
805689910
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4129638191
Short name T980
Test name
Test status
Simulation time 965967364 ps
CPU time 3.39 seconds
Started Aug 04 04:52:46 PM PDT 24
Finished Aug 04 04:52:49 PM PDT 24
Peak memory 233516 kb
Host smart-b6f6fee7-26e7-49e3-a81f-791588619d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129638191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4129638191
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1867073046
Short name T265
Test name
Test status
Simulation time 2708278527 ps
CPU time 20.46 seconds
Started Aug 04 04:52:46 PM PDT 24
Finished Aug 04 04:53:07 PM PDT 24
Peak memory 233532 kb
Host smart-247a7957-dcb1-4256-8c70-c04c2d8556e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867073046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1867073046
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4089624185
Short name T425
Test name
Test status
Simulation time 40891295 ps
CPU time 1.05 seconds
Started Aug 04 04:52:41 PM PDT 24
Finished Aug 04 04:52:42 PM PDT 24
Peak memory 217140 kb
Host smart-c405465f-94c1-451b-adf1-d4bfaa6132a9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089624185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4089624185
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2131769399
Short name T987
Test name
Test status
Simulation time 43880336193 ps
CPU time 30.82 seconds
Started Aug 04 04:52:43 PM PDT 24
Finished Aug 04 04:53:14 PM PDT 24
Peak memory 233564 kb
Host smart-7372daf5-72f9-4e2b-81fc-3b8c4dfba858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131769399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2131769399
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3014181182
Short name T612
Test name
Test status
Simulation time 11433973408 ps
CPU time 11.17 seconds
Started Aug 04 04:52:45 PM PDT 24
Finished Aug 04 04:52:56 PM PDT 24
Peak memory 233424 kb
Host smart-7bdea9b7-dabb-4f46-9c3f-2083bb2853d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014181182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3014181182
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3113691257
Short name T682
Test name
Test status
Simulation time 1798922351 ps
CPU time 14.55 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:52:59 PM PDT 24
Peak memory 219808 kb
Host smart-0170cba3-6155-4d6b-a73b-1e520aa64a73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113691257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3113691257
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2062061384
Short name T585
Test name
Test status
Simulation time 493224331 ps
CPU time 6.14 seconds
Started Aug 04 04:52:45 PM PDT 24
Finished Aug 04 04:52:51 PM PDT 24
Peak memory 216924 kb
Host smart-71df7509-3b96-48f0-8e9b-ffa13b462fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062061384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2062061384
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.984173144
Short name T41
Test name
Test status
Simulation time 1174017245 ps
CPU time 5.57 seconds
Started Aug 04 04:52:43 PM PDT 24
Finished Aug 04 04:52:48 PM PDT 24
Peak memory 216856 kb
Host smart-516a3a34-fcf2-44dd-aefd-5056595ff8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984173144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.984173144
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2864700154
Short name T758
Test name
Test status
Simulation time 195856607 ps
CPU time 1.35 seconds
Started Aug 04 04:52:44 PM PDT 24
Finished Aug 04 04:52:45 PM PDT 24
Peak memory 217064 kb
Host smart-9c9baa1e-9b0e-4bab-a693-c36f1fd6cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864700154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2864700154
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1516109532
Short name T451
Test name
Test status
Simulation time 57430656 ps
CPU time 0.83 seconds
Started Aug 04 04:52:41 PM PDT 24
Finished Aug 04 04:52:42 PM PDT 24
Peak memory 206496 kb
Host smart-c3ae3ec6-35bf-4a79-baca-3cd5646c5190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516109532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1516109532
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1145126383
Short name T250
Test name
Test status
Simulation time 413953906 ps
CPU time 2.41 seconds
Started Aug 04 04:52:46 PM PDT 24
Finished Aug 04 04:52:49 PM PDT 24
Peak memory 225188 kb
Host smart-a48d164b-792b-4c88-b86d-31c471f8a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145126383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1145126383
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3344806846
Short name T614
Test name
Test status
Simulation time 36469904 ps
CPU time 0.72 seconds
Started Aug 04 04:54:46 PM PDT 24
Finished Aug 04 04:54:47 PM PDT 24
Peak memory 205220 kb
Host smart-9e4f07f9-53c3-4379-bbce-d64833c7b4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344806846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3344806846
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1137763533
Short name T346
Test name
Test status
Simulation time 20362929 ps
CPU time 0.78 seconds
Started Aug 04 04:54:51 PM PDT 24
Finished Aug 04 04:54:52 PM PDT 24
Peak memory 206984 kb
Host smart-afed4ffc-c887-45f2-9bf6-8e220450e37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137763533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1137763533
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3979121294
Short name T177
Test name
Test status
Simulation time 856146472 ps
CPU time 16.4 seconds
Started Aug 04 04:54:59 PM PDT 24
Finished Aug 04 04:55:15 PM PDT 24
Peak memory 241592 kb
Host smart-c9074d4f-5632-47c4-881c-2e8f81519a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979121294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3979121294
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2680791772
Short name T1026
Test name
Test status
Simulation time 34551449955 ps
CPU time 231.28 seconds
Started Aug 04 04:54:59 PM PDT 24
Finished Aug 04 04:58:50 PM PDT 24
Peak memory 255764 kb
Host smart-9044aab1-4bd0-43aa-9111-3e4c3bebd8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680791772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2680791772
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1685106821
Short name T444
Test name
Test status
Simulation time 89860676304 ps
CPU time 213.25 seconds
Started Aug 04 04:54:51 PM PDT 24
Finished Aug 04 04:58:24 PM PDT 24
Peak memory 249832 kb
Host smart-3efe4a5c-c2dc-4920-8928-f03063f21460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685106821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1685106821
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3085340824
Short name T664
Test name
Test status
Simulation time 625155958 ps
CPU time 9.45 seconds
Started Aug 04 04:54:50 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 234696 kb
Host smart-bc339e3b-6051-4000-97ac-249e51fdb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085340824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3085340824
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.714069924
Short name T918
Test name
Test status
Simulation time 125118099 ps
CPU time 2.16 seconds
Started Aug 04 04:54:50 PM PDT 24
Finished Aug 04 04:54:53 PM PDT 24
Peak memory 224496 kb
Host smart-f975ec2f-1419-46c3-a049-7e6ac29441ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714069924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.714069924
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.955782660
Short name T93
Test name
Test status
Simulation time 8392422804 ps
CPU time 51.5 seconds
Started Aug 04 04:54:46 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 249600 kb
Host smart-6b8c0c5e-c29d-48bb-bf6a-ded5b0826ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955782660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.955782660
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3026846045
Short name T24
Test name
Test status
Simulation time 12835510561 ps
CPU time 14.67 seconds
Started Aug 04 04:54:51 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 240996 kb
Host smart-b64dd488-aaf6-47ba-a22d-31b91d3cdbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026846045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3026846045
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.98876063
Short name T392
Test name
Test status
Simulation time 2115122938 ps
CPU time 8.99 seconds
Started Aug 04 04:54:46 PM PDT 24
Finished Aug 04 04:54:55 PM PDT 24
Peak memory 233432 kb
Host smart-00e478bc-4bbe-4699-b65f-29f3154d97e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98876063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.98876063
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.171489496
Short name T1030
Test name
Test status
Simulation time 1853501253 ps
CPU time 6.51 seconds
Started Aug 04 04:54:59 PM PDT 24
Finished Aug 04 04:55:05 PM PDT 24
Peak memory 219988 kb
Host smart-df3b1777-a9bd-4c67-aab4-e7bc7bfd02d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=171489496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.171489496
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2881714900
Short name T304
Test name
Test status
Simulation time 334306020165 ps
CPU time 501.26 seconds
Started Aug 04 04:54:47 PM PDT 24
Finished Aug 04 05:03:08 PM PDT 24
Peak memory 274108 kb
Host smart-27202950-9e37-43c2-ab04-46f00a8198e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881714900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2881714900
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3670037516
Short name T484
Test name
Test status
Simulation time 2858027866 ps
CPU time 8.07 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:54:52 PM PDT 24
Peak memory 217136 kb
Host smart-9a2b9fe7-3d5f-4e50-a957-a81138ecda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670037516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3670037516
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.400556586
Short name T953
Test name
Test status
Simulation time 2757203854 ps
CPU time 9.33 seconds
Started Aug 04 04:54:46 PM PDT 24
Finished Aug 04 04:54:56 PM PDT 24
Peak memory 216924 kb
Host smart-cb8c7f27-90e9-48b2-84bb-3e25f1058101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400556586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.400556586
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3631152562
Short name T970
Test name
Test status
Simulation time 399601132 ps
CPU time 3.4 seconds
Started Aug 04 04:54:44 PM PDT 24
Finished Aug 04 04:54:47 PM PDT 24
Peak memory 216856 kb
Host smart-a9b8a2ca-b8f3-4dd4-b8df-1c0a1d878c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631152562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3631152562
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3748329132
Short name T514
Test name
Test status
Simulation time 108411366 ps
CPU time 1.04 seconds
Started Aug 04 04:54:45 PM PDT 24
Finished Aug 04 04:54:46 PM PDT 24
Peak memory 207532 kb
Host smart-be6a4690-d408-4f84-9268-00f3915ec048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748329132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3748329132
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.493342708
Short name T630
Test name
Test status
Simulation time 15890852058 ps
CPU time 28.65 seconds
Started Aug 04 04:54:45 PM PDT 24
Finished Aug 04 04:55:14 PM PDT 24
Peak memory 235916 kb
Host smart-ae42be61-a79e-4c84-8fe2-1092f87d8d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493342708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.493342708
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3448428146
Short name T690
Test name
Test status
Simulation time 15165340 ps
CPU time 0.79 seconds
Started Aug 04 04:54:55 PM PDT 24
Finished Aug 04 04:54:56 PM PDT 24
Peak memory 205332 kb
Host smart-0d233e29-3e67-4408-878e-4813b7fba15f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448428146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3448428146
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.983086468
Short name T90
Test name
Test status
Simulation time 142608005 ps
CPU time 2.52 seconds
Started Aug 04 04:54:51 PM PDT 24
Finished Aug 04 04:54:53 PM PDT 24
Peak memory 225160 kb
Host smart-d9944795-a8fe-4c8a-907e-dee40084aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983086468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.983086468
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.448012528
Short name T403
Test name
Test status
Simulation time 127397634 ps
CPU time 0.8 seconds
Started Aug 04 04:54:47 PM PDT 24
Finished Aug 04 04:54:48 PM PDT 24
Peak memory 207044 kb
Host smart-e5adc34f-639e-41f5-a4c3-9eb70da7f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448012528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.448012528
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.962382291
Short name T174
Test name
Test status
Simulation time 2313702322 ps
CPU time 51.28 seconds
Started Aug 04 04:54:55 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 256672 kb
Host smart-f5867b95-0cd6-4af0-80e3-80a0fd5c8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962382291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.962382291
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4158273799
Short name T526
Test name
Test status
Simulation time 541743786 ps
CPU time 5.74 seconds
Started Aug 04 04:54:58 PM PDT 24
Finished Aug 04 04:55:04 PM PDT 24
Peak memory 233388 kb
Host smart-d3a9d37f-10b2-4c36-bd6c-5b95ff98b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158273799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4158273799
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2648770807
Short name T64
Test name
Test status
Simulation time 7518851846 ps
CPU time 75.13 seconds
Started Aug 04 04:54:55 PM PDT 24
Finished Aug 04 04:56:10 PM PDT 24
Peak memory 241616 kb
Host smart-fc79ab02-af41-4c83-826c-fe8806ff9a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648770807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2648770807
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2349279745
Short name T914
Test name
Test status
Simulation time 1232878510 ps
CPU time 3.15 seconds
Started Aug 04 04:54:59 PM PDT 24
Finished Aug 04 04:55:02 PM PDT 24
Peak memory 233404 kb
Host smart-06459586-c664-433e-ae39-aacec04af6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349279745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2349279745
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1877791382
Short name T11
Test name
Test status
Simulation time 15881306163 ps
CPU time 60.18 seconds
Started Aug 04 04:54:54 PM PDT 24
Finished Aug 04 04:55:54 PM PDT 24
Peak memory 241572 kb
Host smart-794d872f-c8a6-4f96-8b6e-164794a5da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877791382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1877791382
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.188028169
Short name T691
Test name
Test status
Simulation time 671746674 ps
CPU time 3.45 seconds
Started Aug 04 04:54:50 PM PDT 24
Finished Aug 04 04:54:54 PM PDT 24
Peak memory 225140 kb
Host smart-9f6a5fba-9e7d-43c7-9e49-62cbca208fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188028169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.188028169
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3420875079
Short name T707
Test name
Test status
Simulation time 93710665731 ps
CPU time 21.6 seconds
Started Aug 04 04:54:50 PM PDT 24
Finished Aug 04 04:55:11 PM PDT 24
Peak memory 233352 kb
Host smart-116bfc10-de8b-41b9-8c79-d66779599563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420875079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3420875079
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3359384397
Short name T156
Test name
Test status
Simulation time 5473240765 ps
CPU time 15.87 seconds
Started Aug 04 04:54:55 PM PDT 24
Finished Aug 04 04:55:11 PM PDT 24
Peak memory 222480 kb
Host smart-87202a3e-4e4d-435a-ba74-49345af494d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3359384397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3359384397
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3491676144
Short name T1003
Test name
Test status
Simulation time 1281291901111 ps
CPU time 589.24 seconds
Started Aug 04 04:54:54 PM PDT 24
Finished Aug 04 05:04:43 PM PDT 24
Peak memory 273624 kb
Host smart-53ee4745-da93-4cc1-abeb-cb1e5bd498fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491676144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3491676144
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4164856031
Short name T640
Test name
Test status
Simulation time 6813174453 ps
CPU time 20.37 seconds
Started Aug 04 04:54:47 PM PDT 24
Finished Aug 04 04:55:08 PM PDT 24
Peak memory 217080 kb
Host smart-ef96c4ff-90be-431e-971f-84c9228ccc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164856031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4164856031
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3324287332
Short name T348
Test name
Test status
Simulation time 30187761956 ps
CPU time 23.4 seconds
Started Aug 04 04:54:56 PM PDT 24
Finished Aug 04 04:55:20 PM PDT 24
Peak memory 217016 kb
Host smart-04ec9a31-ee0f-4762-878a-056ff0d8956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324287332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3324287332
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3439611290
Short name T454
Test name
Test status
Simulation time 19889057 ps
CPU time 0.93 seconds
Started Aug 04 04:54:51 PM PDT 24
Finished Aug 04 04:54:53 PM PDT 24
Peak memory 207700 kb
Host smart-d236626b-ef9e-4e18-89c8-e0ec5642b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439611290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3439611290
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3850085985
Short name T698
Test name
Test status
Simulation time 136557510 ps
CPU time 0.86 seconds
Started Aug 04 04:54:49 PM PDT 24
Finished Aug 04 04:54:50 PM PDT 24
Peak memory 206864 kb
Host smart-191e2c9c-0255-48c5-a674-1cc759b1609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850085985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3850085985
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1123274383
Short name T266
Test name
Test status
Simulation time 3537326315 ps
CPU time 8.03 seconds
Started Aug 04 04:54:53 PM PDT 24
Finished Aug 04 04:55:01 PM PDT 24
Peak memory 225340 kb
Host smart-5497030b-8f58-4d2f-ad61-d17851c7c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123274383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1123274383
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2876225606
Short name T400
Test name
Test status
Simulation time 41158486 ps
CPU time 0.71 seconds
Started Aug 04 04:54:59 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 206180 kb
Host smart-19915672-6726-4236-81ba-b199ff400bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876225606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2876225606
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4125049585
Short name T289
Test name
Test status
Simulation time 466758460 ps
CPU time 3.29 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:01 PM PDT 24
Peak memory 233424 kb
Host smart-f310238c-8769-453a-82d3-967e2774e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125049585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4125049585
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2028451594
Short name T699
Test name
Test status
Simulation time 15510265 ps
CPU time 0.77 seconds
Started Aug 04 04:54:56 PM PDT 24
Finished Aug 04 04:54:56 PM PDT 24
Peak memory 205960 kb
Host smart-06a3829a-d436-4da2-bb1c-909378c7ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028451594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2028451594
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1165838189
Short name T991
Test name
Test status
Simulation time 178972476536 ps
CPU time 320.12 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 05:00:26 PM PDT 24
Peak memory 257948 kb
Host smart-bd6a4dcf-6d94-418a-bdbf-1c3b0fd98994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165838189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1165838189
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1440451934
Short name T988
Test name
Test status
Simulation time 426519125351 ps
CPU time 848.42 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 273900 kb
Host smart-1a121a0c-c054-43da-8276-cf04f2e7b254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440451934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1440451934
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1328608792
Short name T225
Test name
Test status
Simulation time 24385144042 ps
CPU time 95.75 seconds
Started Aug 04 04:55:05 PM PDT 24
Finished Aug 04 04:56:41 PM PDT 24
Peak memory 255300 kb
Host smart-e5937be6-2b2a-4efd-9d44-407c5916e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328608792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1328608792
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3936279568
Short name T323
Test name
Test status
Simulation time 272734552 ps
CPU time 5.96 seconds
Started Aug 04 04:55:00 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 238904 kb
Host smart-bfcbdb6f-537e-4262-a521-f7da19036037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936279568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3936279568
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4236104299
Short name T129
Test name
Test status
Simulation time 148244763 ps
CPU time 3.47 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 233508 kb
Host smart-5ecdd065-24c2-42a6-a873-f18b81847657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236104299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4236104299
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3673074339
Short name T470
Test name
Test status
Simulation time 921161370 ps
CPU time 18.04 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:15 PM PDT 24
Peak memory 233404 kb
Host smart-cf0b06a0-d1d5-42f1-a87d-f3d293ff2e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673074339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3673074339
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2919611099
Short name T888
Test name
Test status
Simulation time 1965567476 ps
CPU time 3.03 seconds
Started Aug 04 04:55:00 PM PDT 24
Finished Aug 04 04:55:03 PM PDT 24
Peak memory 233340 kb
Host smart-20dd6a7b-6bd0-456e-a9da-ce30728eb798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919611099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2919611099
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1567141207
Short name T645
Test name
Test status
Simulation time 27374052597 ps
CPU time 17.07 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:14 PM PDT 24
Peak memory 240360 kb
Host smart-e750a5fe-702c-4ae4-adc8-477615d6d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567141207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1567141207
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3205891802
Short name T441
Test name
Test status
Simulation time 1330176161 ps
CPU time 10.45 seconds
Started Aug 04 04:55:01 PM PDT 24
Finished Aug 04 04:55:11 PM PDT 24
Peak memory 222568 kb
Host smart-7ba7a0e7-7da1-486e-943b-4e6569c2cd41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205891802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3205891802
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1298864210
Short name T999
Test name
Test status
Simulation time 441276832 ps
CPU time 3.81 seconds
Started Aug 04 04:54:58 PM PDT 24
Finished Aug 04 04:55:02 PM PDT 24
Peak memory 219256 kb
Host smart-f9b04157-c003-4bb0-8893-0bfb123323a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298864210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1298864210
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.911512335
Short name T901
Test name
Test status
Simulation time 17217739163 ps
CPU time 12.36 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:10 PM PDT 24
Peak memory 216948 kb
Host smart-b9a597a7-a363-4fbd-a976-6cc6ab1f333b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911512335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.911512335
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.349669939
Short name T453
Test name
Test status
Simulation time 48034445 ps
CPU time 1.14 seconds
Started Aug 04 04:55:05 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 207820 kb
Host smart-71bf79d4-1717-4f62-8ed6-2723f09987f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349669939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.349669939
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1150484623
Short name T895
Test name
Test status
Simulation time 27061818 ps
CPU time 0.7 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:54:58 PM PDT 24
Peak memory 206028 kb
Host smart-759cd2e9-6637-4535-a287-1042a6197aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150484623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1150484623
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3706334752
Short name T259
Test name
Test status
Simulation time 14374020834 ps
CPU time 21.55 seconds
Started Aug 04 04:54:57 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 235504 kb
Host smart-da7b9b0d-bc60-4c26-96bb-8854f9fb4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706334752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3706334752
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.549533892
Short name T437
Test name
Test status
Simulation time 16049689 ps
CPU time 0.71 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 04:55:07 PM PDT 24
Peak memory 205924 kb
Host smart-c0ce8930-24fb-4bec-9c21-789e3baaf8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549533892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.549533892
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1582943382
Short name T687
Test name
Test status
Simulation time 348143876 ps
CPU time 2.28 seconds
Started Aug 04 04:55:04 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 224792 kb
Host smart-eb6d400d-36bf-4569-b670-a40dbd1b2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582943382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1582943382
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1507163835
Short name T825
Test name
Test status
Simulation time 48950191 ps
CPU time 0.76 seconds
Started Aug 04 04:55:05 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 207068 kb
Host smart-19c275da-6bb0-40fc-8a0f-6c26c3baa1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507163835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1507163835
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2641273855
Short name T496
Test name
Test status
Simulation time 51081075993 ps
CPU time 155.44 seconds
Started Aug 04 04:55:05 PM PDT 24
Finished Aug 04 04:57:40 PM PDT 24
Peak memory 266240 kb
Host smart-831e51a6-ef28-44a5-abf3-5ba71a1a7f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641273855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2641273855
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.597547387
Short name T961
Test name
Test status
Simulation time 41401428918 ps
CPU time 67.51 seconds
Started Aug 04 04:55:07 PM PDT 24
Finished Aug 04 04:56:14 PM PDT 24
Peak memory 233428 kb
Host smart-3f2e47d5-8a42-4ba7-aa94-a8eabb505d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597547387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.597547387
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3580933256
Short name T409
Test name
Test status
Simulation time 1143295263 ps
CPU time 9.22 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 04:55:15 PM PDT 24
Peak memory 234416 kb
Host smart-98e905bf-004b-4314-bddf-95a9fa5db3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580933256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3580933256
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3885690446
Short name T935
Test name
Test status
Simulation time 714863552 ps
CPU time 14.15 seconds
Started Aug 04 04:55:04 PM PDT 24
Finished Aug 04 04:55:18 PM PDT 24
Peak memory 238640 kb
Host smart-e28171e4-2d99-4aab-99a6-c955f269cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885690446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3885690446
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.642664343
Short name T808
Test name
Test status
Simulation time 3326887276 ps
CPU time 9.09 seconds
Started Aug 04 04:55:02 PM PDT 24
Finished Aug 04 04:55:11 PM PDT 24
Peak memory 233024 kb
Host smart-80f52498-100c-4276-a436-a8df589bf456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642664343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.642664343
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3541275631
Short name T205
Test name
Test status
Simulation time 2681263554 ps
CPU time 35.67 seconds
Started Aug 04 04:55:03 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 233440 kb
Host smart-097246d0-0171-4923-9ddd-1e40b4d28f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541275631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3541275631
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4033499992
Short name T772
Test name
Test status
Simulation time 897490691 ps
CPU time 4.65 seconds
Started Aug 04 04:55:02 PM PDT 24
Finished Aug 04 04:55:06 PM PDT 24
Peak memory 224736 kb
Host smart-d80be06e-a8fc-4d20-b96f-09b46e30a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033499992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4033499992
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.929054660
Short name T617
Test name
Test status
Simulation time 383360927 ps
CPU time 4.69 seconds
Started Aug 04 04:55:00 PM PDT 24
Finished Aug 04 04:55:04 PM PDT 24
Peak memory 233428 kb
Host smart-259240d8-78b5-4652-9570-08d78ddf26c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929054660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.929054660
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3095583530
Short name T1016
Test name
Test status
Simulation time 1064780478 ps
CPU time 3.58 seconds
Started Aug 04 04:55:04 PM PDT 24
Finished Aug 04 04:55:08 PM PDT 24
Peak memory 224792 kb
Host smart-8bbffc70-ea3f-4771-a11e-54b71b1bf115
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095583530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3095583530
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2400407769
Short name T334
Test name
Test status
Simulation time 7464386781 ps
CPU time 32.05 seconds
Started Aug 04 04:55:00 PM PDT 24
Finished Aug 04 04:55:32 PM PDT 24
Peak memory 217096 kb
Host smart-a7eb618b-25e2-4810-985c-ba0dd91a1da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400407769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2400407769
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1880468665
Short name T801
Test name
Test status
Simulation time 3066289203 ps
CPU time 5.1 seconds
Started Aug 04 04:55:05 PM PDT 24
Finished Aug 04 04:55:10 PM PDT 24
Peak memory 217036 kb
Host smart-7c1a2ab4-3b72-45c3-826f-7963e83898fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880468665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1880468665
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3397235332
Short name T678
Test name
Test status
Simulation time 18440810 ps
CPU time 0.71 seconds
Started Aug 04 04:55:01 PM PDT 24
Finished Aug 04 04:55:02 PM PDT 24
Peak memory 205612 kb
Host smart-d996b5a8-a9bf-44c1-8b1a-8102e7fd67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397235332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3397235332
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.659238405
Short name T807
Test name
Test status
Simulation time 107406926 ps
CPU time 0.83 seconds
Started Aug 04 04:55:01 PM PDT 24
Finished Aug 04 04:55:01 PM PDT 24
Peak memory 206480 kb
Host smart-729593a1-0797-4a31-8083-54043bac4dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659238405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.659238405
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.496474473
Short name T894
Test name
Test status
Simulation time 14276163406 ps
CPU time 17.1 seconds
Started Aug 04 04:55:04 PM PDT 24
Finished Aug 04 04:55:21 PM PDT 24
Peak memory 233424 kb
Host smart-8676b1e9-930d-4ca6-ac2d-8527acdb2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496474473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.496474473
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1046364647
Short name T49
Test name
Test status
Simulation time 12351951 ps
CPU time 0.72 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 205756 kb
Host smart-79e298e8-4d14-4322-a5d2-744b8329dc3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046364647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1046364647
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3331107065
Short name T57
Test name
Test status
Simulation time 193315864 ps
CPU time 2.51 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:12 PM PDT 24
Peak memory 225244 kb
Host smart-51eff581-9266-4a49-afd2-7aa67f5e0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331107065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3331107065
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1069880678
Short name T473
Test name
Test status
Simulation time 105984123 ps
CPU time 0.8 seconds
Started Aug 04 04:55:06 PM PDT 24
Finished Aug 04 04:55:07 PM PDT 24
Peak memory 205956 kb
Host smart-6c66ce11-5dcc-4da7-9b57-df2cca64e67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069880678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1069880678
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3221389348
Short name T216
Test name
Test status
Simulation time 20453002063 ps
CPU time 178.26 seconds
Started Aug 04 04:55:13 PM PDT 24
Finished Aug 04 04:58:11 PM PDT 24
Peak memory 256296 kb
Host smart-33335744-f662-49bc-a6e9-b0ed5d0aa082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221389348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3221389348
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.830815168
Short name T207
Test name
Test status
Simulation time 76128527209 ps
CPU time 600.76 seconds
Started Aug 04 04:55:12 PM PDT 24
Finished Aug 04 05:05:13 PM PDT 24
Peak memory 260092 kb
Host smart-c36711d7-a676-4241-bfab-b7dace65fec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830815168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.830815168
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.234201825
Short name T718
Test name
Test status
Simulation time 96276955357 ps
CPU time 195.29 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:58:34 PM PDT 24
Peak memory 258088 kb
Host smart-4ba39341-f9b4-47b1-9cbe-15353a38f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234201825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.234201825
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2531801799
Short name T88
Test name
Test status
Simulation time 151581373141 ps
CPU time 50.83 seconds
Started Aug 04 04:55:09 PM PDT 24
Finished Aug 04 04:56:00 PM PDT 24
Peak memory 236924 kb
Host smart-f92aaf02-424b-48ed-8a0f-cd087886f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531801799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2531801799
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2385204393
Short name T762
Test name
Test status
Simulation time 23037447130 ps
CPU time 17.68 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:27 PM PDT 24
Peak memory 225304 kb
Host smart-36d949e5-acbc-46bb-8572-520367e57d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385204393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2385204393
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2949940
Short name T575
Test name
Test status
Simulation time 319257152 ps
CPU time 4.02 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:14 PM PDT 24
Peak memory 225176 kb
Host smart-a1a9604f-0e95-4217-a849-37e0c1da4b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2949940
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1029964017
Short name T862
Test name
Test status
Simulation time 104889052 ps
CPU time 2.35 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:13 PM PDT 24
Peak memory 225224 kb
Host smart-5cf4a12b-1803-4b3b-8007-e496a75c23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029964017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1029964017
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2968390512
Short name T971
Test name
Test status
Simulation time 30326978263 ps
CPU time 15.31 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 233484 kb
Host smart-f8418d5d-f110-48c8-ba38-8d929a5016d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968390512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2968390512
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3045397016
Short name T799
Test name
Test status
Simulation time 1731232837 ps
CPU time 11.64 seconds
Started Aug 04 04:55:13 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 222160 kb
Host smart-f8993822-34b2-45b6-8456-c14a75fc70ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045397016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3045397016
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.312742095
Short name T646
Test name
Test status
Simulation time 191452908 ps
CPU time 1.05 seconds
Started Aug 04 04:55:13 PM PDT 24
Finished Aug 04 04:55:14 PM PDT 24
Peak memory 216576 kb
Host smart-71464fed-50df-4ef4-b535-b07105d6192a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312742095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.312742095
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3014796970
Short name T812
Test name
Test status
Simulation time 112949195182 ps
CPU time 40.39 seconds
Started Aug 04 04:55:09 PM PDT 24
Finished Aug 04 04:55:50 PM PDT 24
Peak memory 217048 kb
Host smart-534f810f-aa89-4483-967f-9181a50ffb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014796970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3014796970
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.981463971
Short name T412
Test name
Test status
Simulation time 957401681 ps
CPU time 5.78 seconds
Started Aug 04 04:55:14 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 216956 kb
Host smart-a210af4a-73ad-47bb-9845-84e8614950e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981463971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.981463971
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.380172193
Short name T623
Test name
Test status
Simulation time 31234126 ps
CPU time 1.11 seconds
Started Aug 04 04:55:08 PM PDT 24
Finished Aug 04 04:55:10 PM PDT 24
Peak memory 207744 kb
Host smart-e9fb966b-584d-45f0-bc97-bed9e6c4a164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380172193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.380172193
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2099570044
Short name T909
Test name
Test status
Simulation time 33661272 ps
CPU time 0.91 seconds
Started Aug 04 04:55:10 PM PDT 24
Finished Aug 04 04:55:11 PM PDT 24
Peak memory 207560 kb
Host smart-e1a04677-d0a5-4043-9c89-55a0397ee734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099570044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2099570044
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3078278427
Short name T951
Test name
Test status
Simulation time 4153323610 ps
CPU time 4.86 seconds
Started Aug 04 04:55:11 PM PDT 24
Finished Aug 04 04:55:16 PM PDT 24
Peak memory 225488 kb
Host smart-c334bb1f-4b0f-49e5-8282-5403e25a8085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078278427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3078278427
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1234548841
Short name T393
Test name
Test status
Simulation time 41038783 ps
CPU time 0.68 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:17 PM PDT 24
Peak memory 205192 kb
Host smart-8a60b4fd-93b2-400e-84e5-252d7a8c2433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234548841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1234548841
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2320079396
Short name T828
Test name
Test status
Simulation time 531423520 ps
CPU time 8.42 seconds
Started Aug 04 04:55:16 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 233328 kb
Host smart-5705f438-d80b-4b55-b7b4-968eacebf782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320079396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2320079396
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1331409273
Short name T896
Test name
Test status
Simulation time 14120482 ps
CPU time 0.79 seconds
Started Aug 04 04:55:13 PM PDT 24
Finished Aug 04 04:55:14 PM PDT 24
Peak memory 206308 kb
Host smart-d1ff31b9-e160-4f7b-b717-e7dcefdccbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331409273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1331409273
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1321786864
Short name T181
Test name
Test status
Simulation time 4371072978 ps
CPU time 29.2 seconds
Started Aug 04 04:55:16 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 252996 kb
Host smart-6bf30375-a77e-4101-8fe6-d385ae05f26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321786864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1321786864
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1867568593
Short name T865
Test name
Test status
Simulation time 102025388155 ps
CPU time 238.69 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:59:16 PM PDT 24
Peak memory 262116 kb
Host smart-1d9b5950-7c42-45cc-80fc-fa92436f80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867568593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1867568593
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2198155242
Short name T14
Test name
Test status
Simulation time 897076455 ps
CPU time 6.44 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 233944 kb
Host smart-6c77ed80-74ab-4a91-8306-0bd6ced2538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198155242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2198155242
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1428253662
Short name T597
Test name
Test status
Simulation time 33592759208 ps
CPU time 252.65 seconds
Started Aug 04 04:55:16 PM PDT 24
Finished Aug 04 04:59:29 PM PDT 24
Peak memory 254296 kb
Host smart-80950a28-cfd2-45a8-a2ca-2d746ff64146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428253662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1428253662
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.993294098
Short name T798
Test name
Test status
Simulation time 580851227 ps
CPU time 7.81 seconds
Started Aug 04 04:55:20 PM PDT 24
Finished Aug 04 04:55:28 PM PDT 24
Peak memory 225140 kb
Host smart-40cffdd7-7f3e-4eb7-be08-9d7882d90a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993294098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.993294098
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1631042594
Short name T284
Test name
Test status
Simulation time 2441820963 ps
CPU time 6.14 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 233456 kb
Host smart-c83eea34-e939-4336-b7dd-67666f32065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631042594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1631042594
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1086002398
Short name T555
Test name
Test status
Simulation time 142314446 ps
CPU time 4.45 seconds
Started Aug 04 04:55:15 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 233344 kb
Host smart-1e93d87a-ba16-4d3b-a12f-feb68242f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086002398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1086002398
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.980148413
Short name T601
Test name
Test status
Simulation time 1362394347 ps
CPU time 3.42 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:21 PM PDT 24
Peak memory 219460 kb
Host smart-f807bd8d-4ad1-4a0b-ac1b-74e182f45402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980148413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.980148413
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2031979583
Short name T911
Test name
Test status
Simulation time 943770677 ps
CPU time 9.95 seconds
Started Aug 04 04:55:15 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 223704 kb
Host smart-4e1b5d73-aa86-4555-86ae-b2bbc2d660d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2031979583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2031979583
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3533829332
Short name T145
Test name
Test status
Simulation time 54747336844 ps
CPU time 468.06 seconds
Started Aug 04 04:55:20 PM PDT 24
Finished Aug 04 05:03:08 PM PDT 24
Peak memory 266296 kb
Host smart-bfafc637-3d37-4424-8856-31e2e4b659cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533829332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3533829332
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3055996053
Short name T395
Test name
Test status
Simulation time 33285690215 ps
CPU time 31.02 seconds
Started Aug 04 04:55:12 PM PDT 24
Finished Aug 04 04:55:43 PM PDT 24
Peak memory 217316 kb
Host smart-30ea024e-e4c8-4259-a97b-4e5c4ae70785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055996053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3055996053
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1748282495
Short name T899
Test name
Test status
Simulation time 4083137242 ps
CPU time 3.55 seconds
Started Aug 04 04:55:14 PM PDT 24
Finished Aug 04 04:55:17 PM PDT 24
Peak memory 216920 kb
Host smart-d8758e6c-110d-426b-87f3-7eed8f2a46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748282495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1748282495
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2064730197
Short name T747
Test name
Test status
Simulation time 62670309 ps
CPU time 1.18 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:20 PM PDT 24
Peak memory 208688 kb
Host smart-f941cdbb-c819-4b8b-a8ce-eab54d06b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064730197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2064730197
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.599774122
Short name T370
Test name
Test status
Simulation time 127748931 ps
CPU time 1.12 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 207536 kb
Host smart-e7cb0ff8-0545-48c0-9af9-c071bc65a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599774122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.599774122
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.936023973
Short name T196
Test name
Test status
Simulation time 2366719143 ps
CPU time 5.97 seconds
Started Aug 04 04:55:15 PM PDT 24
Finished Aug 04 04:55:21 PM PDT 24
Peak memory 233508 kb
Host smart-9b23b6f6-1ebb-46b3-aa86-1b9321e2dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936023973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.936023973
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2899389940
Short name T510
Test name
Test status
Simulation time 11992583 ps
CPU time 0.67 seconds
Started Aug 04 04:55:22 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 206236 kb
Host smart-cc367bc5-be90-48a2-b7f2-c166e2a32260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899389940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2899389940
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.22806781
Short name T568
Test name
Test status
Simulation time 1996070841 ps
CPU time 6.57 seconds
Started Aug 04 04:55:20 PM PDT 24
Finished Aug 04 04:55:26 PM PDT 24
Peak memory 233368 kb
Host smart-e9a41659-600b-4377-a1fb-fa68e99ed207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22806781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.22806781
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1711841297
Short name T952
Test name
Test status
Simulation time 50824567 ps
CPU time 0.78 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:19 PM PDT 24
Peak memory 205936 kb
Host smart-b0f1652d-6697-4e85-a8f1-c9d98cd1e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711841297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1711841297
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4187545633
Short name T809
Test name
Test status
Simulation time 23226330733 ps
CPU time 85.78 seconds
Started Aug 04 04:55:19 PM PDT 24
Finished Aug 04 04:56:45 PM PDT 24
Peak memory 254460 kb
Host smart-be93dd1e-36fa-422e-8a7e-cd0cd72c80d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187545633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4187545633
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1660775593
Short name T179
Test name
Test status
Simulation time 7757785112 ps
CPU time 121.57 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:57:19 PM PDT 24
Peak memory 251976 kb
Host smart-38660a74-6327-447b-99ba-6408514ac0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660775593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1660775593
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2953848070
Short name T769
Test name
Test status
Simulation time 1585698397 ps
CPU time 23.47 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:41 PM PDT 24
Peak memory 218296 kb
Host smart-af866a4b-b082-44ae-a55f-8715e79e4771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953848070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2953848070
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2564903889
Short name T410
Test name
Test status
Simulation time 175471892 ps
CPU time 4.07 seconds
Started Aug 04 04:55:20 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 233384 kb
Host smart-993217bc-434d-41c7-b365-801943ea7199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564903889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2564903889
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2030251130
Short name T550
Test name
Test status
Simulation time 2522355483 ps
CPU time 14.32 seconds
Started Aug 04 04:55:19 PM PDT 24
Finished Aug 04 04:55:33 PM PDT 24
Peak memory 249836 kb
Host smart-9ee6b845-a874-49ae-aba4-3dca85e3e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030251130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2030251130
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1525739636
Short name T1021
Test name
Test status
Simulation time 731535166 ps
CPU time 7.73 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:25 PM PDT 24
Peak memory 233464 kb
Host smart-cdc159df-8408-42cd-b366-8e5983a498aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525739636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1525739636
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2606388790
Short name T257
Test name
Test status
Simulation time 2110821510 ps
CPU time 14.42 seconds
Started Aug 04 04:55:19 PM PDT 24
Finished Aug 04 04:55:34 PM PDT 24
Peak memory 241044 kb
Host smart-3ab4fc90-a4ee-4836-bb0c-ac710323858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606388790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2606388790
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1210585404
Short name T276
Test name
Test status
Simulation time 24081779815 ps
CPU time 15.91 seconds
Started Aug 04 04:55:21 PM PDT 24
Finished Aug 04 04:55:37 PM PDT 24
Peak memory 233416 kb
Host smart-f739aa30-38a0-4a89-aa95-0dd8c13ec3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210585404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1210585404
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1420866281
Short name T802
Test name
Test status
Simulation time 1225047740 ps
CPU time 3.36 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:22 PM PDT 24
Peak memory 233340 kb
Host smart-6ec9eb63-70c7-4c81-ba19-73cf124a035b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420866281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1420866281
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3609623713
Short name T959
Test name
Test status
Simulation time 3547035259 ps
CPU time 23.35 seconds
Started Aug 04 04:55:18 PM PDT 24
Finished Aug 04 04:55:42 PM PDT 24
Peak memory 223272 kb
Host smart-193d6401-a67d-46ac-8c14-07460c21a7ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3609623713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3609623713
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2144040817
Short name T221
Test name
Test status
Simulation time 26173397176 ps
CPU time 63.99 seconds
Started Aug 04 04:55:23 PM PDT 24
Finished Aug 04 04:56:27 PM PDT 24
Peak memory 237272 kb
Host smart-c332ede7-f9d7-4c68-a5b2-c6916e9a4837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144040817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2144040817
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.534544543
Short name T743
Test name
Test status
Simulation time 18197963979 ps
CPU time 32.39 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:49 PM PDT 24
Peak memory 216908 kb
Host smart-9c0bb205-17f7-4291-9665-fa2ef24ecc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534544543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.534544543
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1933581705
Short name T739
Test name
Test status
Simulation time 4151607044 ps
CPU time 6.08 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 217032 kb
Host smart-31483b56-5336-4a79-8157-8e62a026625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933581705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1933581705
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1136859934
Short name T995
Test name
Test status
Simulation time 54636178 ps
CPU time 1 seconds
Started Aug 04 04:55:17 PM PDT 24
Finished Aug 04 04:55:18 PM PDT 24
Peak memory 207312 kb
Host smart-934c45f0-a186-43bf-99d5-a8f67d308a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136859934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1136859934
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1605274550
Short name T529
Test name
Test status
Simulation time 18449137 ps
CPU time 0.71 seconds
Started Aug 04 04:55:14 PM PDT 24
Finished Aug 04 04:55:15 PM PDT 24
Peak memory 206156 kb
Host smart-82670585-9d41-41e5-a926-816c54ebce7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605274550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1605274550
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1837733621
Short name T1032
Test name
Test status
Simulation time 8113701197 ps
CPU time 25.53 seconds
Started Aug 04 04:55:19 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 233476 kb
Host smart-0240d209-c2ed-4367-9ad1-bb05fe5912fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837733621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1837733621
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1068719285
Short name T413
Test name
Test status
Simulation time 44657571 ps
CPU time 0.68 seconds
Started Aug 04 04:55:29 PM PDT 24
Finished Aug 04 04:55:30 PM PDT 24
Peak memory 205196 kb
Host smart-58b9a7a2-eea4-4b90-bd5f-2f85b1a3533a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068719285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1068719285
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3212604564
Short name T733
Test name
Test status
Simulation time 1860760515 ps
CPU time 7.31 seconds
Started Aug 04 04:55:26 PM PDT 24
Finished Aug 04 04:55:33 PM PDT 24
Peak memory 233364 kb
Host smart-005b5093-06a8-440b-8177-44a1c7a27542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212604564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3212604564
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2554693220
Short name T440
Test name
Test status
Simulation time 22216112 ps
CPU time 0.83 seconds
Started Aug 04 04:55:22 PM PDT 24
Finished Aug 04 04:55:23 PM PDT 24
Peak memory 207416 kb
Host smart-66495c95-6fef-49e2-ad41-a9fc102a672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554693220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2554693220
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1397375681
Short name T795
Test name
Test status
Simulation time 873831986 ps
CPU time 5.53 seconds
Started Aug 04 04:55:28 PM PDT 24
Finished Aug 04 04:55:34 PM PDT 24
Peak memory 225136 kb
Host smart-d4e1f591-d27b-4aa0-87e1-9713f5603bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397375681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1397375681
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3310362108
Short name T150
Test name
Test status
Simulation time 160986204165 ps
CPU time 183.07 seconds
Started Aug 04 04:55:29 PM PDT 24
Finished Aug 04 04:58:32 PM PDT 24
Peak memory 255564 kb
Host smart-d93ab85d-d1d5-405d-8b94-270a443bbb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310362108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3310362108
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4004094989
Short name T848
Test name
Test status
Simulation time 7059468174 ps
CPU time 28.89 seconds
Started Aug 04 04:55:28 PM PDT 24
Finished Aug 04 04:55:57 PM PDT 24
Peak memory 225232 kb
Host smart-92c4a18c-37de-41a2-949a-7aa41dbcfad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004094989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4004094989
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2927597583
Short name T562
Test name
Test status
Simulation time 3472830314 ps
CPU time 52.64 seconds
Started Aug 04 04:55:28 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 251480 kb
Host smart-41bf199f-212c-4e74-a7b0-b3d2128f586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927597583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2927597583
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2173526547
Short name T26
Test name
Test status
Simulation time 132267028238 ps
CPU time 89.97 seconds
Started Aug 04 04:55:29 PM PDT 24
Finished Aug 04 04:56:59 PM PDT 24
Peak memory 241672 kb
Host smart-8368074c-c000-4952-8b60-069b352aacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173526547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2173526547
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2151264409
Short name T871
Test name
Test status
Simulation time 198769134 ps
CPU time 4.9 seconds
Started Aug 04 04:55:27 PM PDT 24
Finished Aug 04 04:55:32 PM PDT 24
Peak memory 233368 kb
Host smart-8f6592f5-7185-4251-bdf7-e601abcf134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151264409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2151264409
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.554633040
Short name T638
Test name
Test status
Simulation time 4846748781 ps
CPU time 17.73 seconds
Started Aug 04 04:55:27 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 225268 kb
Host smart-3ca30a88-e24b-4cf4-9f61-cb0e5cbc26c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554633040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.554633040
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.566835651
Short name T299
Test name
Test status
Simulation time 1815004669 ps
CPU time 5.75 seconds
Started Aug 04 04:55:25 PM PDT 24
Finished Aug 04 04:55:31 PM PDT 24
Peak memory 233340 kb
Host smart-b8e35d8f-fbd7-4483-ae58-150b13023d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566835651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.566835651
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1164793540
Short name T246
Test name
Test status
Simulation time 1131655901 ps
CPU time 6.28 seconds
Started Aug 04 04:55:25 PM PDT 24
Finished Aug 04 04:55:32 PM PDT 24
Peak memory 238908 kb
Host smart-285f7326-1e15-4c62-b180-86695db31648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164793540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1164793540
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3257916092
Short name T748
Test name
Test status
Simulation time 145273376 ps
CPU time 4.64 seconds
Started Aug 04 04:55:28 PM PDT 24
Finished Aug 04 04:55:32 PM PDT 24
Peak memory 223156 kb
Host smart-e1e65053-3ae3-4224-ab92-f8c10301d07e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3257916092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3257916092
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2451316450
Short name T149
Test name
Test status
Simulation time 4066410441 ps
CPU time 87.11 seconds
Started Aug 04 04:55:28 PM PDT 24
Finished Aug 04 04:56:55 PM PDT 24
Peak memory 260464 kb
Host smart-32848009-398f-4730-8271-3cd8b659a087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451316450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2451316450
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4074100620
Short name T327
Test name
Test status
Simulation time 30607868156 ps
CPU time 20.77 seconds
Started Aug 04 04:55:23 PM PDT 24
Finished Aug 04 04:55:44 PM PDT 24
Peak memory 216980 kb
Host smart-1680f840-6c7f-4f56-af7d-050ca67cb653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074100620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4074100620
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.79397247
Short name T729
Test name
Test status
Simulation time 18150334829 ps
CPU time 27.3 seconds
Started Aug 04 04:55:21 PM PDT 24
Finished Aug 04 04:55:49 PM PDT 24
Peak memory 216896 kb
Host smart-cd95679d-ff96-47d5-b837-73a386a5f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79397247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.79397247
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.368676316
Short name T30
Test name
Test status
Simulation time 48922683 ps
CPU time 0.96 seconds
Started Aug 04 04:55:25 PM PDT 24
Finished Aug 04 04:55:26 PM PDT 24
Peak memory 207560 kb
Host smart-d05eaaee-faec-4865-90e9-592822859d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368676316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.368676316
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2251725678
Short name T495
Test name
Test status
Simulation time 51174084 ps
CPU time 0.87 seconds
Started Aug 04 04:55:21 PM PDT 24
Finished Aug 04 04:55:22 PM PDT 24
Peak memory 206504 kb
Host smart-b6a7efac-c1b9-400a-884f-248acff1e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251725678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2251725678
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3958659260
Short name T290
Test name
Test status
Simulation time 234987019 ps
CPU time 3.96 seconds
Started Aug 04 04:55:24 PM PDT 24
Finished Aug 04 04:55:28 PM PDT 24
Peak memory 233492 kb
Host smart-abac44d5-41e9-477a-85d8-ebde0a35760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958659260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3958659260
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.357086276
Short name T761
Test name
Test status
Simulation time 130174140 ps
CPU time 0.72 seconds
Started Aug 04 04:55:36 PM PDT 24
Finished Aug 04 04:55:37 PM PDT 24
Peak memory 205780 kb
Host smart-aef91c43-6a4b-4e2c-b38a-ad8273562292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357086276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.357086276
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3548096748
Short name T272
Test name
Test status
Simulation time 432626964 ps
CPU time 4 seconds
Started Aug 04 04:55:34 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 233280 kb
Host smart-8e1aadba-694a-4212-a7d6-fda8762fc76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548096748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3548096748
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1041917629
Short name T416
Test name
Test status
Simulation time 34932190 ps
CPU time 0.83 seconds
Started Aug 04 04:55:31 PM PDT 24
Finished Aug 04 04:55:31 PM PDT 24
Peak memory 206984 kb
Host smart-1721c4d8-933e-49f6-9b76-dcc927af9ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041917629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1041917629
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.65179637
Short name T224
Test name
Test status
Simulation time 78372827726 ps
CPU time 158.28 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:58:17 PM PDT 24
Peak memory 249784 kb
Host smart-a571e9e6-5b49-4aaa-a113-e0dd5edb640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65179637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.65179637
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3015213750
Short name T215
Test name
Test status
Simulation time 8846497480 ps
CPU time 41.24 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:56:19 PM PDT 24
Peak memory 238548 kb
Host smart-2c4e8304-4ea3-4a30-93df-7424b981c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015213750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3015213750
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.288546217
Short name T815
Test name
Test status
Simulation time 5537101889 ps
CPU time 74.25 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:56:52 PM PDT 24
Peak memory 242012 kb
Host smart-abb223eb-7661-4099-85bf-54f5532c5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288546217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.288546217
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2488425357
Short name T362
Test name
Test status
Simulation time 118755939 ps
CPU time 2.78 seconds
Started Aug 04 04:55:36 PM PDT 24
Finished Aug 04 04:55:39 PM PDT 24
Peak memory 225148 kb
Host smart-06c18467-db44-43e5-a6d0-916d3c12ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488425357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2488425357
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2300323179
Short name T595
Test name
Test status
Simulation time 51246548333 ps
CPU time 121.83 seconds
Started Aug 04 04:55:37 PM PDT 24
Finished Aug 04 04:57:38 PM PDT 24
Peak memory 255472 kb
Host smart-9c9a2560-7372-4f86-ad12-8db6f624882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300323179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2300323179
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2627944349
Short name T1007
Test name
Test status
Simulation time 741935863 ps
CPU time 4.71 seconds
Started Aug 04 04:55:34 PM PDT 24
Finished Aug 04 04:55:39 PM PDT 24
Peak memory 225120 kb
Host smart-6aec74f9-087b-4ed7-8bfd-2f74751ad896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627944349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2627944349
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3007420166
Short name T883
Test name
Test status
Simulation time 9888838369 ps
CPU time 64.64 seconds
Started Aug 04 04:55:32 PM PDT 24
Finished Aug 04 04:56:36 PM PDT 24
Peak memory 234520 kb
Host smart-06085302-78d5-4af7-8ba3-84d5cebfa5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007420166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3007420166
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.47377726
Short name T286
Test name
Test status
Simulation time 2259067531 ps
CPU time 8.12 seconds
Started Aug 04 04:55:30 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 225224 kb
Host smart-3027d1a7-b0dc-460d-bbba-e4888d2efea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47377726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.47377726
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.50618221
Short name T656
Test name
Test status
Simulation time 52251906365 ps
CPU time 37.25 seconds
Started Aug 04 04:55:32 PM PDT 24
Finished Aug 04 04:56:09 PM PDT 24
Peak memory 234452 kb
Host smart-f1c0c58d-17eb-44be-815b-de285ec7356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50618221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.50618221
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4108157128
Short name T913
Test name
Test status
Simulation time 524701565 ps
CPU time 6.05 seconds
Started Aug 04 04:55:35 PM PDT 24
Finished Aug 04 04:55:41 PM PDT 24
Peak memory 222660 kb
Host smart-13a97e29-80e4-4e30-a63b-c9f96f04bf13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108157128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4108157128
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2535770441
Short name T588
Test name
Test status
Simulation time 2398259764 ps
CPU time 15.42 seconds
Started Aug 04 04:55:31 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 217476 kb
Host smart-c976b946-b92e-4b05-bfac-5c5691f34e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535770441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2535770441
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.775942464
Short name T864
Test name
Test status
Simulation time 39542719 ps
CPU time 0.72 seconds
Started Aug 04 04:55:30 PM PDT 24
Finished Aug 04 04:55:31 PM PDT 24
Peak memory 206060 kb
Host smart-cc7ff0d1-642c-43df-b8a3-e887f5ec4f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775942464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.775942464
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.79311312
Short name T824
Test name
Test status
Simulation time 278743459 ps
CPU time 3.02 seconds
Started Aug 04 04:55:34 PM PDT 24
Finished Aug 04 04:55:37 PM PDT 24
Peak memory 216904 kb
Host smart-3cd4814b-2858-40b8-80bc-f463b3a50257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79311312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.79311312
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2403293910
Short name T569
Test name
Test status
Simulation time 42726985 ps
CPU time 0.77 seconds
Started Aug 04 04:55:32 PM PDT 24
Finished Aug 04 04:55:33 PM PDT 24
Peak memory 206516 kb
Host smart-7c5e39bb-ead2-4945-b702-1ca25468799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403293910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2403293910
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2712162333
Short name T756
Test name
Test status
Simulation time 1136394196 ps
CPU time 8.71 seconds
Started Aug 04 04:55:31 PM PDT 24
Finished Aug 04 04:55:40 PM PDT 24
Peak memory 225280 kb
Host smart-3168f251-3d16-4936-aed0-11f655486174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712162333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2712162333
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1657893331
Short name T61
Test name
Test status
Simulation time 12678291 ps
CPU time 0.68 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:45 PM PDT 24
Peak memory 205732 kb
Host smart-55cbb9ce-eaae-4476-ab55-2d377ca18a65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657893331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1657893331
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.879734120
Short name T432
Test name
Test status
Simulation time 4281980102 ps
CPU time 9.77 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:55:47 PM PDT 24
Peak memory 233376 kb
Host smart-08a90664-6dd4-4269-a482-91320182cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879734120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.879734120
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3091698982
Short name T374
Test name
Test status
Simulation time 39272576 ps
CPU time 0.78 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:55:39 PM PDT 24
Peak memory 206928 kb
Host smart-528a4741-757a-4fb8-a2dd-ef795f8baa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091698982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3091698982
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4002957959
Short name T471
Test name
Test status
Simulation time 43824397337 ps
CPU time 88.47 seconds
Started Aug 04 04:55:39 PM PDT 24
Finished Aug 04 04:57:08 PM PDT 24
Peak memory 241744 kb
Host smart-6454d1a6-6a22-4392-a282-4f059e9d3af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002957959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4002957959
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1841198390
Short name T993
Test name
Test status
Simulation time 117235822225 ps
CPU time 279.6 seconds
Started Aug 04 04:55:41 PM PDT 24
Finished Aug 04 05:00:21 PM PDT 24
Peak memory 265820 kb
Host smart-c78e4fcb-e014-40e5-a3c0-ea73a6414947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841198390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1841198390
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3158174619
Short name T248
Test name
Test status
Simulation time 28766985938 ps
CPU time 267.91 seconds
Started Aug 04 04:55:42 PM PDT 24
Finished Aug 04 05:00:10 PM PDT 24
Peak memory 253424 kb
Host smart-7f92f149-84a2-4010-b7db-2a5c21196896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158174619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3158174619
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2529907713
Short name T829
Test name
Test status
Simulation time 2059179701 ps
CPU time 4.93 seconds
Started Aug 04 04:55:42 PM PDT 24
Finished Aug 04 04:55:47 PM PDT 24
Peak memory 236468 kb
Host smart-9bccd283-01ed-429b-a3ff-4cf84769c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529907713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2529907713
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.163550003
Short name T943
Test name
Test status
Simulation time 3192744074 ps
CPU time 27.46 seconds
Started Aug 04 04:55:41 PM PDT 24
Finished Aug 04 04:56:09 PM PDT 24
Peak memory 237264 kb
Host smart-70c63974-defc-495c-a586-d4dfae2bf1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163550003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.163550003
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1467877513
Short name T978
Test name
Test status
Simulation time 12097950897 ps
CPU time 18.65 seconds
Started Aug 04 04:55:37 PM PDT 24
Finished Aug 04 04:55:56 PM PDT 24
Peak memory 233500 kb
Host smart-56fc4a73-e8d6-4fe0-98d3-1416f90c7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467877513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1467877513
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1347944370
Short name T344
Test name
Test status
Simulation time 16893443575 ps
CPU time 44.61 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 238488 kb
Host smart-38352a78-194b-49c4-be34-75af26babf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347944370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1347944370
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.322877441
Short name T759
Test name
Test status
Simulation time 19021836076 ps
CPU time 18.28 seconds
Started Aug 04 04:55:39 PM PDT 24
Finished Aug 04 04:55:57 PM PDT 24
Peak memory 233532 kb
Host smart-c7dd4651-9b1f-45da-9510-085631f66a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322877441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.322877441
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4015180680
Short name T229
Test name
Test status
Simulation time 2027315459 ps
CPU time 5.34 seconds
Started Aug 04 04:55:41 PM PDT 24
Finished Aug 04 04:55:47 PM PDT 24
Peak memory 233408 kb
Host smart-46d38809-ff01-476a-b8d2-33ced6fd6bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015180680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4015180680
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2568809527
Short name T10
Test name
Test status
Simulation time 408285837 ps
CPU time 3.83 seconds
Started Aug 04 04:55:42 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 221000 kb
Host smart-51265d07-4a9e-4f22-8137-8d5562903c35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568809527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2568809527
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1101048800
Short name T201
Test name
Test status
Simulation time 64154606626 ps
CPU time 597.85 seconds
Started Aug 04 04:55:42 PM PDT 24
Finished Aug 04 05:05:40 PM PDT 24
Peak memory 274324 kb
Host smart-91cb4426-ea07-48ff-9f78-d072e48a09b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101048800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1101048800
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2675372173
Short name T336
Test name
Test status
Simulation time 4630814376 ps
CPU time 26.23 seconds
Started Aug 04 04:55:38 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 217060 kb
Host smart-edc85f5b-a3b2-4f0e-ac2b-a1b95df6590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675372173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2675372173
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2911795369
Short name T753
Test name
Test status
Simulation time 26514535859 ps
CPU time 18.48 seconds
Started Aug 04 04:55:40 PM PDT 24
Finished Aug 04 04:55:58 PM PDT 24
Peak memory 217016 kb
Host smart-59940c25-9ff5-4d50-aa4b-be4922d082e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911795369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2911795369
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.199710215
Short name T475
Test name
Test status
Simulation time 300285050 ps
CPU time 2.71 seconds
Started Aug 04 04:55:37 PM PDT 24
Finished Aug 04 04:55:40 PM PDT 24
Peak memory 216924 kb
Host smart-270d4ecb-15b2-4ad7-8d46-76af3a528ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199710215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.199710215
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1347199609
Short name T879
Test name
Test status
Simulation time 70327419 ps
CPU time 0.94 seconds
Started Aug 04 04:55:37 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 206548 kb
Host smart-6e53d5fe-d7e3-4826-aa7f-86a9df8cdbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347199609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1347199609
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3414863883
Short name T220
Test name
Test status
Simulation time 3031764520 ps
CPU time 7 seconds
Started Aug 04 04:55:36 PM PDT 24
Finished Aug 04 04:55:43 PM PDT 24
Peak memory 233392 kb
Host smart-0a4699ce-7059-467b-8909-adeff8ae7fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414863883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3414863883
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.11571915
Short name T827
Test name
Test status
Simulation time 34988496 ps
CPU time 0.77 seconds
Started Aug 04 04:53:01 PM PDT 24
Finished Aug 04 04:53:02 PM PDT 24
Peak memory 205848 kb
Host smart-434c608d-d209-4711-a216-dca6ec058631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11571915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.11571915
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3844921870
Short name T1033
Test name
Test status
Simulation time 2849699961 ps
CPU time 7.46 seconds
Started Aug 04 04:52:58 PM PDT 24
Finished Aug 04 04:53:06 PM PDT 24
Peak memory 225296 kb
Host smart-d479b626-3927-44b0-8d12-1b54b0bf7297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844921870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3844921870
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2458367077
Short name T573
Test name
Test status
Simulation time 178610381 ps
CPU time 0.74 seconds
Started Aug 04 04:52:53 PM PDT 24
Finished Aug 04 04:52:54 PM PDT 24
Peak memory 207048 kb
Host smart-16219127-5423-4568-b252-5c09e5d1d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458367077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2458367077
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2239839509
Short name T184
Test name
Test status
Simulation time 3777133506 ps
CPU time 27.24 seconds
Started Aug 04 04:52:57 PM PDT 24
Finished Aug 04 04:53:24 PM PDT 24
Peak memory 249896 kb
Host smart-561d16d7-0624-4c7b-8441-d4581fab65a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239839509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2239839509
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4174443385
Short name T237
Test name
Test status
Simulation time 1189670387 ps
CPU time 28.77 seconds
Started Aug 04 04:52:59 PM PDT 24
Finished Aug 04 04:53:28 PM PDT 24
Peak memory 250492 kb
Host smart-ff92a9e2-71f3-4db9-b4cc-66142e87acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174443385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4174443385
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1116222118
Short name T528
Test name
Test status
Simulation time 294286830 ps
CPU time 4.13 seconds
Started Aug 04 04:52:58 PM PDT 24
Finished Aug 04 04:53:02 PM PDT 24
Peak memory 233360 kb
Host smart-c215a0b6-235f-4ab6-8d04-90771ed9c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116222118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1116222118
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1286071083
Short name T1022
Test name
Test status
Simulation time 42961544465 ps
CPU time 163.74 seconds
Started Aug 04 04:52:58 PM PDT 24
Finished Aug 04 04:55:42 PM PDT 24
Peak memory 250960 kb
Host smart-512cdc6b-5202-47cc-a770-d8cbb1416d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286071083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1286071083
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.524631849
Short name T840
Test name
Test status
Simulation time 2414743517 ps
CPU time 6.46 seconds
Started Aug 04 04:52:57 PM PDT 24
Finished Aug 04 04:53:04 PM PDT 24
Peak memory 225232 kb
Host smart-6f36db02-70b8-492e-a6e0-ff0f37e5ed3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524631849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.524631849
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.95085148
Short name T906
Test name
Test status
Simulation time 1468937101 ps
CPU time 12.6 seconds
Started Aug 04 04:52:58 PM PDT 24
Finished Aug 04 04:53:10 PM PDT 24
Peak memory 225268 kb
Host smart-45ede087-c55e-4f82-b58b-3fb224c20a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95085148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.95085148
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1163391837
Short name T628
Test name
Test status
Simulation time 27609973 ps
CPU time 1.09 seconds
Started Aug 04 04:52:54 PM PDT 24
Finished Aug 04 04:52:55 PM PDT 24
Peak memory 217080 kb
Host smart-7f32062d-0dda-4e5c-ba21-6828d067a96d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163391837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1163391837
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.696006080
Short name T4
Test name
Test status
Simulation time 22443643492 ps
CPU time 34.1 seconds
Started Aug 04 04:52:55 PM PDT 24
Finished Aug 04 04:53:29 PM PDT 24
Peak memory 233352 kb
Host smart-a0f71ca0-02b9-4e6a-b786-7f3ec2299e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696006080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
696006080
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2889309728
Short name T768
Test name
Test status
Simulation time 361153445 ps
CPU time 3.65 seconds
Started Aug 04 04:52:53 PM PDT 24
Finished Aug 04 04:52:57 PM PDT 24
Peak memory 233396 kb
Host smart-30868ee0-fedc-4031-8ed3-928be1dd8882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889309728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2889309728
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.288928876
Short name T364
Test name
Test status
Simulation time 1011683473 ps
CPU time 10.44 seconds
Started Aug 04 04:52:57 PM PDT 24
Finished Aug 04 04:53:08 PM PDT 24
Peak memory 219476 kb
Host smart-99ea709d-94ab-49e1-beee-ef64cb5427e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288928876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.288928876
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1770197571
Short name T72
Test name
Test status
Simulation time 1330458407 ps
CPU time 1.64 seconds
Started Aug 04 04:53:01 PM PDT 24
Finished Aug 04 04:53:02 PM PDT 24
Peak memory 237076 kb
Host smart-ef516b3f-4b60-4687-b48b-732e18da4e69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770197571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1770197571
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3165054771
Short name T37
Test name
Test status
Simulation time 6028791309 ps
CPU time 50.37 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:54:04 PM PDT 24
Peak memory 225424 kb
Host smart-3b0ae4e8-5648-4d1e-b6f0-c4b5ec08bd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165054771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3165054771
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2773143642
Short name T580
Test name
Test status
Simulation time 7287735895 ps
CPU time 37.62 seconds
Started Aug 04 04:52:55 PM PDT 24
Finished Aug 04 04:53:33 PM PDT 24
Peak memory 217124 kb
Host smart-26818c02-5f5d-48e4-81fe-156110b279e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773143642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2773143642
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3116836387
Short name T443
Test name
Test status
Simulation time 14450874863 ps
CPU time 10.56 seconds
Started Aug 04 04:52:55 PM PDT 24
Finished Aug 04 04:53:06 PM PDT 24
Peak memory 216992 kb
Host smart-aa521a34-70bb-4b01-97fb-653bb34e2a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116836387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3116836387
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.47600211
Short name T779
Test name
Test status
Simulation time 130571908 ps
CPU time 1.51 seconds
Started Aug 04 04:52:53 PM PDT 24
Finished Aug 04 04:52:55 PM PDT 24
Peak memory 216916 kb
Host smart-49d0760c-a2c9-4868-9c30-54bdf85c5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47600211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.47600211
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.243713761
Short name T1001
Test name
Test status
Simulation time 164509371 ps
CPU time 0.86 seconds
Started Aug 04 04:52:54 PM PDT 24
Finished Aug 04 04:52:55 PM PDT 24
Peak memory 206476 kb
Host smart-1e21a9ca-d6b0-490e-9edd-6153f7278d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243713761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.243713761
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4104615750
Short name T831
Test name
Test status
Simulation time 7509807364 ps
CPU time 8.95 seconds
Started Aug 04 04:52:56 PM PDT 24
Finished Aug 04 04:53:05 PM PDT 24
Peak memory 233500 kb
Host smart-6cee8073-6cb8-47fa-9618-4c515e65b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104615750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4104615750
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1715787658
Short name T368
Test name
Test status
Simulation time 14739258 ps
CPU time 0.73 seconds
Started Aug 04 04:55:55 PM PDT 24
Finished Aug 04 04:55:55 PM PDT 24
Peak memory 205288 kb
Host smart-f18be7b8-e5a2-474c-a2c3-d44b3a302424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715787658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1715787658
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1706071292
Short name T197
Test name
Test status
Simulation time 37018114 ps
CPU time 2.48 seconds
Started Aug 04 04:55:48 PM PDT 24
Finished Aug 04 04:55:50 PM PDT 24
Peak memory 233440 kb
Host smart-120c7769-14e8-4dd0-b0b9-01dbc34dc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706071292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1706071292
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3084736307
Short name T974
Test name
Test status
Simulation time 125785731 ps
CPU time 0.81 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 207328 kb
Host smart-0ea7db44-b9a1-48a8-bb80-581f597914ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084736307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3084736307
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1725477564
Short name T858
Test name
Test status
Simulation time 907718944 ps
CPU time 12 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:56:06 PM PDT 24
Peak memory 241656 kb
Host smart-1486f3d5-67ac-439c-93f9-6e28aa1ceccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725477564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1725477564
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1292003105
Short name T386
Test name
Test status
Simulation time 3980681608 ps
CPU time 110.1 seconds
Started Aug 04 04:55:52 PM PDT 24
Finished Aug 04 04:57:42 PM PDT 24
Peak memory 254712 kb
Host smart-0f269d62-ac05-401b-b6a0-1fb2e9ff0abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292003105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1292003105
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2293078621
Short name T306
Test name
Test status
Simulation time 3254917531 ps
CPU time 84.11 seconds
Started Aug 04 04:55:52 PM PDT 24
Finished Aug 04 04:57:16 PM PDT 24
Peak memory 257056 kb
Host smart-a5b14eb5-f44c-472c-a807-c2e8383f3f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293078621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2293078621
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3670426627
Short name T794
Test name
Test status
Simulation time 1650772340 ps
CPU time 10.77 seconds
Started Aug 04 04:55:48 PM PDT 24
Finished Aug 04 04:55:59 PM PDT 24
Peak memory 241656 kb
Host smart-4d981d6a-fe03-4031-ae99-3dc18ecd364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670426627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3670426627
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1960476841
Short name T610
Test name
Test status
Simulation time 16619466640 ps
CPU time 61.29 seconds
Started Aug 04 04:55:51 PM PDT 24
Finished Aug 04 04:56:53 PM PDT 24
Peak memory 240984 kb
Host smart-bb63877e-41fb-488c-81f5-4904f8f61ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960476841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1960476841
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.448427764
Short name T420
Test name
Test status
Simulation time 1749102082 ps
CPU time 3.71 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:49 PM PDT 24
Peak memory 233448 kb
Host smart-0bb3b7a3-18dd-4e3c-8f43-77f55527568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448427764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.448427764
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.215153023
Short name T713
Test name
Test status
Simulation time 2312389060 ps
CPU time 11.07 seconds
Started Aug 04 04:55:44 PM PDT 24
Finished Aug 04 04:55:55 PM PDT 24
Peak memory 237072 kb
Host smart-a9d13ddf-f444-4295-b76e-ca17da1f9185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215153023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.215153023
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2450805685
Short name T388
Test name
Test status
Simulation time 112480455 ps
CPU time 2.14 seconds
Started Aug 04 04:55:44 PM PDT 24
Finished Aug 04 04:55:47 PM PDT 24
Peak memory 224304 kb
Host smart-f557c573-448b-43e2-bdcb-01b140be6abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450805685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2450805685
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1927679781
Short name T520
Test name
Test status
Simulation time 56841831 ps
CPU time 2.18 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:48 PM PDT 24
Peak memory 223652 kb
Host smart-21e8d316-3f6a-4a9c-bfc5-a929bcb1ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927679781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1927679781
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1498488425
Short name T766
Test name
Test status
Simulation time 380614835 ps
CPU time 5.77 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:56:00 PM PDT 24
Peak memory 219452 kb
Host smart-452d862c-513b-4717-81fd-9a36de259625
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498488425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1498488425
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2456018142
Short name T21
Test name
Test status
Simulation time 66138575 ps
CPU time 1.09 seconds
Started Aug 04 04:55:55 PM PDT 24
Finished Aug 04 04:55:56 PM PDT 24
Peak memory 207584 kb
Host smart-8c122f0a-d347-42a3-82c7-90f5162081af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456018142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2456018142
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3811033479
Short name T438
Test name
Test status
Simulation time 2366040448 ps
CPU time 22.02 seconds
Started Aug 04 04:55:48 PM PDT 24
Finished Aug 04 04:56:10 PM PDT 24
Peak memory 217052 kb
Host smart-6d0ba014-1274-4d8f-bcdf-558620bb0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811033479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3811033479
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3384713789
Short name T345
Test name
Test status
Simulation time 6786111902 ps
CPU time 17.21 seconds
Started Aug 04 04:55:46 PM PDT 24
Finished Aug 04 04:56:03 PM PDT 24
Peak memory 217108 kb
Host smart-b503c885-0a90-4e22-8cff-4dcbcc74a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384713789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3384713789
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.650111380
Short name T458
Test name
Test status
Simulation time 283266005 ps
CPU time 4.34 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:49 PM PDT 24
Peak memory 216908 kb
Host smart-c410011b-e6b4-4d43-84e6-2d77090cf809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650111380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.650111380
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2378273123
Short name T785
Test name
Test status
Simulation time 105755365 ps
CPU time 0.69 seconds
Started Aug 04 04:55:45 PM PDT 24
Finished Aug 04 04:55:46 PM PDT 24
Peak memory 206176 kb
Host smart-cf63c22b-6852-41a4-b983-07493316eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378273123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2378273123
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1959372869
Short name T782
Test name
Test status
Simulation time 1083749813 ps
CPU time 5.64 seconds
Started Aug 04 04:55:48 PM PDT 24
Finished Aug 04 04:55:54 PM PDT 24
Peak memory 233312 kb
Host smart-22f8703e-67fa-4ff6-88f6-972afd46f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959372869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1959372869
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2019743925
Short name T457
Test name
Test status
Simulation time 36837683 ps
CPU time 0.72 seconds
Started Aug 04 04:55:53 PM PDT 24
Finished Aug 04 04:55:53 PM PDT 24
Peak memory 205896 kb
Host smart-3caeb70c-ac85-472b-bc63-65562a47b93d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019743925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2019743925
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.527031161
Short name T267
Test name
Test status
Simulation time 166257816 ps
CPU time 2.7 seconds
Started Aug 04 04:55:55 PM PDT 24
Finished Aug 04 04:55:58 PM PDT 24
Peak memory 225144 kb
Host smart-3eb35400-e921-42f3-80f3-22e3237ce202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527031161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.527031161
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3726501790
Short name T373
Test name
Test status
Simulation time 17674030 ps
CPU time 0.78 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:55:55 PM PDT 24
Peak memory 206040 kb
Host smart-96629524-9ca5-46ca-8409-1a2fe4a160ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726501790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3726501790
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.429405540
Short name T671
Test name
Test status
Simulation time 3868975469 ps
CPU time 33.6 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:56:29 PM PDT 24
Peak memory 249836 kb
Host smart-a1192283-f596-43ac-86d2-f0ce213eef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429405540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.429405540
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3337470259
Short name T719
Test name
Test status
Simulation time 9477946608 ps
CPU time 86.46 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:57:22 PM PDT 24
Peak memory 250912 kb
Host smart-503b7091-513c-4236-ad4b-4534a92a0c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337470259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3337470259
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1113045649
Short name T965
Test name
Test status
Simulation time 4390060236 ps
CPU time 47.57 seconds
Started Aug 04 04:55:55 PM PDT 24
Finished Aug 04 04:56:42 PM PDT 24
Peak memory 249884 kb
Host smart-673806ce-fa2b-4c4c-bfb4-9ef5ea666f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113045649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1113045649
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4223659791
Short name T478
Test name
Test status
Simulation time 228628167 ps
CPU time 8.37 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:56:02 PM PDT 24
Peak memory 233332 kb
Host smart-6ff1164f-f933-428e-ab69-686a837b46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223659791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4223659791
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2755372707
Short name T419
Test name
Test status
Simulation time 968872758 ps
CPU time 6.96 seconds
Started Aug 04 04:55:55 PM PDT 24
Finished Aug 04 04:56:02 PM PDT 24
Peak memory 234524 kb
Host smart-5ee0b3d1-0b85-4cf9-bdcc-88b5fe42b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755372707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2755372707
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3373520066
Short name T615
Test name
Test status
Simulation time 727486873 ps
CPU time 9.88 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:56:06 PM PDT 24
Peak memory 225200 kb
Host smart-53bb5e60-549c-4f62-bbee-e7e0f2dd4dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373520066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3373520066
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2860669069
Short name T231
Test name
Test status
Simulation time 24669586387 ps
CPU time 32.89 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:56:27 PM PDT 24
Peak memory 241648 kb
Host smart-fcb656c0-a3e3-48f7-a4ad-26b6031cce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860669069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2860669069
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2263332762
Short name T757
Test name
Test status
Simulation time 1654541576 ps
CPU time 3.58 seconds
Started Aug 04 04:55:52 PM PDT 24
Finished Aug 04 04:55:56 PM PDT 24
Peak memory 225172 kb
Host smart-e8598c8b-b969-4d56-bc04-7857ae4bb59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263332762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2263332762
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3923521983
Short name T924
Test name
Test status
Simulation time 66243341 ps
CPU time 2.43 seconds
Started Aug 04 04:55:53 PM PDT 24
Finished Aug 04 04:55:56 PM PDT 24
Peak memory 225176 kb
Host smart-0fc0c9be-200e-40d7-b825-11f726c9201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923521983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3923521983
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.986233205
Short name T25
Test name
Test status
Simulation time 3278947166 ps
CPU time 7.05 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:56:03 PM PDT 24
Peak memory 223632 kb
Host smart-c4074d75-c023-4efd-bc50-c111fc6aff32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986233205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.986233205
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3492438139
Short name T925
Test name
Test status
Simulation time 1761560161 ps
CPU time 12.1 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:56:08 PM PDT 24
Peak memory 217344 kb
Host smart-f75f5846-592e-43c8-afd8-c851048ab05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492438139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3492438139
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1928031306
Short name T35
Test name
Test status
Simulation time 12270626527 ps
CPU time 11.64 seconds
Started Aug 04 04:55:49 PM PDT 24
Finished Aug 04 04:56:01 PM PDT 24
Peak memory 217040 kb
Host smart-24dc57a2-533b-452e-9cad-c080aff37d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928031306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1928031306
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1178908254
Short name T648
Test name
Test status
Simulation time 55172252 ps
CPU time 1.75 seconds
Started Aug 04 04:55:54 PM PDT 24
Finished Aug 04 04:55:56 PM PDT 24
Peak memory 208688 kb
Host smart-ce909ad4-16d9-4be0-9215-246c8ab427b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178908254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1178908254
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1291007484
Short name T712
Test name
Test status
Simulation time 14531399 ps
CPU time 0.75 seconds
Started Aug 04 04:55:52 PM PDT 24
Finished Aug 04 04:55:53 PM PDT 24
Peak memory 206448 kb
Host smart-456142c8-cbbd-4389-9c3b-f7323bed257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291007484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1291007484
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2993270572
Short name T997
Test name
Test status
Simulation time 1189071936 ps
CPU time 7.03 seconds
Started Aug 04 04:55:56 PM PDT 24
Finished Aug 04 04:56:03 PM PDT 24
Peak memory 233428 kb
Host smart-d420623a-25b7-4b16-8469-c2cc4f9e6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993270572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2993270572
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3963180780
Short name T469
Test name
Test status
Simulation time 14801550 ps
CPU time 0.73 seconds
Started Aug 04 04:56:01 PM PDT 24
Finished Aug 04 04:56:02 PM PDT 24
Peak memory 205320 kb
Host smart-526fb344-b24e-47d8-9659-887f394f421f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963180780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3963180780
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.247011256
Short name T517
Test name
Test status
Simulation time 179467852 ps
CPU time 4.93 seconds
Started Aug 04 04:55:59 PM PDT 24
Finished Aug 04 04:56:04 PM PDT 24
Peak memory 225256 kb
Host smart-81adc8e0-52eb-4362-9150-a6938932a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247011256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.247011256
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4221194991
Short name T379
Test name
Test status
Simulation time 12357645 ps
CPU time 0.78 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:56:04 PM PDT 24
Peak memory 205924 kb
Host smart-a82d4835-05bb-48d1-8e5d-56181c8526ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221194991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4221194991
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3122813901
Short name T254
Test name
Test status
Simulation time 1036494112 ps
CPU time 6.63 seconds
Started Aug 04 04:55:58 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 241544 kb
Host smart-509ae100-68b1-4750-a00d-50a3de6f4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122813901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3122813901
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.218977976
Short name T318
Test name
Test status
Simulation time 233833050554 ps
CPU time 632.8 seconds
Started Aug 04 04:56:02 PM PDT 24
Finished Aug 04 05:06:35 PM PDT 24
Peak memory 257364 kb
Host smart-17bddab6-215a-4cb5-8d48-2086aa4ddc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218977976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.218977976
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.369010417
Short name T876
Test name
Test status
Simulation time 292224927981 ps
CPU time 111.6 seconds
Started Aug 04 04:56:01 PM PDT 24
Finished Aug 04 04:57:53 PM PDT 24
Peak memory 249864 kb
Host smart-55538e88-3e61-4735-bddf-436227cc4efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369010417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.369010417
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.547872042
Short name T423
Test name
Test status
Simulation time 339292982 ps
CPU time 5.9 seconds
Started Aug 04 04:55:59 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 225164 kb
Host smart-7ec90d80-f4cf-412b-b2bd-dacc7c735f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547872042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.547872042
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1991943469
Short name T316
Test name
Test status
Simulation time 63006568293 ps
CPU time 92.77 seconds
Started Aug 04 04:55:58 PM PDT 24
Finished Aug 04 04:57:31 PM PDT 24
Peak memory 258008 kb
Host smart-6159df42-ec62-4488-a0f7-dfc82a2aa2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991943469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1991943469
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.462752479
Short name T774
Test name
Test status
Simulation time 1851042246 ps
CPU time 25.1 seconds
Started Aug 04 04:56:00 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 225424 kb
Host smart-0d5cc1ec-8f8d-4d24-88d2-4f54d0ec0f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462752479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.462752479
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1785935991
Short name T584
Test name
Test status
Simulation time 396725097 ps
CPU time 12.65 seconds
Started Aug 04 04:55:59 PM PDT 24
Finished Aug 04 04:56:12 PM PDT 24
Peak memory 241764 kb
Host smart-4ee45395-51f2-4c8d-bfe2-e33e3f73101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785935991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1785935991
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2242183143
Short name T792
Test name
Test status
Simulation time 2850432394 ps
CPU time 12.14 seconds
Started Aug 04 04:55:57 PM PDT 24
Finished Aug 04 04:56:10 PM PDT 24
Peak memory 241172 kb
Host smart-618ada1f-46d1-44ed-a7ef-cd7b45360ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242183143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2242183143
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.789886256
Short name T620
Test name
Test status
Simulation time 13268519609 ps
CPU time 17.35 seconds
Started Aug 04 04:55:57 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 225292 kb
Host smart-17ce2d4b-6f0f-41fe-95b2-00b8440748a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789886256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.789886256
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3693153480
Short name T551
Test name
Test status
Simulation time 633740043 ps
CPU time 9.82 seconds
Started Aug 04 04:55:57 PM PDT 24
Finished Aug 04 04:56:07 PM PDT 24
Peak memory 222508 kb
Host smart-9508a424-b88f-43c2-b4a1-92dd3030a362
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3693153480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3693153480
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3018818226
Short name T332
Test name
Test status
Simulation time 239041050 ps
CPU time 4.03 seconds
Started Aug 04 04:55:57 PM PDT 24
Finished Aug 04 04:56:01 PM PDT 24
Peak memory 216964 kb
Host smart-3e2d7dbd-7bd3-4e56-95ea-dcb6d361d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018818226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3018818226
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.412176593
Short name T34
Test name
Test status
Simulation time 525140176 ps
CPU time 1.77 seconds
Started Aug 04 04:55:58 PM PDT 24
Finished Aug 04 04:56:00 PM PDT 24
Peak memory 208484 kb
Host smart-6989d6e0-6ced-4d85-b6de-9ebb4091f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412176593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.412176593
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3434361945
Short name T860
Test name
Test status
Simulation time 96766287 ps
CPU time 1.21 seconds
Started Aug 04 04:55:58 PM PDT 24
Finished Aug 04 04:56:00 PM PDT 24
Peak memory 216724 kb
Host smart-21e25400-2b54-48f5-b946-364dc1fa3e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434361945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3434361945
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1747499711
Short name T80
Test name
Test status
Simulation time 155569038 ps
CPU time 0.86 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:56:04 PM PDT 24
Peak memory 206460 kb
Host smart-6c5c2f98-e084-4235-957a-ab54fd83b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747499711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1747499711
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1340742212
Short name T533
Test name
Test status
Simulation time 2023640392 ps
CPU time 11.01 seconds
Started Aug 04 04:55:57 PM PDT 24
Finished Aug 04 04:56:08 PM PDT 24
Peak memory 225296 kb
Host smart-032910d3-e1f7-4def-b16e-82efe4e05663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340742212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1340742212
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1812891144
Short name T915
Test name
Test status
Simulation time 35446533 ps
CPU time 0.68 seconds
Started Aug 04 04:56:02 PM PDT 24
Finished Aug 04 04:56:03 PM PDT 24
Peak memory 205316 kb
Host smart-d5241b60-2aea-4009-9a8c-f1433327a14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812891144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1812891144
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.496571589
Short name T618
Test name
Test status
Simulation time 1753079489 ps
CPU time 11.54 seconds
Started Aug 04 04:56:05 PM PDT 24
Finished Aug 04 04:56:17 PM PDT 24
Peak memory 225284 kb
Host smart-4bc77040-4d76-4e56-99b4-c02ba7699443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496571589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.496571589
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3432733641
Short name T65
Test name
Test status
Simulation time 14435287 ps
CPU time 0.83 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:56:04 PM PDT 24
Peak memory 207280 kb
Host smart-d635c8a3-d300-4fce-ab14-0126da540254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432733641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3432733641
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.320487712
Short name T244
Test name
Test status
Simulation time 2129779666 ps
CPU time 17.65 seconds
Started Aug 04 04:56:04 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 225128 kb
Host smart-a75ca38e-465c-40df-a170-4ff67435b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320487712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.320487712
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.604934977
Short name T566
Test name
Test status
Simulation time 32791942897 ps
CPU time 78.06 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:57:22 PM PDT 24
Peak memory 240244 kb
Host smart-0a9f97db-51be-4700-ab24-3d92c249c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604934977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.604934977
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.411708061
Short name T236
Test name
Test status
Simulation time 53899275248 ps
CPU time 157.54 seconds
Started Aug 04 04:56:08 PM PDT 24
Finished Aug 04 04:58:45 PM PDT 24
Peak memory 265396 kb
Host smart-7de8518b-d9cb-4df6-91ea-365eaeae9978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411708061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.411708061
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3602250475
Short name T319
Test name
Test status
Simulation time 3808225086 ps
CPU time 28.91 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 225248 kb
Host smart-e35a8321-26d1-43d7-9ed1-ab9e2e67861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602250475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3602250475
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2454727618
Short name T282
Test name
Test status
Simulation time 4150494753 ps
CPU time 16.12 seconds
Started Aug 04 04:56:05 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 241772 kb
Host smart-d42644af-992f-4e6c-b93f-6a3aa4ee90d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454727618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2454727618
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.725098567
Short name T570
Test name
Test status
Simulation time 2814054651 ps
CPU time 7.94 seconds
Started Aug 04 04:56:05 PM PDT 24
Finished Aug 04 04:56:13 PM PDT 24
Peak memory 225328 kb
Host smart-f510a9ca-2945-4cbe-ae0c-df75a458033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725098567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.725098567
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1887331250
Short name T605
Test name
Test status
Simulation time 740692690 ps
CPU time 14.72 seconds
Started Aug 04 04:56:07 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 240176 kb
Host smart-3211c08c-66be-40d8-b7b3-018df67e5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887331250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1887331250
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2080087433
Short name T942
Test name
Test status
Simulation time 84567392 ps
CPU time 2.41 seconds
Started Aug 04 04:56:02 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 225156 kb
Host smart-59bba180-cdcd-4320-85a3-ea52f1301a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080087433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2080087433
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3969490102
Short name T811
Test name
Test status
Simulation time 4304278337 ps
CPU time 17.64 seconds
Started Aug 04 04:56:03 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 253368 kb
Host smart-b97302f8-188b-4049-b7fa-6be85df4f34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969490102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3969490102
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3275157500
Short name T394
Test name
Test status
Simulation time 403089352 ps
CPU time 4.82 seconds
Started Aug 04 04:56:05 PM PDT 24
Finished Aug 04 04:56:10 PM PDT 24
Peak memory 221040 kb
Host smart-56d062f9-455e-4876-a7d2-d67aa7d01b06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275157500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3275157500
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2602664388
Short name T945
Test name
Test status
Simulation time 122627208 ps
CPU time 1.15 seconds
Started Aug 04 04:56:04 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 208104 kb
Host smart-1470abf9-2cf1-48c4-bb33-4cc9d795355f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602664388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2602664388
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.329309170
Short name T535
Test name
Test status
Simulation time 32656819473 ps
CPU time 48.55 seconds
Started Aug 04 04:56:00 PM PDT 24
Finished Aug 04 04:56:49 PM PDT 24
Peak memory 217016 kb
Host smart-8c1e5709-a67d-45da-8b8d-e0b5fdb454e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329309170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.329309170
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2409587335
Short name T927
Test name
Test status
Simulation time 31402368 ps
CPU time 0.73 seconds
Started Aug 04 04:56:00 PM PDT 24
Finished Aug 04 04:56:01 PM PDT 24
Peak memory 206128 kb
Host smart-a20397f2-a7cc-4585-a6b3-590258d6b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409587335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2409587335
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.230011640
Short name T722
Test name
Test status
Simulation time 66753464 ps
CPU time 1.89 seconds
Started Aug 04 04:56:01 PM PDT 24
Finished Aug 04 04:56:03 PM PDT 24
Peak memory 216944 kb
Host smart-4553b236-358a-4eb7-8371-1bbf76fe69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230011640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.230011640
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2126743995
Short name T536
Test name
Test status
Simulation time 119983285 ps
CPU time 0.83 seconds
Started Aug 04 04:56:01 PM PDT 24
Finished Aug 04 04:56:02 PM PDT 24
Peak memory 207600 kb
Host smart-a35e41fc-35bd-4130-beb6-16a16f8abc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126743995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2126743995
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2392110630
Short name T501
Test name
Test status
Simulation time 1374557977 ps
CPU time 11.85 seconds
Started Aug 04 04:56:04 PM PDT 24
Finished Aug 04 04:56:17 PM PDT 24
Peak memory 235948 kb
Host smart-ffe0ca2c-3b4c-4f86-897f-0113760236d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392110630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2392110630
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.619742113
Short name T836
Test name
Test status
Simulation time 21924538 ps
CPU time 0.74 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 205204 kb
Host smart-d684abe7-4a53-41b8-a36d-2a65389de1ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619742113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.619742113
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.404670734
Short name T701
Test name
Test status
Simulation time 154344743 ps
CPU time 2.23 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:13 PM PDT 24
Peak memory 225132 kb
Host smart-8e8b97ac-684d-47dd-a5e5-d58d014b078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404670734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.404670734
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.64360515
Short name T577
Test name
Test status
Simulation time 34657760 ps
CPU time 0.79 seconds
Started Aug 04 04:56:07 PM PDT 24
Finished Aug 04 04:56:07 PM PDT 24
Peak memory 207312 kb
Host smart-5eb290db-495f-47c3-8780-4ce287352a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64360515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.64360515
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4264293972
Short name T300
Test name
Test status
Simulation time 45881833557 ps
CPU time 349.49 seconds
Started Aug 04 04:56:10 PM PDT 24
Finished Aug 04 05:02:00 PM PDT 24
Peak memory 254212 kb
Host smart-de960bf5-ef55-4575-90e7-cedae8b3cea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264293972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4264293972
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.529123964
Short name T1036
Test name
Test status
Simulation time 6308267472 ps
CPU time 35.69 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:56:50 PM PDT 24
Peak memory 220172 kb
Host smart-0a92cacb-b1be-4425-bc45-f24435f8a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529123964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.529123964
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.629771307
Short name T800
Test name
Test status
Simulation time 2136576099 ps
CPU time 55.13 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:57:10 PM PDT 24
Peak memory 266180 kb
Host smart-1c7e605a-98c9-415d-a883-ba25c6be2dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629771307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.629771307
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1039311059
Short name T560
Test name
Test status
Simulation time 1024093127 ps
CPU time 5.94 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:17 PM PDT 24
Peak memory 225224 kb
Host smart-1e6cd98d-ea25-4fa3-b741-9afd386a5072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039311059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1039311059
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2354067060
Short name T508
Test name
Test status
Simulation time 2450701990 ps
CPU time 9.25 seconds
Started Aug 04 04:56:10 PM PDT 24
Finished Aug 04 04:56:19 PM PDT 24
Peak memory 233404 kb
Host smart-fa0b62e4-0580-4256-b5cf-ecd82e81698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354067060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2354067060
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3336394568
Short name T281
Test name
Test status
Simulation time 1777816548 ps
CPU time 9.96 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 239644 kb
Host smart-b869ae66-a379-4636-b1d2-dddd3ceb01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336394568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3336394568
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.939873382
Short name T235
Test name
Test status
Simulation time 3216264830 ps
CPU time 11.63 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:26 PM PDT 24
Peak memory 241192 kb
Host smart-1a672e57-c744-4d2c-a959-14a4f10f0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939873382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.939873382
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1137785004
Short name T608
Test name
Test status
Simulation time 4060103246 ps
CPU time 11.22 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 233480 kb
Host smart-779cd2d5-e841-4e52-9b6c-1f5052e22b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137785004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1137785004
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.650768099
Short name T516
Test name
Test status
Simulation time 1743274667 ps
CPU time 12.75 seconds
Started Aug 04 04:56:12 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 223536 kb
Host smart-a99cb21e-3209-41fa-b495-c6c47a465832
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650768099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.650768099
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2650324262
Short name T163
Test name
Test status
Simulation time 85293956 ps
CPU time 0.95 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:16 PM PDT 24
Peak memory 206976 kb
Host smart-f149016b-c359-49d5-bcca-c59e408f3cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650324262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2650324262
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3666389841
Short name T329
Test name
Test status
Simulation time 21918883867 ps
CPU time 11.79 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:23 PM PDT 24
Peak memory 217184 kb
Host smart-003932da-c00f-4857-9634-babf07a56eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666389841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3666389841
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1135598572
Short name T347
Test name
Test status
Simulation time 1442421662 ps
CPU time 1.87 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:13 PM PDT 24
Peak memory 216928 kb
Host smart-94461127-2f36-4678-bcdb-b34d0cc60066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135598572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1135598572
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1189095702
Short name T492
Test name
Test status
Simulation time 43601107 ps
CPU time 0.76 seconds
Started Aug 04 04:56:11 PM PDT 24
Finished Aug 04 04:56:12 PM PDT 24
Peak memory 206600 kb
Host smart-123dcb2c-f978-4af8-a28f-4cf26a28ba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189095702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1189095702
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2107703296
Short name T674
Test name
Test status
Simulation time 19447374981 ps
CPU time 18.95 seconds
Started Aug 04 04:56:10 PM PDT 24
Finished Aug 04 04:56:29 PM PDT 24
Peak memory 225232 kb
Host smart-a6022900-b078-4f51-a561-68f09f67f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107703296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2107703296
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3343645266
Short name T525
Test name
Test status
Simulation time 13090904 ps
CPU time 0.7 seconds
Started Aug 04 04:56:18 PM PDT 24
Finished Aug 04 04:56:19 PM PDT 24
Peak memory 205860 kb
Host smart-0ba74481-a05c-48e8-9974-63d0976f6e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343645266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3343645266
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2138666680
Short name T878
Test name
Test status
Simulation time 124566022 ps
CPU time 3.42 seconds
Started Aug 04 04:56:18 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 225192 kb
Host smart-bd41c882-ff17-4bed-b2dc-0ff03e84fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138666680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2138666680
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2319042971
Short name T844
Test name
Test status
Simulation time 41146124 ps
CPU time 0.8 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:16 PM PDT 24
Peak memory 207096 kb
Host smart-e9e3a772-6943-4359-ad30-df135aab7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319042971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2319042971
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3075282376
Short name T1013
Test name
Test status
Simulation time 75530480070 ps
CPU time 137.6 seconds
Started Aug 04 04:56:23 PM PDT 24
Finished Aug 04 04:58:41 PM PDT 24
Peak memory 252900 kb
Host smart-13817d70-d789-4bf1-8d42-d595f65d7798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075282376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3075282376
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1981636523
Short name T731
Test name
Test status
Simulation time 19575589687 ps
CPU time 63.67 seconds
Started Aug 04 04:56:24 PM PDT 24
Finished Aug 04 04:57:28 PM PDT 24
Peak memory 249932 kb
Host smart-1354d884-6f6b-48ae-870c-eb8c91437386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981636523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1981636523
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3760788496
Short name T55
Test name
Test status
Simulation time 11729174609 ps
CPU time 74.66 seconds
Started Aug 04 04:56:19 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 250728 kb
Host smart-487326cb-7ce6-4eb4-acc6-fdb6bfd21128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760788496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3760788496
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4083135287
Short name T78
Test name
Test status
Simulation time 384429776 ps
CPU time 6.21 seconds
Started Aug 04 04:56:18 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 233372 kb
Host smart-412a89ec-72c7-4ddc-ada7-58173436fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083135287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4083135287
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3638722199
Short name T194
Test name
Test status
Simulation time 3489544037 ps
CPU time 49.89 seconds
Started Aug 04 04:56:18 PM PDT 24
Finished Aug 04 04:57:08 PM PDT 24
Peak memory 253884 kb
Host smart-27c2d078-fa20-4c1c-8b11-3a2cafab1d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638722199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3638722199
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1623382602
Short name T572
Test name
Test status
Simulation time 949261005 ps
CPU time 4.32 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:19 PM PDT 24
Peak memory 225252 kb
Host smart-00f284cc-e101-4898-8a91-8f01d49d3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623382602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1623382602
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1963671120
Short name T204
Test name
Test status
Simulation time 5933819913 ps
CPU time 37.56 seconds
Started Aug 04 04:56:20 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 225388 kb
Host smart-029f8889-1117-48f1-a243-b18cbcd5dbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963671120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1963671120
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4085112516
Short name T97
Test name
Test status
Simulation time 21951723633 ps
CPU time 14.73 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:30 PM PDT 24
Peak memory 233484 kb
Host smart-4b016793-49b0-4137-9fb0-c6ebc410fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085112516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4085112516
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1072976481
Short name T823
Test name
Test status
Simulation time 105018539 ps
CPU time 2.22 seconds
Started Aug 04 04:56:15 PM PDT 24
Finished Aug 04 04:56:17 PM PDT 24
Peak memory 227440 kb
Host smart-35e3cded-6376-4015-bbe9-a546916c98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072976481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1072976481
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4270075650
Short name T777
Test name
Test status
Simulation time 583854951 ps
CPU time 3.97 seconds
Started Aug 04 04:56:17 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 220832 kb
Host smart-43e01e77-7f9a-44a2-a0d8-247a9f994f41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270075650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4270075650
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4270096702
Short name T838
Test name
Test status
Simulation time 85667045978 ps
CPU time 166.5 seconds
Started Aug 04 04:56:17 PM PDT 24
Finished Aug 04 04:59:04 PM PDT 24
Peak memory 253108 kb
Host smart-92fd1bdc-e1a6-4b3a-a069-08737db16fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270096702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4270096702
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.651018890
Short name T52
Test name
Test status
Simulation time 503933772 ps
CPU time 4.09 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:56:18 PM PDT 24
Peak memory 217200 kb
Host smart-dee635df-cc0b-449e-9a53-40ca497d3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651018890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.651018890
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1247250521
Short name T613
Test name
Test status
Simulation time 5921532048 ps
CPU time 3.35 seconds
Started Aug 04 04:56:16 PM PDT 24
Finished Aug 04 04:56:20 PM PDT 24
Peak memory 216900 kb
Host smart-0cb2f968-540c-46e5-abec-d16cc8166d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247250521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1247250521
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1598948213
Short name T654
Test name
Test status
Simulation time 23974344 ps
CPU time 1.18 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 208700 kb
Host smart-1146d3ee-8298-46cd-8fd0-7a6ca0365275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598948213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1598948213
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1976469959
Short name T356
Test name
Test status
Simulation time 97501908 ps
CPU time 0.99 seconds
Started Aug 04 04:56:14 PM PDT 24
Finished Aug 04 04:56:15 PM PDT 24
Peak memory 207620 kb
Host smart-35515c01-5111-452b-8931-72ee173162b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976469959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1976469959
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.830169925
Short name T898
Test name
Test status
Simulation time 35618576245 ps
CPU time 25.78 seconds
Started Aug 04 04:56:17 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 241604 kb
Host smart-3a1db5ad-b260-4756-940b-c1fdffab29c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830169925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.830169925
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1957719233
Short name T406
Test name
Test status
Simulation time 26197860 ps
CPU time 0.73 seconds
Started Aug 04 04:56:23 PM PDT 24
Finished Aug 04 04:56:24 PM PDT 24
Peak memory 205756 kb
Host smart-49364b06-478d-477b-a585-c8e94bb6a773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957719233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1957719233
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3541029505
Short name T271
Test name
Test status
Simulation time 417961207 ps
CPU time 2.66 seconds
Started Aug 04 04:56:22 PM PDT 24
Finished Aug 04 04:56:24 PM PDT 24
Peak memory 225272 kb
Host smart-1f146009-7b9e-4f41-8483-4e68c4b8a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541029505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3541029505
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2080409835
Short name T483
Test name
Test status
Simulation time 49288205 ps
CPU time 0.8 seconds
Started Aug 04 04:56:19 PM PDT 24
Finished Aug 04 04:56:20 PM PDT 24
Peak memory 207016 kb
Host smart-7d01d9df-472b-45e9-b22d-1d2322584597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080409835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2080409835
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2325591613
Short name T983
Test name
Test status
Simulation time 6602168517 ps
CPU time 32.53 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:54 PM PDT 24
Peak memory 241572 kb
Host smart-9e077c3e-1a06-4188-900d-1c65e437e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325591613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2325591613
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1428184100
Short name T675
Test name
Test status
Simulation time 1590035617 ps
CPU time 5.68 seconds
Started Aug 04 04:56:20 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 235792 kb
Host smart-239bc2ee-b88b-4143-a18a-581a6e3ab90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428184100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1428184100
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3198433967
Short name T900
Test name
Test status
Simulation time 9901676825 ps
CPU time 40.48 seconds
Started Aug 04 04:56:25 PM PDT 24
Finished Aug 04 04:57:05 PM PDT 24
Peak memory 251968 kb
Host smart-17bee390-16fb-41c0-812c-04a266e42abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198433967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3198433967
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.656498123
Short name T262
Test name
Test status
Simulation time 4026316041 ps
CPU time 10.61 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 225184 kb
Host smart-929893c1-a041-4cbe-bede-3e3c842c395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656498123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.656498123
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2160662628
Short name T455
Test name
Test status
Simulation time 67248889103 ps
CPU time 153.04 seconds
Started Aug 04 04:56:25 PM PDT 24
Finished Aug 04 04:58:58 PM PDT 24
Peak memory 234492 kb
Host smart-43eae094-11eb-41a0-8a9e-6c6c7769975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160662628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2160662628
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2630683308
Short name T278
Test name
Test status
Simulation time 3992020662 ps
CPU time 9.23 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:30 PM PDT 24
Peak memory 233428 kb
Host smart-2d760e22-e0a6-41b8-a712-a7d4e5ab68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630683308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2630683308
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1758128438
Short name T260
Test name
Test status
Simulation time 80517867 ps
CPU time 2.26 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:24 PM PDT 24
Peak memory 225204 kb
Host smart-83b1be3c-2ce2-46d1-8a81-1b69475ff921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758128438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1758128438
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3787995208
Short name T655
Test name
Test status
Simulation time 160905696 ps
CPU time 3.65 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 223640 kb
Host smart-c5fbbf3e-926d-4ede-b379-9b0d3ca5ab50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3787995208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3787995208
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3726999646
Short name T415
Test name
Test status
Simulation time 75655290 ps
CPU time 1.03 seconds
Started Aug 04 04:56:25 PM PDT 24
Finished Aug 04 04:56:26 PM PDT 24
Peak memory 208172 kb
Host smart-e0f653b3-a0ba-4a4e-bd25-a22abcd41feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726999646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3726999646
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2339594763
Short name T369
Test name
Test status
Simulation time 428883362 ps
CPU time 2.9 seconds
Started Aug 04 04:56:19 PM PDT 24
Finished Aug 04 04:56:22 PM PDT 24
Peak memory 216864 kb
Host smart-c201c618-e8c1-4baa-bedb-397e6ddd200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339594763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2339594763
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1358841448
Short name T76
Test name
Test status
Simulation time 420030661 ps
CPU time 2.75 seconds
Started Aug 04 04:56:20 PM PDT 24
Finished Aug 04 04:56:23 PM PDT 24
Peak memory 216876 kb
Host smart-98795e52-7452-40d3-8d34-70ba1919286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358841448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1358841448
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2794456721
Short name T842
Test name
Test status
Simulation time 234550537 ps
CPU time 1.31 seconds
Started Aug 04 04:56:24 PM PDT 24
Finished Aug 04 04:56:26 PM PDT 24
Peak memory 216932 kb
Host smart-6bb22a91-c646-41b3-a74b-12c59fdf75ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794456721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2794456721
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3234229840
Short name T1004
Test name
Test status
Simulation time 39626447 ps
CPU time 0.95 seconds
Started Aug 04 04:56:20 PM PDT 24
Finished Aug 04 04:56:21 PM PDT 24
Peak memory 206924 kb
Host smart-710a3cd0-1bd7-448f-87a7-3fb9079c82d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234229840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3234229840
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2773717879
Short name T74
Test name
Test status
Simulation time 281031131 ps
CPU time 3.28 seconds
Started Aug 04 04:56:21 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 225108 kb
Host smart-03d63fb8-6e6f-4e1a-86f1-9e60d2d65bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773717879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2773717879
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2708517016
Short name T359
Test name
Test status
Simulation time 11760743 ps
CPU time 0.74 seconds
Started Aug 04 04:56:33 PM PDT 24
Finished Aug 04 04:56:34 PM PDT 24
Peak memory 206144 kb
Host smart-90906e7b-fb5b-40c0-8ae5-4807b5139216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708517016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2708517016
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3967340861
Short name T106
Test name
Test status
Simulation time 2517480042 ps
CPU time 3.1 seconds
Started Aug 04 04:56:28 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 233504 kb
Host smart-899ddcf7-be73-40cc-bf75-2b26a954dd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967340861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3967340861
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3580785318
Short name T31
Test name
Test status
Simulation time 41769976 ps
CPU time 0.79 seconds
Started Aug 04 04:56:24 PM PDT 24
Finished Aug 04 04:56:25 PM PDT 24
Peak memory 207064 kb
Host smart-72419d5e-7097-46f3-9e1b-017dfc26472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580785318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3580785318
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.681412417
Short name T182
Test name
Test status
Simulation time 2714845336 ps
CPU time 20.31 seconds
Started Aug 04 04:56:32 PM PDT 24
Finished Aug 04 04:56:52 PM PDT 24
Peak memory 251348 kb
Host smart-87ce8d47-9235-492a-8831-b7fe366379f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681412417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.681412417
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3370214493
Short name T950
Test name
Test status
Simulation time 69180761591 ps
CPU time 637.98 seconds
Started Aug 04 04:56:32 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 257500 kb
Host smart-e1829c1a-45a4-44a6-917b-aec05c9b1354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370214493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3370214493
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.973312400
Short name T497
Test name
Test status
Simulation time 294307307 ps
CPU time 7.26 seconds
Started Aug 04 04:56:28 PM PDT 24
Finished Aug 04 04:56:35 PM PDT 24
Peak memory 225092 kb
Host smart-c149e7ac-3f0e-4e12-830d-842568929f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973312400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.973312400
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.315501966
Short name T973
Test name
Test status
Simulation time 544004562863 ps
CPU time 317.97 seconds
Started Aug 04 04:56:30 PM PDT 24
Finished Aug 04 05:01:48 PM PDT 24
Peak memory 272960 kb
Host smart-709f5296-e3bd-4fc0-80e0-a448c0dc504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315501966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.315501966
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2743520966
Short name T787
Test name
Test status
Simulation time 2345838232 ps
CPU time 22.9 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:52 PM PDT 24
Peak memory 233480 kb
Host smart-81ca40e8-27ff-4fed-bcef-e15d77eda12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743520966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2743520966
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1723564334
Short name T222
Test name
Test status
Simulation time 1613445763 ps
CPU time 17.65 seconds
Started Aug 04 04:56:30 PM PDT 24
Finished Aug 04 04:56:48 PM PDT 24
Peak memory 233488 kb
Host smart-ad34321a-ef94-4972-85c5-0e017d99b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723564334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1723564334
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.445272564
Short name T720
Test name
Test status
Simulation time 1076226391 ps
CPU time 4 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:33 PM PDT 24
Peak memory 225240 kb
Host smart-67717499-58ae-47f2-b084-dede5831cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445272564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.445272564
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3011122332
Short name T928
Test name
Test status
Simulation time 76213363 ps
CPU time 2.95 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 233368 kb
Host smart-8ebd6b4d-3b58-4e00-90cd-6a968c261f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011122332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3011122332
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2691156318
Short name T700
Test name
Test status
Simulation time 263385385 ps
CPU time 5.54 seconds
Started Aug 04 04:56:27 PM PDT 24
Finished Aug 04 04:56:33 PM PDT 24
Peak memory 219236 kb
Host smart-a15af96b-a2f0-4723-935f-26e81dfb3ea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691156318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2691156318
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1136559661
Short name T381
Test name
Test status
Simulation time 12310547795 ps
CPU time 135.54 seconds
Started Aug 04 04:56:33 PM PDT 24
Finished Aug 04 04:58:48 PM PDT 24
Peak memory 254740 kb
Host smart-744dfdd9-2716-4694-8f67-38322e82ab2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136559661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1136559661
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.854047131
Short name T837
Test name
Test status
Simulation time 12664428 ps
CPU time 0.74 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:30 PM PDT 24
Peak memory 206516 kb
Host smart-cf0ea0d7-14c2-4c6b-83bb-99c0139fb249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854047131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.854047131
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.700629562
Short name T1025
Test name
Test status
Simulation time 6206323317 ps
CPU time 18.05 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:47 PM PDT 24
Peak memory 216996 kb
Host smart-1a113a7e-0ae9-40ee-87c8-59a40a349c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700629562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.700629562
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1788205686
Short name T565
Test name
Test status
Simulation time 37543653 ps
CPU time 0.85 seconds
Started Aug 04 04:56:30 PM PDT 24
Finished Aug 04 04:56:31 PM PDT 24
Peak memory 207076 kb
Host smart-fdf09be3-1844-47ff-b799-1574bf859df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788205686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1788205686
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2859477073
Short name T781
Test name
Test status
Simulation time 74275227 ps
CPU time 0.75 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:30 PM PDT 24
Peak memory 206568 kb
Host smart-7cde9418-3bde-4d8e-9629-e365cd245a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859477073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2859477073
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3049241668
Short name T644
Test name
Test status
Simulation time 1858244527 ps
CPU time 7.72 seconds
Started Aug 04 04:56:29 PM PDT 24
Finished Aug 04 04:56:37 PM PDT 24
Peak memory 233372 kb
Host smart-b17e1f03-8290-459e-84c9-fa56ab6d2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049241668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3049241668
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3512376211
Short name T989
Test name
Test status
Simulation time 43657714 ps
CPU time 0.73 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:56:39 PM PDT 24
Peak memory 205812 kb
Host smart-aed5cbc8-f8ec-4c91-9436-74d0eef8433c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512376211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3512376211
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4104120771
Short name T404
Test name
Test status
Simulation time 108197813 ps
CPU time 2.34 seconds
Started Aug 04 04:56:35 PM PDT 24
Finished Aug 04 04:56:38 PM PDT 24
Peak memory 225128 kb
Host smart-cca8280b-fddc-4fc6-86c0-7ba133e46070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104120771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4104120771
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2106661999
Short name T593
Test name
Test status
Simulation time 34040078 ps
CPU time 0.88 seconds
Started Aug 04 04:56:31 PM PDT 24
Finished Aug 04 04:56:32 PM PDT 24
Peak memory 207068 kb
Host smart-d4637661-b400-41da-9c25-223e00b83677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106661999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2106661999
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4049935602
Short name T631
Test name
Test status
Simulation time 12857876488 ps
CPU time 58.72 seconds
Started Aug 04 04:56:35 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 251552 kb
Host smart-9c56cec6-a7ce-4b1f-8e0b-07f06b764e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049935602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4049935602
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3017245464
Short name T897
Test name
Test status
Simulation time 54082165352 ps
CPU time 204.73 seconds
Started Aug 04 04:56:36 PM PDT 24
Finished Aug 04 05:00:01 PM PDT 24
Peak memory 250068 kb
Host smart-5a031900-a6d7-4a88-bf57-eeefe65d5813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017245464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3017245464
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3943368043
Short name T398
Test name
Test status
Simulation time 13038769784 ps
CPU time 81.12 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:57:59 PM PDT 24
Peak memory 240072 kb
Host smart-dac201c3-18be-431b-a66d-d968f9a5ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943368043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3943368043
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.24206795
Short name T684
Test name
Test status
Simulation time 732259412 ps
CPU time 5.59 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 233524 kb
Host smart-24ce53ce-706b-4d20-8adf-6272af1f9ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24206795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.24206795
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1219850922
Short name T270
Test name
Test status
Simulation time 62494823084 ps
CPU time 113.3 seconds
Started Aug 04 04:56:37 PM PDT 24
Finished Aug 04 04:58:30 PM PDT 24
Peak memory 249928 kb
Host smart-5b41b3d7-9a54-4a03-abdc-8ee184a46b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219850922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1219850922
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1082237694
Short name T755
Test name
Test status
Simulation time 324358747 ps
CPU time 5.67 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 04:56:47 PM PDT 24
Peak memory 225048 kb
Host smart-77ca15c3-fc75-430e-8710-478ad100b54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082237694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1082237694
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2836273163
Short name T714
Test name
Test status
Simulation time 57289090298 ps
CPU time 28.44 seconds
Started Aug 04 04:56:37 PM PDT 24
Finished Aug 04 04:57:05 PM PDT 24
Peak memory 225196 kb
Host smart-61474fa9-8dd9-4458-bb35-363a3d10ed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836273163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2836273163
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2666835076
Short name T452
Test name
Test status
Simulation time 146242090 ps
CPU time 2.36 seconds
Started Aug 04 04:56:36 PM PDT 24
Finished Aug 04 04:56:38 PM PDT 24
Peak memory 224392 kb
Host smart-afcdc7b1-5474-4bf7-b2ea-1a70a1e7803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666835076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2666835076
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3664126937
Short name T553
Test name
Test status
Simulation time 12145963960 ps
CPU time 10.22 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:56:48 PM PDT 24
Peak memory 233432 kb
Host smart-53038350-ec82-4db8-8392-a6302ab0055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664126937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3664126937
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2462321115
Short name T446
Test name
Test status
Simulation time 1113573109 ps
CPU time 7.55 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 04:56:48 PM PDT 24
Peak memory 220644 kb
Host smart-f16131cc-fc52-4f70-84b4-5bf343591090
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2462321115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2462321115
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2912843337
Short name T19
Test name
Test status
Simulation time 58739432 ps
CPU time 1.09 seconds
Started Aug 04 04:56:36 PM PDT 24
Finished Aug 04 04:56:37 PM PDT 24
Peak memory 207300 kb
Host smart-3d6738bb-705e-4151-978b-60d4ad7cc995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912843337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2912843337
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.337943144
Short name T923
Test name
Test status
Simulation time 10981344700 ps
CPU time 17.53 seconds
Started Aug 04 04:56:35 PM PDT 24
Finished Aug 04 04:56:53 PM PDT 24
Peak memory 217180 kb
Host smart-047ac7a9-b887-4cdb-b88b-4977e651c7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337943144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.337943144
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.539296363
Short name T773
Test name
Test status
Simulation time 702730705 ps
CPU time 4.14 seconds
Started Aug 04 04:56:34 PM PDT 24
Finished Aug 04 04:56:38 PM PDT 24
Peak memory 216860 kb
Host smart-104a2a28-0cfa-416b-9a8a-bbe77dd34a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539296363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.539296363
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3995110600
Short name T990
Test name
Test status
Simulation time 94385263 ps
CPU time 1.16 seconds
Started Aug 04 04:56:36 PM PDT 24
Finished Aug 04 04:56:37 PM PDT 24
Peak memory 208724 kb
Host smart-6595037d-afcb-4413-855d-6642934ae7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995110600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3995110600
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2475449869
Short name T28
Test name
Test status
Simulation time 349693119 ps
CPU time 0.99 seconds
Started Aug 04 04:56:37 PM PDT 24
Finished Aug 04 04:56:38 PM PDT 24
Peak memory 207624 kb
Host smart-537cf784-30c1-44d9-9355-015e1b7781fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475449869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2475449869
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.97929001
Short name T949
Test name
Test status
Simulation time 326615239 ps
CPU time 2.33 seconds
Started Aug 04 04:56:36 PM PDT 24
Finished Aug 04 04:56:38 PM PDT 24
Peak memory 224148 kb
Host smart-1cd2b64d-23a8-4917-afc0-787855520b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97929001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.97929001
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4213973197
Short name T893
Test name
Test status
Simulation time 22975328 ps
CPU time 0.75 seconds
Started Aug 04 04:56:42 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 205852 kb
Host smart-592f0567-b207-40d3-8582-162a7417f4bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213973197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4213973197
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4135241525
Short name T592
Test name
Test status
Simulation time 90297342 ps
CPU time 2.94 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 04:56:44 PM PDT 24
Peak memory 225208 kb
Host smart-66a6012a-a40e-433b-b36c-46d8a3e1df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135241525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4135241525
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1110025199
Short name T981
Test name
Test status
Simulation time 16400453 ps
CPU time 0.8 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 04:56:42 PM PDT 24
Peak memory 207324 kb
Host smart-9b9e01e7-3f6d-45ff-a200-a0295ab48e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110025199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1110025199
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2415400107
Short name T252
Test name
Test status
Simulation time 52494989634 ps
CPU time 221.71 seconds
Started Aug 04 04:56:43 PM PDT 24
Finished Aug 04 05:00:25 PM PDT 24
Peak memory 258000 kb
Host smart-d9d4da09-14f5-4c86-a322-f6c133b85bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415400107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2415400107
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2000995598
Short name T486
Test name
Test status
Simulation time 11396453093 ps
CPU time 109.38 seconds
Started Aug 04 04:56:43 PM PDT 24
Finished Aug 04 04:58:33 PM PDT 24
Peak memory 256412 kb
Host smart-adf05504-b6b2-45fc-9550-9ab4e6db0a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000995598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2000995598
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3151572909
Short name T147
Test name
Test status
Simulation time 7768949337 ps
CPU time 82.86 seconds
Started Aug 04 04:56:44 PM PDT 24
Finished Aug 04 04:58:07 PM PDT 24
Peak memory 257352 kb
Host smart-62681a67-b30e-445f-8453-014fb50dddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151572909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3151572909
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3341298345
Short name T752
Test name
Test status
Simulation time 1351848542 ps
CPU time 17.88 seconds
Started Aug 04 04:56:43 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 234088 kb
Host smart-813ba502-3496-4d5e-b425-5b3bb0bc6078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341298345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3341298345
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.130435774
Short name T308
Test name
Test status
Simulation time 4538676032 ps
CPU time 80.44 seconds
Started Aug 04 04:56:42 PM PDT 24
Finished Aug 04 04:58:03 PM PDT 24
Peak memory 274000 kb
Host smart-fe34db04-29e5-4404-afd5-91188544b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130435774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.130435774
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2811099721
Short name T532
Test name
Test status
Simulation time 15528089087 ps
CPU time 12.75 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:56:51 PM PDT 24
Peak memory 225224 kb
Host smart-2883bc79-cfe6-4530-b9a9-ddab7606d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811099721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2811099721
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3021498431
Short name T869
Test name
Test status
Simulation time 300724695 ps
CPU time 2.16 seconds
Started Aug 04 04:56:39 PM PDT 24
Finished Aug 04 04:56:41 PM PDT 24
Peak memory 223712 kb
Host smart-305dd158-3322-45be-9713-29e790a3f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021498431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3021498431
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2155199594
Short name T303
Test name
Test status
Simulation time 2722433056 ps
CPU time 8.15 seconds
Started Aug 04 04:56:40 PM PDT 24
Finished Aug 04 04:56:48 PM PDT 24
Peak memory 233420 kb
Host smart-cb4a7c4d-5b40-4411-a603-cc2b442f3526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155199594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2155199594
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.926837253
Short name T946
Test name
Test status
Simulation time 37064177435 ps
CPU time 23.62 seconds
Started Aug 04 04:56:39 PM PDT 24
Finished Aug 04 04:57:02 PM PDT 24
Peak memory 233468 kb
Host smart-2479b73d-5620-44d3-91b1-100a44ddde62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926837253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.926837253
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.212178646
Short name T658
Test name
Test status
Simulation time 555005606 ps
CPU time 3.88 seconds
Started Aug 04 04:56:42 PM PDT 24
Finished Aug 04 04:56:46 PM PDT 24
Peak memory 222256 kb
Host smart-24710096-9249-4983-8f9c-7a067f4ca042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212178646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.212178646
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2566702572
Short name T146
Test name
Test status
Simulation time 483537403944 ps
CPU time 395.1 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 05:03:17 PM PDT 24
Peak memory 267368 kb
Host smart-8acddc68-872d-4cc9-a9d0-dd464098f747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566702572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2566702572
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3598936913
Short name T680
Test name
Test status
Simulation time 4337597999 ps
CPU time 33.51 seconds
Started Aug 04 04:56:39 PM PDT 24
Finished Aug 04 04:57:12 PM PDT 24
Peak memory 216916 kb
Host smart-4a3e030a-4e55-45b9-9739-9fd34212a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598936913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3598936913
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3190687743
Short name T947
Test name
Test status
Simulation time 388113562 ps
CPU time 2.9 seconds
Started Aug 04 04:56:40 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 216976 kb
Host smart-5519e7ab-8cbb-4659-8adc-76dcd1a2629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190687743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3190687743
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1250761693
Short name T421
Test name
Test status
Simulation time 154407087 ps
CPU time 2.42 seconds
Started Aug 04 04:56:38 PM PDT 24
Finished Aug 04 04:56:41 PM PDT 24
Peak memory 216904 kb
Host smart-3e4fe606-401b-4f3c-87f2-53ebc1b30ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250761693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1250761693
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.964368968
Short name T916
Test name
Test status
Simulation time 62321608 ps
CPU time 0.79 seconds
Started Aug 04 04:56:40 PM PDT 24
Finished Aug 04 04:56:40 PM PDT 24
Peak memory 206644 kb
Host smart-a02c6d8f-8473-4331-ae4d-9cb4626685a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964368968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.964368968
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2853835171
Short name T629
Test name
Test status
Simulation time 481384511 ps
CPU time 2.52 seconds
Started Aug 04 04:56:43 PM PDT 24
Finished Aug 04 04:56:46 PM PDT 24
Peak memory 233052 kb
Host smart-b23ddda7-b0c2-4427-a0c9-2cf9be65910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853835171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2853835171
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3518626414
Short name T354
Test name
Test status
Simulation time 45336158 ps
CPU time 0.74 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:10 PM PDT 24
Peak memory 205872 kb
Host smart-84083dd7-b0cc-400e-9eca-5a0cdcc62988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518626414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
518626414
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1354536270
Short name T1031
Test name
Test status
Simulation time 2965960291 ps
CPU time 9.35 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:12 PM PDT 24
Peak memory 233492 kb
Host smart-de1c8a08-76d7-4665-8e95-cdcf4feaecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354536270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1354536270
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4258563032
Short name T411
Test name
Test status
Simulation time 63956051 ps
CPU time 0.81 seconds
Started Aug 04 04:53:02 PM PDT 24
Finished Aug 04 04:53:03 PM PDT 24
Peak memory 207416 kb
Host smart-d000d29b-fd34-4764-9f14-b311353460d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258563032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4258563032
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2983076968
Short name T430
Test name
Test status
Simulation time 1918849354 ps
CPU time 16.86 seconds
Started Aug 04 04:53:07 PM PDT 24
Finished Aug 04 04:53:24 PM PDT 24
Peak memory 236836 kb
Host smart-89c74908-bd8d-450e-bcb9-bedfb77e9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983076968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2983076968
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3521440385
Short name T209
Test name
Test status
Simulation time 191259812406 ps
CPU time 646.26 seconds
Started Aug 04 04:53:07 PM PDT 24
Finished Aug 04 05:03:53 PM PDT 24
Peak memory 251912 kb
Host smart-fc98bb35-b457-42e7-8c9e-71a7ef62cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521440385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3521440385
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3976992307
Short name T960
Test name
Test status
Simulation time 14385883240 ps
CPU time 36.94 seconds
Started Aug 04 04:53:07 PM PDT 24
Finished Aug 04 04:53:44 PM PDT 24
Peak memory 218464 kb
Host smart-0050e51e-8e6e-4001-84bd-3d9b72c800d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976992307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3976992307
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2703135177
Short name T582
Test name
Test status
Simulation time 1283389974 ps
CPU time 20.7 seconds
Started Aug 04 04:53:12 PM PDT 24
Finished Aug 04 04:53:33 PM PDT 24
Peak memory 233388 kb
Host smart-6b252bf7-435c-4301-9c86-f218483036da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703135177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2703135177
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3270346228
Short name T642
Test name
Test status
Simulation time 2161574510 ps
CPU time 16.39 seconds
Started Aug 04 04:53:12 PM PDT 24
Finished Aug 04 04:53:28 PM PDT 24
Peak memory 225244 kb
Host smart-a3ae2305-18b8-4691-a97c-1f6c9fcd8532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270346228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3270346228
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1633731553
Short name T465
Test name
Test status
Simulation time 84276792 ps
CPU time 3.81 seconds
Started Aug 04 04:53:04 PM PDT 24
Finished Aug 04 04:53:08 PM PDT 24
Peak memory 233500 kb
Host smart-d538d3c2-3b0d-4d60-8904-da46f5b054ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633731553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1633731553
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3098028946
Short name T208
Test name
Test status
Simulation time 9022506642 ps
CPU time 21.42 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:24 PM PDT 24
Peak memory 234428 kb
Host smart-317e5a3a-26f4-491d-aa45-9338ce7c2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098028946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3098028946
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2604227286
Short name T591
Test name
Test status
Simulation time 24417268 ps
CPU time 1.1 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:04 PM PDT 24
Peak memory 218476 kb
Host smart-e787a7af-4a53-42f7-95bb-481f201a294d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604227286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2604227286
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1967224862
Short name T549
Test name
Test status
Simulation time 4058684048 ps
CPU time 12.54 seconds
Started Aug 04 04:53:05 PM PDT 24
Finished Aug 04 04:53:18 PM PDT 24
Peak memory 233516 kb
Host smart-bc5aeef5-af5e-4833-9856-bcb817d26682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967224862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1967224862
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.39569109
Short name T242
Test name
Test status
Simulation time 17074723659 ps
CPU time 13.75 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:17 PM PDT 24
Peak memory 256876 kb
Host smart-89125639-56cc-4827-98ed-826da0b012e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39569109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.39569109
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1724010998
Short name T382
Test name
Test status
Simulation time 5917434735 ps
CPU time 11.89 seconds
Started Aug 04 04:53:07 PM PDT 24
Finished Aug 04 04:53:19 PM PDT 24
Peak memory 219528 kb
Host smart-e2980def-649e-4a2b-8558-990a83b61eb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1724010998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1724010998
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.983550614
Short name T71
Test name
Test status
Simulation time 204571226 ps
CPU time 1.14 seconds
Started Aug 04 04:53:07 PM PDT 24
Finished Aug 04 04:53:08 PM PDT 24
Peak memory 235828 kb
Host smart-9e484f00-5a20-48a2-8600-fc0c27e9c67d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983550614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.983550614
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2389167085
Short name T214
Test name
Test status
Simulation time 72035463801 ps
CPU time 196.12 seconds
Started Aug 04 04:53:12 PM PDT 24
Finished Aug 04 04:56:29 PM PDT 24
Peak memory 266372 kb
Host smart-8a68a097-965c-4f69-b695-3fd920553d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389167085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2389167085
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.297203324
Short name T796
Test name
Test status
Simulation time 353214712 ps
CPU time 2.96 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:06 PM PDT 24
Peak memory 216856 kb
Host smart-48d071c9-183c-4706-9313-8c751e94315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297203324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.297203324
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1874453441
Short name T624
Test name
Test status
Simulation time 367584900 ps
CPU time 2.96 seconds
Started Aug 04 04:53:00 PM PDT 24
Finished Aug 04 04:53:03 PM PDT 24
Peak memory 216848 kb
Host smart-f73471a6-a8c4-4834-9863-4891e8528cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874453441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1874453441
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2623450987
Short name T546
Test name
Test status
Simulation time 213146857 ps
CPU time 1.39 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:05 PM PDT 24
Peak memory 208580 kb
Host smart-e30449c2-e7ce-491d-9e9c-330106e938c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623450987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2623450987
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1152539199
Short name T449
Test name
Test status
Simulation time 76336885 ps
CPU time 0.75 seconds
Started Aug 04 04:53:03 PM PDT 24
Finished Aug 04 04:53:04 PM PDT 24
Peak memory 206440 kb
Host smart-84436507-7753-4690-8605-9f757dd6ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152539199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1152539199
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.264102428
Short name T285
Test name
Test status
Simulation time 19104299312 ps
CPU time 18.7 seconds
Started Aug 04 04:53:02 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 233540 kb
Host smart-db289941-cc69-4bf0-9c40-d5cfb59ee2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264102428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.264102428
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3778561356
Short name T982
Test name
Test status
Simulation time 71099259 ps
CPU time 0.71 seconds
Started Aug 04 04:56:53 PM PDT 24
Finished Aug 04 04:56:54 PM PDT 24
Peak memory 205296 kb
Host smart-ee1211d2-e0b3-4ddd-8732-ee10035b8efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778561356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3778561356
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2334084926
Short name T676
Test name
Test status
Simulation time 5357530538 ps
CPU time 4.16 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:51 PM PDT 24
Peak memory 225160 kb
Host smart-58e57905-00c2-4790-b8ae-0b4d3f15ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334084926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2334084926
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3600731069
Short name T730
Test name
Test status
Simulation time 68890589 ps
CPU time 0.79 seconds
Started Aug 04 04:56:41 PM PDT 24
Finished Aug 04 04:56:42 PM PDT 24
Peak memory 207316 kb
Host smart-71663a24-dd23-4512-b5d0-86514e2fac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600731069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3600731069
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2561987977
Short name T297
Test name
Test status
Simulation time 2436861878 ps
CPU time 63.39 seconds
Started Aug 04 04:56:50 PM PDT 24
Finished Aug 04 04:57:53 PM PDT 24
Peak memory 265412 kb
Host smart-9409189d-ccba-40e3-9979-a4595b164cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561987977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2561987977
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2251816959
Short name T333
Test name
Test status
Simulation time 2186376663 ps
CPU time 33.71 seconds
Started Aug 04 04:56:50 PM PDT 24
Finished Aug 04 04:57:24 PM PDT 24
Peak memory 233600 kb
Host smart-72cd7f14-89fb-40d2-b000-6c540bcfa4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251816959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2251816959
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.108294237
Short name T326
Test name
Test status
Simulation time 18566159706 ps
CPU time 57.96 seconds
Started Aug 04 04:56:52 PM PDT 24
Finished Aug 04 04:57:50 PM PDT 24
Peak memory 249968 kb
Host smart-106764ce-878f-4261-9a37-dc46fce8630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108294237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.108294237
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.755089501
Short name T689
Test name
Test status
Simulation time 13675136128 ps
CPU time 16.55 seconds
Started Aug 04 04:56:49 PM PDT 24
Finished Aug 04 04:57:05 PM PDT 24
Peak memory 237740 kb
Host smart-df3e8da3-dbd3-4b28-9cb3-f419145a66de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755089501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.755089501
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3869914015
Short name T301
Test name
Test status
Simulation time 13808305298 ps
CPU time 76.72 seconds
Started Aug 04 04:56:48 PM PDT 24
Finished Aug 04 04:58:05 PM PDT 24
Peak memory 252800 kb
Host smart-60a599bb-147b-468a-a220-a40557ae5b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869914015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3869914015
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.930795904
Short name T233
Test name
Test status
Simulation time 1398754648 ps
CPU time 2.29 seconds
Started Aug 04 04:56:45 PM PDT 24
Finished Aug 04 04:56:48 PM PDT 24
Peak memory 225060 kb
Host smart-d92fcc32-c4b1-44cd-ab25-1ea46db96f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930795904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.930795904
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2395136778
Short name T854
Test name
Test status
Simulation time 2342331339 ps
CPU time 7.23 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:53 PM PDT 24
Peak memory 233428 kb
Host smart-554c1824-cea0-4cc1-9844-ba266e72acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395136778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2395136778
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.151017071
Short name T462
Test name
Test status
Simulation time 346304321 ps
CPU time 6.29 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:52 PM PDT 24
Peak memory 225192 kb
Host smart-a00b2f51-2586-4ff9-8223-c71474316c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151017071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.151017071
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4090426128
Short name T975
Test name
Test status
Simulation time 1633050954 ps
CPU time 10.31 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:56 PM PDT 24
Peak memory 233392 kb
Host smart-2511a395-226d-4254-841f-b821e49a333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090426128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4090426128
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2042803629
Short name T741
Test name
Test status
Simulation time 9643161887 ps
CPU time 17.02 seconds
Started Aug 04 04:56:50 PM PDT 24
Finished Aug 04 04:57:07 PM PDT 24
Peak memory 222744 kb
Host smart-b2949539-59ca-4103-9ed3-46f2ec12371a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2042803629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2042803629
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2305443898
Short name T692
Test name
Test status
Simulation time 7236435526 ps
CPU time 111.93 seconds
Started Aug 04 04:56:51 PM PDT 24
Finished Aug 04 04:58:43 PM PDT 24
Peak memory 240200 kb
Host smart-2ab31a39-0e11-4b1a-ad9d-36d545861bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305443898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2305443898
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1688238135
Short name T442
Test name
Test status
Simulation time 6845087609 ps
CPU time 37.72 seconds
Started Aug 04 04:56:48 PM PDT 24
Finished Aug 04 04:57:25 PM PDT 24
Peak memory 217292 kb
Host smart-a2185a4b-fa78-4840-b801-b3a1cac7cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688238135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1688238135
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.305928186
Short name T540
Test name
Test status
Simulation time 6873193678 ps
CPU time 20.87 seconds
Started Aug 04 04:56:42 PM PDT 24
Finished Aug 04 04:57:03 PM PDT 24
Peak memory 216876 kb
Host smart-6728ce35-41a5-4c4a-95ef-ed415843e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305928186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.305928186
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3889197958
Short name T889
Test name
Test status
Simulation time 261468477 ps
CPU time 4.79 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:51 PM PDT 24
Peak memory 217000 kb
Host smart-1138d63b-17f8-42d0-85fb-eb6f2e102c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889197958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3889197958
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3486902710
Short name T375
Test name
Test status
Simulation time 128652783 ps
CPU time 0.92 seconds
Started Aug 04 04:56:45 PM PDT 24
Finished Aug 04 04:56:46 PM PDT 24
Peak memory 206580 kb
Host smart-26f3f009-b5d6-406c-803b-08a42c56120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486902710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3486902710
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2978486243
Short name T62
Test name
Test status
Simulation time 398444884 ps
CPU time 4.86 seconds
Started Aug 04 04:56:46 PM PDT 24
Finished Aug 04 04:56:51 PM PDT 24
Peak memory 225188 kb
Host smart-2cc146a8-ea97-431d-b1f2-d24da26243f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978486243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2978486243
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1620101661
Short name T647
Test name
Test status
Simulation time 17147777 ps
CPU time 0.68 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:56:57 PM PDT 24
Peak memory 205304 kb
Host smart-e5383ea5-6a3e-43cf-a1de-81cfb15f4eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620101661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1620101661
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2048011159
Short name T732
Test name
Test status
Simulation time 130079209 ps
CPU time 3.55 seconds
Started Aug 04 04:56:57 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 233348 kb
Host smart-46c405eb-1850-458a-afb7-5a9650f11869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048011159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2048011159
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.795530211
Short name T576
Test name
Test status
Simulation time 18024863 ps
CPU time 0.8 seconds
Started Aug 04 04:56:49 PM PDT 24
Finished Aug 04 04:56:50 PM PDT 24
Peak memory 205976 kb
Host smart-06580665-e2b4-40fb-8a7f-b71edd6c11a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795530211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.795530211
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.981862428
Short name T480
Test name
Test status
Simulation time 60855114931 ps
CPU time 212.91 seconds
Started Aug 04 04:56:54 PM PDT 24
Finished Aug 04 05:00:27 PM PDT 24
Peak memory 249840 kb
Host smart-8e71d650-e5a1-4531-84f8-7324021daf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981862428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.981862428
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3632911962
Short name T53
Test name
Test status
Simulation time 3219180214 ps
CPU time 35.92 seconds
Started Aug 04 04:56:51 PM PDT 24
Finished Aug 04 04:57:27 PM PDT 24
Peak memory 239072 kb
Host smart-f457d099-2d79-4027-9401-de482e5538a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632911962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3632911962
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3985175464
Short name T223
Test name
Test status
Simulation time 55644639567 ps
CPU time 210.26 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 05:00:25 PM PDT 24
Peak memory 256972 kb
Host smart-f80905db-0945-461f-892e-e20a23adf83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985175464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3985175464
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3518353057
Short name T767
Test name
Test status
Simulation time 1243426904 ps
CPU time 20.82 seconds
Started Aug 04 04:56:54 PM PDT 24
Finished Aug 04 04:57:15 PM PDT 24
Peak memory 225280 kb
Host smart-41769732-63d6-438d-ada9-f1f943a09849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518353057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3518353057
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2447787580
Short name T193
Test name
Test status
Simulation time 28420763907 ps
CPU time 181.63 seconds
Started Aug 04 04:56:54 PM PDT 24
Finished Aug 04 04:59:56 PM PDT 24
Peak memory 250608 kb
Host smart-641abab6-a036-42a4-b71c-cd1b72f56464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447787580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2447787580
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.901977208
Short name T450
Test name
Test status
Simulation time 2115036926 ps
CPU time 4.67 seconds
Started Aug 04 04:56:54 PM PDT 24
Finished Aug 04 04:56:59 PM PDT 24
Peak memory 233360 kb
Host smart-15480b20-8b4c-4901-913d-eed2eba3bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901977208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.901977208
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2168945873
Short name T389
Test name
Test status
Simulation time 5383455506 ps
CPU time 31.3 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 249348 kb
Host smart-1f3c11aa-97a4-4d9b-8a20-d08240ba78b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168945873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2168945873
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2944171159
Short name T746
Test name
Test status
Simulation time 19813501366 ps
CPU time 30.2 seconds
Started Aug 04 04:56:52 PM PDT 24
Finished Aug 04 04:57:22 PM PDT 24
Peak memory 225228 kb
Host smart-03f04315-0f1f-4236-beb2-f7e47d79364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944171159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2944171159
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.450682505
Short name T996
Test name
Test status
Simulation time 10323328425 ps
CPU time 13.29 seconds
Started Aug 04 04:56:51 PM PDT 24
Finished Aug 04 04:57:05 PM PDT 24
Peak memory 225228 kb
Host smart-ab1214db-d49e-4510-98f1-f8ec8aa297ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450682505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.450682505
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.76646296
Short name T482
Test name
Test status
Simulation time 2864186290 ps
CPU time 14.68 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:57:11 PM PDT 24
Peak memory 223824 kb
Host smart-436ee5bc-3dab-4e3a-96e1-b0518f698468
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76646296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.76646296
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4032923028
Short name T804
Test name
Test status
Simulation time 19210521387 ps
CPU time 38.34 seconds
Started Aug 04 04:56:54 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 241828 kb
Host smart-eabfbd5e-52c4-49f9-be81-1b179130c7cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032923028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4032923028
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2205161181
Short name T874
Test name
Test status
Simulation time 11779821 ps
CPU time 0.75 seconds
Started Aug 04 04:56:51 PM PDT 24
Finished Aug 04 04:56:52 PM PDT 24
Peak memory 206216 kb
Host smart-b31a0802-6e30-4c7a-84dd-4602e09ab6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205161181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2205161181
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.460225114
Short name T1028
Test name
Test status
Simulation time 3581164265 ps
CPU time 4.98 seconds
Started Aug 04 04:56:51 PM PDT 24
Finished Aug 04 04:56:56 PM PDT 24
Peak memory 216904 kb
Host smart-4d80a377-c34f-4a4e-b20b-5637e2621802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460225114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.460225114
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.932107629
Short name T803
Test name
Test status
Simulation time 484438284 ps
CPU time 4.52 seconds
Started Aug 04 04:56:50 PM PDT 24
Finished Aug 04 04:56:55 PM PDT 24
Peak memory 216984 kb
Host smart-3cf11595-817d-4612-a9b0-9c1858e07e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932107629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.932107629
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3375640460
Short name T175
Test name
Test status
Simulation time 1037319513 ps
CPU time 1.04 seconds
Started Aug 04 04:56:52 PM PDT 24
Finished Aug 04 04:56:53 PM PDT 24
Peak memory 207664 kb
Host smart-030ddfcc-3b2d-46c0-a658-0fbf544ec38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375640460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3375640460
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1547240896
Short name T291
Test name
Test status
Simulation time 633848627 ps
CPU time 3.81 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 225300 kb
Host smart-836d1ac7-3d93-4252-86d4-54f022b15bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547240896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1547240896
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.754256354
Short name T59
Test name
Test status
Simulation time 17909661 ps
CPU time 0.7 seconds
Started Aug 04 04:57:00 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 205780 kb
Host smart-ad5e35bb-30a8-4473-ae1c-36d004a249c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754256354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.754256354
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.492360456
Short name T456
Test name
Test status
Simulation time 35896870 ps
CPU time 2.48 seconds
Started Aug 04 04:56:57 PM PDT 24
Finished Aug 04 04:56:59 PM PDT 24
Peak memory 233392 kb
Host smart-a471d52b-bef7-4142-8a26-39d60ee1e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492360456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.492360456
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3439454293
Short name T493
Test name
Test status
Simulation time 31901030 ps
CPU time 0.8 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 04:56:55 PM PDT 24
Peak memory 207132 kb
Host smart-797687f3-12ef-4133-8ab1-2e0f0c0588f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439454293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3439454293
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.342528878
Short name T1035
Test name
Test status
Simulation time 3586558900 ps
CPU time 43.97 seconds
Started Aug 04 04:56:57 PM PDT 24
Finished Aug 04 04:57:41 PM PDT 24
Peak memory 249808 kb
Host smart-35005dc3-ac09-4a0b-a388-97adfed9d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342528878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.342528878
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3008818454
Short name T43
Test name
Test status
Simulation time 27112823925 ps
CPU time 254.83 seconds
Started Aug 04 04:57:00 PM PDT 24
Finished Aug 04 05:01:15 PM PDT 24
Peak memory 266328 kb
Host smart-ff62017a-0414-4a0c-9782-243f15b54c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008818454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3008818454
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.796631244
Short name T288
Test name
Test status
Simulation time 2786872782 ps
CPU time 60.61 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 04:57:55 PM PDT 24
Peak memory 258028 kb
Host smart-9a23ac30-a8dd-4609-8bf5-b887d3e03d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796631244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.796631244
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.259941691
Short name T964
Test name
Test status
Simulation time 1633930174 ps
CPU time 26.62 seconds
Started Aug 04 04:56:55 PM PDT 24
Finished Aug 04 04:57:22 PM PDT 24
Peak memory 233488 kb
Host smart-f679228d-9a04-4401-b497-db6e46bfe88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259941691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.259941691
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3647534200
Short name T198
Test name
Test status
Simulation time 54045610761 ps
CPU time 395.77 seconds
Started Aug 04 04:57:03 PM PDT 24
Finished Aug 04 05:03:39 PM PDT 24
Peak memory 257420 kb
Host smart-8cd97928-467f-46a2-a26e-50541897cd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647534200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3647534200
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3910824857
Short name T464
Test name
Test status
Simulation time 77755871 ps
CPU time 2.13 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 223708 kb
Host smart-f91030ce-b7ef-4700-9a64-6c83704bb316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910824857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3910824857
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.96928109
Short name T622
Test name
Test status
Simulation time 7947336037 ps
CPU time 43.96 seconds
Started Aug 04 04:57:00 PM PDT 24
Finished Aug 04 04:57:44 PM PDT 24
Peak memory 233432 kb
Host smart-924ecf66-7142-4235-8e57-3cd858766d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96928109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.96928109
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2779060740
Short name T277
Test name
Test status
Simulation time 3353397756 ps
CPU time 10.66 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:57:07 PM PDT 24
Peak memory 233552 kb
Host smart-8c897345-c810-4bea-a141-fa2cb248405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779060740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2779060740
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2428075420
Short name T637
Test name
Test status
Simulation time 129414923 ps
CPU time 3.28 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:56:59 PM PDT 24
Peak memory 233700 kb
Host smart-7e6a714c-55d0-4426-bfb4-393d55913a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428075420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2428075420
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3369111258
Short name T523
Test name
Test status
Simulation time 10202947989 ps
CPU time 17.23 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:57:13 PM PDT 24
Peak memory 220092 kb
Host smart-8466040e-94b3-49b2-a365-6806cf4f8e6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3369111258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3369111258
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3245300989
Short name T902
Test name
Test status
Simulation time 1492872941 ps
CPU time 24.6 seconds
Started Aug 04 04:57:01 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 218200 kb
Host smart-adc166d8-d2b4-4374-be32-2cadb26442cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245300989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3245300989
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1384898139
Short name T867
Test name
Test status
Simulation time 6151601632 ps
CPU time 25.79 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:28 PM PDT 24
Peak memory 221272 kb
Host smart-4dd9532c-aeb2-4d6c-b967-c26ce30253ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384898139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1384898139
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.704435864
Short name T841
Test name
Test status
Simulation time 3631199218 ps
CPU time 6.15 seconds
Started Aug 04 04:56:52 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 217040 kb
Host smart-1bb2159d-0559-490c-98ef-53d364d01ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704435864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.704435864
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1788028754
Short name T672
Test name
Test status
Simulation time 78403722 ps
CPU time 1.01 seconds
Started Aug 04 04:56:57 PM PDT 24
Finished Aug 04 04:56:58 PM PDT 24
Peak memory 207524 kb
Host smart-d75fc08c-6f1e-4f79-9d99-f9ed04501033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788028754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1788028754
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2184558021
Short name T805
Test name
Test status
Simulation time 57804851 ps
CPU time 0.92 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:03 PM PDT 24
Peak memory 206512 kb
Host smart-c66ea848-b401-44c6-b857-94c638a84799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184558021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2184558021
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3776940862
Short name T850
Test name
Test status
Simulation time 17380889530 ps
CPU time 24.1 seconds
Started Aug 04 04:57:00 PM PDT 24
Finished Aug 04 04:57:24 PM PDT 24
Peak memory 231104 kb
Host smart-52dc26c7-2c22-4608-b9be-a7861bdb6aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776940862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3776940862
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1583796197
Short name T476
Test name
Test status
Simulation time 27645529 ps
CPU time 0.75 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:06 PM PDT 24
Peak memory 205300 kb
Host smart-65e402e0-f7f1-4da4-b0ff-27bd92f202ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583796197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1583796197
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3983905001
Short name T666
Test name
Test status
Simulation time 33481521 ps
CPU time 2.46 seconds
Started Aug 04 04:57:01 PM PDT 24
Finished Aug 04 04:57:04 PM PDT 24
Peak memory 225180 kb
Host smart-de6149c2-11fe-4c88-a9d7-bd3ead40d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983905001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3983905001
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1764173498
Short name T890
Test name
Test status
Simulation time 50309089 ps
CPU time 0.78 seconds
Started Aug 04 04:56:56 PM PDT 24
Finished Aug 04 04:56:57 PM PDT 24
Peak memory 206056 kb
Host smart-d722e6d6-e50c-41af-b0b6-33e8305751e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764173498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1764173498
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.263981152
Short name T199
Test name
Test status
Simulation time 1727410810 ps
CPU time 12.09 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:14 PM PDT 24
Peak memory 233328 kb
Host smart-e2a81448-1141-48ba-9ecb-fdd7b47cd5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263981152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.263981152
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4241495228
Short name T328
Test name
Test status
Simulation time 50009373053 ps
CPU time 44.74 seconds
Started Aug 04 04:57:04 PM PDT 24
Finished Aug 04 04:57:49 PM PDT 24
Peak memory 225276 kb
Host smart-d398eb64-3d5e-4861-9f03-98b747cb4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241495228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4241495228
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2082619796
Short name T639
Test name
Test status
Simulation time 1813338931 ps
CPU time 7.13 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:09 PM PDT 24
Peak memory 233528 kb
Host smart-101499ad-1ed0-4924-8471-32a20df46579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082619796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2082619796
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1911048851
Short name T539
Test name
Test status
Simulation time 125449083 ps
CPU time 3.55 seconds
Started Aug 04 04:57:01 PM PDT 24
Finished Aug 04 04:57:05 PM PDT 24
Peak memory 225132 kb
Host smart-5607b267-b7a2-4e3f-9df9-91e2755a6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911048851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1911048851
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.770706958
Short name T887
Test name
Test status
Simulation time 58848117 ps
CPU time 0.83 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:03 PM PDT 24
Peak memory 216376 kb
Host smart-fb85449d-cb93-4775-a696-b8dcfe018070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770706958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.770706958
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3970703096
Short name T251
Test name
Test status
Simulation time 658100006 ps
CPU time 7.81 seconds
Started Aug 04 04:56:59 PM PDT 24
Finished Aug 04 04:57:07 PM PDT 24
Peak memory 225132 kb
Host smart-f531f8f6-1672-4189-8176-04bf7e790caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970703096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3970703096
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1192524598
Short name T263
Test name
Test status
Simulation time 26750713612 ps
CPU time 75.89 seconds
Started Aug 04 04:56:59 PM PDT 24
Finished Aug 04 04:58:15 PM PDT 24
Peak memory 249840 kb
Host smart-0070db28-e9a6-4d54-9245-1e811f9d36d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192524598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1192524598
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.905731036
Short name T407
Test name
Test status
Simulation time 710637727 ps
CPU time 4.89 seconds
Started Aug 04 04:56:57 PM PDT 24
Finished Aug 04 04:57:02 PM PDT 24
Peak memory 233460 kb
Host smart-227489a4-a940-4bc0-8b46-a5321a8234e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905731036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.905731036
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1047626694
Short name T770
Test name
Test status
Simulation time 357390636 ps
CPU time 3.23 seconds
Started Aug 04 04:56:58 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 233552 kb
Host smart-f8a6d1e0-fd9b-4c39-a945-db76f32c6241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047626694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1047626694
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2698852593
Short name T153
Test name
Test status
Simulation time 2247969958 ps
CPU time 26.9 seconds
Started Aug 04 04:57:03 PM PDT 24
Finished Aug 04 04:57:30 PM PDT 24
Peak memory 219964 kb
Host smart-c93ff612-e8e7-4595-98f8-be6c851e0a0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698852593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2698852593
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2504938414
Short name T317
Test name
Test status
Simulation time 6668503443 ps
CPU time 96.87 seconds
Started Aug 04 04:57:04 PM PDT 24
Finished Aug 04 04:58:41 PM PDT 24
Peak memory 257992 kb
Host smart-0b47a40d-4ab2-47b0-9633-4cbce21876aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504938414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2504938414
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2371183921
Short name T335
Test name
Test status
Simulation time 11326511343 ps
CPU time 18.62 seconds
Started Aug 04 04:56:59 PM PDT 24
Finished Aug 04 04:57:18 PM PDT 24
Peak memory 216900 kb
Host smart-3ac3179c-02d1-460c-a956-e7c703ed00ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371183921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2371183921
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2301525191
Short name T3
Test name
Test status
Simulation time 483032645 ps
CPU time 1.64 seconds
Started Aug 04 04:56:59 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 208456 kb
Host smart-589d614d-f762-46fa-908f-b5898bd3cea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301525191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2301525191
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1669368929
Short name T903
Test name
Test status
Simulation time 985614717 ps
CPU time 4.27 seconds
Started Aug 04 04:56:58 PM PDT 24
Finished Aug 04 04:57:02 PM PDT 24
Peak memory 216968 kb
Host smart-b2340180-74ec-42af-964f-621657bbe60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669368929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1669368929
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.600855424
Short name T405
Test name
Test status
Simulation time 101728597 ps
CPU time 0.91 seconds
Started Aug 04 04:57:00 PM PDT 24
Finished Aug 04 04:57:01 PM PDT 24
Peak memory 207548 kb
Host smart-9c1be005-82e4-4349-9e5a-f38d748a5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600855424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.600855424
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3352822957
Short name T531
Test name
Test status
Simulation time 216726754 ps
CPU time 3.29 seconds
Started Aug 04 04:56:59 PM PDT 24
Finished Aug 04 04:57:02 PM PDT 24
Peak memory 233352 kb
Host smart-dfc8c5fd-2771-4258-af04-c0be8a5708a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352822957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3352822957
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2227037436
Short name T558
Test name
Test status
Simulation time 54237534 ps
CPU time 0.75 seconds
Started Aug 04 04:57:11 PM PDT 24
Finished Aug 04 04:57:11 PM PDT 24
Peak memory 206216 kb
Host smart-49a512a1-f631-4dfc-97a7-68ea44262946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227037436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2227037436
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.540742069
Short name T635
Test name
Test status
Simulation time 91822372 ps
CPU time 2.88 seconds
Started Aug 04 04:57:07 PM PDT 24
Finished Aug 04 04:57:10 PM PDT 24
Peak memory 233380 kb
Host smart-d3828981-399a-410b-8e0b-2f283ee31f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540742069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.540742069
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1360515969
Short name T933
Test name
Test status
Simulation time 53511465 ps
CPU time 0.8 seconds
Started Aug 04 04:57:02 PM PDT 24
Finished Aug 04 04:57:03 PM PDT 24
Peak memory 207236 kb
Host smart-d60a06e5-7357-4680-aaac-61519a721a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360515969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1360515969
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1824327691
Short name T619
Test name
Test status
Simulation time 2086271072 ps
CPU time 11.84 seconds
Started Aug 04 04:57:07 PM PDT 24
Finished Aug 04 04:57:19 PM PDT 24
Peak memory 240116 kb
Host smart-dace23d2-6264-4be3-be65-981af45bb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824327691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1824327691
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2092603673
Short name T48
Test name
Test status
Simulation time 57914316105 ps
CPU time 275.27 seconds
Started Aug 04 04:57:10 PM PDT 24
Finished Aug 04 05:01:45 PM PDT 24
Peak memory 257804 kb
Host smart-bc4012db-3e0b-4d93-9a09-2210bff1ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092603673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2092603673
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.989715623
Short name T749
Test name
Test status
Simulation time 99617004971 ps
CPU time 502.08 seconds
Started Aug 04 04:57:08 PM PDT 24
Finished Aug 04 05:05:30 PM PDT 24
Peak memory 266372 kb
Host smart-91574b8a-8b25-45e8-ac54-44117aede805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989715623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.989715623
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.829965513
Short name T515
Test name
Test status
Simulation time 7453412007 ps
CPU time 9.28 seconds
Started Aug 04 04:57:04 PM PDT 24
Finished Aug 04 04:57:13 PM PDT 24
Peak memory 233472 kb
Host smart-b0adf3ef-f027-4c88-8ce6-541b444b0cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829965513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.829965513
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.897860873
Short name T985
Test name
Test status
Simulation time 20017038274 ps
CPU time 66.53 seconds
Started Aug 04 04:57:08 PM PDT 24
Finished Aug 04 04:58:15 PM PDT 24
Peak memory 233432 kb
Host smart-647be023-d58d-468a-a320-09f98f356f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897860873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.897860873
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.17984868
Short name T264
Test name
Test status
Simulation time 130966873 ps
CPU time 3.31 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:08 PM PDT 24
Peak memory 225484 kb
Host smart-ccc5d42e-1a82-4121-aff2-9308d420c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17984868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.17984868
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1877735138
Short name T557
Test name
Test status
Simulation time 1999479781 ps
CPU time 20.91 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 233508 kb
Host smart-563e1454-470a-49e6-8bc5-a4ca1454d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877735138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1877735138
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1508427028
Short name T502
Test name
Test status
Simulation time 21555902300 ps
CPU time 15.13 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:20 PM PDT 24
Peak memory 241696 kb
Host smart-a4de1873-b8d2-4b11-a05a-7948f0f4ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508427028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1508427028
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1267723696
Short name T693
Test name
Test status
Simulation time 30137811 ps
CPU time 2.38 seconds
Started Aug 04 04:57:06 PM PDT 24
Finished Aug 04 04:57:08 PM PDT 24
Peak memory 233156 kb
Host smart-7b6065c5-94b4-46d9-9219-a7a41023c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267723696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1267723696
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.146758534
Short name T665
Test name
Test status
Simulation time 5071637447 ps
CPU time 13.27 seconds
Started Aug 04 04:57:08 PM PDT 24
Finished Aug 04 04:57:22 PM PDT 24
Peak memory 223268 kb
Host smart-d95c77cc-446f-4aef-94dc-e0c10334b2db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=146758534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.146758534
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1051568016
Short name T54
Test name
Test status
Simulation time 47502593312 ps
CPU time 299.37 seconds
Started Aug 04 04:57:08 PM PDT 24
Finished Aug 04 05:02:07 PM PDT 24
Peak memory 268876 kb
Host smart-c07c5c2d-a9c0-481f-9a08-fdf7080dc541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051568016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1051568016
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3105058644
Short name T429
Test name
Test status
Simulation time 2569200367 ps
CPU time 32.4 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:37 PM PDT 24
Peak memory 217116 kb
Host smart-b2bcd39b-ac76-4af2-8632-43c628024aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105058644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3105058644
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3379378315
Short name T365
Test name
Test status
Simulation time 4955140826 ps
CPU time 7.87 seconds
Started Aug 04 04:57:07 PM PDT 24
Finished Aug 04 04:57:15 PM PDT 24
Peak memory 217028 kb
Host smart-6504d5b7-902d-43e9-96f2-4fb28da958f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379378315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3379378315
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1127281822
Short name T377
Test name
Test status
Simulation time 29024208 ps
CPU time 0.68 seconds
Started Aug 04 04:57:07 PM PDT 24
Finished Aug 04 04:57:08 PM PDT 24
Peak memory 206092 kb
Host smart-27df6ce3-75b5-4555-a6db-e65339640ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127281822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1127281822
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.875335715
Short name T704
Test name
Test status
Simulation time 86920649 ps
CPU time 0.8 seconds
Started Aug 04 04:57:06 PM PDT 24
Finished Aug 04 04:57:07 PM PDT 24
Peak memory 206536 kb
Host smart-3db0cb28-1e52-426f-a799-c1220dad705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875335715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.875335715
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2389656366
Short name T47
Test name
Test status
Simulation time 5123890672 ps
CPU time 12.94 seconds
Started Aug 04 04:57:05 PM PDT 24
Finished Aug 04 04:57:18 PM PDT 24
Peak memory 236740 kb
Host smart-113ce266-dc70-4f23-bde7-d52eb5395168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389656366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2389656366
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.485012211
Short name T726
Test name
Test status
Simulation time 109276061 ps
CPU time 0.75 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:16 PM PDT 24
Peak memory 205200 kb
Host smart-e473037e-7f07-452a-94ca-d4b02f620312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485012211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.485012211
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4069882146
Short name T530
Test name
Test status
Simulation time 2278107659 ps
CPU time 7.28 seconds
Started Aug 04 04:57:17 PM PDT 24
Finished Aug 04 04:57:24 PM PDT 24
Peak memory 225292 kb
Host smart-f9db3d74-431d-4bcb-b99e-44db8bd1c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069882146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4069882146
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.33508285
Short name T477
Test name
Test status
Simulation time 22247357 ps
CPU time 0.77 seconds
Started Aug 04 04:57:11 PM PDT 24
Finished Aug 04 04:57:11 PM PDT 24
Peak memory 206976 kb
Host smart-8b2be50b-8b50-4d01-a908-a0670e3b2f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33508285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.33508285
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2115277634
Short name T547
Test name
Test status
Simulation time 1775055623 ps
CPU time 35.06 seconds
Started Aug 04 04:57:14 PM PDT 24
Finished Aug 04 04:57:49 PM PDT 24
Peak memory 249752 kb
Host smart-ebff2cb6-9a00-451d-9863-ad09a803106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115277634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2115277634
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1189967942
Short name T966
Test name
Test status
Simulation time 9468601394 ps
CPU time 170.87 seconds
Started Aug 04 04:57:14 PM PDT 24
Finished Aug 04 05:00:05 PM PDT 24
Peak memory 273996 kb
Host smart-fba1d5d2-7d6c-4870-b7cd-2aaeabc25a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189967942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1189967942
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1556072176
Short name T695
Test name
Test status
Simulation time 4278926992 ps
CPU time 22.88 seconds
Started Aug 04 04:57:17 PM PDT 24
Finished Aug 04 04:57:40 PM PDT 24
Peak memory 225248 kb
Host smart-a9e44491-539f-47d1-849a-e4c75e31af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556072176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1556072176
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.392874357
Short name T956
Test name
Test status
Simulation time 4447599166 ps
CPU time 60.73 seconds
Started Aug 04 04:57:15 PM PDT 24
Finished Aug 04 04:58:16 PM PDT 24
Peak memory 233436 kb
Host smart-08ecae8d-e5fb-4f4f-b3ff-62259edd55f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392874357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.392874357
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3551203313
Short name T499
Test name
Test status
Simulation time 15724560 ps
CPU time 0.81 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:16 PM PDT 24
Peak memory 216488 kb
Host smart-8935a33d-1660-48e7-b3dd-05a919e3d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551203313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3551203313
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.762482378
Short name T203
Test name
Test status
Simulation time 1192184101 ps
CPU time 4.83 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:21 PM PDT 24
Peak memory 225220 kb
Host smart-09cf3435-c4b3-4fda-a602-981445985742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762482378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.762482378
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2309327037
Short name T481
Test name
Test status
Simulation time 2854370075 ps
CPU time 7.7 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:24 PM PDT 24
Peak memory 233404 kb
Host smart-64cf7576-5cd4-4bf7-88b3-0f22191afdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309327037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2309327037
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2455039386
Short name T445
Test name
Test status
Simulation time 1960695289 ps
CPU time 11.03 seconds
Started Aug 04 04:57:15 PM PDT 24
Finished Aug 04 04:57:27 PM PDT 24
Peak memory 219360 kb
Host smart-16ed097b-0f8b-47c6-91e3-3a7d163a7e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455039386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2455039386
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2095135187
Short name T598
Test name
Test status
Simulation time 13998730278 ps
CPU time 19.91 seconds
Started Aug 04 04:57:11 PM PDT 24
Finished Aug 04 04:57:31 PM PDT 24
Peak memory 237852 kb
Host smart-119e36db-6a9f-41b9-9aea-d925b05dee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095135187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2095135187
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2286017832
Short name T157
Test name
Test status
Simulation time 209955676 ps
CPU time 5.06 seconds
Started Aug 04 04:57:15 PM PDT 24
Finished Aug 04 04:57:20 PM PDT 24
Peak memory 220948 kb
Host smart-a9a43ee5-3f68-425e-b1d4-843ac92463a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2286017832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2286017832
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.450796379
Short name T1012
Test name
Test status
Simulation time 192433547 ps
CPU time 1.07 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:18 PM PDT 24
Peak memory 207056 kb
Host smart-25596be7-1f2e-4190-99f7-91d46004c152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450796379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.450796379
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1382710616
Short name T609
Test name
Test status
Simulation time 6420878104 ps
CPU time 34.52 seconds
Started Aug 04 04:57:11 PM PDT 24
Finished Aug 04 04:57:45 PM PDT 24
Peak memory 217052 kb
Host smart-d67c9122-8cb9-4887-9709-3459e3ad83f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382710616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1382710616
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2788990995
Short name T479
Test name
Test status
Simulation time 1992346412 ps
CPU time 5.41 seconds
Started Aug 04 04:57:12 PM PDT 24
Finished Aug 04 04:57:18 PM PDT 24
Peak memory 216916 kb
Host smart-23cd4239-ea4f-4152-a1e0-ea2b8c8ffda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788990995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2788990995
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1836592282
Short name T172
Test name
Test status
Simulation time 446596017 ps
CPU time 1.4 seconds
Started Aug 04 04:57:12 PM PDT 24
Finished Aug 04 04:57:13 PM PDT 24
Peak memory 216908 kb
Host smart-a02a371c-c990-40e9-bdd5-48b9bfde6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836592282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1836592282
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1299882511
Short name T503
Test name
Test status
Simulation time 142940130 ps
CPU time 0.92 seconds
Started Aug 04 04:57:12 PM PDT 24
Finished Aug 04 04:57:13 PM PDT 24
Peak memory 206564 kb
Host smart-2fedc855-9d52-4de0-aee7-a41e5a0e92e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299882511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1299882511
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1610863883
Short name T384
Test name
Test status
Simulation time 9061614494 ps
CPU time 10.43 seconds
Started Aug 04 04:57:16 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 225148 kb
Host smart-aee4c8d6-b139-436f-b11c-1ec9f1b69adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610863883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1610863883
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.425623600
Short name T602
Test name
Test status
Simulation time 26890418 ps
CPU time 0.74 seconds
Started Aug 04 04:57:22 PM PDT 24
Finished Aug 04 04:57:23 PM PDT 24
Peak memory 205760 kb
Host smart-c52e9b4d-2aec-420e-9ca6-d1322840fd7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425623600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.425623600
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1560437744
Short name T1008
Test name
Test status
Simulation time 733654020 ps
CPU time 10.38 seconds
Started Aug 04 04:57:23 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 233340 kb
Host smart-bd5dab0f-1731-41fa-94ce-2a424cc87091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560437744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1560437744
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1838555815
Short name T534
Test name
Test status
Simulation time 19952796 ps
CPU time 0.81 seconds
Started Aug 04 04:57:19 PM PDT 24
Finished Aug 04 04:57:20 PM PDT 24
Peak memory 207012 kb
Host smart-d509f9eb-b0b7-451c-af11-fb6f638748ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838555815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1838555815
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2977307240
Short name T227
Test name
Test status
Simulation time 58581116613 ps
CPU time 60.02 seconds
Started Aug 04 04:57:24 PM PDT 24
Finished Aug 04 04:58:24 PM PDT 24
Peak memory 252520 kb
Host smart-df24c88f-512c-437c-9334-3e28b49f647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977307240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2977307240
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2670376636
Short name T944
Test name
Test status
Simulation time 20469290804 ps
CPU time 128.68 seconds
Started Aug 04 04:57:22 PM PDT 24
Finished Aug 04 04:59:31 PM PDT 24
Peak memory 270604 kb
Host smart-fb37d890-6cea-4271-826b-59e16ac83653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670376636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2670376636
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3552805260
Short name T13
Test name
Test status
Simulation time 28756530619 ps
CPU time 71.14 seconds
Started Aug 04 04:57:21 PM PDT 24
Finished Aug 04 04:58:32 PM PDT 24
Peak memory 265424 kb
Host smart-1a089ac0-5532-41cf-850b-1e16a63eab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552805260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3552805260
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.456270812
Short name T431
Test name
Test status
Simulation time 40054474652 ps
CPU time 41.14 seconds
Started Aug 04 04:57:23 PM PDT 24
Finished Aug 04 04:58:04 PM PDT 24
Peak memory 225344 kb
Host smart-8911f9bf-4a41-4207-9fcf-98e17fa4b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456270812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.456270812
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.744083615
Short name T38
Test name
Test status
Simulation time 237375032 ps
CPU time 4.81 seconds
Started Aug 04 04:57:23 PM PDT 24
Finished Aug 04 04:57:28 PM PDT 24
Peak memory 233484 kb
Host smart-56f378c7-3661-4500-a9b3-0119063e6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744083615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.744083615
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1047429372
Short name T957
Test name
Test status
Simulation time 270652345 ps
CPU time 5.78 seconds
Started Aug 04 04:57:19 PM PDT 24
Finished Aug 04 04:57:25 PM PDT 24
Peak memory 233340 kb
Host smart-89bcfe55-21be-4111-ab0c-0cf45b0f4b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047429372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1047429372
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2196849430
Short name T461
Test name
Test status
Simulation time 596594263 ps
CPU time 9.25 seconds
Started Aug 04 04:57:20 PM PDT 24
Finished Aug 04 04:57:29 PM PDT 24
Peak memory 233388 kb
Host smart-2d23c414-a332-4442-9ef7-8ee534277277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196849430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2196849430
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3486260185
Short name T249
Test name
Test status
Simulation time 15727609010 ps
CPU time 18.42 seconds
Started Aug 04 04:57:21 PM PDT 24
Finished Aug 04 04:57:39 PM PDT 24
Peak memory 233492 kb
Host smart-52af5e22-7b93-4dc3-8ef2-6ca37634f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486260185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3486260185
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4006678242
Short name T341
Test name
Test status
Simulation time 163596117 ps
CPU time 2.13 seconds
Started Aug 04 04:57:19 PM PDT 24
Finished Aug 04 04:57:21 PM PDT 24
Peak memory 224248 kb
Host smart-dfc00acd-3a08-40ff-9f1a-5fada646d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006678242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4006678242
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3977630106
Short name T677
Test name
Test status
Simulation time 2709979527 ps
CPU time 10.02 seconds
Started Aug 04 04:57:22 PM PDT 24
Finished Aug 04 04:57:32 PM PDT 24
Peak memory 221424 kb
Host smart-94a1e954-e3ff-4fe4-aa1f-4efb86fc2a6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977630106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3977630106
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.702212609
Short name T522
Test name
Test status
Simulation time 45533298 ps
CPU time 1.02 seconds
Started Aug 04 04:57:21 PM PDT 24
Finished Aug 04 04:57:23 PM PDT 24
Peak memory 207260 kb
Host smart-48d74c00-3c68-4bc3-9276-80269bd1321a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702212609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.702212609
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.224110950
Short name T519
Test name
Test status
Simulation time 7322990245 ps
CPU time 28.05 seconds
Started Aug 04 04:57:19 PM PDT 24
Finished Aug 04 04:57:47 PM PDT 24
Peak memory 216924 kb
Host smart-3af078cb-56de-467d-b74d-757d8d3ba165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224110950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.224110950
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2040484884
Short name T463
Test name
Test status
Simulation time 20622252860 ps
CPU time 16.21 seconds
Started Aug 04 04:57:20 PM PDT 24
Finished Aug 04 04:57:36 PM PDT 24
Peak memory 216956 kb
Host smart-a694426a-bca1-48ae-9d49-62b9f7e17974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040484884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2040484884
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4036814522
Short name T728
Test name
Test status
Simulation time 93556019 ps
CPU time 1.88 seconds
Started Aug 04 04:57:18 PM PDT 24
Finished Aug 04 04:57:20 PM PDT 24
Peak memory 217016 kb
Host smart-c119cfa3-fed0-423c-b57b-32448e20d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036814522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4036814522
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2446607816
Short name T603
Test name
Test status
Simulation time 145462899 ps
CPU time 0.84 seconds
Started Aug 04 04:57:20 PM PDT 24
Finished Aug 04 04:57:21 PM PDT 24
Peak memory 206600 kb
Host smart-9b143d95-70f0-43d5-9f13-3f2697bbb9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446607816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2446607816
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1531529741
Short name T107
Test name
Test status
Simulation time 10524820545 ps
CPU time 10.53 seconds
Started Aug 04 04:57:19 PM PDT 24
Finished Aug 04 04:57:30 PM PDT 24
Peak memory 225188 kb
Host smart-2a2de57c-7a5b-44b1-ae45-a0b778f91a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531529741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1531529741
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2630968900
Short name T1018
Test name
Test status
Simulation time 22645592 ps
CPU time 0.73 seconds
Started Aug 04 04:57:28 PM PDT 24
Finished Aug 04 04:57:29 PM PDT 24
Peak memory 205856 kb
Host smart-55a4cd71-04e6-4a2c-872f-1272a34947a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630968900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2630968900
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.959080163
Short name T969
Test name
Test status
Simulation time 3189435661 ps
CPU time 23.69 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:57:50 PM PDT 24
Peak memory 233452 kb
Host smart-944d723f-fe51-446f-9bac-8cf545a618c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959080163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.959080163
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2763017437
Short name T357
Test name
Test status
Simulation time 19871120 ps
CPU time 0.73 seconds
Started Aug 04 04:57:22 PM PDT 24
Finished Aug 04 04:57:23 PM PDT 24
Peak memory 206084 kb
Host smart-170cfcce-da45-4495-ad27-a3f7a47a3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763017437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2763017437
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2318569598
Short name T521
Test name
Test status
Simulation time 7853798856 ps
CPU time 87.18 seconds
Started Aug 04 04:57:30 PM PDT 24
Finished Aug 04 04:58:57 PM PDT 24
Peak memory 249824 kb
Host smart-455b276c-e5d1-4f9e-aa97-797d66c7fe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318569598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2318569598
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3168662814
Short name T206
Test name
Test status
Simulation time 114433895326 ps
CPU time 286.95 seconds
Started Aug 04 04:57:29 PM PDT 24
Finished Aug 04 05:02:16 PM PDT 24
Peak memory 258072 kb
Host smart-759a2c9d-1f98-41dc-a0c3-2d7195f37af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168662814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3168662814
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.37870060
Short name T627
Test name
Test status
Simulation time 64294531726 ps
CPU time 89.12 seconds
Started Aug 04 04:57:28 PM PDT 24
Finished Aug 04 04:58:57 PM PDT 24
Peak memory 251996 kb
Host smart-8ce34712-76f5-45cf-a62c-213e2b725f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37870060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.37870060
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3481547471
Short name T790
Test name
Test status
Simulation time 8716180256 ps
CPU time 33.05 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:57:59 PM PDT 24
Peak memory 234780 kb
Host smart-936a247c-4b2e-456c-879e-af7c7c750f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481547471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3481547471
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3471748277
Short name T788
Test name
Test status
Simulation time 14500040166 ps
CPU time 56.1 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:58:23 PM PDT 24
Peak memory 258008 kb
Host smart-891d5425-d8a0-4ea1-8440-621bd16ce52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471748277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3471748277
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4137204497
Short name T258
Test name
Test status
Simulation time 806108682 ps
CPU time 6.03 seconds
Started Aug 04 04:57:27 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 225248 kb
Host smart-2775c5f0-abf5-40c4-a899-86faaff1b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137204497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4137204497
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2380517079
Short name T930
Test name
Test status
Simulation time 12913230257 ps
CPU time 46.39 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:58:13 PM PDT 24
Peak memory 233428 kb
Host smart-26f78be8-7c67-4984-81d0-6bbfa3271d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380517079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2380517079
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3620681919
Short name T51
Test name
Test status
Simulation time 29374780817 ps
CPU time 13.41 seconds
Started Aug 04 04:57:27 PM PDT 24
Finished Aug 04 04:57:41 PM PDT 24
Peak memory 233536 kb
Host smart-28dc86e4-a656-4535-9678-0a8bda19cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620681919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3620681919
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2371702480
Short name T23
Test name
Test status
Simulation time 3950200816 ps
CPU time 4.98 seconds
Started Aug 04 04:57:28 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 225232 kb
Host smart-134c89d3-0ad5-429c-9f8d-5e904124868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371702480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2371702480
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3057883940
Short name T717
Test name
Test status
Simulation time 1776711678 ps
CPU time 8.63 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 223672 kb
Host smart-c402badc-b8e6-4ca5-b6ba-14cdb7b44e8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3057883940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3057883940
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.652278620
Short name T659
Test name
Test status
Simulation time 65195724157 ps
CPU time 309.19 seconds
Started Aug 04 04:57:30 PM PDT 24
Finished Aug 04 05:02:39 PM PDT 24
Peak memory 254948 kb
Host smart-1b64125f-7187-46c5-9b4a-e0a55378674f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652278620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.652278620
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1241508002
Short name T6
Test name
Test status
Simulation time 1220018210 ps
CPU time 6.72 seconds
Started Aug 04 04:57:24 PM PDT 24
Finished Aug 04 04:57:31 PM PDT 24
Peak memory 216992 kb
Host smart-9b941074-4dea-436a-9f5e-0e315a19c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241508002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1241508002
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2406824144
Short name T857
Test name
Test status
Simulation time 1311989348 ps
CPU time 3.29 seconds
Started Aug 04 04:57:20 PM PDT 24
Finished Aug 04 04:57:23 PM PDT 24
Peak memory 216884 kb
Host smart-ab1c6e26-8973-4b25-ad24-dddf8c5e98e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406824144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2406824144
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1098108816
Short name T378
Test name
Test status
Simulation time 17010694 ps
CPU time 0.88 seconds
Started Aug 04 04:57:25 PM PDT 24
Finished Aug 04 04:57:26 PM PDT 24
Peak memory 207248 kb
Host smart-5ec2950f-01da-42bd-a2c3-4101daf5ab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098108816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1098108816
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2036865237
Short name T604
Test name
Test status
Simulation time 11879499 ps
CPU time 0.74 seconds
Started Aug 04 04:57:26 PM PDT 24
Finished Aug 04 04:57:27 PM PDT 24
Peak memory 206032 kb
Host smart-a299fad9-5317-4905-9b0f-bcb00f2dbf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036865237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2036865237
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3383264874
Short name T383
Test name
Test status
Simulation time 17957621785 ps
CPU time 10.22 seconds
Started Aug 04 04:57:24 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 233388 kb
Host smart-8b5736ee-8372-4c3d-bf82-c6e8bcbb8991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383264874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3383264874
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.609514726
Short name T885
Test name
Test status
Simulation time 23943331 ps
CPU time 0.75 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:57:37 PM PDT 24
Peak memory 205204 kb
Host smart-0ea6f7cf-853d-4c3f-9df7-1fa1436c21cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609514726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.609514726
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.908174887
Short name T91
Test name
Test status
Simulation time 1537454958 ps
CPU time 3.07 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 04:57:38 PM PDT 24
Peak memory 224796 kb
Host smart-d1e42d78-8155-46c3-ae74-b2bfce505ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908174887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.908174887
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.573206883
Short name T703
Test name
Test status
Simulation time 57011520 ps
CPU time 0.78 seconds
Started Aug 04 04:57:28 PM PDT 24
Finished Aug 04 04:57:29 PM PDT 24
Peak memory 207436 kb
Host smart-ebf15dc3-24e6-4e96-9c6e-05888e1585db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573206883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.573206883
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3276947026
Short name T466
Test name
Test status
Simulation time 16049481050 ps
CPU time 117.01 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 04:59:32 PM PDT 24
Peak memory 240280 kb
Host smart-4c6f79d3-b0a2-4b13-ba72-cbd236df67f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276947026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3276947026
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3622195449
Short name T764
Test name
Test status
Simulation time 15392546434 ps
CPU time 63.82 seconds
Started Aug 04 04:57:33 PM PDT 24
Finished Aug 04 04:58:37 PM PDT 24
Peak memory 223212 kb
Host smart-3d5d04cb-e23c-4683-adca-81a8c7abae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622195449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3622195449
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1558231364
Short name T296
Test name
Test status
Simulation time 19523445494 ps
CPU time 227.69 seconds
Started Aug 04 04:57:34 PM PDT 24
Finished Aug 04 05:01:22 PM PDT 24
Peak memory 268124 kb
Host smart-eb09b3d2-95b8-4419-8e48-a840971202f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558231364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1558231364
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1480332652
Short name T158
Test name
Test status
Simulation time 769979435 ps
CPU time 7.56 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:57:40 PM PDT 24
Peak memory 233360 kb
Host smart-ff2d197b-23c0-4ff1-a88d-821d45fd8be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480332652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1480332652
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2675562234
Short name T563
Test name
Test status
Simulation time 844395808 ps
CPU time 9 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 04:57:44 PM PDT 24
Peak memory 225108 kb
Host smart-eb0c93b2-b573-4c52-bd28-674ff34db0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675562234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2675562234
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2599949291
Short name T1029
Test name
Test status
Simulation time 3316992076 ps
CPU time 12.71 seconds
Started Aug 04 04:57:31 PM PDT 24
Finished Aug 04 04:57:44 PM PDT 24
Peak memory 239396 kb
Host smart-72f79933-8670-44bd-b29d-28860e5e6162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599949291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2599949291
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1567205214
Short name T294
Test name
Test status
Simulation time 12975442874 ps
CPU time 13.4 seconds
Started Aug 04 04:57:30 PM PDT 24
Finished Aug 04 04:57:44 PM PDT 24
Peak memory 239868 kb
Host smart-2ba6bda4-853a-48c1-aa79-4768e2859aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567205214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1567205214
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.359574277
Short name T745
Test name
Test status
Simulation time 22097575662 ps
CPU time 27.64 seconds
Started Aug 04 04:57:29 PM PDT 24
Finished Aug 04 04:57:56 PM PDT 24
Peak memory 233428 kb
Host smart-feeec3fe-809b-47af-96b8-82c04e562920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359574277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.359574277
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1916903072
Short name T447
Test name
Test status
Simulation time 757122947 ps
CPU time 6.3 seconds
Started Aug 04 04:57:34 PM PDT 24
Finished Aug 04 04:57:40 PM PDT 24
Peak memory 221068 kb
Host smart-232fea6f-7220-4cc3-ab32-b7da1c28cfe4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1916903072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1916903072
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3048871188
Short name T820
Test name
Test status
Simulation time 176620077325 ps
CPU time 324.62 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 05:03:00 PM PDT 24
Peak memory 266268 kb
Host smart-2e2d3c25-941e-43fb-a24c-4e9e9f669789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048871188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3048871188
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2243258757
Short name T962
Test name
Test status
Simulation time 4345415614 ps
CPU time 13.79 seconds
Started Aug 04 04:57:31 PM PDT 24
Finished Aug 04 04:57:45 PM PDT 24
Peak memory 217372 kb
Host smart-5bf3c442-6087-4769-a179-583545fd1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243258757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2243258757
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.396531506
Short name T641
Test name
Test status
Simulation time 275738285 ps
CPU time 2.48 seconds
Started Aug 04 04:57:29 PM PDT 24
Finished Aug 04 04:57:32 PM PDT 24
Peak memory 216988 kb
Host smart-5e554464-29b2-44cc-a21c-08427e4edcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396531506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.396531506
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.242277884
Short name T939
Test name
Test status
Simulation time 45290298 ps
CPU time 0.99 seconds
Started Aug 04 04:57:28 PM PDT 24
Finished Aug 04 04:57:29 PM PDT 24
Peak memory 208188 kb
Host smart-c32ed638-4cd0-4d52-93b5-34b4ea420efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242277884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.242277884
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4132098470
Short name T86
Test name
Test status
Simulation time 102980417 ps
CPU time 0.93 seconds
Started Aug 04 04:57:29 PM PDT 24
Finished Aug 04 04:57:31 PM PDT 24
Peak memory 206576 kb
Host smart-0dd53ad4-2bde-41af-85b3-234d9286d5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132098470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4132098470
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2529963245
Short name T834
Test name
Test status
Simulation time 480372263 ps
CPU time 2.56 seconds
Started Aug 04 04:57:33 PM PDT 24
Finished Aug 04 04:57:35 PM PDT 24
Peak memory 224432 kb
Host smart-d0748adf-32c4-46c3-888d-c4a1e1e9cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529963245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2529963245
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3560726256
Short name T1000
Test name
Test status
Simulation time 16559864 ps
CPU time 0.76 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:57:37 PM PDT 24
Peak memory 205892 kb
Host smart-05d29c45-6b13-482b-81aa-37ff5ccf94af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560726256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3560726256
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1444206810
Short name T268
Test name
Test status
Simulation time 2692318398 ps
CPU time 16.8 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:57:53 PM PDT 24
Peak memory 225344 kb
Host smart-9b17884e-b3fd-4c85-95da-5d6df07ed82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444206810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1444206810
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3079284989
Short name T994
Test name
Test status
Simulation time 21509189 ps
CPU time 0.73 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 206408 kb
Host smart-0b8e67b1-7282-4d9a-b549-8c22c5b7c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079284989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3079284989
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2740265715
Short name T366
Test name
Test status
Simulation time 74072406 ps
CPU time 0.75 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:57:36 PM PDT 24
Peak memory 216408 kb
Host smart-4bcc847d-67cd-402b-94ee-256037dd4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740265715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2740265715
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1330288063
Short name T740
Test name
Test status
Simulation time 31249689985 ps
CPU time 77.67 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:58:54 PM PDT 24
Peak memory 239012 kb
Host smart-96c10510-6d32-40ae-a8fb-550d060a02a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330288063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1330288063
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1100343050
Short name T518
Test name
Test status
Simulation time 34243266 ps
CPU time 0.81 seconds
Started Aug 04 04:57:37 PM PDT 24
Finished Aug 04 04:57:38 PM PDT 24
Peak memory 217612 kb
Host smart-dc6676e3-7479-4160-96a1-2a2e05ad7852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100343050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1100343050
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1367475381
Short name T868
Test name
Test status
Simulation time 4162486548 ps
CPU time 37.93 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:58:14 PM PDT 24
Peak memory 249960 kb
Host smart-a2714006-bb88-4e84-a7ce-21342a54e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367475381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1367475381
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3914377037
Short name T96
Test name
Test status
Simulation time 35325381516 ps
CPU time 242.86 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 05:01:38 PM PDT 24
Peak memory 253836 kb
Host smart-e26b4605-ace1-4d14-8894-b019ccd1b475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914377037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3914377037
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2078909090
Short name T934
Test name
Test status
Simulation time 5633576915 ps
CPU time 24.83 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:58:01 PM PDT 24
Peak memory 233524 kb
Host smart-3897fcfd-aba5-4c54-8656-04cfce0fc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078909090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2078909090
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3807468600
Short name T611
Test name
Test status
Simulation time 104962004 ps
CPU time 2.42 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 04:57:38 PM PDT 24
Peak memory 223736 kb
Host smart-ea0133d3-1bfe-4298-9a98-40708bc495fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807468600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3807468600
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2799403298
Short name T589
Test name
Test status
Simulation time 361863188 ps
CPU time 2.11 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 224564 kb
Host smart-b437cf3f-6a88-47e1-81ba-243646216563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799403298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2799403298
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.397782402
Short name T852
Test name
Test status
Simulation time 418567193 ps
CPU time 2.43 seconds
Started Aug 04 04:57:31 PM PDT 24
Finished Aug 04 04:57:34 PM PDT 24
Peak memory 225188 kb
Host smart-198cd721-36d0-41c5-a7af-46bb684e7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397782402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.397782402
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3766096089
Short name T705
Test name
Test status
Simulation time 196659335 ps
CPU time 4 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 04:57:42 PM PDT 24
Peak memory 219932 kb
Host smart-1306efe8-ab14-4236-934b-41e570848975
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766096089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3766096089
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2386873752
Short name T170
Test name
Test status
Simulation time 3956998800 ps
CPU time 49.32 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 04:58:28 PM PDT 24
Peak memory 235536 kb
Host smart-05d6b602-e180-472c-a378-c8998ecd3392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386873752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2386873752
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.562539841
Short name T736
Test name
Test status
Simulation time 171465736377 ps
CPU time 45.44 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:58:17 PM PDT 24
Peak memory 216936 kb
Host smart-5dd60fb3-93cb-4563-9927-254b9156be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562539841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.562539841
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.611703755
Short name T581
Test name
Test status
Simulation time 2178384730 ps
CPU time 7.07 seconds
Started Aug 04 04:57:35 PM PDT 24
Finished Aug 04 04:57:42 PM PDT 24
Peak memory 216880 kb
Host smart-3ed0e229-d472-4fd9-931e-b88dceb8af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611703755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.611703755
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3851461849
Short name T485
Test name
Test status
Simulation time 825975797 ps
CPU time 9.35 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:57:42 PM PDT 24
Peak memory 216884 kb
Host smart-ceb66389-d8dc-4fcd-9d15-fe931519e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851461849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3851461849
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2218034722
Short name T474
Test name
Test status
Simulation time 55771161 ps
CPU time 0.78 seconds
Started Aug 04 04:57:32 PM PDT 24
Finished Aug 04 04:57:33 PM PDT 24
Peak memory 206584 kb
Host smart-becf12fb-1dad-426c-b404-ff4e40d706ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218034722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2218034722
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1607881728
Short name T621
Test name
Test status
Simulation time 1923606367 ps
CPU time 3.14 seconds
Started Aug 04 04:57:36 PM PDT 24
Finished Aug 04 04:57:39 PM PDT 24
Peak memory 225112 kb
Host smart-4dd4a230-ba23-43b9-b611-cf0dd9431d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607881728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1607881728
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1091108058
Short name T839
Test name
Test status
Simulation time 15126456 ps
CPU time 0.74 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:17 PM PDT 24
Peak memory 205736 kb
Host smart-f8e56ef6-33a8-40dc-a051-c43ab5df12d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091108058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
091108058
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2504416572
Short name T727
Test name
Test status
Simulation time 411954819 ps
CPU time 4.37 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:53:18 PM PDT 24
Peak memory 233364 kb
Host smart-4caeadb1-8c85-4f92-9d62-1345230e2ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504416572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2504416572
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4133818214
Short name T859
Test name
Test status
Simulation time 19654344 ps
CPU time 0.77 seconds
Started Aug 04 04:53:11 PM PDT 24
Finished Aug 04 04:53:12 PM PDT 24
Peak memory 207048 kb
Host smart-ffb455ca-bb08-4fff-bb1e-781ae07740b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133818214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4133818214
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2475403011
Short name T226
Test name
Test status
Simulation time 75424290806 ps
CPU time 200.49 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:56:33 PM PDT 24
Peak memory 250704 kb
Host smart-fa7e4839-77d8-4ff7-9da9-1ccac17a8dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475403011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2475403011
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3525221239
Short name T56
Test name
Test status
Simulation time 29353692460 ps
CPU time 350.58 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:59:03 PM PDT 24
Peak memory 265688 kb
Host smart-c81dbb77-e21c-4319-800a-3dab2316a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525221239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3525221239
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.871788487
Short name T545
Test name
Test status
Simulation time 1078564210 ps
CPU time 12.57 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:53:26 PM PDT 24
Peak memory 233412 kb
Host smart-da6bad73-1dca-431c-b75f-0ce2b453ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871788487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.871788487
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.133353252
Short name T298
Test name
Test status
Simulation time 6134474526 ps
CPU time 62.06 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:54:15 PM PDT 24
Peak memory 255276 kb
Host smart-878ec33a-9c51-4884-85f2-7d394039daaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133353252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
133353252
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3512082925
Short name T108
Test name
Test status
Simulation time 640449042 ps
CPU time 8.75 seconds
Started Aug 04 04:53:11 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 233384 kb
Host smart-efffd982-6f7e-49af-8d44-e07f7a6af3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512082925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3512082925
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3902508120
Short name T650
Test name
Test status
Simulation time 4154223785 ps
CPU time 28.54 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:38 PM PDT 24
Peak memory 241580 kb
Host smart-3eebd277-a84d-487c-ba49-3cac22a8fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902508120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3902508120
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.511084745
Short name T494
Test name
Test status
Simulation time 116422312 ps
CPU time 1.14 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:11 PM PDT 24
Peak memory 217144 kb
Host smart-f750fe1b-8d4b-444f-b4fe-6edc20644172
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511084745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.511084745
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2887469317
Short name T908
Test name
Test status
Simulation time 571033000 ps
CPU time 3.29 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:13 PM PDT 24
Peak memory 225124 kb
Host smart-50679ed2-eb08-4a64-9cb1-a6047a3ddc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887469317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2887469317
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2882102564
Short name T754
Test name
Test status
Simulation time 23364509270 ps
CPU time 17.58 seconds
Started Aug 04 04:53:12 PM PDT 24
Finished Aug 04 04:53:30 PM PDT 24
Peak memory 233436 kb
Host smart-776c5ecb-562d-469f-9490-fe4ae7637fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882102564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2882102564
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3952710687
Short name T778
Test name
Test status
Simulation time 723742876 ps
CPU time 6.05 seconds
Started Aug 04 04:53:13 PM PDT 24
Finished Aug 04 04:53:19 PM PDT 24
Peak memory 222648 kb
Host smart-20aab1d1-af34-4e9f-bbb0-23da54ddfc2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3952710687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3952710687
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4120555345
Short name T500
Test name
Test status
Simulation time 82195308 ps
CPU time 1.02 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:18 PM PDT 24
Peak memory 207232 kb
Host smart-cd16d3d3-b5e5-4f7d-84e4-f07195a88b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120555345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4120555345
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2742136200
Short name T504
Test name
Test status
Simulation time 2766834281 ps
CPU time 11.65 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:21 PM PDT 24
Peak memory 217120 kb
Host smart-bca5fb6f-4981-4c49-917c-4603b0451079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742136200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2742136200
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3833990628
Short name T543
Test name
Test status
Simulation time 2960920274 ps
CPU time 4.98 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:14 PM PDT 24
Peak memory 216916 kb
Host smart-2bef9be2-6ce4-4f7b-a720-afc6790cd8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833990628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3833990628
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.691773
Short name T784
Test name
Test status
Simulation time 52003361 ps
CPU time 1.19 seconds
Started Aug 04 04:53:09 PM PDT 24
Finished Aug 04 04:53:11 PM PDT 24
Peak memory 208408 kb
Host smart-34ebd1b1-fab2-4cda-8479-22f17ed0a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.691773
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1654196779
Short name T427
Test name
Test status
Simulation time 58022737 ps
CPU time 0.72 seconds
Started Aug 04 04:53:10 PM PDT 24
Finished Aug 04 04:53:11 PM PDT 24
Peak memory 206444 kb
Host smart-db0c9268-4547-4a3f-96e6-71eb3af56999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654196779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1654196779
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4291505914
Short name T818
Test name
Test status
Simulation time 2447911740 ps
CPU time 2.63 seconds
Started Aug 04 04:53:12 PM PDT 24
Finished Aug 04 04:53:15 PM PDT 24
Peak memory 225300 kb
Host smart-ebd8d037-8d16-423c-9af7-f9fbb4effc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291505914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4291505914
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.403456056
Short name T439
Test name
Test status
Simulation time 25344597 ps
CPU time 0.73 seconds
Started Aug 04 04:53:20 PM PDT 24
Finished Aug 04 04:53:21 PM PDT 24
Peak memory 205808 kb
Host smart-71d5c8d3-8203-4614-9aa1-e2c104b4412f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403456056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.403456056
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2406534453
Short name T261
Test name
Test status
Simulation time 1484321872 ps
CPU time 17.26 seconds
Started Aug 04 04:53:19 PM PDT 24
Finished Aug 04 04:53:37 PM PDT 24
Peak memory 225168 kb
Host smart-6907265d-b891-46af-826e-74cc3b70c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406534453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2406534453
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3105051968
Short name T338
Test name
Test status
Simulation time 34209466 ps
CPU time 0.8 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:18 PM PDT 24
Peak memory 206912 kb
Host smart-6f735f7d-666a-4eae-80f9-26463b08ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105051968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3105051968
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2641153665
Short name T314
Test name
Test status
Simulation time 46908167004 ps
CPU time 250.7 seconds
Started Aug 04 04:53:19 PM PDT 24
Finished Aug 04 04:57:30 PM PDT 24
Peak memory 250472 kb
Host smart-5ad53b26-ef79-433d-acbb-0dff67d8ee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641153665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2641153665
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3109143948
Short name T309
Test name
Test status
Simulation time 69462875476 ps
CPU time 305.93 seconds
Started Aug 04 04:53:21 PM PDT 24
Finished Aug 04 04:58:27 PM PDT 24
Peak memory 254804 kb
Host smart-330d56f4-84c3-4ca4-afe7-69890ff115bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109143948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3109143948
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1862698102
Short name T247
Test name
Test status
Simulation time 6824857197 ps
CPU time 35.84 seconds
Started Aug 04 04:53:22 PM PDT 24
Finished Aug 04 04:53:58 PM PDT 24
Peak memory 233532 kb
Host smart-16c5d2b8-bab6-4d29-964a-7ebd30bddb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862698102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1862698102
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.641152954
Short name T564
Test name
Test status
Simulation time 2122125547 ps
CPU time 29.77 seconds
Started Aug 04 04:53:21 PM PDT 24
Finished Aug 04 04:53:51 PM PDT 24
Peak memory 250252 kb
Host smart-196ee54f-2907-45e7-8321-250fb8973fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641152954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
641152954
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1507983557
Short name T245
Test name
Test status
Simulation time 600891499 ps
CPU time 7.85 seconds
Started Aug 04 04:53:19 PM PDT 24
Finished Aug 04 04:53:27 PM PDT 24
Peak memory 233348 kb
Host smart-50d1d67d-7cab-4047-a2a9-4bc8f9e935ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507983557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1507983557
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1087816465
Short name T649
Test name
Test status
Simulation time 6407031110 ps
CPU time 56.51 seconds
Started Aug 04 04:53:20 PM PDT 24
Finished Aug 04 04:54:16 PM PDT 24
Peak memory 233452 kb
Host smart-33123d03-12e3-42b6-9996-d74293f503cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087816465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1087816465
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1896193069
Short name T667
Test name
Test status
Simulation time 49163965 ps
CPU time 1.02 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:19 PM PDT 24
Peak memory 218412 kb
Host smart-d333014a-b20e-459e-b839-a8b1d7c56b80
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896193069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1896193069
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1796937773
Short name T873
Test name
Test status
Simulation time 887744789 ps
CPU time 4.95 seconds
Started Aug 04 04:53:15 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 233272 kb
Host smart-95e589dd-1d65-446b-8298-1381dd6006ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796937773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1796937773
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.166062587
Short name T255
Test name
Test status
Simulation time 50330929 ps
CPU time 3.24 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 233400 kb
Host smart-4e499968-5658-4da5-a26c-d94836a9176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166062587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.166062587
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.187544688
Short name T967
Test name
Test status
Simulation time 2133389741 ps
CPU time 8.53 seconds
Started Aug 04 04:53:20 PM PDT 24
Finished Aug 04 04:53:29 PM PDT 24
Peak memory 222924 kb
Host smart-0bc224ab-b749-4407-b461-51a9bd52fbd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187544688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.187544688
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1382972605
Short name T1023
Test name
Test status
Simulation time 76889882 ps
CPU time 1.01 seconds
Started Aug 04 04:53:19 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 207076 kb
Host smart-36f15e89-2fd2-4a2f-a5a7-76d6c70595b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382972605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1382972605
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2100119168
Short name T856
Test name
Test status
Simulation time 174983493 ps
CPU time 2.92 seconds
Started Aug 04 04:53:18 PM PDT 24
Finished Aug 04 04:53:21 PM PDT 24
Peak memory 217388 kb
Host smart-6c52e5a8-c907-4a6d-a0ab-84eb8eede24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100119168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2100119168
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3494902980
Short name T1002
Test name
Test status
Simulation time 2701797983 ps
CPU time 9.31 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:26 PM PDT 24
Peak memory 216960 kb
Host smart-36be5acd-9208-4183-9111-dd69a40c1e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494902980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3494902980
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1025509951
Short name T835
Test name
Test status
Simulation time 470373394 ps
CPU time 3.27 seconds
Started Aug 04 04:53:16 PM PDT 24
Finished Aug 04 04:53:20 PM PDT 24
Peak memory 216864 kb
Host smart-2cb59356-fef7-4104-bfac-b45bdf8b1b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025509951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1025509951
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1730100364
Short name T922
Test name
Test status
Simulation time 26047856 ps
CPU time 0.79 seconds
Started Aug 04 04:53:17 PM PDT 24
Finished Aug 04 04:53:17 PM PDT 24
Peak memory 206496 kb
Host smart-f7259df0-a56a-4261-ba63-fc814cf152c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730100364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1730100364
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4197004987
Short name T742
Test name
Test status
Simulation time 1321836378 ps
CPU time 7.38 seconds
Started Aug 04 04:53:22 PM PDT 24
Finished Aug 04 04:53:30 PM PDT 24
Peak memory 225260 kb
Host smart-ab803039-1599-4a6b-895c-b0180ca6acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197004987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4197004987
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2912054680
Short name T498
Test name
Test status
Simulation time 13389614 ps
CPU time 0.72 seconds
Started Aug 04 04:53:28 PM PDT 24
Finished Aug 04 04:53:29 PM PDT 24
Peak memory 205328 kb
Host smart-e37868a8-b5d8-4ecf-9835-c368db23c3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912054680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
912054680
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3413405400
Short name T414
Test name
Test status
Simulation time 2798231923 ps
CPU time 5.3 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 233428 kb
Host smart-dfa565b0-eaf0-4426-a298-3e6c870a8ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413405400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3413405400
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4277286051
Short name T814
Test name
Test status
Simulation time 13363099 ps
CPU time 0.78 seconds
Started Aug 04 04:53:22 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 207336 kb
Host smart-bc133248-b4fa-40ee-9eac-eaf63c03e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277286051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4277286051
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1033963657
Short name T408
Test name
Test status
Simulation time 3094771721 ps
CPU time 14.64 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:41 PM PDT 24
Peak memory 234720 kb
Host smart-5d382158-9da1-4258-85bc-7c557e4c880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033963657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1033963657
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2895263206
Short name T843
Test name
Test status
Simulation time 37683433 ps
CPU time 0.86 seconds
Started Aug 04 04:53:29 PM PDT 24
Finished Aug 04 04:53:30 PM PDT 24
Peak memory 217940 kb
Host smart-067537ad-2c28-4a2f-90f1-26f9ac38415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895263206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2895263206
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.980992413
Short name T325
Test name
Test status
Simulation time 91474639 ps
CPU time 4.84 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 233544 kb
Host smart-c2844828-fe4a-4e13-9c5e-e35738dd3489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980992413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.980992413
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.373673392
Short name T932
Test name
Test status
Simulation time 68568405 ps
CPU time 0.8 seconds
Started Aug 04 04:53:28 PM PDT 24
Finished Aug 04 04:53:29 PM PDT 24
Peak memory 216428 kb
Host smart-24886766-79df-4f8d-af68-55a1a6c07e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373673392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
373673392
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4179666192
Short name T396
Test name
Test status
Simulation time 1058147065 ps
CPU time 10.66 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:37 PM PDT 24
Peak memory 228500 kb
Host smart-54afd062-3cbf-45e8-8b71-dff33819e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179666192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4179666192
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4079929837
Short name T358
Test name
Test status
Simulation time 96397907 ps
CPU time 1.02 seconds
Started Aug 04 04:53:21 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 217096 kb
Host smart-6bb3e372-e3c9-4261-a53f-a4a89e562f28
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079929837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4079929837
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2656283504
Short name T968
Test name
Test status
Simulation time 118480462 ps
CPU time 2.26 seconds
Started Aug 04 04:53:27 PM PDT 24
Finished Aug 04 04:53:30 PM PDT 24
Peak memory 233064 kb
Host smart-05a9431f-da45-44d5-af33-2002695e9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656283504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2656283504
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.811517145
Short name T866
Test name
Test status
Simulation time 2687816503 ps
CPU time 9.43 seconds
Started Aug 04 04:53:22 PM PDT 24
Finished Aug 04 04:53:32 PM PDT 24
Peak memory 233336 kb
Host smart-3e62e54e-3d8e-4cdb-abf1-dca17c3df649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811517145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.811517145
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2726135924
Short name T155
Test name
Test status
Simulation time 239349103 ps
CPU time 4.79 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 223572 kb
Host smart-ef23bc5e-13f1-4c79-9676-0d7d77c0cd48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2726135924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2726135924
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.601994409
Short name T750
Test name
Test status
Simulation time 81698547913 ps
CPU time 813.37 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 05:07:04 PM PDT 24
Peak memory 272800 kb
Host smart-a7639f90-65fa-4dab-bd69-87ede65a14f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601994409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.601994409
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1612647126
Short name T652
Test name
Test status
Simulation time 4438099585 ps
CPU time 22.63 seconds
Started Aug 04 04:53:23 PM PDT 24
Finished Aug 04 04:53:46 PM PDT 24
Peak memory 217224 kb
Host smart-afabb902-8402-4c23-94df-2ed02d5e7b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612647126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1612647126
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1580204336
Short name T171
Test name
Test status
Simulation time 12722898881 ps
CPU time 18.05 seconds
Started Aug 04 04:53:22 PM PDT 24
Finished Aug 04 04:53:41 PM PDT 24
Peak memory 216936 kb
Host smart-1874293c-27e6-4d90-b731-8ed967bfc86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580204336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1580204336
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.487115999
Short name T661
Test name
Test status
Simulation time 50251572 ps
CPU time 1.54 seconds
Started Aug 04 04:53:26 PM PDT 24
Finished Aug 04 04:53:27 PM PDT 24
Peak memory 216888 kb
Host smart-09c8b470-00b7-491f-8c40-e0daa4ad487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487115999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.487115999
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.369850224
Short name T579
Test name
Test status
Simulation time 197057240 ps
CPU time 0.91 seconds
Started Aug 04 04:53:24 PM PDT 24
Finished Aug 04 04:53:25 PM PDT 24
Peak memory 206476 kb
Host smart-d4f6742a-fd8a-49ca-8fb7-830b98a6f0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369850224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.369850224
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.87788562
Short name T872
Test name
Test status
Simulation time 131417630 ps
CPU time 2.5 seconds
Started Aug 04 04:53:25 PM PDT 24
Finished Aug 04 04:53:27 PM PDT 24
Peak memory 225160 kb
Host smart-2efddd65-9c49-43e1-b3a5-cb3183ec7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87788562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.87788562
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1691770882
Short name T507
Test name
Test status
Simulation time 14559911 ps
CPU time 0.75 seconds
Started Aug 04 04:53:36 PM PDT 24
Finished Aug 04 04:53:37 PM PDT 24
Peak memory 206220 kb
Host smart-29c91620-cf3a-46c9-99a5-3adeb45f4368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691770882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
691770882
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3451703375
Short name T709
Test name
Test status
Simulation time 1165320634 ps
CPU time 12.87 seconds
Started Aug 04 04:53:31 PM PDT 24
Finished Aug 04 04:53:44 PM PDT 24
Peak memory 233424 kb
Host smart-aa2dc766-ba17-43ef-8989-06343ecf9128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451703375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3451703375
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2015446511
Short name T954
Test name
Test status
Simulation time 39159306 ps
CPU time 0.78 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 206904 kb
Host smart-8dd107b2-c36d-4061-b4ee-97375ee5e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015446511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2015446511
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3387421693
Short name T819
Test name
Test status
Simulation time 23463523105 ps
CPU time 87.14 seconds
Started Aug 04 04:53:32 PM PDT 24
Finished Aug 04 04:54:59 PM PDT 24
Peak memory 239756 kb
Host smart-f7ba9b45-eea8-477e-8670-0a31d875b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387421693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3387421693
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.153004777
Short name T926
Test name
Test status
Simulation time 69282609302 ps
CPU time 166.2 seconds
Started Aug 04 04:53:40 PM PDT 24
Finished Aug 04 04:56:27 PM PDT 24
Peak memory 257908 kb
Host smart-d7f8e534-2b6c-4bd2-b5e7-9b12d1571bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153004777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.153004777
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2046031635
Short name T217
Test name
Test status
Simulation time 3695905360 ps
CPU time 32.19 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:54:11 PM PDT 24
Peak memory 238908 kb
Host smart-0a2c9811-09b5-459d-b6e5-a9902b24d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046031635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2046031635
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1002012747
Short name T1
Test name
Test status
Simulation time 666046120 ps
CPU time 15.12 seconds
Started Aug 04 04:53:33 PM PDT 24
Finished Aug 04 04:53:48 PM PDT 24
Peak memory 253140 kb
Host smart-0ee3bfc9-38b0-4b9d-97f0-3d2b0029cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002012747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1002012747
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2711906938
Short name T279
Test name
Test status
Simulation time 3834032900 ps
CPU time 26.6 seconds
Started Aug 04 04:53:33 PM PDT 24
Finished Aug 04 04:53:59 PM PDT 24
Peak memory 241604 kb
Host smart-b1bfe958-1337-482c-962e-c5ea05a6c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711906938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2711906938
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1391421246
Short name T706
Test name
Test status
Simulation time 138360461 ps
CPU time 2.24 seconds
Started Aug 04 04:53:33 PM PDT 24
Finished Aug 04 04:53:36 PM PDT 24
Peak memory 223704 kb
Host smart-7593817e-043a-4b4a-af30-0697a4fc2d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391421246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1391421246
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3506605144
Short name T710
Test name
Test status
Simulation time 4484098193 ps
CPU time 23.37 seconds
Started Aug 04 04:53:29 PM PDT 24
Finished Aug 04 04:53:53 PM PDT 24
Peak memory 225208 kb
Host smart-b0013246-aa93-407e-93c4-48170ce774c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506605144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3506605144
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2235110484
Short name T459
Test name
Test status
Simulation time 25022628 ps
CPU time 1.02 seconds
Started Aug 04 04:53:31 PM PDT 24
Finished Aug 04 04:53:32 PM PDT 24
Peak memory 217132 kb
Host smart-09e7009a-d04b-4c88-b9f7-fb6e9a02b769
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235110484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2235110484
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3205633174
Short name T280
Test name
Test status
Simulation time 1668283696 ps
CPU time 9.92 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 04:53:40 PM PDT 24
Peak memory 233468 kb
Host smart-6ce4589c-8f14-4b6a-8c97-ce56ed613949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205633174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3205633174
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4202623750
Short name T1034
Test name
Test status
Simulation time 885689422 ps
CPU time 4.86 seconds
Started Aug 04 04:53:29 PM PDT 24
Finished Aug 04 04:53:34 PM PDT 24
Peak memory 233404 kb
Host smart-c24256e2-3144-4765-a6f2-d7542cbf31e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202623750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4202623750
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1364023867
Short name T633
Test name
Test status
Simulation time 1567858003 ps
CPU time 15.11 seconds
Started Aug 04 04:53:33 PM PDT 24
Finished Aug 04 04:53:48 PM PDT 24
Peak memory 219856 kb
Host smart-95c541a6-a2cd-4e7e-9e68-df46b1fad4af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364023867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1364023867
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1910303489
Short name T855
Test name
Test status
Simulation time 12105931136 ps
CPU time 19.25 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 04:53:50 PM PDT 24
Peak memory 216984 kb
Host smart-9d496890-9daf-4a3f-9f73-41c3a4a9ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910303489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1910303489
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1466775826
Short name T793
Test name
Test status
Simulation time 628758662 ps
CPU time 3.03 seconds
Started Aug 04 04:53:31 PM PDT 24
Finished Aug 04 04:53:34 PM PDT 24
Peak memory 216680 kb
Host smart-57008caa-e7d7-4dab-bc57-04825115f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466775826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1466775826
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.540094286
Short name T552
Test name
Test status
Simulation time 55767845 ps
CPU time 1.52 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 04:53:32 PM PDT 24
Peak memory 216908 kb
Host smart-fab0bb29-a532-4e2b-a2ec-187d620ec86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540094286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.540094286
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1903215699
Short name T361
Test name
Test status
Simulation time 104094249 ps
CPU time 0.93 seconds
Started Aug 04 04:53:30 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 207532 kb
Host smart-e171a286-061c-4e7d-8b31-d2ad7747681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903215699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1903215699
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3822740898
Short name T1027
Test name
Test status
Simulation time 59144561 ps
CPU time 2.34 seconds
Started Aug 04 04:53:34 PM PDT 24
Finished Aug 04 04:53:37 PM PDT 24
Peak memory 225284 kb
Host smart-6bc19a07-24a0-452e-ad87-f53ac2fa560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822740898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3822740898
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.583524549
Short name T60
Test name
Test status
Simulation time 81362904 ps
CPU time 0.75 seconds
Started Aug 04 04:53:44 PM PDT 24
Finished Aug 04 04:53:45 PM PDT 24
Peak memory 205900 kb
Host smart-5f4c0c74-6a14-4a43-85c6-20ebd8c353a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583524549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.583524549
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.37886714
Short name T391
Test name
Test status
Simulation time 4306053658 ps
CPU time 4.21 seconds
Started Aug 04 04:53:42 PM PDT 24
Finished Aug 04 04:53:46 PM PDT 24
Peak memory 225524 kb
Host smart-1e48ec67-208e-4ed1-baf7-fd5610b531e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37886714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.37886714
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3890656836
Short name T702
Test name
Test status
Simulation time 19519122 ps
CPU time 0.77 seconds
Started Aug 04 04:53:37 PM PDT 24
Finished Aug 04 04:53:38 PM PDT 24
Peak memory 206072 kb
Host smart-74e72736-7033-4f4c-a57d-8f0372e12a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890656836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3890656836
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2941865303
Short name T833
Test name
Test status
Simulation time 11297245772 ps
CPU time 120.14 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:55:40 PM PDT 24
Peak memory 258068 kb
Host smart-c3cefdea-be31-4d48-b887-96575f7cfe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941865303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2941865303
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1862208210
Short name T315
Test name
Test status
Simulation time 65535100070 ps
CPU time 433.7 seconds
Started Aug 04 04:53:41 PM PDT 24
Finished Aug 04 05:00:55 PM PDT 24
Peak memory 251784 kb
Host smart-9ca367fe-a755-425f-8632-d69b2933bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862208210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1862208210
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1787912775
Short name T312
Test name
Test status
Simulation time 7011590055 ps
CPU time 88.9 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:55:08 PM PDT 24
Peak memory 258044 kb
Host smart-4d828d21-4536-4d63-b3ef-4de4bce480a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787912775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1787912775
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1437112798
Short name T183
Test name
Test status
Simulation time 30084799568 ps
CPU time 55.42 seconds
Started Aug 04 04:53:42 PM PDT 24
Finished Aug 04 04:54:37 PM PDT 24
Peak memory 249848 kb
Host smart-b586f989-2c1c-43ec-844e-c9ac929232bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437112798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1437112798
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3119967453
Short name T875
Test name
Test status
Simulation time 1434020209 ps
CPU time 7.5 seconds
Started Aug 04 04:53:41 PM PDT 24
Finished Aug 04 04:53:49 PM PDT 24
Peak memory 225284 kb
Host smart-ce40b8f1-4a70-47c6-ba83-c0c61dd26600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119967453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3119967453
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1171219399
Short name T219
Test name
Test status
Simulation time 30790802405 ps
CPU time 61.76 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:54:41 PM PDT 24
Peak memory 249936 kb
Host smart-5d580933-24d4-4cb3-917b-0e805b407876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171219399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1171219399
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1657178107
Short name T963
Test name
Test status
Simulation time 98868391 ps
CPU time 1.07 seconds
Started Aug 04 04:53:38 PM PDT 24
Finished Aug 04 04:53:39 PM PDT 24
Peak memory 218328 kb
Host smart-056900e0-738e-4527-84eb-68c146a6f8b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657178107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1657178107
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3207043653
Short name T660
Test name
Test status
Simulation time 136381091 ps
CPU time 3.16 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:53:43 PM PDT 24
Peak memory 233356 kb
Host smart-3b8fc9c3-21c5-402e-9f35-a5b834d25ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207043653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3207043653
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3646476710
Short name T830
Test name
Test status
Simulation time 17104725043 ps
CPU time 14.08 seconds
Started Aug 04 04:53:39 PM PDT 24
Finished Aug 04 04:53:53 PM PDT 24
Peak memory 233424 kb
Host smart-c8bb9e9a-771a-4d92-92b8-09ec79ff6f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646476710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3646476710
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2261216238
Short name T663
Test name
Test status
Simulation time 363827698 ps
CPU time 3.6 seconds
Started Aug 04 04:53:40 PM PDT 24
Finished Aug 04 04:53:43 PM PDT 24
Peak memory 223256 kb
Host smart-48f67dba-2e8a-4954-bc16-f6295ab725c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261216238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2261216238
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4189069822
Short name T16
Test name
Test status
Simulation time 5082868990 ps
CPU time 57.34 seconds
Started Aug 04 04:53:45 PM PDT 24
Finished Aug 04 04:54:42 PM PDT 24
Peak memory 256476 kb
Host smart-af88e0ab-c1bb-477d-aff6-563e2fc5ab23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189069822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4189069822
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3008231428
Short name T600
Test name
Test status
Simulation time 490698519 ps
CPU time 2.2 seconds
Started Aug 04 04:53:40 PM PDT 24
Finished Aug 04 04:53:43 PM PDT 24
Peak memory 217296 kb
Host smart-c2fc6e33-4189-4451-843c-d02d0df6868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008231428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3008231428
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1690636217
Short name T352
Test name
Test status
Simulation time 13531548879 ps
CPU time 6.16 seconds
Started Aug 04 04:53:36 PM PDT 24
Finished Aug 04 04:53:42 PM PDT 24
Peak memory 217056 kb
Host smart-a85d4cf8-11ca-42a8-a477-d78585ff8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690636217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1690636217
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2307934488
Short name T371
Test name
Test status
Simulation time 67966733 ps
CPU time 1.33 seconds
Started Aug 04 04:53:37 PM PDT 24
Finished Aug 04 04:53:38 PM PDT 24
Peak memory 208692 kb
Host smart-49de6d78-835d-4e02-9b65-7ea71a9b392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307934488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2307934488
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2039908917
Short name T567
Test name
Test status
Simulation time 74319567 ps
CPU time 0.89 seconds
Started Aug 04 04:53:37 PM PDT 24
Finished Aug 04 04:53:38 PM PDT 24
Peak memory 207612 kb
Host smart-1942bbe6-e2a1-4ea7-a131-4f11a50d0ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039908917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2039908917
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2746217671
Short name T711
Test name
Test status
Simulation time 5107125324 ps
CPU time 17.92 seconds
Started Aug 04 04:53:41 PM PDT 24
Finished Aug 04 04:53:59 PM PDT 24
Peak memory 235656 kb
Host smart-897bc230-5dbc-4087-95da-31d3564cc057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746217671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2746217671
Directory /workspace/9.spi_device_upload/latest
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