Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2466891	1			T1	1693		T3	1		T4	24
all_values[1]	2466891	1			T1	1693		T3	1		T4	24
all_values[2]	2466891	1			T1	1693		T3	1		T4	24
all_values[3]	2466891	1			T1	1693		T3	1		T4	24
all_values[4]	2466891	1			T1	1693		T3	1		T4	24
all_values[5]	2466891	1			T1	1693		T3	1		T4	24
all_values[6]	2466891	1			T1	1693		T3	1		T4	24
all_values[7]	2466891	1			T1	1693		T3	1		T4	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19258077

1

T1

13544

T3

8

T4

192

auto[1]

477051

1

T19

93

T20

155

T21

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19707285

1

T1

13544

T3

8

T4

192

auto[1]

27843

1

T13

809

T14

202

T16

112

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2378963	1			T1	1693		T3	1		T4	24
all_values[0]	auto[0]	auto[1]	12785	1			T13	459		T14	82		T16	71
all_values[0]	auto[1]	auto[0]	74544	1			T19	4		T20	7		T21	1
all_values[0]	auto[1]	auto[1]	599	1			T19	5		T20	10		T22	259
all_values[1]	auto[0]	auto[0]	2427397	1			T1	1693		T3	1		T4	24
all_values[1]	auto[0]	auto[1]	8698	1			T13	255		T14	82		T16	41
all_values[1]	auto[1]	auto[0]	30344	1			T19	7		T20	16		T21	3
all_values[1]	auto[1]	auto[1]	452	1			T19	3		T20	8		T22	190
all_values[2]	auto[0]	auto[0]	2393058	1			T1	1693		T3	1		T4	24
all_values[2]	auto[0]	auto[1]	3058	1			T13	95		T14	38		T17	131
all_values[2]	auto[1]	auto[0]	70518	1			T19	11		T20	14		T21	1
all_values[2]	auto[1]	auto[1]	257	1			T19	4		T20	6		T21	5
all_values[3]	auto[0]	auto[0]	2377717	1			T1	1693		T3	1		T4	24
all_values[3]	auto[0]	auto[1]	214	1			T19	5		T20	9		T21	2
all_values[3]	auto[1]	auto[0]	88763	1			T19	4		T20	14		T21	5
all_values[3]	auto[1]	auto[1]	197	1			T19	3		T20	4		T22	1
all_values[4]	auto[0]	auto[0]	2403368	1			T1	1693		T3	1		T4	24
all_values[4]	auto[0]	auto[1]	202	1			T19	1		T20	6		T21	2
all_values[4]	auto[1]	auto[0]	63131	1			T19	10		T20	13		T21	3
all_values[4]	auto[1]	auto[1]	190	1			T19	2		T20	4		T22	2
all_values[5]	auto[0]	auto[0]	2379940	1			T1	1693		T3	1		T4	24
all_values[5]	auto[0]	auto[1]	189	1			T19	5		T20	9		T21	3
all_values[5]	auto[1]	auto[0]	86594	1			T19	8		T20	14		T21	4
all_values[5]	auto[1]	auto[1]	168	1			T19	1		T20	5		T22	1
all_values[6]	auto[0]	auto[0]	2431244	1			T1	1693		T3	1		T4	24
all_values[6]	auto[0]	auto[1]	191	1			T19	2		T20	9		T21	2
all_values[6]	auto[1]	auto[0]	35240	1			T19	9		T20	13		T21	4
all_values[6]	auto[1]	auto[1]	216	1			T19	7		T20	8		T21	1
all_values[7]	auto[0]	auto[0]	2440831	1			T1	1693		T3	1		T4	24
all_values[7]	auto[0]	auto[1]	222	1			T19	3		T20	9		T21	2
all_values[7]	auto[1]	auto[0]	25633	1			T19	7		T20	16		T21	7
all_values[7]	auto[1]	auto[1]	205	1			T19	8		T20	3		T21	2