Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36166	1			T3	4		T4	12		T5	70
auto[SpiFlashAddrCfg]	7500	1			T5	21		T9	14		T13	40
auto[SpiFlashAddr3b]	9543	1			T4	2		T5	28		T8	6
auto[SpiFlashAddr4b]	7755	1			T5	15		T8	8		T9	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34234

1

T3

4

T4

14

T5

79

auto[1]

26730

1

T5

55

T8

22

T9

129

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33003

1

T3

4

T5

68

T8

6

auto[1]

27961

1

T4

14

T5

66

T8

16

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40863	1			T3	4		T4	14		T5	87
values[1]	1110	1			T5	2		T9	2		T13	13
values[2]	1489	1			T9	3		T13	7		T14	4
values[3]	1423	1			T5	5		T9	7		T13	2
values[4]	1478	1			T5	1		T8	4		T9	2
values[5]	1549	1			T5	5		T13	9		T14	9
values[6]	1497	1			T8	2		T9	1		T13	10
values[7]	1414	1			T5	3		T9	5		T13	5
values[8]	10141	1			T5	31		T9	16		T13	65

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27794

1

T3

4

T4

14

T8

22

auto[1]

33170

1

T5

134

T13

330

T17

169

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57551

1

T3

4

T4

12

T5

126

write

3413

1

T4

2

T5

8

T8

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19887

1

T3

4

T5

45

T8

4

valids[0x1]

41077

1

T4

14

T5

89

T8

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1690	1			T5	3		T9	2		T13	10
internal_process_ops[0x5a]	1669	1			T5	5		T9	5		T12	2
internal_process_ops[0x05]	21428	1			T4	12		T5	37		T8	2
internal_process_ops[0x35]	1577	1			T5	4		T9	1		T13	14
internal_process_ops[0x15]	1653	1			T5	3		T8	2		T9	3
internal_process_ops[0x03]	997	1			T5	5		T9	2		T13	1
internal_process_ops[0x0b]	977	1			T5	1		T9	3		T13	6
internal_process_ops[0x3b]	1002	1			T5	4		T9	3		T13	3
internal_process_ops[0x6b]	972	1			T13	1		T14	7		T15	6
internal_process_ops[0xbb]	971	1			T5	3		T9	1		T13	2
internal_process_ops[0xeb]	963	1			T5	1		T9	6		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59356

1

T3

4

T4

14

T5

131

auto[1]

1608

1

T5

3

T8

12

T9

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58543

1

T3

4

T4

12

T5

130

auto[1]

2421

1

T4

2

T5

4

T9

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9746

1

T3

4

T4

12

T9

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6046

1

T8

4

T9

108

T14

307

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1669

1

T9

6

T14

11

T15

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1484

1

T9

7

T14

10

T15

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2184

1

T9

5

T14

12

T15

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1891

1

T8

6

T9

9

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1734

1

T9

8

T14

19

T15

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1621

1

T9

4

T14

15

T15

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

130

1

T14

7

T16

1

T93

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T14

1

T16

1

T18

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T15

4

T17

1

T28

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T8

4

T14

2

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T14

1

T17

2

T18

8

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

79

1

T14

2

T15

1

T17

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T9

1

T16

2

T17

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T17

3

T51

1

T177

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T4

2

T14

1

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T9

1

T14

1

T15

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T17

1

T28

1

T178

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

80

1

T14

1

T18

9

T179

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

91

1

T14

1

T28

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

71

1

T28

2

T18

5

T180

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T14

1

T15

5

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T8

8

T17

1

T18

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11259

1

T5

51

T13

113

T17

48

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8264

1

T5

17

T13

51

T17

37

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1786

1

T5

8

T13

21

T17

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1683

1

T5

11

T13

14

T17

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2242

1

T5

15

T13

28

T17

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2373

1

T5

10

T13

34

T17

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1811

1

T5

3

T13

20

T17

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1758

1

T5

11

T13

21

T17

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

133

1

T5

2

T13

4

T17

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T13

1

T17

1

T26

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

102

1

T13

1

T181

3

T182

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

113

1

T13

4

T26

1

T183

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

148

1

T17

3

T183

2

T182

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

146

1

T13

3

T181

1

T184

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

121

1

T13

1

T17

2

T26

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

118

1

T5

2

T13

1

T185

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

137

1

T13

2

T26

2

T186

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T26

2

T186

1

T22

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

141

1

T5

3

T17

1

T186

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T26

3

T184

1

T186

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

151

1

T13

4

T26

2

T168

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T13

1

T26

3

T183

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

115

1

T13

1

T26

2

T181

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

124

1

T5

1

T13

5

T17

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3416	1			T3	4		T9	11		T14	21
auto[0]	values[0]	valids[0x1]	14874	1			T4	14		T8	16		T9	114
auto[0]	values[1]	valids[0x1]	484	1			T9	2		T14	3		T15	4
auto[0]	values[2]	valids[0x0]	454	1			T9	3		T15	2		T16	2
auto[0]	values[2]	valids[0x1]	276	1			T14	4		T15	6		T16	1
auto[0]	values[3]	valids[0x0]	431	1			T9	7		T14	6		T15	9
auto[0]	values[3]	valids[0x1]	243	1			T14	4		T16	3		T17	1
auto[0]	values[4]	valids[0x0]	446	1			T8	4		T14	3		T15	4
auto[0]	values[4]	valids[0x1]	253	1			T9	2		T15	3		T16	2
auto[0]	values[5]	valids[0x0]	478	1			T14	7		T15	4		T17	9
auto[0]	values[5]	valids[0x1]	268	1			T14	2		T15	2		T16	2
auto[0]	values[6]	valids[0x0]	448	1			T14	4		T15	4		T94	4
auto[0]	values[6]	valids[0x1]	262	1			T8	2		T9	1		T15	1
auto[0]	values[7]	valids[0x0]	435	1			T9	1		T14	5		T15	4
auto[0]	values[7]	valids[0x1]	227	1			T9	4		T14	3		T17	4
auto[0]	values[8]	valids[0x0]	2935	1			T9	12		T14	24		T15	14
auto[0]	values[8]	valids[0x1]	1864	1			T9	4		T14	18		T15	12
auto[1]	values[0]	valids[0x0]	4863	1			T5	19		T13	72		T17	21
auto[1]	values[0]	valids[0x1]	17710	1			T5	68		T13	135		T17	84
auto[1]	values[1]	valids[0x1]	626	1			T5	2		T13	13		T17	7
auto[1]	values[2]	valids[0x0]	465	1			T13	4		T17	1		T26	5
auto[1]	values[2]	valids[0x1]	294	1			T13	3		T17	3		T26	3
auto[1]	values[3]	valids[0x0]	433	1			T5	2		T13	1		T17	2
auto[1]	values[3]	valids[0x1]	316	1			T5	3		T13	1		T26	3
auto[1]	values[4]	valids[0x0]	446	1			T13	5		T17	2		T26	2
auto[1]	values[4]	valids[0x1]	333	1			T5	1		T13	7		T17	3
auto[1]	values[5]	valids[0x0]	508	1			T5	4		T13	5		T17	3
auto[1]	values[5]	valids[0x1]	295	1			T5	1		T13	4		T17	3
auto[1]	values[6]	valids[0x0]	491	1			T13	8		T17	2		T26	3
auto[1]	values[6]	valids[0x1]	296	1			T13	2		T17	2		T26	2
auto[1]	values[7]	valids[0x0]	493	1			T5	3		T13	2		T17	2
auto[1]	values[7]	valids[0x1]	259	1			T13	3		T43	1		T181	1
auto[1]	values[8]	valids[0x0]	3145	1			T5	17		T13	29		T17	13
auto[1]	values[8]	valids[0x1]	2197	1			T5	14		T13	36		T17	21