Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3281099

1

T3

2371

T4

261

T5

3195

auto[1]

31814

1

T4

10

T5

34

T9

101

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

886535

1

T3

2371

T4

5

T5

29

auto[1]

2426378

1

T4

266

T5

3200

T9

5758

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	661254	1			T3	753		T4	271		T5	11
auto[524288:1048575]	345800	1			T13	79		T14	8425		T15	65
auto[1048576:1572863]	331641	1			T3	1590		T5	2		T9	128
auto[1572864:2097151]	436580	1			T5	388		T9	70		T13	160
auto[2097152:2621439]	378512	1			T3	5		T5	6		T9	1
auto[2621440:3145727]	400600	1			T5	272		T9	2727		T13	44
auto[3145728:3670015]	399395	1			T5	1017		T9	2568		T13	791
auto[3670016:4194303]	359131	1			T3	23		T5	1533		T9	277

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2461060

1

T3

13

T4

269

T5

3227

auto[1]

851853

1

T3

2358

T4

2

T5

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2890256

1

T3

2371

T4

271

T5

2347

auto[1]

422657

1

T5

882

T9

1

T13

3022

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	206987	1			T3	753		T4	3		T5	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	398045	1			T4	258		T5	1		T9	5
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	93426	1			T13	5		T14	7		T15	52
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	202913	1			T13	69		T14	8372		T17	2372
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	76786	1			T3	1590		T5	2		T13	16
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	225356	1			T9	128		T13	2746		T14	2623
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112914	1			T5	2		T9	5		T13	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	246574	1			T5	386		T9	1		T13	146
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	85169	1			T3	5		T5	1		T9	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	238994	1			T5	1		T13	519		T14	877
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	108275	1			T5	3		T9	1		T13	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	223800	1			T9	2725		T13	22		T14	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	102881	1			T5	5		T9	6		T13	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	238859	1			T5	385		T9	2544		T13	771
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84292	1			T3	23		T5	4		T9	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	219028	1			T5	1529		T9	257		T13	258
auto[0]	auto[1]	auto[0:524287]	auto[0]	912	1			T13	1		T17	7		T26	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	51254	1			T17	3004		T28	1570		T18	390
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1783	1			T14	2		T15	10		T17	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42354	1			T14	1		T17	1170		T18	138
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1330	1			T13	5		T14	5		T15	8
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	25261	1			T13	517		T14	2		T17	131
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3425	1			T13	1		T14	6		T15	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	68033	1			T14	2634		T17	413		T28	261
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	691	1			T13	1		T28	15		T18	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49817	1			T13	701		T18	636		T178	1795
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1286	1			T5	3		T9	1		T13	7
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	64513	1			T5	257		T13	3		T14	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1536	1			T5	2		T13	3		T15	21
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52755	1			T5	611		T13	1		T17	1024
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	663	1			T13	3		T17	3		T28	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	51187	1			T13	1769		T17	129		T18	3920
auto[1]	auto[0]	auto[0:524287]	auto[0]	594	1			T4	2		T5	1		T13	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2832	1			T4	8		T5	6		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	443	1			T13	2		T14	3		T15	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3344	1			T13	3		T14	28		T17	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	383	1			T13	5		T14	1		T15	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1908	1			T13	3		T14	5		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	549	1			T9	1		T13	2		T14	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4352	1			T9	63		T14	14		T17	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	399	1			T5	1		T13	4		T14	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2827	1			T5	3		T13	4		T14	56
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	272	1			T13	1		T14	2		T17	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1992	1			T13	1		T14	54		T18	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	361	1			T5	1		T9	1		T13	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2321	1			T5	13		T9	17		T13	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	402	1			T9	1		T13	2		T17	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2978	1			T9	18		T13	2		T17	16
auto[1]	auto[1]	auto[0:524287]	auto[0]	127	1			T17	3		T18	2		T214	10
auto[1]	auto[1]	auto[0:524287]	auto[1]	503	1			T17	6		T18	14		T214	126
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	98	1			T14	1		T17	1		T18	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1439	1			T14	11		T18	12		T170	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	98	1			T13	2		T14	2		T26	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	519	1			T14	13		T26	23		T21	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	71	1			T14	1		T17	3		T21	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	662	1			T14	49		T17	2		T32	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	80	1			T18	1		T177	1		T21	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	535	1			T18	1		T177	3		T21	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T5	1		T13	3		T17	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	373	1			T5	8		T13	1		T17	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	103	1			T13	1		T18	2		T177	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	579	1			T13	3		T18	49		T177	37
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	110	1			T17	1		T18	3		T51	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	471	1			T18	19		T181	12		T177	63

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2019200	1			T3	13		T4	260		T5	2320
auto[0]	auto[0]	auto[1]	845099	1			T3	2358		T4	1		T5	2
auto[0]	auto[1]	auto[0]	410740	1			T5	873		T9	1		T13	3012
auto[0]	auto[1]	auto[1]	6060	1			T14	2		T18	2		T177	3
auto[1]	auto[0]	auto[0]	25371	1			T4	9		T5	25		T9	101
auto[1]	auto[0]	auto[1]	586	1			T4	1		T13	1		T14	1
auto[1]	auto[1]	auto[0]	5749	1			T5	9		T13	10		T14	77
auto[1]	auto[1]	auto[1]	108	1			T17	1		T181	1		T183	1