Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2466891	1			T1	1693		T3	1		T4	24
all_pins[1]	2466891	1			T1	1693		T3	1		T4	24
all_pins[2]	2466891	1			T1	1693		T3	1		T4	24
all_pins[3]	2466891	1			T1	1693		T3	1		T4	24
all_pins[4]	2466891	1			T1	1693		T3	1		T4	24
all_pins[5]	2466891	1			T1	1693		T3	1		T4	24
all_pins[6]	2466891	1			T1	1693		T3	1		T4	24
all_pins[7]	2466891	1			T1	1693		T3	1		T4	24

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19696868	1			T1	13544		T3	8		T4	192
values[0x1]	38260	1			T19	33		T20	48		T21	8
transitions[0x0=>0x1]	36713	1			T19	22		T20	38		T21	8
transitions[0x1=>0x0]	36726	1			T19	22		T20	38		T21	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2466245	1			T1	1693		T3	1		T4	24
all_pins[0]	values[0x1]	646	1			T19	5		T20	10		T22	276
all_pins[0]	transitions[0x0=>0x1]	392	1			T19	4		T20	9		T22	79
all_pins[0]	transitions[0x1=>0x0]	228	1			T19	2		T20	7		T22	4
all_pins[1]	values[0x0]	2466409	1			T1	1693		T3	1		T4	24
all_pins[1]	values[0x1]	482	1			T19	3		T20	8		T22	201
all_pins[1]	transitions[0x0=>0x1]	409	1			T19	2		T20	7		T22	199
all_pins[1]	transitions[0x1=>0x0]	195	1			T19	3		T20	5		T21	5
all_pins[2]	values[0x0]	2466623	1			T1	1693		T3	1		T4	24
all_pins[2]	values[0x1]	268	1			T19	4		T20	6		T21	5
all_pins[2]	transitions[0x0=>0x1]	214	1			T19	3		T20	5		T21	5
all_pins[2]	transitions[0x1=>0x0]	143	1			T19	2		T20	3		T22	1
all_pins[3]	values[0x0]	2466694	1			T1	1693		T3	1		T4	24
all_pins[3]	values[0x1]	197	1			T19	3		T20	4		T22	1
all_pins[3]	transitions[0x0=>0x1]	154	1			T19	3		T20	3		T22	1
all_pins[3]	transitions[0x1=>0x0]	147	1			T19	2		T20	3		T22	2
all_pins[4]	values[0x0]	2466701	1			T1	1693		T3	1		T4	24
all_pins[4]	values[0x1]	190	1			T19	2		T20	4		T22	2
all_pins[4]	transitions[0x0=>0x1]	159	1			T19	1		T20	3		T22	2
all_pins[4]	transitions[0x1=>0x0]	1302	1			T20	4		T22	1		T23	1
all_pins[5]	values[0x0]	2465558	1			T1	1693		T3	1		T4	24
all_pins[5]	values[0x1]	1333	1			T19	1		T20	5		T22	1
all_pins[5]	transitions[0x0=>0x1]	360	1			T19	1		T20	2		T22	1
all_pins[5]	transitions[0x1=>0x0]	33966	1			T19	7		T20	5		T21	1
all_pins[6]	values[0x0]	2431952	1			T1	1693		T3	1		T4	24
all_pins[6]	values[0x1]	34939	1			T19	7		T20	8		T21	1
all_pins[6]	transitions[0x0=>0x1]	34888	1			T19	2		T20	8		T21	1
all_pins[6]	transitions[0x1=>0x0]	154	1			T19	3		T20	3		T21	2
all_pins[7]	values[0x0]	2466686	1			T1	1693		T3	1		T4	24
all_pins[7]	values[0x1]	205	1			T19	8		T20	3		T21	2
all_pins[7]	transitions[0x0=>0x1]	137	1			T19	6		T20	1		T21	2
all_pins[7]	transitions[0x1=>0x0]	591	1			T19	3		T20	8		T22	276