Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16096

1

T3

4

T4

14

T9

32

auto[1]

11698

1

T8

22

T9

129

T12

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3891	1			T8	22		T14	35		T15	40
values[1]	3489	1			T4	14		T9	39		T14	205
values[2]	3467	1			T17	20		T28	40		T18	23
values[3]	3422	1			T14	35		T15	20		T47	4
values[4]	3243	1			T9	122		T15	40		T16	43
values[5]	3760	1			T12	2		T14	97		T17	29
values[6]	3719	1			T15	20		T46	2		T93	10
values[7]	2803	1			T3	4		T14	114		T15	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3247	1			T9	20		T14	49		T15	20
values[1]	3208	1			T4	14		T9	102		T46	2
values[2]	3394	1			T9	39		T14	73		T16	24
values[3]	3924	1			T3	4		T14	76		T15	40
values[4]	3636	1			T14	35		T48	6		T17	43
values[5]	2955	1			T14	156		T15	20		T28	20
values[6]	3401	1			T14	97		T15	60		T94	16
values[7]	4029	1			T8	22		T12	2		T16	43

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	308	1			T17	15		T178	14		T38	8
auto[0]	values[0]	values[1]	151	1			T177	11		T219	12		T138	26
auto[0]	values[0]	values[2]	331	1			T170	11		T204	22		T244	10
auto[0]	values[0]	values[3]	230	1			T15	12		T90	16		T178	11
auto[0]	values[0]	values[4]	470	1			T14	12		T236	22		T31	17
auto[0]	values[0]	values[5]	196	1			T196	22		T245	11		T246	14
auto[0]	values[0]	values[6]	338	1			T15	11		T177	100		T38	6
auto[0]	values[0]	values[7]	325	1			T18	14		T177	87		T171	16
auto[0]	values[1]	values[0]	259	1			T14	37		T170	13		T22	14
auto[0]	values[1]	values[1]	205	1			T4	14		T18	12		T38	16
auto[0]	values[1]	values[2]	271	1			T9	9		T16	8		T18	13
auto[0]	values[1]	values[3]	233	1			T178	14		T177	13		T247	6
auto[0]	values[1]	values[4]	198	1			T17	9		T178	14		T31	15
auto[0]	values[1]	values[5]	275	1			T14	11		T18	96		T180	12
auto[0]	values[1]	values[6]	273	1			T28	29		T18	29		T248	2
auto[0]	values[1]	values[7]	144	1			T17	11		T38	19		T92	9
auto[0]	values[2]	values[0]	272	1			T17	13		T38	15		T249	18
auto[0]	values[2]	values[1]	224	1			T28	12		T179	29		T178	14
auto[0]	values[2]	values[2]	290	1			T177	13		T170	15		T199	81
auto[0]	values[2]	values[3]	365	1			T178	12		T38	31		T31	21
auto[0]	values[2]	values[4]	243	1			T18	11		T177	14		T170	16
auto[0]	values[2]	values[5]	118	1			T78	18		T201	28		T250	12
auto[0]	values[2]	values[6]	163	1			T28	8		T222	8		T221	12
auto[0]	values[2]	values[7]	290	1			T51	13		T178	9		T214	11
auto[0]	values[3]	values[0]	162	1			T18	8		T51	16		T22	12
auto[0]	values[3]	values[1]	255	1			T177	75		T214	10		T31	7
auto[0]	values[3]	values[2]	471	1			T14	24		T17	19		T177	11
auto[0]	values[3]	values[3]	199	1			T47	4		T178	12		T91	11
auto[0]	values[3]	values[4]	273	1			T214	8		T251	4		T230	10
auto[0]	values[3]	values[5]	322	1			T118	4		T170	11		T214	10
auto[0]	values[3]	values[6]	345	1			T15	10		T17	9		T18	14
auto[0]	values[3]	values[7]	95	1			T22	37		T252	10		T201	24
auto[0]	values[4]	values[0]	353	1			T9	13		T15	13		T178	13
auto[0]	values[4]	values[1]	209	1			T9	10		T253	61		T133	18
auto[0]	values[4]	values[2]	97	1			T138	10		T235	10		T228	9
auto[0]	values[4]	values[3]	214	1			T17	10		T18	8		T51	16
auto[0]	values[4]	values[4]	256	1			T177	9		T170	10		T214	11
auto[0]	values[4]	values[5]	182	1			T51	8		T22	18		T92	14
auto[0]	values[4]	values[6]	121	1			T15	5		T180	16		T178	15
auto[0]	values[4]	values[7]	464	1			T16	10		T51	13		T254	4
auto[0]	values[5]	values[0]	110	1			T214	9		T91	8		T255	40
auto[0]	values[5]	values[1]	347	1			T18	10		T219	11		T91	11
auto[0]	values[5]	values[2]	194	1			T179	13		T31	10		T91	9
auto[0]	values[5]	values[3]	218	1			T177	15		T197	10		T256	14
auto[0]	values[5]	values[4]	206	1			T28	16		T197	22		T201	13
auto[0]	values[5]	values[5]	201	1			T28	8		T18	11		T178	11
auto[0]	values[5]	values[6]	247	1			T14	13		T17	11		T18	20
auto[0]	values[5]	values[7]	350	1			T180	14		T198	10		T200	11
auto[0]	values[6]	values[0]	212	1			T17	15		T18	7		T178	8
auto[0]	values[6]	values[1]	207	1			T46	2		T93	10		T18	13
auto[0]	values[6]	values[2]	192	1			T17	15		T219	16		T257	16
auto[0]	values[6]	values[3]	362	1			T18	10		T214	11		T233	16
auto[0]	values[6]	values[4]	375	1			T48	6		T28	12		T177	140
auto[0]	values[6]	values[5]	184	1			T15	12		T178	13		T258	8
auto[0]	values[6]	values[6]	533	1			T17	12		T219	12		T259	40
auto[0]	values[6]	values[7]	218	1			T179	9		T197	13		T260	22
auto[0]	values[7]	values[0]	314	1			T219	14		T221	19		T235	8
auto[0]	values[7]	values[1]	175	1			T28	15		T18	17		T219	13
auto[0]	values[7]	values[2]	157	1			T14	25		T179	11		T261	14
auto[0]	values[7]	values[3]	275	1			T3	4		T14	9		T15	10
auto[0]	values[7]	values[4]	261	1			T17	8		T28	11		T18	9
auto[0]	values[7]	values[5]	232	1			T18	28		T179	15		T214	14
auto[0]	values[7]	values[6]	157	1			T18	14		T219	7		T262	4
auto[0]	values[7]	values[7]	179	1			T38	12		T91	29		T207	16
auto[1]	values[0]	values[0]	156	1			T17	5		T178	6		T38	12
auto[1]	values[0]	values[1]	265	1			T177	57		T219	8		T263	20
auto[1]	values[0]	values[2]	230	1			T170	10		T244	10		T91	5
auto[1]	values[0]	values[3]	182	1			T15	8		T178	9		T38	11
auto[1]	values[0]	values[4]	156	1			T14	23		T31	3		T230	9
auto[1]	values[0]	values[5]	107	1			T264	20		T245	9		T246	6
auto[1]	values[0]	values[6]	137	1			T15	9		T94	16		T177	13
auto[1]	values[0]	values[7]	309	1			T8	22		T18	85		T36	22
auto[1]	values[1]	values[0]	139	1			T14	12		T170	7		T22	6
auto[1]	values[1]	values[1]	163	1			T18	18		T38	4		T31	52
auto[1]	values[1]	values[2]	250	1			T9	30		T16	16		T18	9
auto[1]	values[1]	values[3]	231	1			T178	6		T177	7		T234	12
auto[1]	values[1]	values[4]	64	1			T17	11		T178	6		T31	8
auto[1]	values[1]	values[5]	232	1			T14	145		T18	8		T180	12
auto[1]	values[1]	values[6]	222	1			T28	11		T18	70		T199	12
auto[1]	values[1]	values[7]	330	1			T17	10		T38	26		T92	11
auto[1]	values[2]	values[0]	149	1			T17	7		T38	6		T31	9
auto[1]	values[2]	values[1]	195	1			T28	8		T179	11		T178	6
auto[1]	values[2]	values[2]	146	1			T177	7		T170	7		T199	6
auto[1]	values[2]	values[3]	359	1			T178	8		T38	15		T31	7
auto[1]	values[2]	values[4]	225	1			T18	12		T177	6		T170	10
auto[1]	values[2]	values[5]	69	1			T201	13		T240	14		T265	6
auto[1]	values[2]	values[6]	70	1			T28	12		T221	8		T201	20
auto[1]	values[2]	values[7]	289	1			T51	7		T178	11		T214	9
auto[1]	values[3]	values[0]	126	1			T18	14		T51	4		T22	34
auto[1]	values[3]	values[1]	193	1			T177	4		T214	10		T31	13
auto[1]	values[3]	values[2]	189	1			T14	11		T17	3		T177	40
auto[1]	values[3]	values[3]	102	1			T178	8		T91	9		T198	7
auto[1]	values[3]	values[4]	293	1			T214	12		T230	10		T136	14
auto[1]	values[3]	values[5]	147	1			T170	9		T214	10		T205	8
auto[1]	values[3]	values[6]	197	1			T15	10		T17	17		T18	47
auto[1]	values[3]	values[7]	53	1			T213	16		T22	8		T201	5
auto[1]	values[4]	values[0]	132	1			T9	7		T15	7		T178	7
auto[1]	values[4]	values[1]	225	1			T9	92		T50	16		T266	2
auto[1]	values[4]	values[2]	87	1			T138	10		T235	10		T228	11
auto[1]	values[4]	values[3]	186	1			T17	12		T18	12		T51	4
auto[1]	values[4]	values[4]	264	1			T177	21		T170	10		T214	9
auto[1]	values[4]	values[5]	180	1			T51	12		T225	2		T22	2
auto[1]	values[4]	values[6]	107	1			T15	15		T180	9		T178	5
auto[1]	values[4]	values[7]	166	1			T16	33		T51	7		T267	10
auto[1]	values[5]	values[0]	275	1			T214	11		T91	12		T268	220
auto[1]	values[5]	values[1]	156	1			T18	10		T219	9		T91	9
auto[1]	values[5]	values[2]	319	1			T179	7		T31	11		T91	11
auto[1]	values[5]	values[3]	286	1			T177	14		T197	55		T203	13
auto[1]	values[5]	values[4]	83	1			T28	4		T197	20		T201	12
auto[1]	values[5]	values[5]	308	1			T28	12		T18	9		T178	9
auto[1]	values[5]	values[6]	214	1			T14	84		T17	18		T18	27
auto[1]	values[5]	values[7]	246	1			T12	2		T180	9		T198	10
auto[1]	values[6]	values[0]	195	1			T17	5		T18	17		T178	12
auto[1]	values[6]	values[1]	165	1			T18	26		T221	8		T203	18
auto[1]	values[6]	values[2]	55	1			T17	12		T219	4		T230	13
auto[1]	values[6]	values[3]	235	1			T18	77		T214	9		T38	22
auto[1]	values[6]	values[4]	136	1			T28	8		T177	9		T170	34
auto[1]	values[6]	values[5]	96	1			T15	8		T178	7		T197	8
auto[1]	values[6]	values[6]	178	1			T17	14		T209	6		T219	8
auto[1]	values[6]	values[7]	376	1			T179	12		T197	7		T138	98
auto[1]	values[7]	values[0]	85	1			T219	6		T74	24		T221	1
auto[1]	values[7]	values[1]	73	1			T28	5		T18	12		T219	7
auto[1]	values[7]	values[2]	115	1			T14	13		T179	10		T269	12
auto[1]	values[7]	values[3]	247	1			T14	67		T15	10		T170	15
auto[1]	values[7]	values[4]	133	1			T17	15		T28	9		T18	28
auto[1]	values[7]	values[5]	106	1			T18	7		T179	7		T214	6
auto[1]	values[7]	values[6]	99	1			T18	6		T219	13		T201	9
auto[1]	values[7]	values[7]	195	1			T38	10		T91	11		T199	65